diff --git a/.cvsignore b/.cvsignore index 976083d..7d6e9ef 100644 --- a/.cvsignore +++ b/.cvsignore @@ -1 +1 @@ -xf86-video-ati-6.12.0.tar.bz2 +xf86-video-ati-6.12.1.tar.bz2 diff --git a/radeon-6.12.0-git-fixes.patch b/radeon-6.12.0-git-fixes.patch index 8b3f0f9..c3153dc 100644 --- a/radeon-6.12.0-git-fixes.patch +++ b/radeon-6.12.0-git-fixes.patch @@ -1,514 +1,2097 @@ +diff --git a/configure.ac b/configure.ac +index 3848f4c..660ea1f 100644 +--- a/configure.ac ++++ b/configure.ac +@@ -22,7 +22,7 @@ + + AC_PREREQ(2.57) + AC_INIT([xf86-video-ati], +- 6.12.1, ++ 6.12.1.99, + [https://bugs.freedesktop.org/enter_bug.cgi?product=xorg], + xf86-video-ati) + +diff --git a/src/ati_pciids_gen.h b/src/ati_pciids_gen.h +index d532f16..f31cadb 100644 +--- a/src/ati_pciids_gen.h ++++ b/src/ati_pciids_gen.h +@@ -429,3 +429,10 @@ + #define PCI_CHIP_RS780_9612 0x9612 + #define PCI_CHIP_RS780_9613 0x9613 + #define PCI_CHIP_RS780_9614 0x9614 ++#define PCI_CHIP_RS780_9615 0x9615 ++#define PCI_CHIP_RS780_9616 0x9616 ++#define PCI_CHIP_RS880_9710 0x9710 ++#define PCI_CHIP_RS880_9711 0x9711 ++#define PCI_CHIP_RS880_9712 0x9712 ++#define PCI_CHIP_RS880_9713 0x9713 ++#define PCI_CHIP_RS880_9714 0x9714 diff --git a/src/atombios_output.c b/src/atombios_output.c -index 130ab93..70e716c 100644 +index 35d1767..4af04c1 100644 --- a/src/atombios_output.c +++ b/src/atombios_output.c -@@ -1019,30 +1019,11 @@ static void atom_rv515_force_tv_scaler(ScrnInfoPtr pScrn) - static int - atombios_output_yuv_setup(xf86OutputPtr output, Bool enable) - { -- RADEONOutputPrivatePtr radeon_output = output->driver_private; - RADEONInfoPtr info = RADEONPTR(output->scrn); - RADEONCrtcPrivatePtr radeon_crtc = output->crtc->driver_private; - ENABLE_YUV_PS_ALLOCATION disp_data; - AtomBiosArgRec data; - unsigned char *space; -- unsigned char *RADEONMMIO = info->MMIO; -- uint32_t temp, reg; -- -- if (info->ChipFamily >= CHIP_FAMILY_R600) -- reg = R600_BIOS_3_SCRATCH; +@@ -1406,8 +1406,12 @@ atombios_set_output_crtc_source(xf86OutputPtr output) + default: + if (IS_AVIVO_VARIANT) + crtc_src_param.ucCRTC = radeon_crtc->crtc_id; +- else +- crtc_src_param.ucCRTC = radeon_crtc->crtc_id << 2; ++ else { ++ if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ++ crtc_src_param.ucCRTC = radeon_crtc->crtc_id; ++ else ++ crtc_src_param.ucCRTC = radeon_crtc->crtc_id << 2; ++ } + switch (radeon_encoder->encoder_id) { + case ENCODER_OBJECT_ID_INTERNAL_TMDS1: + case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: +diff --git a/src/pcidb/ati_pciids.csv b/src/pcidb/ati_pciids.csv +index 4d4e625..bff80ca 100644 +--- a/src/pcidb/ati_pciids.csv ++++ b/src/pcidb/ati_pciids.csv +@@ -430,3 +430,10 @@ + "0x9612","RS780_9612","RS780",,1,,,1,"ATI Radeon HD 3200 Graphics" + "0x9613","RS780_9613","RS780",,1,,,1,"ATI Radeon 3100 Graphics" + "0x9614","RS780_9614","RS780",,1,,,1,"ATI Radeon HD 3300 Graphics" ++"0x9615","RS780_9615","RS780",,1,,,1,"ATI Radeon HD 3200 Graphics" ++"0x9616","RS780_9616","RS780",,1,,,1,"ATI Radeon 3000 Graphics" ++"0x9710","RS880_9710","RS880",,1,,,1,"ATI Radeon HD Graphics" ++"0x9711","RS880_9711","RS880",,1,,,1,"ATI Radeon Graphics" ++"0x9712","RS880_9712","RS880",1,1,,,1,"ATI Mobility Radeon HD Graphics" ++"0x9713","RS880_9713","RS880",1,1,,,1,"ATI Mobility Radeon Graphics" ++"0x9714","RS880_9714","RS880",,1,,,1,"ATI Radeon Graphics" +diff --git a/src/r600_exa.c b/src/r600_exa.c +index 40f02e1..2dc33a8 100644 +--- a/src/r600_exa.c ++++ b/src/r600_exa.c +@@ -1098,6 +1098,7 @@ static Bool R600TextureSetup(PicturePtr pPict, PixmapPtr pPix, + unsigned int i; + tex_resource_t tex_res; + tex_sampler_t tex_samp; ++ int pix_r, pix_g, pix_b, pix_a; + + CLEAR (tex_res); + CLEAR (tex_samp); +@@ -1142,46 +1143,102 @@ static Bool R600TextureSetup(PicturePtr pPict, PixmapPtr pPix, + switch (pPict->format) { + case PICT_a1r5g5b5: + case PICT_a8r8g8b8: +- tex_res.dst_sel_x = SQ_SEL_Z; /* R */ +- tex_res.dst_sel_y = SQ_SEL_Y; /* G */ +- tex_res.dst_sel_z = SQ_SEL_X; /* B */ +- tex_res.dst_sel_w = SQ_SEL_W; /* A */ ++ pix_r = SQ_SEL_Z; /* R */ ++ pix_g = SQ_SEL_Y; /* G */ ++ pix_b = SQ_SEL_X; /* B */ ++ pix_a = SQ_SEL_W; /* A */ + break; + case PICT_a8b8g8r8: +- tex_res.dst_sel_x = SQ_SEL_X; /* R */ +- tex_res.dst_sel_y = SQ_SEL_Y; /* G */ +- tex_res.dst_sel_z = SQ_SEL_Z; /* B */ +- tex_res.dst_sel_w = SQ_SEL_W; /* A */ ++ pix_r = SQ_SEL_X; /* R */ ++ pix_g = SQ_SEL_Y; /* G */ ++ pix_b = SQ_SEL_Z; /* B */ ++ pix_a = SQ_SEL_W; /* A */ + break; + case PICT_x8b8g8r8: +- tex_res.dst_sel_x = SQ_SEL_X; /* R */ +- tex_res.dst_sel_y = SQ_SEL_Y; /* G */ +- tex_res.dst_sel_z = SQ_SEL_Z; /* B */ +- tex_res.dst_sel_w = SQ_SEL_1; /* A */ ++ pix_r = SQ_SEL_X; /* R */ ++ pix_g = SQ_SEL_Y; /* G */ ++ pix_b = SQ_SEL_Z; /* B */ ++ pix_a = SQ_SEL_1; /* A */ + break; + case PICT_x1r5g5b5: + case PICT_x8r8g8b8: +- tex_res.dst_sel_x = SQ_SEL_Z; /* R */ +- tex_res.dst_sel_y = SQ_SEL_Y; /* G */ +- tex_res.dst_sel_z = SQ_SEL_X; /* B */ +- tex_res.dst_sel_w = SQ_SEL_1; /* A */ +- break; + case PICT_r5g6b5: +- tex_res.dst_sel_x = SQ_SEL_Z; /* R */ +- tex_res.dst_sel_y = SQ_SEL_Y; /* G */ +- tex_res.dst_sel_z = SQ_SEL_X; /* B */ +- tex_res.dst_sel_w = SQ_SEL_1; /* A */ ++ pix_r = SQ_SEL_Z; /* R */ ++ pix_g = SQ_SEL_Y; /* G */ ++ pix_b = SQ_SEL_X; /* B */ ++ pix_a = SQ_SEL_1; /* A */ + break; + case PICT_a8: +- tex_res.dst_sel_x = SQ_SEL_0; /* R */ +- tex_res.dst_sel_y = SQ_SEL_0; /* G */ +- tex_res.dst_sel_z = SQ_SEL_0; /* B */ +- tex_res.dst_sel_w = SQ_SEL_X; /* A */ ++ pix_r = SQ_SEL_0; /* R */ ++ pix_g = SQ_SEL_0; /* G */ ++ pix_b = SQ_SEL_0; /* B */ ++ pix_a = SQ_SEL_X; /* A */ + break; + default: + RADEON_FALLBACK(("Bad format 0x%x\n", pPict->format)); + } + ++ if (unit == 0) { ++ if (!accel_state->has_mask) { ++ if (PICT_FORMAT_RGB(pPict->format) == 0) { ++ pix_r = SQ_SEL_0; ++ pix_g = SQ_SEL_0; ++ pix_b = SQ_SEL_0; ++ } ++ ++ if (PICT_FORMAT_A(pPict->format) == 0) ++ pix_a = SQ_SEL_1; ++ } else { ++ if (accel_state->component_alpha) { ++ if (accel_state->src_alpha) { ++ if (PICT_FORMAT_A(pPict->format) == 0) { ++ pix_r = SQ_SEL_1; ++ pix_g = SQ_SEL_1; ++ pix_b = SQ_SEL_1; ++ pix_a = SQ_SEL_1; ++ } else { ++ pix_r = pix_a; ++ pix_g = pix_a; ++ pix_b = pix_a; ++ } ++ } else { ++ if (PICT_FORMAT_A(pPict->format) == 0) ++ pix_a = SQ_SEL_1; ++ } ++ } else { ++ if (PICT_FORMAT_RGB(pPict->format) == 0) { ++ pix_r = SQ_SEL_0; ++ pix_g = SQ_SEL_0; ++ pix_b = SQ_SEL_0; ++ } ++ ++ if (PICT_FORMAT_A(pPict->format) == 0) ++ pix_a = SQ_SEL_1; ++ } ++ } ++ } else { ++ if (accel_state->component_alpha) { ++ if (PICT_FORMAT_A(pPict->format) == 0) ++ pix_a = SQ_SEL_1; ++ } else { ++ if (PICT_FORMAT_A(pPict->format) == 0) { ++ pix_r = SQ_SEL_1; ++ pix_g = SQ_SEL_1; ++ pix_b = SQ_SEL_1; ++ pix_a = SQ_SEL_1; ++ } else { ++ pix_r = pix_a; ++ pix_g = pix_a; ++ pix_b = pix_a; ++ } ++ } ++ } ++ ++ tex_res.dst_sel_x = pix_r; /* R */ ++ tex_res.dst_sel_y = pix_g; /* G */ ++ tex_res.dst_sel_z = pix_b; /* B */ ++ tex_res.dst_sel_w = pix_a; /* A */ ++ + tex_res.base_level = 0; + tex_res.last_level = 0; + tex_res.perf_modulation = 0; +@@ -1324,14 +1381,26 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture, + uint32_t blendcntl, dst_format; + cb_config_t cb_conf; + shader_config_t vs_conf, ps_conf; +- uint32_t ps[24]; + + /* return FALSE; */ + +- if (pMask) ++ if (pMask) { + accel_state->has_mask = TRUE; - else -- reg = RADEON_BIOS_3_SCRATCH; ++ if (pMaskPicture->componentAlpha) { ++ accel_state->component_alpha = TRUE; ++ if (R600BlendOp[op].src_alpha) ++ accel_state->src_alpha = TRUE; ++ else ++ accel_state->src_alpha = FALSE; ++ } else { ++ accel_state->component_alpha = FALSE; ++ accel_state->src_alpha = FALSE; ++ } ++ } else { + accel_state->has_mask = FALSE; ++ accel_state->component_alpha = FALSE; ++ accel_state->src_alpha = FALSE; ++ } + + accel_state->dst_mc_addr = exaGetPixmapOffset(pDst) + info->fbLocation + pScrn->fbOffset; + accel_state->dst_pitch = exaGetPixmapPitch(pDst) / (pDst->drawable.bitsPerPixel / 8); +@@ -1346,116 +1415,6 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture, + if (!R600GetDestFormat(pDstPicture, &dst_format)) + return FALSE; + +- if (pMask) { +- int src_a, src_r, src_g, src_b; +- int mask_a, mask_r, mask_g, mask_b; - -- //fix up scratch reg handling -- temp = INREG(reg); -- if (radeon_output->active_device & (ATOM_DEVICE_TV_SUPPORT)) -- OUTREG(reg, (ATOM_S3_TV1_ACTIVE | -- (radeon_crtc->crtc_id << 18))); -- else if (radeon_output->active_device & (ATOM_DEVICE_CV_SUPPORT)) -- OUTREG(reg, (ATOM_S3_CV_ACTIVE | -- (radeon_crtc->crtc_id << 24))); -- else -- OUTREG(reg, 0); +- /* setup pixel shader */ +- if (PICT_FORMAT_RGB(pSrcPicture->format) == 0) { +- src_r = SQ_SEL_0; +- src_g = SQ_SEL_0; +- src_b = SQ_SEL_0; +- } else { +- src_r = SQ_SEL_X; +- src_g = SQ_SEL_Y; +- src_b = SQ_SEL_Z; +- } +- +- if (PICT_FORMAT_A(pSrcPicture->format) == 0) { +- src_a = SQ_SEL_1; +- } else { +- src_a = SQ_SEL_W; +- } +- +- if (pMaskPicture->componentAlpha) { +- if (R600BlendOp[op].src_alpha) { +- if (PICT_FORMAT_A(pSrcPicture->format) == 0) { +- src_r = SQ_SEL_1; +- src_g = SQ_SEL_1; +- src_b = SQ_SEL_1; +- src_a = SQ_SEL_1; +- } else { +- src_r = SQ_SEL_W; +- src_g = SQ_SEL_W; +- src_b = SQ_SEL_W; +- src_a = SQ_SEL_W; +- } +- +- mask_r = SQ_SEL_X; +- mask_g = SQ_SEL_Y; +- mask_b = SQ_SEL_Z; +- +- if (PICT_FORMAT_A(pMaskPicture->format) == 0) { +- mask_a = SQ_SEL_1; +- } else { +- mask_a = SQ_SEL_W; +- } +- } else { +- src_r = SQ_SEL_X; +- src_g = SQ_SEL_Y; +- src_b = SQ_SEL_Z; +- +- if (PICT_FORMAT_A(pSrcPicture->format) == 0) { +- src_a = SQ_SEL_1; +- } else { +- src_a = SQ_SEL_W; +- } +- +- mask_r = SQ_SEL_X; +- mask_g = SQ_SEL_Y; +- mask_b = SQ_SEL_Z; +- +- if (PICT_FORMAT_A(pMaskPicture->format) == 0) { +- mask_a = SQ_SEL_1; +- } else { +- mask_a = SQ_SEL_W; +- } +- } +- } else { +- if (PICT_FORMAT_A(pMaskPicture->format) == 0) { +- mask_r = SQ_SEL_1; +- mask_g = SQ_SEL_1; +- mask_b = SQ_SEL_1; +- } else { +- mask_r = SQ_SEL_W; +- mask_g = SQ_SEL_W; +- mask_b = SQ_SEL_W; +- } +- if (PICT_FORMAT_A(pMaskPicture->format) == 0) { +- mask_a = SQ_SEL_1; +- } else { +- mask_a = SQ_SEL_W; +- } +- } +- +- R600_comp_mask_ps(info->ChipFamily, ps, +- src_a, src_r, src_g, src_b, +- mask_a, mask_r, mask_g, mask_b); +- +- } else { +- int src_a, src_r, src_g, src_b; +- /* setup pixel shader */ +- if (PICT_FORMAT_RGB(pSrcPicture->format) == 0) { +- src_r = SQ_SEL_0; +- src_g = SQ_SEL_0; +- src_b = SQ_SEL_0; +- } else { +- src_r = SQ_SEL_X; +- src_g = SQ_SEL_Y; +- src_b = SQ_SEL_Z; +- } +- +- if (PICT_FORMAT_A(pSrcPicture->format) == 0) { +- src_a = SQ_SEL_1; +- } else { +- src_a = SQ_SEL_W; +- } +- +- R600_comp_ps(info->ChipFamily, ps, +- src_a, src_r, src_g, src_b); +- +- } +- + CLEAR (cb_conf); + CLEAR (vs_conf); + CLEAR (ps_conf); +@@ -1484,19 +1443,19 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture, + } else + accel_state->is_transform[1] = FALSE; - memset(&disp_data, 0, sizeof(disp_data)); +- /* VS bool constant */ +- if (pMask) +- set_bool_const(pScrn, accel_state->ib, 1, 1); +- else +- set_bool_const(pScrn, accel_state->ib, 1, 0); ++ if (pMask) { ++ set_bool_consts(pScrn, accel_state->ib, SQ_BOOL_CONST_vs, (1 << 0)); ++ accel_state->ps_mc_addr = info->fbLocation + pScrn->fbOffset + accel_state->shaders->offset + ++ accel_state->comp_mask_ps_offset; ++ } else { ++ set_bool_consts(pScrn, accel_state->ib, SQ_BOOL_CONST_vs, (0 << 0)); ++ accel_state->ps_mc_addr = info->fbLocation + pScrn->fbOffset + accel_state->shaders->offset + ++ accel_state->comp_ps_offset; ++ } -@@ -1055,15 +1036,10 @@ atombios_output_yuv_setup(xf86OutputPtr output, Bool enable) - data.exec.pspace = &disp_data; + accel_state->vs_mc_addr = info->fbLocation + pScrn->fbOffset + accel_state->shaders->offset + + accel_state->comp_vs_offset; - if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) { +- memcpy ((char *)accel_state->ib->address + (accel_state->ib->total / 2) - 256, ps, sizeof(ps)); +- accel_state->ps_mc_addr = info->gartLocation + info->dri->bufStart + +- (accel_state->ib->idx * accel_state->ib->total) + (accel_state->ib->total / 2) - 256; - -- OUTREG(reg, temp); + accel_state->vs_size = 512; + accel_state->ps_size = 512; + +@@ -2013,11 +1972,11 @@ R600LoadShaders(ScrnInfoPtr pScrn) + + /* comp ps --------------------------------------- */ + accel_state->comp_ps_offset = 2560; +- /* not yet */ ++ R600_comp_ps(ChipSet, shader + accel_state->comp_ps_offset / 4); + + /* comp mask ps --------------------------------------- */ + accel_state->comp_mask_ps_offset = 3072; +- /* not yet */ ++ R600_comp_mask_ps(ChipSet, shader + accel_state->comp_mask_ps_offset / 4); + + /* xv vs --------------------------------------- */ + accel_state->xv_vs_offset = 3584; +@@ -2105,10 +2064,10 @@ R600DrawInit(ScreenPtr pScreen) + #if EXA_VERSION_MAJOR > 2 || (EXA_VERSION_MAJOR == 2 && EXA_VERSION_MINOR >= 3) + xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Setting EXA maxPitchBytes\n"); + +- info->accel_state->exa->maxPitchBytes = 16320; ++ info->accel_state->exa->maxPitchBytes = 32768; + info->accel_state->exa->maxX = 8192; + #else +- info->accel_state->exa->maxX = 16320 / 4; ++ info->accel_state->exa->maxX = 8192; + #endif + info->accel_state->exa->maxY = 8192; + +diff --git a/src/r600_reg.h b/src/r600_reg.h +index 9036e2a..937926b 100644 +--- a/src/r600_reg.h ++++ b/src/r600_reg.h +@@ -51,8 +51,8 @@ enum { + SET_LOOP_CONST_offset = 0x0003e200, + SET_LOOP_CONST_end = 0x0003e380, + SET_BOOL_CONST_offset = 0x0003e380, +- SET_BOOL_CONST_end = 0x00040000, +-} ; ++ SET_BOOL_CONST_end = 0x0003e38c, ++}; + + /* packet3 IT_SURFACE_BASE_UPDATE bits */ + enum { +diff --git a/src/r600_reg_r6xx.h b/src/r600_reg_r6xx.h +index 2e7dfa9..b4cc639 100644 +--- a/src/r600_reg_r6xx.h ++++ b/src/r600_reg_r6xx.h +@@ -488,7 +488,16 @@ enum { + SQ_LOOP_CONST_ps = 0, + SQ_LOOP_CONST_vs = SQ_LOOP_CONST_ps + SQ_LOOP_CONST_ps_num, + SQ_LOOP_CONST_gs = SQ_LOOP_CONST_vs + SQ_LOOP_CONST_vs_num, +-} ; ++ SQ_BOOL_CONST = SQ_BOOL_CONST_0, /* 32 bits per PS, VS, GS */ ++ SQ_BOOL_CONST_ps_num = 1, ++ SQ_BOOL_CONST_vs_num = 1, ++ SQ_BOOL_CONST_gs_num = 1, ++ SQ_BOOL_CONST_all_num = 3, ++ SQ_BOOL_CONST_offset = 4, ++ SQ_BOOL_CONST_ps = 0, ++ SQ_BOOL_CONST_vs = SQ_BOOL_CONST_ps + SQ_BOOL_CONST_ps_num, ++ SQ_BOOL_CONST_gs = SQ_BOOL_CONST_vs + SQ_BOOL_CONST_vs_num, ++}; + + + #endif +diff --git a/src/r600_shader.c b/src/r600_shader.c +index 21c4c68..addba36 100644 +--- a/src/r600_shader.c ++++ b/src/r600_shader.c +@@ -1245,10 +1245,7 @@ int R600_xv_ps(RADEONChipFamily ChipSet, uint32_t* shader) + } + + /* comp mask ps --------------------------------------- */ +-int R600_comp_mask_ps(RADEONChipFamily ChipSet, +- uint32_t* shader, +- int src_a, int src_r, int src_g, int src_b, +- int mask_a, int mask_r, int mask_g, int mask_b) ++int R600_comp_mask_ps(RADEONChipFamily ChipSet, uint32_t* shader) + { + int i = 0; + +@@ -1421,10 +1418,10 @@ int R600_comp_mask_ps(RADEONChipFamily ChipSet, + R7xx_ALT_CONST(0)); + shader[i++] = TEX_DWORD1(DST_GPR(0), + DST_REL(ABSOLUTE), +- DST_SEL_X(src_r), +- DST_SEL_Y(src_g), +- DST_SEL_Z(src_b), +- DST_SEL_W(src_a), ++ DST_SEL_X(SQ_SEL_X), ++ DST_SEL_Y(SQ_SEL_Y), ++ DST_SEL_Z(SQ_SEL_Z), ++ DST_SEL_W(SQ_SEL_W), + LOD_BIAS(0), + COORD_TYPE_X(TEX_NORMALIZED), + COORD_TYPE_Y(TEX_NORMALIZED), +@@ -1449,10 +1446,10 @@ int R600_comp_mask_ps(RADEONChipFamily ChipSet, + R7xx_ALT_CONST(0)); + shader[i++] = TEX_DWORD1(DST_GPR(1), + DST_REL(ABSOLUTE), +- DST_SEL_X(mask_r), +- DST_SEL_Y(mask_g), +- DST_SEL_Z(mask_b), +- DST_SEL_W(mask_a), ++ DST_SEL_X(SQ_SEL_X), ++ DST_SEL_Y(SQ_SEL_Y), ++ DST_SEL_Z(SQ_SEL_Z), ++ DST_SEL_W(SQ_SEL_W), + LOD_BIAS(0), + COORD_TYPE_X(TEX_NORMALIZED), + COORD_TYPE_Y(TEX_NORMALIZED), +@@ -1781,10 +1778,7 @@ int R600_comp_vs(RADEONChipFamily ChipSet, uint32_t* shader) + } + + /* comp ps --------------------------------------- */ +-int R600_comp_ps(RADEONChipFamily ChipSet, +- uint32_t* shader, +- int src_a, int src_r, int src_g, int src_b +-) ++int R600_comp_ps(RADEONChipFamily ChipSet, uint32_t* shader) + { + int i = 0; + +@@ -1831,10 +1825,10 @@ int R600_comp_ps(RADEONChipFamily ChipSet, + R7xx_ALT_CONST(0)); + shader[i++] = TEX_DWORD1(DST_GPR(0), + DST_REL(ABSOLUTE), +- DST_SEL_X(src_r), +- DST_SEL_Y(src_g), +- DST_SEL_Z(src_b), +- DST_SEL_W(src_a), ++ DST_SEL_X(SQ_SEL_X), ++ DST_SEL_Y(SQ_SEL_Y), ++ DST_SEL_Z(SQ_SEL_Z), ++ DST_SEL_W(SQ_SEL_W), + LOD_BIAS(0), + COORD_TYPE_X(TEX_NORMALIZED), + COORD_TYPE_Y(TEX_NORMALIZED), +diff --git a/src/r600_shader.h b/src/r600_shader.h +index 67b64ff..6c12614 100644 +--- a/src/r600_shader.h ++++ b/src/r600_shader.h +@@ -352,15 +352,8 @@ extern int R600_copy_ps(RADEONChipFamily ChipSet, uint32_t* ps); + extern int R600_xv_vs(RADEONChipFamily ChipSet, uint32_t* shader); + extern int R600_xv_ps(RADEONChipFamily ChipSet, uint32_t* shader); + +-extern int R600_comp_mask_vs(RADEONChipFamily ChipSet, uint32_t* vs); +-extern int R600_comp_mask_ps(RADEONChipFamily ChipSet, +- uint32_t* ps, +- int src_a, int src_r, int src_g, int src_b, +- int mask_a, int mask_r, int mask_g, int mask_b); - - ErrorF("crtc %d YUV %s setup success\n", radeon_crtc->crtc_id, enable ? "enable" : "disable"); - return ATOM_SUCCESS; + extern int R600_comp_vs(RADEONChipFamily ChipSet, uint32_t* vs); +-extern int R600_comp_ps(RADEONChipFamily ChipSet, +- uint32_t* ps, +- int src_a, int src_r, int src_g, int src_b); ++extern int R600_comp_mask_ps(RADEONChipFamily ChipSet, uint32_t* ps); ++extern int R600_comp_ps(RADEONChipFamily ChipSet, uint32_t* ps); + + #endif +diff --git a/src/r600_state.h b/src/r600_state.h +index c903ded..181e167 100644 +--- a/src/r600_state.h ++++ b/src/r600_state.h +@@ -255,7 +255,7 @@ ps_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *ps_conf); + void + set_alu_consts(ScrnInfoPtr pScrn, drmBufPtr ib, int offset, int count, float *const_buf); + void +-set_bool_const(ScrnInfoPtr pScrn, drmBufPtr ib, int offset, uint32_t val); ++set_bool_consts(ScrnInfoPtr pScrn, drmBufPtr ib, int offset, uint32_t val); + void + set_vtx_resource(ScrnInfoPtr pScrn, drmBufPtr ib, vtx_resource_t *res); + void +diff --git a/src/r600_textured_videofuncs.c b/src/r600_textured_videofuncs.c +index 735231b..3dfe151 100644 +--- a/src/r600_textured_videofuncs.c ++++ b/src/r600_textured_videofuncs.c +@@ -172,12 +172,12 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) + switch(pPriv->id) { + case FOURCC_YV12: + case FOURCC_I420: +- set_bool_const(pScrn, accel_state->ib, 0, 1); ++ set_bool_consts(pScrn, accel_state->ib, SQ_BOOL_CONST_ps, (1 << 0)); + break; + case FOURCC_UYVY: + case FOURCC_YUY2: + default: +- set_bool_const(pScrn, accel_state->ib, 0, 0); ++ set_bool_consts(pScrn, accel_state->ib, SQ_BOOL_CONST_ps, (0 << 0)); + break; } -- OUTREG(reg, temp); -- - ErrorF("crtc %d YUV %s setup failed\n", radeon_crtc->crtc_id, enable ? "enable" : "disable"); - return ATOM_NOT_IMPLEMENTED; - -diff --git a/src/radeon_accel.c b/src/radeon_accel.c -index dffbc57..a9a4848 100644 ---- a/src/radeon_accel.c -+++ b/src/radeon_accel.c -@@ -688,8 +688,6 @@ void RADEONCPFlushIndirect(ScrnInfoPtr pScrn, int discard) - drmBufPtr buffer = info->cp->indirectBuffer; - int start = info->cp->indirectStart; - drm_radeon_indirect_t indirect; -- RING_LOCALS; -- RADEONCP_REFRESH(pScrn, info); - - if (!buffer) return; - if (start == buffer->used && !discard) return; -@@ -700,10 +698,14 @@ void RADEONCPFlushIndirect(ScrnInfoPtr pScrn, int discard) +diff --git a/src/r6xx_accel.c b/src/r6xx_accel.c +index f93ca01..bce597b 100644 +--- a/src/r6xx_accel.c ++++ b/src/r6xx_accel.c +@@ -153,8 +153,10 @@ reset_bool_loop_const(ScrnInfoPtr pScrn, drmBufPtr ib) + { + int i; + +- for (i = 0; i < SQ_BOOL_CONST_0_num; i++) +- EREG(ib, SQ_BOOL_CONST_0 + (i << 2), 0); ++ ++ PACK0(ib, SQ_BOOL_CONST, SQ_BOOL_CONST_all_num); ++ for (i = 0; i < SQ_BOOL_CONST_all_num; i++) ++ E32(ib, 0); + + PACK0(ib, SQ_LOOP_CONST, SQ_LOOP_CONST_all_num); + +@@ -430,10 +432,12 @@ set_alu_consts(ScrnInfoPtr pScrn, drmBufPtr ib, int offset, int count, float *co + } + + void +-set_bool_const(ScrnInfoPtr pScrn, drmBufPtr ib, int offset, uint32_t val) ++set_bool_consts(ScrnInfoPtr pScrn, drmBufPtr ib, int offset, uint32_t val) + { +- /* bool order is: ps, vs, gs, ps, vs, gs, ... */ +- EREG(ib, SQ_BOOL_CONST_0 + (offset << 2), val); ++ /* bool register order is: ps, vs, gs; one register each ++ * 1 bits per bool; 32 bools each for ps, vs, gs. ++ */ ++ EREG(ib, SQ_BOOL_CONST + offset * SQ_BOOL_CONST_offset, val); + } + + void +diff --git a/src/radeon.h b/src/radeon.h +index 7bb720a..d488429 100644 +--- a/src/radeon.h ++++ b/src/radeon.h +@@ -325,6 +325,7 @@ typedef enum { + CHIP_FAMILY_RV620, + CHIP_FAMILY_RV635, + CHIP_FAMILY_RS780, ++ CHIP_FAMILY_RS880, + CHIP_FAMILY_RV770, + CHIP_FAMILY_RV730, + CHIP_FAMILY_RV710, +@@ -655,6 +656,10 @@ struct radeon_accel_state { + Bool same_surface; + int rop; + uint32_t planemask; ++ ++ // composite ++ Bool component_alpha; ++ Bool src_alpha; + #endif + + #ifdef USE_XAA +@@ -1051,8 +1056,10 @@ extern RADEONEntPtr RADEONEntPriv(ScrnInfoPtr pScrn); + extern int RADEONMinBits(int val); + extern unsigned RADEONINMC(ScrnInfoPtr pScrn, int addr); + extern unsigned RADEONINPLL(ScrnInfoPtr pScrn, int addr); ++extern unsigned RADEONINPCIE(ScrnInfoPtr pScrn, int addr); + extern void RADEONOUTMC(ScrnInfoPtr pScrn, int addr, uint32_t data); + extern void RADEONOUTPLL(ScrnInfoPtr pScrn, int addr, uint32_t data); ++extern void RADEONOUTPCIE(ScrnInfoPtr pScrn, int addr, uint32_t data); + extern void RADEONPllErrataAfterData(RADEONInfoPtr info); + extern void RADEONPllErrataAfterIndex(RADEONInfoPtr info); + extern void RADEONWaitForVerticalSync(ScrnInfoPtr pScrn); +diff --git a/src/radeon_atombios.c b/src/radeon_atombios.c +index 0b17cbd..47f5103 100644 +--- a/src/radeon_atombios.c ++++ b/src/radeon_atombios.c +@@ -1784,7 +1784,7 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn) + continue; + } + +- if ((info->ChipFamily == CHIP_FAMILY_RS780) && ++ if (info->IsIGP && + (con_obj_id == CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) { + uint32_t slot_config, ct; + +diff --git a/src/radeon_bios.c b/src/radeon_bios.c +index 6fc0cf4..9b5cb88 100644 +--- a/src/radeon_bios.c ++++ b/src/radeon_bios.c +@@ -740,6 +740,9 @@ static Bool RADEONGetLegacyConnectorInfoFromBIOS (ScrnInfoPtr pScrn) + if (tmp1) { + DDCType = tmp1; + switch (DDCType) { ++ case DDC_NONE_DETECTED: ++ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "No DDC for LCD\n"); ++ break; + case DDC_MONID: + info->BiosConnector[4].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_MONID); + break; +@@ -973,8 +976,8 @@ Bool RADEONGetClockInfoFromBIOS (ScrnInfoPtr pScrn) + + pll->xclk = RADEON_BIOS16(pll_info_block + 0x08); + +- info->sclk = RADEON_BIOS16(pll_info_block + 8) / 100.0; +- info->mclk = RADEON_BIOS16(pll_info_block + 10) / 100.0; ++ info->sclk = RADEON_BIOS16(pll_info_block + 10) / 100.0; ++ info->mclk = RADEON_BIOS16(pll_info_block + 8) / 100.0; + } + + if (info->sclk == 0) info->sclk = 200; +diff --git a/src/radeon_chipinfo_gen.h b/src/radeon_chipinfo_gen.h +index eb2df17..e36828c 100644 +--- a/src/radeon_chipinfo_gen.h ++++ b/src/radeon_chipinfo_gen.h +@@ -349,4 +349,11 @@ RADEONCardInfo RADEONCards[] = { + { 0x9612, CHIP_FAMILY_RS780, 0, 1, 0, 0, 1 }, + { 0x9613, CHIP_FAMILY_RS780, 0, 1, 0, 0, 1 }, + { 0x9614, CHIP_FAMILY_RS780, 0, 1, 0, 0, 1 }, ++ { 0x9615, CHIP_FAMILY_RS780, 0, 1, 0, 0, 1 }, ++ { 0x9616, CHIP_FAMILY_RS780, 0, 1, 0, 0, 1 }, ++ { 0x9710, CHIP_FAMILY_RS880, 0, 1, 0, 0, 1 }, ++ { 0x9711, CHIP_FAMILY_RS880, 0, 1, 0, 0, 1 }, ++ { 0x9712, CHIP_FAMILY_RS880, 1, 1, 0, 0, 1 }, ++ { 0x9713, CHIP_FAMILY_RS880, 1, 1, 0, 0, 1 }, ++ { 0x9714, CHIP_FAMILY_RS880, 0, 1, 0, 0, 1 }, + }; +diff --git a/src/radeon_chipset_gen.h b/src/radeon_chipset_gen.h +index 3c86ae6..caa497a 100644 +--- a/src/radeon_chipset_gen.h ++++ b/src/radeon_chipset_gen.h +@@ -349,5 +349,12 @@ static SymTabRec RADEONChipsets[] = { + { PCI_CHIP_RS780_9612, "ATI Radeon HD 3200 Graphics" }, + { PCI_CHIP_RS780_9613, "ATI Radeon 3100 Graphics" }, + { PCI_CHIP_RS780_9614, "ATI Radeon HD 3300 Graphics" }, ++ { PCI_CHIP_RS780_9615, "ATI Radeon HD 3200 Graphics" }, ++ { PCI_CHIP_RS780_9616, "ATI Radeon 3000 Graphics" }, ++ { PCI_CHIP_RS880_9710, "ATI Radeon HD Graphics" }, ++ { PCI_CHIP_RS880_9711, "ATI Radeon Graphics" }, ++ { PCI_CHIP_RS880_9712, "ATI Mobility Radeon HD Graphics" }, ++ { PCI_CHIP_RS880_9713, "ATI Mobility Radeon Graphics" }, ++ { PCI_CHIP_RS880_9714, "ATI Radeon Graphics" }, + { -1, NULL } + }; +diff --git a/src/radeon_driver.c b/src/radeon_driver.c +index 5a15c70..8673f5e 100644 +--- a/src/radeon_driver.c ++++ b/src/radeon_driver.c +@@ -668,7 +668,30 @@ void RADEONOUTMC(ScrnInfoPtr pScrn, int addr, uint32_t data) } + } - if (info->ChipFamily >= CHIP_FAMILY_R600) { -- while (buffer->used & 0x3c){ -- BEGIN_RING(1); -- OUT_RING(CP_PACKET2()); /* fill up to multiple of 16 dwords */ -- ADVANCE_RING(); -+ if (buffer->used & 0x3c) { -+ RING_LOCALS; -+ -+ while (buffer->used & 0x3c) { -+ BEGIN_RING(1); -+ OUT_RING(CP_PACKET2()); /* fill up to multiple of 16 dwords */ -+ ADVANCE_RING(); -+ } +-static Bool avivo_get_mc_idle(ScrnInfoPtr pScrn) ++/* Read PCIE register */ ++unsigned RADEONINPCIE(ScrnInfoPtr pScrn, int addr) ++{ ++ RADEONInfoPtr info = RADEONPTR(pScrn); ++ unsigned char *RADEONMMIO = info->MMIO; ++ CARD32 data; ++ ++ OUTREG(RADEON_PCIE_INDEX, addr & 0xff); ++ data = INREG(RADEON_PCIE_DATA); ++ ++ return data; ++} ++ ++/* Write PCIE register */ ++void RADEONOUTPCIE(ScrnInfoPtr pScrn, int addr, uint32_t data) ++{ ++ RADEONInfoPtr info = RADEONPTR(pScrn); ++ unsigned char *RADEONMMIO = info->MMIO; ++ ++ OUTREG(RADEON_PCIE_INDEX, ((addr) & 0xff)); ++ OUTREG(RADEON_PCIE_DATA, data); ++} ++ ++static Bool radeon_get_mc_idle(ScrnInfoPtr pScrn) + { + RADEONInfoPtr info = RADEONPTR(pScrn); + unsigned char *RADEONMMIO = info->MMIO; +@@ -694,11 +717,21 @@ static Bool avivo_get_mc_idle(ScrnInfoPtr pScrn) + return TRUE; + else + return FALSE; +- } else { ++ } else if (info->ChipFamily >= CHIP_FAMILY_R520) { + if (INMC(pScrn, R520_MC_STATUS) & R520_MC_STATUS_IDLE) + return TRUE; + else + return FALSE; ++ } else if (IS_R300_VARIANT) { ++ if (INREG(RADEON_MC_STATUS) & R300_MC_IDLE) ++ return TRUE; ++ else ++ return FALSE; ++ } else { ++ if (INREG(RADEON_MC_STATUS) & RADEON_MC_IDLE) ++ return TRUE; ++ else ++ return FALSE; + } + } + +@@ -1333,7 +1366,8 @@ static void RADEONInitMemoryMap(ScrnInfoPtr pScrn) + if ((info->ChipFamily != CHIP_FAMILY_RS600) && + (info->ChipFamily != CHIP_FAMILY_RS690) && + (info->ChipFamily != CHIP_FAMILY_RS740) && +- (info->ChipFamily != CHIP_FAMILY_RS780)) { ++ (info->ChipFamily != CHIP_FAMILY_RS780) && ++ (info->ChipFamily != CHIP_FAMILY_RS880)) { + if (info->IsIGP) + info->mc_fb_location = INREG(RADEON_NB_TOM); + else +@@ -2204,6 +2238,8 @@ static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn) } } -@@ -735,12 +737,11 @@ void RADEONCPReleaseIndirect(ScrnInfoPtr pScrn) - drmBufPtr buffer = info->cp->indirectBuffer; - int start = info->cp->indirectStart; - drm_radeon_indirect_t indirect; -- RING_LOCALS; -- RADEONCP_REFRESH(pScrn, info); ++ if (info->ChipFamily == CHIP_FAMILY_RS880) ++ return FALSE; + + if (!xf86ReturnOptValBool(info->Options, OPTION_DRI, TRUE)) { + xf86DrvMsg(pScrn->scrnIndex, X_INFO, +@@ -3818,7 +3854,7 @@ void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn, + + usleep(10000); + timeout = 0; +- while (!(avivo_get_mc_idle(pScrn))) { ++ while (!(radeon_get_mc_idle(pScrn))) { + if (++timeout > 1000000) { + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, + "Timeout trying to update memory controller settings !\n"); +@@ -3858,7 +3894,7 @@ void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn, + if (mc_fb_loc != restore->mc_fb_location || + mc_agp_loc != restore->mc_agp_location) { + uint32_t crtc_ext_cntl, crtc_gen_cntl, crtc2_gen_cntl=0, ov0_scale_cntl; +- uint32_t old_mc_status, status_idle; ++ uint32_t old_mc_status; + + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + " Map Changed ! Applying ...\n"); +@@ -3897,15 +3933,8 @@ void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn, + + /* Make sure the chip settles down (paranoid !) */ + usleep(100000); +- +- /* Wait for MC idle */ +- if (IS_R300_VARIANT) +- status_idle = R300_MC_IDLE; +- else +- status_idle = RADEON_MC_IDLE; +- + timeout = 0; +- while (!(INREG(RADEON_MC_STATUS) & status_idle)) { ++ while (!(radeon_get_mc_idle(pScrn))) { + if (++timeout > 1000000) { + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, + "Timeout trying to update memory controller settings !\n"); +diff --git a/src/radeon_macros.h b/src/radeon_macros.h +index 387e5f5..b7056b0 100644 +--- a/src/radeon_macros.h ++++ b/src/radeon_macros.h +@@ -152,7 +152,9 @@ do { \ + } while (0) + + #define INMC(pScrn, addr) RADEONINMC(pScrn, addr) - + #define OUTMC(pScrn, addr, val) RADEONOUTMC(pScrn, addr, val) - if (info->ChipFamily >= CHIP_FAMILY_R600) { -- if (buffer) { -+ if (buffer && (buffer->used & 0x3c)) { -+ RING_LOCALS; ++#define INPCIE(pScrn, addr) RADEONINPCIE(pScrn, addr) ++#define OUTPCIE(pScrn, addr, val) RADEONOUTPCIE(pScrn, addr, val + - while (buffer->used & 0x3c) { - BEGIN_RING(1); - OUT_RING(CP_PACKET2()); /* fill up to multiple of 16 dwords */ + #endif diff --git a/src/radeon_output.c b/src/radeon_output.c -index aab88fb..3931db4 100644 +index 3931db4..719f9e8 100644 --- a/src/radeon_output.c +++ b/src/radeon_output.c -@@ -631,93 +631,60 @@ radeon_bios_output_dpms(xf86OutputPtr output, int mode) - - if (info->IsAtomBios) { - if (radeon_output->active_device & ATOM_DEVICE_TV1_SUPPORT) { -- if (mode == DPMSModeOn) { -+ if (mode == DPMSModeOn) - save->bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE; -- save->bios_3_scratch |= ATOM_S3_TV1_ACTIVE; -- } else { -+ else - save->bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE; -- save->bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE; -- } - } else if (radeon_output->active_device & ATOM_DEVICE_CV_SUPPORT) { -- if (mode == DPMSModeOn) { -+ if (mode == DPMSModeOn) - save->bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE; -- save->bios_3_scratch |= ATOM_S3_CV_ACTIVE; -- } else { -+ else - save->bios_2_scratch |= ATOM_S2_CV_DPMS_STATE; -- save->bios_3_scratch &= ~ATOM_S3_CV_ACTIVE; -- } - } else if (radeon_output->active_device & ATOM_DEVICE_CRT1_SUPPORT) { -- if (mode == DPMSModeOn) { -+ if (mode == DPMSModeOn) - save->bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE; -- save->bios_3_scratch |= ATOM_S3_CRT1_ACTIVE; -- } else { -+ else - save->bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE; -- save->bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE; -- } - } else if (radeon_output->active_device & ATOM_DEVICE_CRT2_SUPPORT) { -- if (mode == DPMSModeOn) { -+ if (mode == DPMSModeOn) - save->bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE; -- save->bios_3_scratch |= ATOM_S3_CRT2_ACTIVE; -- } else { -+ else - save->bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE; -- save->bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE; -- } - } else if (radeon_output->active_device & ATOM_DEVICE_LCD1_SUPPORT) { -- if (mode == DPMSModeOn) { -+ if (mode == DPMSModeOn) - save->bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE; -- save->bios_3_scratch |= ATOM_S3_LCD1_ACTIVE; -- } else { -+ else - save->bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE; -- save->bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE; -- } - } else if (radeon_output->active_device & ATOM_DEVICE_DFP1_SUPPORT) { -- if (mode == DPMSModeOn) { -+ if (mode == DPMSModeOn) - save->bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE; -- save->bios_3_scratch |= ATOM_S3_DFP1_ACTIVE; -- } else { -+ else - save->bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE; -- save->bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE; -- } - } else if (radeon_output->active_device & ATOM_DEVICE_DFP2_SUPPORT) { -- if (mode == DPMSModeOn) { -+ if (mode == DPMSModeOn) - save->bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE; -- save->bios_3_scratch |= ATOM_S3_DFP2_ACTIVE; -- } else { -+ else - save->bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE; -- save->bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE; -- } - } else if (radeon_output->active_device & ATOM_DEVICE_DFP3_SUPPORT) { -- if (mode == DPMSModeOn) { -+ if (mode == DPMSModeOn) - save->bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE; -- save->bios_3_scratch |= ATOM_S3_DFP3_ACTIVE; -- } else { -+ else - save->bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE; -- save->bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE; -- } - } else if (radeon_output->active_device & ATOM_DEVICE_DFP4_SUPPORT) { -- if (mode == DPMSModeOn) { -+ if (mode == DPMSModeOn) - save->bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE; -- save->bios_3_scratch |= ATOM_S3_DFP4_ACTIVE; -- } else { -+ else - save->bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE; -- save->bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE; -- } - } else if (radeon_output->active_device & ATOM_DEVICE_DFP5_SUPPORT) { -- if (mode == DPMSModeOn) { -+ if (mode == DPMSModeOn) - save->bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE; -- save->bios_3_scratch |= ATOM_S3_DFP5_ACTIVE; -- } else { -+ else - save->bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE; -- save->bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE; -- } +@@ -1263,10 +1263,21 @@ radeon_create_resources(xf86OutputPtr output) + "RRConfigureOutputProperty error, %d\n", err); } -- if (info->ChipFamily >= CHIP_FAMILY_R600) { -+ if (info->ChipFamily >= CHIP_FAMILY_R600) - OUTREG(R600_BIOS_2_SCRATCH, save->bios_2_scratch); -- OUTREG(R600_BIOS_3_SCRATCH, save->bios_3_scratch); -- } else { -+ else - OUTREG(RADEON_BIOS_2_SCRATCH, save->bios_2_scratch); -- OUTREG(RADEON_BIOS_3_SCRATCH, save->bios_3_scratch); -- } - } else { - if (mode == DPMSModeOn) { - save->bios_6_scratch &= ~(RADEON_DPMS_MASK | RADEON_SCREEN_BLANKING); -@@ -727,55 +694,36 @@ radeon_bios_output_dpms(xf86OutputPtr output, int mode) - save->bios_6_scratch |= (RADEON_DPMS_OFF | RADEON_SCREEN_BLANKING); - } - if (radeon_output->active_device & ATOM_DEVICE_TV1_SUPPORT) { -- if (mode == DPMSModeOn) { -- save->bios_5_scratch |= RADEON_TV1_ON; -+ if (mode == DPMSModeOn) - save->bios_6_scratch |= RADEON_TV_DPMS_ON; -- } else { -- save->bios_5_scratch &= ~RADEON_TV1_ON; -+ else - save->bios_6_scratch &= ~RADEON_TV_DPMS_ON; -- } - } else if (radeon_output->active_device & ATOM_DEVICE_CRT1_SUPPORT) { -- if (mode == DPMSModeOn) { -- save->bios_5_scratch |= RADEON_CRT1_ON; -+ if (mode == DPMSModeOn) - save->bios_6_scratch |= RADEON_CRT_DPMS_ON; -- } else { -- save->bios_5_scratch &= ~RADEON_CRT1_ON; -+ else - save->bios_6_scratch &= ~RADEON_CRT_DPMS_ON; -- } - } else if (radeon_output->active_device & ATOM_DEVICE_CRT2_SUPPORT) { -- if (mode == DPMSModeOn) { -- save->bios_5_scratch |= RADEON_CRT2_ON; -+ if (mode == DPMSModeOn) - save->bios_6_scratch |= RADEON_CRT_DPMS_ON; -- } else { -- save->bios_5_scratch &= ~RADEON_CRT2_ON; -+ else - save->bios_6_scratch &= ~RADEON_CRT_DPMS_ON; -- } - } else if (radeon_output->active_device & ATOM_DEVICE_LCD1_SUPPORT) { -- if (mode == DPMSModeOn) { -- save->bios_5_scratch |= RADEON_LCD1_ON; -+ if (mode == DPMSModeOn) - save->bios_6_scratch |= RADEON_LCD_DPMS_ON; -- } else { -- save->bios_5_scratch &= ~RADEON_LCD1_ON; -+ else - save->bios_6_scratch &= ~RADEON_LCD_DPMS_ON; -- } - } else if (radeon_output->active_device & ATOM_DEVICE_DFP1_SUPPORT) { -- if (mode == DPMSModeOn) { -- save->bios_5_scratch |= RADEON_DFP1_ON; -+ if (mode == DPMSModeOn) - save->bios_6_scratch |= RADEON_DFP_DPMS_ON; -- } else { -- save->bios_5_scratch &= ~RADEON_DFP1_ON; -+ else - save->bios_6_scratch &= ~RADEON_DFP_DPMS_ON; -- } - } else if (radeon_output->active_device & ATOM_DEVICE_DFP2_SUPPORT) { -- if (mode == DPMSModeOn) { -- save->bios_5_scratch |= RADEON_DFP2_ON; -+ if (mode == DPMSModeOn) - save->bios_6_scratch |= RADEON_DFP_DPMS_ON; -- } else { -- save->bios_5_scratch &= ~RADEON_DFP2_ON; -+ else - save->bios_6_scratch &= ~RADEON_DFP_DPMS_ON; -- } - } -- OUTREG(RADEON_BIOS_5_SCRATCH, save->bios_5_scratch); - OUTREG(RADEON_BIOS_6_SCRATCH, save->bios_6_scratch); - } + /* Set the current value of the property */ +- if (radeon_output->devices & (ATOM_DEVICE_LCD_SUPPORT)) +- s = "full"; +- else ++ switch (radeon_output->rmx_type) { ++ case RMX_OFF: ++ default: + s = "off"; ++ break; ++ case RMX_FULL: ++ s = "full"; ++ break; ++ case RMX_CENTER: ++ s = "center"; ++ break; ++ case RMX_ASPECT: ++ s = "aspect"; ++ break; ++ } + err = RRChangeOutputProperty(output->randr_output, rmx_atom, + XA_STRING, 8, PropModeReplace, strlen(s), (pointer)s, + FALSE, FALSE); +@@ -1884,6 +1895,10 @@ void RADEONInitConnector(xf86OutputPtr output) + else + radeon_output->rmx_type = RMX_OFF; + ++ /* dce 3.2 chips have problems with low dot clocks, so use the scaler */ ++ if (IS_DCE32_VARIANT && (radeon_output->devices & (ATOM_DEVICE_DFP_SUPPORT))) ++ radeon_output->rmx_type = RMX_FULL; ++ + if (!IS_AVIVO_VARIANT) { + if (radeon_output->devices & (ATOM_DEVICE_CRT2_SUPPORT)) { + if (xf86ReturnOptValBool(info->Options, OPTION_TVDAC_LOAD_DETECT, FALSE)) +@@ -2067,12 +2082,12 @@ static Bool RADEONSetupAppleConnectors(ScrnInfoPtr pScrn) + info->BiosConnector[0].load_detection = FALSE; + info->BiosConnector[0].ConnectorType = CONNECTOR_DVI_I; + info->BiosConnector[0].valid = TRUE; +- info->BiosConnector[0].devices = ATOM_DEVICE_CRT1_SUPPORT | ATOM_DEVICE_DFP2_SUPPORT; ++ info->BiosConnector[0].devices = ATOM_DEVICE_CRT2_SUPPORT | ATOM_DEVICE_DFP2_SUPPORT; + if (!radeon_add_encoder(pScrn, + radeon_get_encoder_id_from_supported_device(pScrn, +- ATOM_DEVICE_CRT1_SUPPORT, +- 1), +- ATOM_DEVICE_CRT1_SUPPORT)) ++ ATOM_DEVICE_CRT2_SUPPORT, ++ 2), ++ ATOM_DEVICE_CRT2_SUPPORT)) + return FALSE; + if (!radeon_add_encoder(pScrn, + radeon_get_encoder_id_from_supported_device(pScrn, +@@ -2098,12 +2113,12 @@ static Bool RADEONSetupAppleConnectors(ScrnInfoPtr pScrn) + info->BiosConnector[0].load_detection = FALSE; + info->BiosConnector[0].ConnectorType = CONNECTOR_DVI_I; + info->BiosConnector[0].valid = TRUE; +- info->BiosConnector[0].devices = ATOM_DEVICE_CRT1_SUPPORT | ATOM_DEVICE_DFP1_SUPPORT; ++ info->BiosConnector[0].devices = ATOM_DEVICE_CRT2_SUPPORT | ATOM_DEVICE_DFP1_SUPPORT; + if (!radeon_add_encoder(pScrn, + radeon_get_encoder_id_from_supported_device(pScrn, +- ATOM_DEVICE_CRT1_SUPPORT, +- 1), +- ATOM_DEVICE_CRT1_SUPPORT)) ++ ATOM_DEVICE_CRT2_SUPPORT, ++ 2), ++ ATOM_DEVICE_CRT2_SUPPORT)) + return FALSE; + if (!radeon_add_encoder(pScrn, + radeon_get_encoder_id_from_supported_device(pScrn, +diff --git a/src/radeon_pci_chipset_gen.h b/src/radeon_pci_chipset_gen.h +index 31b032a..b9368d7 100644 +--- a/src/radeon_pci_chipset_gen.h ++++ b/src/radeon_pci_chipset_gen.h +@@ -349,5 +349,12 @@ PciChipsets RADEONPciChipsets[] = { + { PCI_CHIP_RS780_9612, PCI_CHIP_RS780_9612, RES_SHARED_VGA }, + { PCI_CHIP_RS780_9613, PCI_CHIP_RS780_9613, RES_SHARED_VGA }, + { PCI_CHIP_RS780_9614, PCI_CHIP_RS780_9614, RES_SHARED_VGA }, ++ { PCI_CHIP_RS780_9615, PCI_CHIP_RS780_9615, RES_SHARED_VGA }, ++ { PCI_CHIP_RS780_9616, PCI_CHIP_RS780_9616, RES_SHARED_VGA }, ++ { PCI_CHIP_RS880_9710, PCI_CHIP_RS880_9710, RES_SHARED_VGA }, ++ { PCI_CHIP_RS880_9711, PCI_CHIP_RS880_9711, RES_SHARED_VGA }, ++ { PCI_CHIP_RS880_9712, PCI_CHIP_RS880_9712, RES_SHARED_VGA }, ++ { PCI_CHIP_RS880_9713, PCI_CHIP_RS880_9713, RES_SHARED_VGA }, ++ { PCI_CHIP_RS880_9714, PCI_CHIP_RS880_9714, RES_SHARED_VGA }, + { -1, -1, RES_UNDEFINED } + }; +diff --git a/src/radeon_pci_device_match_gen.h b/src/radeon_pci_device_match_gen.h +index b310ce8..3923371 100644 +--- a/src/radeon_pci_device_match_gen.h ++++ b/src/radeon_pci_device_match_gen.h +@@ -349,5 +349,12 @@ static const struct pci_id_match radeon_device_match[] = { + ATI_DEVICE_MATCH( PCI_CHIP_RS780_9612, 0 ), + ATI_DEVICE_MATCH( PCI_CHIP_RS780_9613, 0 ), + ATI_DEVICE_MATCH( PCI_CHIP_RS780_9614, 0 ), ++ ATI_DEVICE_MATCH( PCI_CHIP_RS780_9615, 0 ), ++ ATI_DEVICE_MATCH( PCI_CHIP_RS780_9616, 0 ), ++ ATI_DEVICE_MATCH( PCI_CHIP_RS880_9710, 0 ), ++ ATI_DEVICE_MATCH( PCI_CHIP_RS880_9711, 0 ), ++ ATI_DEVICE_MATCH( PCI_CHIP_RS880_9712, 0 ), ++ ATI_DEVICE_MATCH( PCI_CHIP_RS880_9713, 0 ), ++ ATI_DEVICE_MATCH( PCI_CHIP_RS880_9714, 0 ), + { 0, 0, 0 } + }; +diff --git a/src/radeon_reg.h b/src/radeon_reg.h +index 0af8859..a130794 100644 +--- a/src/radeon_reg.h ++++ b/src/radeon_reg.h +@@ -274,6 +274,9 @@ + #define RADEON_BUS_CNTL1 0x0034 + # define RADEON_BUS_WAIT_ON_LOCK_EN (1 << 4) + ++#define RADEON_PCIE_INDEX 0x0030 ++#define RADEON_PCIE_DATA 0x0034 ++ + #define RADEON_CACHE_CNTL 0x1724 + #define RADEON_CACHE_LINE 0x0f0c /* PCI */ + #define RADEON_CAPABILITIES_ID 0x0f50 /* PCI */ +@@ -3027,6 +3030,18 @@ + # define R200_TXA_REPL_ARG_B_MASK (3 << 28) + # define R200_TXA_REPL_ARG_C_SHIFT 30 + # define R200_TXA_REPL_ARG_C_MASK (3 << 30) ++#define R200_PP_TXCBLEND_1 0x2f10 ++#define R200_PP_TXCBLEND2_1 0x2f14 ++#define R200_PP_TXABLEND_1 0x2f18 ++#define R200_PP_TXABLEND2_1 0x2f1c ++#define R200_PP_TXCBLEND_2 0x2f20 ++#define R200_PP_TXCBLEND2_2 0x2f24 ++#define R200_PP_TXABLEND_2 0x2f28 ++#define R200_PP_TXABLEND2_2 0x2f2c ++#define R200_PP_TXCBLEND_3 0x2f30 ++#define R200_PP_TXCBLEND2_3 0x2f34 ++#define R200_PP_TXABLEND_3 0x2f38 ++#define R200_PP_TXABLEND2_3 0x2f3c + + #define R200_SE_VTX_FMT_0 0x2088 + # define R200_VTX_XY 0 /* always have xy */ +@@ -3291,7 +3306,9 @@ + # define RADEON_RGB_CONVERT_BY_PASS (1 << 10) + # define RADEON_UVRAM_READ_MARGIN_SHIFT 16 + # define RADEON_FIFORAM_FFMACRO_READ_MARGIN_SHIFT 20 ++# define RADEON_RGB_ATTEN_SEL(x) ((x) << 24) + # define RADEON_TVOUT_SCALE_EN (1 << 26) ++# define RADEON_RGB_ATTEN_VAL(x) ((x) << 28) + #define RADEON_TV_SYNC_CNTL 0x0808 + # define RADEON_SYNC_OE (1 << 0) + # define RADEON_SYNC_OUT (1 << 1) +@@ -4406,6 +4423,7 @@ + #define R300_TX_INVALTAGS 0x4100 + #define R300_TX_FILTER0_0 0x4400 + #define R300_TX_FILTER0_1 0x4404 ++#define R300_TX_FILTER0_2 0x4408 + # define R300_TX_CLAMP_S(x) ((x) << 0) + # define R300_TX_CLAMP_T(x) ((x) << 3) + # define R300_TX_CLAMP_R(x) ((x) << 6) +@@ -4424,8 +4442,10 @@ + # define R300_TX_ID_SHIFT 28 + #define R300_TX_FILTER1_0 0x4440 + #define R300_TX_FILTER1_1 0x4444 ++#define R300_TX_FILTER1_2 0x4448 + #define R300_TX_FORMAT0_0 0x4480 + #define R300_TX_FORMAT0_1 0x4484 ++#define R300_TX_FORMAT0_2 0x4488 + # define R300_TXWIDTH_SHIFT 0 + # define R300_TXHEIGHT_SHIFT 11 + # define R300_NUM_LEVELS_SHIFT 26 +@@ -4434,6 +4454,7 @@ + # define R300_TXPITCH_EN (1 << 31) + #define R300_TX_FORMAT1_0 0x44c0 + #define R300_TX_FORMAT1_1 0x44c4 ++#define R300_TX_FORMAT1_2 0x44c8 + # define R300_TX_FORMAT_X8 0x0 + # define R300_TX_FORMAT_X16 0x1 + # define R300_TX_FORMAT_Y4X4 0x2 +@@ -4506,13 +4527,23 @@ + # define R300_TX_FORMAT_YUV_TO_RGB_NO_CLAMP (2 << 22) + # define R300_TX_FORMAT_SWAP_YUV (1 << 24) + ++# define R300_TX_FORMAT_CACHE_WHOLE (0 << 27) ++# define R300_TX_FORMAT_CACHE_HALF_REGION_0 (2 << 27) ++# define R300_TX_FORMAT_CACHE_HALF_REGION_1 (3 << 27) ++# define R300_TX_FORMAT_CACHE_FOURTH_REGION_0 (4 << 27) ++# define R300_TX_FORMAT_CACHE_FOURTH_REGION_1 (5 << 27) ++# define R300_TX_FORMAT_CACHE_FOURTH_REGION_2 (6 << 27) ++# define R300_TX_FORMAT_CACHE_FOURTH_REGION_3 (7 << 27) ++ + #define R300_TX_FORMAT2_0 0x4500 + #define R300_TX_FORMAT2_1 0x4504 ++#define R300_TX_FORMAT2_2 0x4508 + # define R500_TXWIDTH_11 (1 << 15) + # define R500_TXHEIGHT_11 (1 << 16) + + #define R300_TX_OFFSET_0 0x4540 + #define R300_TX_OFFSET_1 0x4544 ++#define R300_TX_OFFSET_2 0x4548 + # define R300_ENDIAN_SWAP_16_BIT (1 << 0) + # define R300_ENDIAN_SWAP_32_BIT (2 << 0) + # define R300_ENDIAN_SWAP_HALF_DWORD (3 << 0) +@@ -4523,6 +4554,7 @@ + #define R300_TX_ENABLE 0x4104 + # define R300_TEX_0_ENABLE (1 << 0) + # define R300_TEX_1_ENABLE (1 << 1) ++# define R300_TEX_2_ENABLE (1 << 2) + + #define R300_US_W_FMT 0x46b4 + #define R300_US_OUT_FMT_1 0x46a8 +diff --git a/src/radeon_textured_video.c b/src/radeon_textured_video.c +index 2df299f..79671c0 100644 +--- a/src/radeon_textured_video.c ++++ b/src/radeon_textured_video.c +@@ -119,6 +119,15 @@ static __inline__ uint32_t F_TO_24(float val) + return float24; } -@@ -796,25 +744,25 @@ radeon_bios_output_crtc(xf86OutputPtr output) - save->bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE; - save->bios_3_scratch |= (radeon_crtc->crtc_id << 18); - } else if (radeon_output->active_device & ATOM_DEVICE_CV_SUPPORT) { -- save->bios_2_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE; -+ save->bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE; - save->bios_3_scratch |= (radeon_crtc->crtc_id << 24); - } else if (radeon_output->active_device & ATOM_DEVICE_CRT1_SUPPORT) { -- save->bios_2_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE; -+ save->bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE; - save->bios_3_scratch |= (radeon_crtc->crtc_id << 16); - } else if (radeon_output->active_device & ATOM_DEVICE_CRT2_SUPPORT) { -- save->bios_2_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE; -+ save->bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE; - save->bios_3_scratch |= (radeon_crtc->crtc_id << 20); - } else if (radeon_output->active_device & ATOM_DEVICE_LCD1_SUPPORT) { -- save->bios_2_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE; -+ save->bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE; - save->bios_3_scratch |= (radeon_crtc->crtc_id << 17); - } else if (radeon_output->active_device & ATOM_DEVICE_DFP1_SUPPORT) { -- save->bios_2_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE; -+ save->bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE; - save->bios_3_scratch |= (radeon_crtc->crtc_id << 19); - } else if (radeon_output->active_device & ATOM_DEVICE_DFP2_SUPPORT) { -- save->bios_2_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE; -+ save->bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE; - save->bios_3_scratch |= (radeon_crtc->crtc_id << 23); - } else if (radeon_output->active_device & ATOM_DEVICE_DFP3_SUPPORT) { -- save->bios_2_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE; -+ save->bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE; - save->bios_3_scratch |= (radeon_crtc->crtc_id << 25); - } - if (info->ChipFamily >= CHIP_FAMILY_R600) -@@ -857,66 +805,101 @@ radeon_bios_output_connected(xf86OutputPtr output, Bool connected) - if (info->IsAtomBios) { - switch (radeon_output->active_device) { - case ATOM_DEVICE_TV1_SUPPORT: -- if (!connected) -+ if (connected) -+ save->bios_3_scratch |= ATOM_S3_TV1_ACTIVE; -+ else { - save->bios_0_scratch &= ~ATOM_S0_TV1_MASK; -+ save->bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE; -+ } - break; - case ATOM_DEVICE_CV_SUPPORT: -- if (!connected) -+ if (connected) -+ save->bios_3_scratch |= ATOM_S3_CV_ACTIVE; -+ else { - save->bios_0_scratch &= ~ATOM_S0_CV_MASK; -+ save->bios_3_scratch &= ~ATOM_S3_CV_ACTIVE; -+ } - break; - case ATOM_DEVICE_LCD1_SUPPORT: -- if (connected) -+ if (connected) { - save->bios_0_scratch |= ATOM_S0_LCD1; -- else -+ save->bios_3_scratch |= ATOM_S3_LCD1_ACTIVE; -+ } else { - save->bios_0_scratch &= ~ATOM_S0_LCD1; -+ save->bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE; -+ } - break; - case ATOM_DEVICE_CRT1_SUPPORT: -- if (connected) -+ if (connected) { - save->bios_0_scratch |= ATOM_S0_CRT1_COLOR; -- else -+ save->bios_3_scratch |= ATOM_S3_CRT1_ACTIVE; -+ } else { - save->bios_0_scratch &= ~ATOM_S0_CRT1_MASK; -+ save->bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE; -+ } - break; - case ATOM_DEVICE_CRT2_SUPPORT: -- if (connected) -+ if (connected) { - save->bios_0_scratch |= ATOM_S0_CRT2_COLOR; -- else -+ save->bios_3_scratch |= ATOM_S3_CRT2_ACTIVE; -+ } else { - save->bios_0_scratch &= ~ATOM_S0_CRT2_MASK; -+ save->bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE; -+ } - break; - case ATOM_DEVICE_DFP1_SUPPORT: -- if (connected) -+ if (connected) { - save->bios_0_scratch |= ATOM_S0_DFP1; -- else -+ save->bios_3_scratch |= ATOM_S3_DFP1_ACTIVE; -+ } else { - save->bios_0_scratch &= ~ATOM_S0_DFP1; -+ save->bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE; -+ } - break; - case ATOM_DEVICE_DFP2_SUPPORT: -- if (connected) -+ if (connected) { - save->bios_0_scratch |= ATOM_S0_DFP2; -- else -+ save->bios_3_scratch |= ATOM_S3_DFP2_ACTIVE; -+ } else { - save->bios_0_scratch &= ~ATOM_S0_DFP2; -+ save->bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE; -+ } - break; - case ATOM_DEVICE_DFP3_SUPPORT: -- if (connected) -+ if (connected) { - save->bios_0_scratch |= ATOM_S0_DFP3; -- else -+ save->bios_3_scratch |= ATOM_S3_DFP3_ACTIVE; -+ } else { - save->bios_0_scratch &= ~ATOM_S0_DFP3; -+ save->bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE; -+ } - break; - case ATOM_DEVICE_DFP4_SUPPORT: -- if (connected) -+ if (connected) { - save->bios_0_scratch |= ATOM_S0_DFP4; -- else -+ save->bios_3_scratch |= ATOM_S3_DFP4_ACTIVE; -+ } else { - save->bios_0_scratch &= ~ATOM_S0_DFP4; -+ save->bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE; -+ } - break; - case ATOM_DEVICE_DFP5_SUPPORT: -- if (connected) -+ if (connected) { - save->bios_0_scratch |= ATOM_S0_DFP5; -- else -+ save->bios_3_scratch |= ATOM_S3_DFP5_ACTIVE; -+ } else { - save->bios_0_scratch &= ~ATOM_S0_DFP5; -+ save->bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE; + ++static __inline__ uint32_t float4touint(float fr, float fg, float fb, float fa) ++{ ++ unsigned ur = fr * 255.0 + 0.5; ++ unsigned ug = fg * 255.0 + 0.5; ++ unsigned ub = fb * 255.0 + 0.5; ++ unsigned ua = fa * 255.0 + 0.5; ++ return (ua << 24) | (ur << 16) | (ug << 8) | ub; ++} ++ + #define ACCEL_MMIO + #define ACCEL_PREAMBLE() unsigned char *RADEONMMIO = info->MMIO + #define BEGIN_ACCEL(n) RADEONWaitForFifo(pScrn, (n)) +@@ -304,8 +313,9 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn, + RADEONInfoPtr info = RADEONPTR(pScrn); + RADEONPortPrivPtr pPriv = (RADEONPortPrivPtr)data; + INT32 x1, x2, y1, y2; +- int srcPitch, srcPitch2, dstPitch; ++ int srcPitch, srcPitch2, dstPitch, dstPitch2 = 0; + int s2offset, s3offset, tmp; ++ int d2line, d3line; + int top, left, npixels, nlines, size; + BoxRec dstBox; + int dst_width = width, dst_height = height; +@@ -327,36 +337,64 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn, + if (!xf86XVClipVideoHelper(&dstBox, &x1, &x2, &y1, &y2, clipBoxes, width, height)) + return Success; + +- src_w = (x2 - x1) >> 16; ++/* src_w = (x2 - x1) >> 16; + src_h = (y2 - y1) >> 16; + drw_w = dstBox.x2 - dstBox.x1; +- drw_h = dstBox.y2 - dstBox.y1; ++ drw_h = dstBox.y2 - dstBox.y1;*/ + + if ((x1 >= x2) || (y1 >= y2)) + return Success; + ++ /* Bicubic filter setup */ ++ pPriv->bicubic_enabled = (pPriv->bicubic_state != BICUBIC_OFF); ++ if (!(IS_R300_3D || IS_R500_3D || IS_R600_3D)) ++ pPriv->bicubic_enabled = FALSE; ++ if (pPriv->bicubic_enabled && (pPriv->bicubic_state == BICUBIC_AUTO)) { ++ /* ++ * Applying the bicubic filter with a scale of less than 200% ++ * results in a blurred picture, so disable the filter. ++ */ ++ if ((src_w > drw_w / 2) || (src_h > drw_h / 2)) ++ pPriv->bicubic_enabled = FALSE; ++ } ++ ++ pPriv->planar_hw = pPriv->planar_state; ++ if (pPriv->bicubic_enabled || !( IS_R300_3D || ++ (info->ChipFamily == CHIP_FAMILY_RV250) || ++ (info->ChipFamily == CHIP_FAMILY_RV280) || ++ (info->ChipFamily == CHIP_FAMILY_RS300) || ++ (info->ChipFamily == CHIP_FAMILY_R200) )) ++ pPriv->planar_hw = 0; ++ + switch(id) { + case FOURCC_YV12: + case FOURCC_I420: +- dstPitch = ((dst_width << 1) + 15) & ~15; + srcPitch = (width + 3) & ~3; + srcPitch2 = ((width >> 1) + 3) & ~3; +- size = dstPitch * dst_height; ++ if (pPriv->planar_hw) { ++ dstPitch = (dst_width + 15) & ~15; ++ dstPitch = (dstPitch + 63) & ~63; ++ dstPitch2 = ((dst_width >> 1) + 15) & ~15; ++ dstPitch2 = (dstPitch2 + 63) & ~63; ++ } else { ++ dstPitch = ((dst_width << 1) + 15) & ~15; ++ dstPitch = (dstPitch + 63) & ~63; ++ } + break; + case FOURCC_UYVY: + case FOURCC_YUY2: + default: + dstPitch = ((dst_width << 1) + 15) & ~15; ++ dstPitch = (dstPitch + 63) & ~63; + srcPitch = (width << 1); + srcPitch2 = 0; +- size = dstPitch * dst_height; + break; + } + + if (info->ChipFamily >= CHIP_FAMILY_R600) + dstPitch = (dstPitch + 255) & ~255; +- else +- dstPitch = (dstPitch + 63) & ~63; ++ ++ size = dstPitch * dst_height + 2 * dstPitch2 * ((dst_height + 1) >> 1); + + if (pPriv->video_memory != NULL && size != pPriv->size) { + radeon_legacy_free_memory(pScrn, pPriv->video_memory); +@@ -376,19 +414,6 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn, + return BadAlloc; + } + +- /* Bicubic filter setup */ +- pPriv->bicubic_enabled = (pPriv->bicubic_state != BICUBIC_OFF); +- if (!(IS_R300_3D || IS_R500_3D || IS_R600_3D)) +- pPriv->bicubic_enabled = FALSE; +- if (pPriv->bicubic_enabled && (pPriv->bicubic_state == BICUBIC_AUTO)) { +- /* +- * Applying the bicubic filter with a scale of less than 200% +- * results in a blurred picture, so disable the filter. +- */ +- if ((src_w > drw_w / 2) || (src_h > drw_h / 2)) +- pPriv->bicubic_enabled = FALSE; +- } +- + /* Bicubic filter loading */ + if (pPriv->bicubic_memory == NULL && pPriv->bicubic_enabled) { + pPriv->bicubic_offset = radeon_legacy_allocate_memory(pScrn, +@@ -432,10 +457,16 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn, + else + pPriv->src_addr = (uint8_t *)(info->FB + pPriv->video_offset + (top * dstPitch)); + pPriv->src_pitch = dstPitch; ++ pPriv->planeu_offset = dstPitch * dst_height; ++ pPriv->planev_offset = pPriv->planeu_offset + dstPitch2 * ((dst_height + 1) >> 1); + pPriv->size = size; + pPriv->pDraw = pDraw; + ++ + #if 0 ++ ErrorF("planeu_offset: 0x%x\n", pPriv->planeu_offset); ++ ErrorF("planev_offset: 0x%x\n", pPriv->planev_offset); ++ ErrorF("dstPitch2: 0x%x\n", dstPitch2); + ErrorF("src_offset: 0x%x\n", pPriv->src_offset); + ErrorF("src_addr: 0x%x\n", pPriv->src_addr); + ErrorF("src_pitch: 0x%x\n", pPriv->src_pitch); +@@ -470,12 +501,34 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn, + srcPitch, srcPitch2, pPriv->src_pitch, + width, height); + } ++ } ++ else if (pPriv->planar_hw) { ++ top &= ~1; ++ s2offset = srcPitch * ((height + 1) & ~1); ++ s3offset = s2offset + srcPitch2 * ((height + 1) >> 1); ++ s2offset += (top >> 1) * srcPitch2 + (left >> 1); ++ s3offset += (top >> 1) * srcPitch2 + (left >> 1); ++ d2line = pPriv->planeu_offset; ++ d3line = pPriv->planev_offset; ++ d2line += (top >> 1) * dstPitch2 - (top * dstPitch); ++ d3line += (top >> 1) * dstPitch2 - (top * dstPitch); ++ nlines = ((y2 + 0xffff) >> 16) - top; ++ if(id == FOURCC_YV12) { ++ tmp = s2offset; ++ s2offset = s3offset; ++ s3offset = tmp; + } - break; ++ RADEONCopyData(pScrn, buf + (top * srcPitch) + left, pPriv->src_addr + left, ++ srcPitch, dstPitch, nlines, npixels, 1); ++ RADEONCopyData(pScrn, buf + s2offset, pPriv->src_addr + d2line + (left >> 1), ++ srcPitch2, dstPitch2, (nlines + 1) >> 1, npixels >> 1, 1); ++ RADEONCopyData(pScrn, buf + s3offset, pPriv->src_addr + d3line + (left >> 1), ++ srcPitch2, dstPitch2, (nlines + 1) >> 1, npixels >> 1, 1); + } else { + top &= ~1; + nlines = ((((y2 + 0xffff) >> 16) + 1) & ~1) - top; + s2offset = srcPitch * height; + s3offset = (srcPitch2 * (height >> 1)) + s2offset; +- top &= ~1; + pPriv->src_addr += left << 1; + tmp = ((top >> 1) * srcPitch2) + (left >> 1); + s2offset += tmp; +@@ -504,7 +557,9 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn, + width, height); + } else { + nlines = ((y2 + 0xffff) >> 16) - top; +- RADEONCopyData(pScrn, buf, pPriv->src_addr, srcPitch, dstPitch, nlines, npixels, 2); ++ pPriv->src_addr += left << 1; ++ RADEONCopyData(pScrn, buf + (top * srcPitch) + (left << 1), ++ pPriv->src_addr, srcPitch, dstPitch, nlines, npixels, 2); } -- if (info->ChipFamily >= CHIP_FAMILY_R600) -+ if (info->ChipFamily >= CHIP_FAMILY_R600) { - OUTREG(R600_BIOS_0_SCRATCH, save->bios_0_scratch); + break; + } +@@ -581,25 +636,28 @@ static XF86VideoFormatRec Formats[NUM_FORMATS] = + {15, TrueColor}, {16, TrueColor}, {24, TrueColor} + }; + +-#define NUM_ATTRIBUTES 1 ++#define NUM_ATTRIBUTES 2 + + static XF86AttributeRec Attributes[NUM_ATTRIBUTES+1] = + { + {XvSettable | XvGettable, 0, 1, "XV_VSYNC"}, ++ {XvSettable | XvGettable, 0, 1, "XV_HWPLANAR"}, + {0, 0, 0, NULL} + }; + +-#define NUM_ATTRIBUTES_R300 2 ++#define NUM_ATTRIBUTES_R300 3 + + static XF86AttributeRec Attributes_r300[NUM_ATTRIBUTES_R300+1] = + { + {XvSettable | XvGettable, 0, 2, "XV_BICUBIC"}, + {XvSettable | XvGettable, 0, 1, "XV_VSYNC"}, ++ {XvSettable | XvGettable, 0, 1, "XV_HWPLANAR"}, + {0, 0, 0, NULL} + }; + + static Atom xvBicubic; + static Atom xvVSync; ++static Atom xvHWPlanar; + + #define NUM_IMAGES 4 + +@@ -626,6 +684,8 @@ RADEONGetTexPortAttribute(ScrnInfoPtr pScrn, + *value = pPriv->bicubic_state; + else if (attribute == xvVSync) + *value = pPriv->vsync; ++ else if (attribute == xvHWPlanar) ++ *value = pPriv->planar_state; + else + return BadMatch; + +@@ -647,6 +707,8 @@ RADEONSetTexPortAttribute(ScrnInfoPtr pScrn, + pPriv->bicubic_state = ClipValue (value, 0, 2); + else if (attribute == xvVSync) + pPriv->vsync = ClipValue (value, 0, 1); ++ else if (attribute == xvHWPlanar) ++ pPriv->planar_state = ClipValue (value, 0, 1); + else + return BadMatch; + +@@ -670,6 +732,7 @@ RADEONSetupImageTexturedVideo(ScreenPtr pScreen) + + xvBicubic = MAKE_ATOM("XV_BICUBIC"); + xvVSync = MAKE_ATOM("XV_VSYNC"); ++ xvHWPlanar = MAKE_ATOM("XV_HWPLANAR"); + + adapt->type = XvWindowMask | XvInputMask | XvImageMask; + adapt->flags = 0; +@@ -719,6 +782,7 @@ RADEONSetupImageTexturedVideo(ScreenPtr pScreen) + pPriv->doubleBuffer = 0; + pPriv->bicubic_state = BICUBIC_AUTO; + pPriv->vsync = TRUE; ++ pPriv->planar_state = 1; + + /* gotta uninit this someplace, XXX: shouldn't be necessary for textured */ + REGION_NULL(pScreen, &pPriv->clip); +diff --git a/src/radeon_textured_videofuncs.c b/src/radeon_textured_videofuncs.c +index f55ae12..05acb93 100644 +--- a/src/radeon_textured_videofuncs.c ++++ b/src/radeon_textured_videofuncs.c +@@ -97,6 +97,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv + uint32_t dst_offset, dst_pitch, dst_format; + uint32_t txenable, colorpitch; + uint32_t blendcntl; ++ Bool isplanar = FALSE; + int dstxoff, dstyoff, pixel_shift, vtx_count; + BoxPtr pBox = REGION_RECTS(&pPriv->clip); + int nBox = REGION_NUM_RECTS(&pPriv->clip); +@@ -181,16 +182,29 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv + if (RADEONTilingEnabled(pScrn, pPixmap)) + colorpitch |= R300_COLORTILE; + +- if (pPriv->id == FOURCC_UYVY) +- txformat1 = R300_TX_FORMAT_YVYU422; - else -+ OUTREG(R600_BIOS_3_SCRATCH, save->bios_3_scratch); +- txformat1 = R300_TX_FORMAT_VYUY422; ++ if (pPriv->planar_hw && (pPriv->id == FOURCC_I420 || pPriv->id == FOURCC_YV12)) { ++ isplanar = TRUE; ++ } ++ ++ if (isplanar) { ++ txformat1 = R300_TX_FORMAT_X8 | R300_TX_FORMAT_CACHE_HALF_REGION_0; ++ txpitch = pPriv->src_pitch; + } else { - OUTREG(RADEON_BIOS_0_SCRATCH, save->bios_0_scratch); -+ OUTREG(RADEON_BIOS_3_SCRATCH, save->bios_3_scratch); ++ if (pPriv->id == FOURCC_UYVY) ++ txformat1 = R300_TX_FORMAT_YVYU422; ++ else ++ txformat1 = R300_TX_FORMAT_VYUY422; ++ ++ txformat1 |= R300_TX_FORMAT_YUV_TO_RGB_CLAMP; + +- txformat1 |= R300_TX_FORMAT_YUV_TO_RGB_CLAMP; ++ /* pitch is in pixels */ ++ txpitch = pPriv->src_pitch / 2; + } - } else { - switch (radeon_output->active_device) { - case ATOM_DEVICE_TV1_SUPPORT: -@@ -925,41 +908,60 @@ radeon_bios_output_connected(xf86OutputPtr output, Bool connected) - save->bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO; - else if (radeon_output->MonType == MT_CTV) - save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; -- } else -+ save->bios_5_scratch |= RADEON_TV1_ON; -+ } else { - save->bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK; -+ save->bios_5_scratch &= ~RADEON_TV1_ON; -+ } - break; - case ATOM_DEVICE_LCD1_SUPPORT: -- if (connected) -+ if (connected) { - save->bios_4_scratch |= RADEON_LCD1_ATTACHED; -- else -+ save->bios_5_scratch |= RADEON_LCD1_ON; -+ } else { - save->bios_4_scratch &= ~RADEON_LCD1_ATTACHED; -+ save->bios_5_scratch &= ~RADEON_LCD1_ON; -+ } - break; - case ATOM_DEVICE_CRT1_SUPPORT: -- if (connected) -+ if (connected) { - save->bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR; -- else -+ save->bios_5_scratch |= RADEON_CRT1_ON; -+ } else { - save->bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK; -+ save->bios_5_scratch &= ~RADEON_CRT1_ON; ++ txpitch -= 1; + + txformat0 = ((((pPriv->w - 1) & 0x7ff) << R300_TXWIDTH_SHIFT) | +- (((pPriv->h - 1) & 0x7ff) << R300_TXHEIGHT_SHIFT) | +- R300_TXPITCH_EN); ++ (((pPriv->h - 1) & 0x7ff) << R300_TXHEIGHT_SHIFT) | ++ R300_TXPITCH_EN); + + info->accel_state->texW[0] = pPriv->w; + info->accel_state->texH[0] = pPriv->h; +@@ -201,9 +215,6 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv + R300_TX_MIN_FILTER_LINEAR | + (0 << R300_TX_ID_SHIFT)); + +- /* pitch is in pixels */ +- txpitch = pPriv->src_pitch / 2; +- txpitch -= 1; + + if (IS_R500_3D && ((pPriv->w - 1) & 0x800)) + txpitch |= R500_TXWIDTH_11; +@@ -224,6 +235,34 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv + + txenable = R300_TEX_0_ENABLE; + ++ if (isplanar) { ++ txformat0 = ((((((pPriv->w + 1 ) >> 1) - 1) & 0x7ff) << R300_TXWIDTH_SHIFT) | ++ (((((pPriv->h + 1 ) >> 1 ) - 1) & 0x7ff) << R300_TXHEIGHT_SHIFT) | ++ R300_TXPITCH_EN); ++ txpitch = ((pPriv->src_pitch >> 1) + 63) & ~63; ++ txpitch -= 1; ++ txfilter = (R300_TX_CLAMP_S(R300_TX_CLAMP_CLAMP_LAST) | ++ R300_TX_CLAMP_T(R300_TX_CLAMP_CLAMP_LAST) | ++ R300_TX_MIN_FILTER_LINEAR | ++ R300_TX_MAG_FILTER_LINEAR); ++ ++ BEGIN_ACCEL(12); ++ OUT_ACCEL_REG(R300_TX_FILTER0_1, txfilter | (1 << R300_TX_ID_SHIFT)); ++ OUT_ACCEL_REG(R300_TX_FILTER1_1, 0); ++ OUT_ACCEL_REG(R300_TX_FORMAT0_1, txformat0); ++ OUT_ACCEL_REG(R300_TX_FORMAT1_1, R300_TX_FORMAT_X8 | R300_TX_FORMAT_CACHE_FOURTH_REGION_2); ++ OUT_ACCEL_REG(R300_TX_FORMAT2_1, txpitch); ++ OUT_ACCEL_REG(R300_TX_OFFSET_1, txoffset + pPriv->planeu_offset); ++ OUT_ACCEL_REG(R300_TX_FILTER0_2, txfilter | (2 << R300_TX_ID_SHIFT)); ++ OUT_ACCEL_REG(R300_TX_FILTER1_2, 0); ++ OUT_ACCEL_REG(R300_TX_FORMAT0_2, txformat0); ++ OUT_ACCEL_REG(R300_TX_FORMAT1_2, R300_TX_FORMAT_X8 | R300_TX_FORMAT_CACHE_FOURTH_REGION_3); ++ OUT_ACCEL_REG(R300_TX_FORMAT2_2, txpitch); ++ OUT_ACCEL_REG(R300_TX_OFFSET_2, txoffset + pPriv->planev_offset); ++ FINISH_ACCEL(); ++ txenable |= R300_TEX_1_ENABLE | R300_TEX_2_ENABLE; ++ } ++ + if (pPriv->bicubic_enabled) { + /* Size is 128x1 */ + txformat0 = ((0x7f << R300_TXWIDTH_SHIFT) | +@@ -691,6 +730,171 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv + OUT_ACCEL_REG(R300_US_ALU_CONST_A(1), 0); + + FINISH_ACCEL(); ++ } else if (isplanar) { ++ /* ++ * y' = y - .0625 ++ * u' = u - .5 ++ * v' = v - .5; ++ * ++ * r = 1.1643 * y' + 0.0 * u' + 1.5958 * v' ++ * g = 1.1643 * y' - 0.39173 * u' - 0.81290 * v' ++ * b = 1.1643 * y' + 2.017 * u' + 0.0 * v' ++ * ++ * DP3 might look like the straightforward solution ++ * but we'd need to move the texture yuv values in ++ * the same reg for this to work. Therefore use MADs. ++ * Without changing the shader at all (only the constants) ++ * could also provide hue/saturation/brightness/contrast control. ++ * ++ * yco = 1.1643 ++ * uco = 0, -0.39173, 2.017 ++ * vco = 1.5958, -0.8129, 0 ++ * off = -0.0625 * yco + -0.5 * uco[r] + -0.5 * vco[r], ++ * -0.0625 * yco + -0.5 * uco[g] + -0.5 * vco[g], ++ * -0.0625 * yco + -0.5 * uco[b] + -0.5 * vco[b], ++ * ++ * temp = MAD(yco, yuv.yyyy, off) ++ * temp = MAD(uco, yuv.uuuu, temp) ++ * result = MAD(vco, yuv.vvvv, temp) ++ */ ++ float yco = 1.1643; ++ float uco[3] = {0.0, -0.39173, 2.018}; ++ float vco[3] = {1.5958, -0.8129, 0.0}; ++ float off[3] = {-0.0625 * yco + -0.5 * uco[0] + -0.5 * vco[0], ++ -0.0625 * yco + -0.5 * uco[1] + -0.5 * vco[1], ++ -0.0625 * yco + -0.5 * uco[2] + -0.5 * vco[2]}; ++ ++ BEGIN_ACCEL(33); ++ /* 2 components: same 2 for tex0/1/2 */ ++ OUT_ACCEL_REG(R300_RS_COUNT, ++ ((2 << R300_RS_COUNT_IT_COUNT_SHIFT) | ++ R300_RS_COUNT_HIRES_EN)); ++ /* R300_INST_COUNT_RS - highest RS instruction used */ ++ OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(0) | R300_TX_OFFSET_RS(6)); ++ ++ OUT_ACCEL_REG(R300_US_PIXSIZE, 2); /* highest temp used */ ++ ++ /* Indirection levels */ ++ OUT_ACCEL_REG(R300_US_CONFIG, ((0 << R300_NLEVEL_SHIFT) | ++ R300_FIRST_TEX)); ++ ++ OUT_ACCEL_REG(R300_US_CODE_OFFSET, (R300_ALU_CODE_OFFSET(0) | ++ R300_ALU_CODE_SIZE(3) | ++ R300_TEX_CODE_OFFSET(0) | ++ R300_TEX_CODE_SIZE(3))); ++ ++ OUT_ACCEL_REG(R300_US_CODE_ADDR_3, (R300_ALU_START(0) | ++ R300_ALU_SIZE(2) | ++ R300_TEX_START(0) | ++ R300_TEX_SIZE(2) | ++ R300_RGBA_OUT)); ++ ++ /* tex inst */ ++ OUT_ACCEL_REG(R300_US_TEX_INST_0, (R300_TEX_SRC_ADDR(0) | ++ R300_TEX_DST_ADDR(0) | ++ R300_TEX_ID(0) | ++ R300_TEX_INST(R300_TEX_INST_LD))); ++ OUT_ACCEL_REG(R300_US_TEX_INST_1, (R300_TEX_SRC_ADDR(0) | ++ R300_TEX_DST_ADDR(1) | ++ R300_TEX_ID(1) | ++ R300_TEX_INST(R300_TEX_INST_LD))); ++ OUT_ACCEL_REG(R300_US_TEX_INST_2, (R300_TEX_SRC_ADDR(0) | ++ R300_TEX_DST_ADDR(2) | ++ R300_TEX_ID(2) | ++ R300_TEX_INST(R300_TEX_INST_LD))); ++ ++ /* ALU inst */ ++ /* MAD temp0, const0.a, temp0, const0.rgb */ ++ OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR(0), (R300_ALU_RGB_ADDR0(R300_ALU_RGB_CONST(0)) | ++ R300_ALU_RGB_ADDR1(0) | ++ R300_ALU_RGB_ADDR2(0) | ++ R300_ALU_RGB_ADDRD(0) | ++ R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_RGB))); ++ OUT_ACCEL_REG(R300_US_ALU_RGB_INST(0), (R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_AAA) | ++ R300_ALU_RGB_MOD_A(R300_ALU_RGB_MOD_NOP) | ++ R300_ALU_RGB_SEL_B(R300_ALU_RGB_SRC1_RGB) | ++ R300_ALU_RGB_MOD_B(R300_ALU_RGB_MOD_NOP) | ++ R300_ALU_RGB_SEL_C(R300_ALU_RGB_SRC0_RGB) | ++ R300_ALU_RGB_MOD_C(R300_ALU_RGB_MOD_NOP) | ++ R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) | ++ R300_ALU_RGB_OMOD(R300_ALU_RGB_OMOD_NONE))); ++ /* alpha nop, but need to set up alpha source for rgb usage */ ++ OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(0), (R300_ALU_ALPHA_ADDR0(R300_ALU_ALPHA_CONST(0)) | ++ R300_ALU_ALPHA_ADDR1(0) | ++ R300_ALU_ALPHA_ADDR2(0) | ++ R300_ALU_ALPHA_ADDRD(0) | ++ R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE))); ++ OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST(0), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) | ++ R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_0_0) | ++ R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) | ++ R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0))); ++ ++ /* MAD const1, temp1, temp0 */ ++ OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR(1), (R300_ALU_RGB_ADDR0(R300_ALU_RGB_CONST(1)) | ++ R300_ALU_RGB_ADDR1(1) | ++ R300_ALU_RGB_ADDR2(0) | ++ R300_ALU_RGB_ADDRD(0) | ++ R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_RGB))); ++ OUT_ACCEL_REG(R300_US_ALU_RGB_INST(1), (R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_RGB) | ++ R300_ALU_RGB_MOD_A(R300_ALU_RGB_MOD_NOP) | ++ R300_ALU_RGB_SEL_B(R300_ALU_RGB_SRC1_RGB) | ++ R300_ALU_RGB_MOD_B(R300_ALU_RGB_MOD_NOP) | ++ R300_ALU_RGB_SEL_C(R300_ALU_RGB_SRC2_RGB) | ++ R300_ALU_RGB_MOD_C(R300_ALU_RGB_MOD_NOP) | ++ R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) | ++ R300_ALU_RGB_OMOD(R300_ALU_RGB_OMOD_NONE))); ++ /* alpha nop */ ++ OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(1), (R300_ALU_ALPHA_ADDRD(0) | ++ R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE))); ++ OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST(1), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) | ++ R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_0_0) | ++ R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) | ++ R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0))); ++ ++ /* MAD result, const2, temp2, temp0 */ ++ OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR(2), (R300_ALU_RGB_ADDR0(R300_ALU_RGB_CONST(2)) | ++ R300_ALU_RGB_ADDR1(2) | ++ R300_ALU_RGB_ADDR2(0) | ++ R300_ALU_RGB_ADDRD(0) | ++ R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_RGB) | ++ R300_ALU_RGB_OMASK(R300_ALU_RGB_MASK_RGB))); ++ OUT_ACCEL_REG(R300_US_ALU_RGB_INST(2), (R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_RGB) | ++ R300_ALU_RGB_MOD_A(R300_ALU_RGB_MOD_NOP) | ++ R300_ALU_RGB_SEL_B(R300_ALU_RGB_SRC1_RGB) | ++ R300_ALU_RGB_MOD_B(R300_ALU_RGB_MOD_NOP) | ++ R300_ALU_RGB_SEL_C(R300_ALU_RGB_SRC2_RGB) | ++ R300_ALU_RGB_MOD_C(R300_ALU_RGB_MOD_NOP) | ++ R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) | ++ R300_ALU_RGB_OMOD(R300_ALU_RGB_OMOD_NONE) | ++ R300_ALU_RGB_CLAMP)); ++ /* write alpha 1 */ ++ OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(4), (R300_ALU_ALPHA_ADDRD(0) | ++ R300_ALU_ALPHA_OMASK(R300_ALU_ALPHA_MASK_A) | ++ R300_ALU_ALPHA_TARGET_A)); ++ OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST(4), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) | ++ R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_0_0) | ++ R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) | ++ R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_1_0))); ++ ++ /* Shader constants. */ ++ /* constant 0: off, yco */ ++ OUT_ACCEL_REG(R300_US_ALU_CONST_R(0), F_TO_24(off[0])); ++ OUT_ACCEL_REG(R300_US_ALU_CONST_G(0), F_TO_24(off[1])); ++ OUT_ACCEL_REG(R300_US_ALU_CONST_B(0), F_TO_24(off[2])); ++ OUT_ACCEL_REG(R300_US_ALU_CONST_A(0), F_TO_24(yco)); ++ /* constant 1: uco */ ++ OUT_ACCEL_REG(R300_US_ALU_CONST_R(1), F_TO_24(uco[0])); ++ OUT_ACCEL_REG(R300_US_ALU_CONST_G(1), F_TO_24(uco[1])); ++ OUT_ACCEL_REG(R300_US_ALU_CONST_B(1), F_TO_24(uco[2])); ++ OUT_ACCEL_REG(R300_US_ALU_CONST_A(1), F_TO_24(0.0)); ++ /* constant 2: vco */ ++ OUT_ACCEL_REG(R300_US_ALU_CONST_R(2), F_TO_24(vco[0])); ++ OUT_ACCEL_REG(R300_US_ALU_CONST_G(2), F_TO_24(vco[1])); ++ OUT_ACCEL_REG(R300_US_ALU_CONST_B(2), F_TO_24(vco[2])); ++ OUT_ACCEL_REG(R300_US_ALU_CONST_A(2), F_TO_24(0.0)); ++ ++ FINISH_ACCEL(); ++ + } else { + BEGIN_ACCEL(11); + /* 2 components: 2 for tex0 */ +@@ -760,7 +964,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv + R300_ALU_ALPHA_OMOD(R300_ALU_ALPHA_OMOD_NONE) | + R300_ALU_ALPHA_CLAMP)); + FINISH_ACCEL(); +- } + } - break; - case ATOM_DEVICE_CRT2_SUPPORT: -- if (connected) -+ if (connected) { - save->bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR; -- else -+ save->bios_5_scratch |= RADEON_CRT2_ON; -+ } else { - save->bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK; -+ save->bios_5_scratch &= ~RADEON_CRT2_ON; + } else { + if (pPriv->bicubic_enabled) { + BEGIN_ACCEL(7); +@@ -1363,10 +1567,18 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv + return; + } + +- if (pPriv->id == FOURCC_UYVY) +- txformat = RADEON_TXFORMAT_YVYU422; +- else +- txformat = RADEON_TXFORMAT_VYUY422; ++ if (pPriv->planar_hw && (pPriv->id == FOURCC_I420 || pPriv->id == FOURCC_YV12)) { ++ isplanar = TRUE; ++ } ++ ++ if (isplanar) { ++ txformat = RADEON_TXFORMAT_I8; ++ } else { ++ if (pPriv->id == FOURCC_UYVY) ++ txformat = RADEON_TXFORMAT_YVYU422; ++ else ++ txformat = RADEON_TXFORMAT_VYUY422; ++ } + + txformat |= RADEON_TXFORMAT_NON_POWER2; + +@@ -1375,12 +1587,10 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv + if (RADEONTilingEnabled(pScrn, pPixmap)) + colorpitch |= RADEON_COLOR_TILE_ENABLE; + +- BEGIN_ACCEL(5); ++ BEGIN_ACCEL(4); + +- OUT_ACCEL_REG(RADEON_PP_CNTL, +- RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE); + OUT_ACCEL_REG(RADEON_RB3D_CNTL, +- dst_format | RADEON_ALPHA_BLEND_ENABLE); ++ dst_format /*| RADEON_ALPHA_BLEND_ENABLE*/); + OUT_ACCEL_REG(RADEON_RB3D_COLOROFFSET, dst_offset); + + OUT_ACCEL_REG(RADEON_RB3D_COLORPITCH, colorpitch); +@@ -1399,48 +1609,346 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv + info->accel_state->texW[0] = pPriv->w; + info->accel_state->texH[0] = pPriv->h; + +- BEGIN_ACCEL(12); +- +- OUT_ACCEL_REG(R200_SE_VTX_FMT_0, R200_VTX_XY); +- OUT_ACCEL_REG(R200_SE_VTX_FMT_1, +- (2 << R200_VTX_TEX0_COMP_CNT_SHIFT)); +- +- OUT_ACCEL_REG(R200_PP_TXFILTER_0, +- R200_MAG_FILTER_LINEAR | +- R200_MIN_FILTER_LINEAR | +- R200_CLAMP_S_CLAMP_LAST | +- R200_CLAMP_T_CLAMP_LAST | +- R200_YUV_TO_RGB); +- OUT_ACCEL_REG(R200_PP_TXFORMAT_0, txformat); +- OUT_ACCEL_REG(R200_PP_TXFORMAT_X_0, 0); +- OUT_ACCEL_REG(R200_PP_TXSIZE_0, +- (pPriv->w - 1) | +- ((pPriv->h - 1) << RADEON_TEX_VSIZE_SHIFT)); +- OUT_ACCEL_REG(R200_PP_TXPITCH_0, pPriv->src_pitch - 32); +- +- OUT_ACCEL_REG(R200_PP_TXOFFSET_0, pPriv->src_offset); +- +- OUT_ACCEL_REG(R200_PP_TXCBLEND_0, +- R200_TXC_ARG_A_ZERO | +- R200_TXC_ARG_B_ZERO | +- R200_TXC_ARG_C_R0_COLOR | +- R200_TXC_OP_MADD); +- OUT_ACCEL_REG(R200_PP_TXCBLEND2_0, +- R200_TXC_CLAMP_0_1 | R200_TXC_OUTPUT_REG_R0); +- OUT_ACCEL_REG(R200_PP_TXABLEND_0, +- R200_TXA_ARG_A_ZERO | +- R200_TXA_ARG_B_ZERO | +- R200_TXA_ARG_C_R0_ALPHA | +- R200_TXA_OP_MADD); +- OUT_ACCEL_REG(R200_PP_TXABLEND2_0, +- R200_TXA_CLAMP_0_1 | R200_TXA_OUTPUT_REG_R0); +- FINISH_ACCEL(); ++ if (isplanar) { ++ /* note: in contrast to r300, use input biasing on uv components */ ++ float yco = 1.1643; ++ float yoff = -0.0625 * yco; ++ float uco[3] = {0.0, -0.39173, 2.018}; ++ float vco[3] = {1.5958, -0.8129, 0.0}; ++ ++ /* need 2 texcoord sets (even though they are identical) due ++ to denormalization! hw apparently can't premultiply ++ same coord set by different texture size */ ++ vtx_count = 6; ++ ++ txformat0 = (((((pPriv->w + 1 ) >> 1) - 1) & 0x7ff) | ++ (((((pPriv->h + 1 ) >> 1) - 1) & 0x7ff) << RADEON_TEX_VSIZE_SHIFT)); ++ txpitch = ((pPriv->src_pitch >> 1) + 63) & ~63; ++ txpitch -= 32; ++ txfilter = R200_MAG_FILTER_LINEAR | ++ R200_MIN_FILTER_LINEAR | ++ R200_CLAMP_S_CLAMP_LAST | ++ R200_CLAMP_T_CLAMP_LAST; ++ ++ BEGIN_ACCEL(36); ++ ++ OUT_ACCEL_REG(RADEON_PP_CNTL, ++ RADEON_TEX_0_ENABLE | RADEON_TEX_1_ENABLE | RADEON_TEX_2_ENABLE | ++ RADEON_TEX_BLEND_0_ENABLE | RADEON_TEX_BLEND_1_ENABLE | ++ RADEON_TEX_BLEND_2_ENABLE); ++ ++ OUT_ACCEL_REG(R200_SE_VTX_FMT_0, R200_VTX_XY); ++ OUT_ACCEL_REG(R200_SE_VTX_FMT_1, ++ (2 << R200_VTX_TEX0_COMP_CNT_SHIFT) | ++ (2 << R200_VTX_TEX1_COMP_CNT_SHIFT)); ++ ++ OUT_ACCEL_REG(R200_PP_TXFILTER_0, txfilter); ++ OUT_ACCEL_REG(R200_PP_TXFORMAT_0, txformat); ++ OUT_ACCEL_REG(R200_PP_TXFORMAT_X_0, 0); ++ OUT_ACCEL_REG(R200_PP_TXSIZE_0, ++ (pPriv->w - 1) | ++ ((pPriv->h - 1) << RADEON_TEX_VSIZE_SHIFT)); ++ OUT_ACCEL_REG(R200_PP_TXPITCH_0, pPriv->src_pitch - 32); ++ OUT_ACCEL_REG(R200_PP_TXOFFSET_0, pPriv->src_offset); ++ ++ OUT_ACCEL_REG(R200_PP_TXFILTER_1, txfilter); ++ OUT_ACCEL_REG(R200_PP_TXFORMAT_1, txformat | R200_TXFORMAT_ST_ROUTE_STQ1); ++ OUT_ACCEL_REG(R200_PP_TXFORMAT_X_1, 0); ++ OUT_ACCEL_REG(R200_PP_TXSIZE_1, txformat0); ++ OUT_ACCEL_REG(R200_PP_TXPITCH_1, txpitch); ++ OUT_ACCEL_REG(R200_PP_TXOFFSET_1, pPriv->src_offset + pPriv->planeu_offset); ++ ++ OUT_ACCEL_REG(R200_PP_TXFILTER_2, txfilter); ++ OUT_ACCEL_REG(R200_PP_TXFORMAT_2, txformat | R200_TXFORMAT_ST_ROUTE_STQ1); ++ OUT_ACCEL_REG(R200_PP_TXFORMAT_X_2, 0); ++ OUT_ACCEL_REG(R200_PP_TXSIZE_2, txformat0); ++ OUT_ACCEL_REG(R200_PP_TXPITCH_2, txpitch); ++ OUT_ACCEL_REG(R200_PP_TXOFFSET_2, pPriv->src_offset + pPriv->planev_offset); ++ ++ /* similar to r300 code. Note the big problem is that hardware constants ++ * are 8 bits only, representing 0.0-1.0. We can get that up (using bias ++ * + scale) to -1.0-1.0 (but precision will suffer). AFAIK the hw actually ++ * has 12 bits fractional precision (plus 1 sign bit, 3 range bits) but ++ * the constants not. To get larger range can use output scale, but for ++ * that 2.018 value we need a total scale by 8, which means the constants ++ * really have no accuracy whatsoever (5 fractional bits only). ++ * The only direct way to get high precision "constants" into the fragment ++ * pipe I know of is to use the texcoord interpolator (not color, this one ++ * is 8 bit only too), which seems a bit expensive. We're lucky though it ++ * seems the values we need seem to fit better than worst case (get about ++ * 6 fractional bits for this instead of 5, at least when not correcting for ++ * hue/saturation/contrast/brightness, which is the same as for vco - yco and ++ * yoff get 8 fractional bits). ++ * ++ * A higher precision (8 fractional bits) version might just put uco into ++ * a texcoord, and calculate a new vcoconst in the shader, like so: ++ * cohelper = {1.0, 0.0, 0.0} - shouldn't use 0.5 since not exactly representable ++ * vco = {1.5958 - 1.0, -0.8129 + 1.0, 1.0} ++ * vcocalc = ADD temp, bias/scale(cohelper), vco ++ * would in total use 4 tex units, 4 instructions which seems fairly ++ * balanced for this architecture (instead of 3 + 3 for the solution here) ++ * ++ * temp = MAD(yco, yuv.yyyy, yoff) ++ * temp = MAD(uco, yuv.uuuu, temp) ++ * result = MAD(vco, yuv.vvvv, temp) ++ * ++ * note first mad produces actually scalar, hence we transform ++ * it into a dp2a to get 8 bit precision of yco instead of 7 - ++ * That's assuming hw correctly expands consts to internal precision. ++ * (y * 1 + y * (yco - 1) + yoff) ++ * temp = DP2A / 2 (yco, yuv.yyyy, yoff) ++ * temp = MAD (uco / 4, yuv.uuuu * 2, temp) ++ * result = MAD x2 (vco / 2, yuv.vvvv, temp) ++ * ++ * vco, uco need bias (and hence scale too) ++ * ++ */ ++ ++ /* MAD temp0 / 2, const0.a * 2, temp0, -const0.rgb */ ++ OUT_ACCEL_REG(R200_PP_TXCBLEND_0, ++ R200_TXC_ARG_A_TFACTOR_COLOR | ++ R200_TXC_ARG_B_R0_COLOR | ++ R200_TXC_ARG_C_TFACTOR_COLOR | ++ R200_TXC_NEG_ARG_C | ++ R200_TXC_OP_DOT2_ADD); ++ OUT_ACCEL_REG(R200_PP_TXCBLEND2_0, ++ (0 << R200_TXC_TFACTOR_SEL_SHIFT) | ++ R200_TXC_SCALE_INV2 | ++ R200_TXC_CLAMP_8_8 | R200_TXC_OUTPUT_REG_R0); ++ OUT_ACCEL_REG(R200_PP_TXABLEND_0, ++ R200_TXA_ARG_A_ZERO | ++ R200_TXA_ARG_B_ZERO | ++ R200_TXA_ARG_C_ZERO | ++ R200_TXA_OP_MADD); ++ OUT_ACCEL_REG(R200_PP_TXABLEND2_0, ++ R200_TXA_OUTPUT_REG_NONE); ++ ++ /* MAD temp0, (const1 - 0.5) * 2, (temp1 - 0.5) * 2, temp0 */ ++ OUT_ACCEL_REG(R200_PP_TXCBLEND_1, ++ R200_TXC_ARG_A_TFACTOR_COLOR | ++ R200_TXC_BIAS_ARG_A | ++ R200_TXC_SCALE_ARG_A | ++ R200_TXC_ARG_B_R1_COLOR | ++ R200_TXC_BIAS_ARG_B | ++ R200_TXC_SCALE_ARG_B | ++ R200_TXC_ARG_C_R0_COLOR | ++ R200_TXC_OP_MADD); ++ OUT_ACCEL_REG(R200_PP_TXCBLEND2_1, ++ (1 << R200_TXC_TFACTOR_SEL_SHIFT) | ++ R200_TXC_CLAMP_8_8 | R200_TXC_OUTPUT_REG_R0); ++ OUT_ACCEL_REG(R200_PP_TXABLEND_1, ++ R200_TXA_ARG_A_ZERO | ++ R200_TXA_ARG_B_ZERO | ++ R200_TXA_ARG_C_ZERO | ++ R200_TXA_OP_MADD); ++ OUT_ACCEL_REG(R200_PP_TXABLEND2_1, ++ R200_TXA_OUTPUT_REG_NONE); ++ ++ /* MAD temp0 x 2, (const2 - 0.5) * 2, (temp2 - 0.5), temp0 */ ++ OUT_ACCEL_REG(R200_PP_TXCBLEND_2, ++ R200_TXC_ARG_A_TFACTOR_COLOR | ++ R200_TXC_BIAS_ARG_A | ++ R200_TXC_SCALE_ARG_A | ++ R200_TXC_ARG_B_R2_COLOR | ++ R200_TXC_BIAS_ARG_B | ++ R200_TXC_ARG_C_R0_COLOR | ++ R200_TXC_OP_MADD); ++ OUT_ACCEL_REG(R200_PP_TXCBLEND2_2, ++ (2 << R200_TXC_TFACTOR_SEL_SHIFT) | ++ R200_TXC_SCALE_2X | ++ R200_TXC_CLAMP_0_1 | R200_TXC_OUTPUT_REG_R0); ++ OUT_ACCEL_REG(R200_PP_TXABLEND_2, ++ R200_TXA_ARG_A_ZERO | ++ R200_TXA_ARG_B_ZERO | ++ R200_TXA_ARG_C_ZERO | ++ R200_TXA_COMP_ARG_C | ++ R200_TXA_OP_MADD); ++ OUT_ACCEL_REG(R200_PP_TXABLEND2_2, ++ R200_TXA_CLAMP_0_1 | R200_TXA_OUTPUT_REG_R0); ++ ++ /* shader constants */ ++ OUT_ACCEL_REG(R200_PP_TFACTOR_0, float4touint(1.0, /* src range [1, 2] */ ++ yco - 1.0, ++ -yoff, /* range [-1, 0] */ ++ 0.0)); ++ OUT_ACCEL_REG(R200_PP_TFACTOR_1, float4touint(uco[0] * 0.125 + 0.5, /* range [-4, 4] */ ++ uco[1] * 0.125 + 0.5, ++ uco[2] * 0.125 + 0.5, ++ 0.0)); ++ OUT_ACCEL_REG(R200_PP_TFACTOR_2, float4touint(vco[0] * 0.25 + 0.5, /* range [-2, 2] */ ++ vco[1] * 0.25 + 0.5, ++ vco[2] * 0.25 + 0.5, ++ 0.0)); ++ ++ FINISH_ACCEL(); + } - break; - case ATOM_DEVICE_DFP1_SUPPORT: -- if (connected) -+ if (connected) { - save->bios_4_scratch |= RADEON_DFP1_ATTACHED; -- else -+ save->bios_5_scratch |= RADEON_DFP1_ON; -+ } else { - save->bios_4_scratch &= ~RADEON_DFP1_ATTACHED; -+ save->bios_5_scratch &= ~RADEON_DFP1_ON; ++ else if (info->ChipFamily == CHIP_FAMILY_RV250) { ++ /* fix up broken packed yuv - shader same as above except ++ yuv compoents are all in same reg */ ++ float yco = 1.1643; ++ float yoff = -0.0625 * yco; ++ float uco[3] = {0.0, -0.39173, 2.018}; ++ float vco[3] = {1.5958, -0.8129, 0.0}; ++ ++ txformat0 = (((((pPriv->w + 1 ) >> 1) - 1) & 0x7ff) | ++ (((((pPriv->h + 1 ) >> 1 ) - 1) & 0x7ff) << RADEON_TEX_VSIZE_SHIFT)); ++ txpitch = ((pPriv->src_pitch >> 1) + 63) & ~63; ++ txpitch -= 32; ++ txfilter = R200_MAG_FILTER_LINEAR | ++ R200_MIN_FILTER_LINEAR | ++ R200_CLAMP_S_CLAMP_LAST | ++ R200_CLAMP_T_CLAMP_LAST; ++ ++ BEGIN_ACCEL(24); ++ ++ OUT_ACCEL_REG(RADEON_PP_CNTL, ++ RADEON_TEX_0_ENABLE | ++ RADEON_TEX_BLEND_0_ENABLE | RADEON_TEX_BLEND_1_ENABLE | ++ RADEON_TEX_BLEND_2_ENABLE); ++ ++ OUT_ACCEL_REG(R200_SE_VTX_FMT_0, R200_VTX_XY); ++ OUT_ACCEL_REG(R200_SE_VTX_FMT_1, ++ (2 << R200_VTX_TEX0_COMP_CNT_SHIFT)); ++ ++ OUT_ACCEL_REG(R200_PP_TXFILTER_0, txfilter); ++ OUT_ACCEL_REG(R200_PP_TXFORMAT_0, txformat); ++ OUT_ACCEL_REG(R200_PP_TXFORMAT_X_0, 0); ++ OUT_ACCEL_REG(R200_PP_TXSIZE_0, ++ (pPriv->w - 1) | ++ ((pPriv->h - 1) << RADEON_TEX_VSIZE_SHIFT)); ++ OUT_ACCEL_REG(R200_PP_TXPITCH_0, pPriv->src_pitch - 32); ++ OUT_ACCEL_REG(R200_PP_TXOFFSET_0, pPriv->src_offset); ++ ++ /* MAD temp1 / 2, const0.a * 2, temp0.ggg, -const0.rgb */ ++ OUT_ACCEL_REG(R200_PP_TXCBLEND_0, ++ R200_TXC_ARG_A_TFACTOR_COLOR | ++ R200_TXC_ARG_B_R0_COLOR | ++ R200_TXC_ARG_C_TFACTOR_COLOR | ++ R200_TXC_NEG_ARG_C | ++ R200_TXC_OP_DOT2_ADD); ++ OUT_ACCEL_REG(R200_PP_TXCBLEND2_0, ++ (0 << R200_TXC_TFACTOR_SEL_SHIFT) | ++ R200_TXC_SCALE_INV2 | ++ (R200_TXC_REPL_GREEN << R200_TXC_REPL_ARG_B_SHIFT) | ++ R200_TXC_CLAMP_8_8 | R200_TXC_OUTPUT_REG_R1); ++ OUT_ACCEL_REG(R200_PP_TXABLEND_0, ++ R200_TXA_ARG_A_ZERO | ++ R200_TXA_ARG_B_ZERO | ++ R200_TXA_ARG_C_ZERO | ++ R200_TXA_OP_MADD); ++ OUT_ACCEL_REG(R200_PP_TXABLEND2_0, ++ R200_TXA_OUTPUT_REG_NONE); ++ ++ /* MAD temp1, (const1 - 0.5) * 2, (temp0.rrr - 0.5) * 2, temp1 */ ++ OUT_ACCEL_REG(R200_PP_TXCBLEND_1, ++ R200_TXC_ARG_A_TFACTOR_COLOR | ++ R200_TXC_BIAS_ARG_A | ++ R200_TXC_SCALE_ARG_A | ++ R200_TXC_ARG_B_R0_COLOR | ++ R200_TXC_BIAS_ARG_B | ++ R200_TXC_SCALE_ARG_B | ++ R200_TXC_ARG_C_R1_COLOR | ++ R200_TXC_OP_MADD); ++ OUT_ACCEL_REG(R200_PP_TXCBLEND2_1, ++ (1 << R200_TXC_TFACTOR_SEL_SHIFT) | ++ (R200_TXC_REPL_BLUE << R200_TXC_REPL_ARG_B_SHIFT) | ++ R200_TXC_CLAMP_8_8 | R200_TXC_OUTPUT_REG_R1); ++ OUT_ACCEL_REG(R200_PP_TXABLEND_1, ++ R200_TXA_ARG_A_ZERO | ++ R200_TXA_ARG_B_ZERO | ++ R200_TXA_ARG_C_ZERO | ++ R200_TXA_OP_MADD); ++ OUT_ACCEL_REG(R200_PP_TXABLEND2_1, ++ R200_TXA_OUTPUT_REG_NONE); ++ ++ /* MAD temp0 x 2, (const2 - 0.5) * 2, (temp0.bbb - 0.5), temp1 */ ++ OUT_ACCEL_REG(R200_PP_TXCBLEND_2, ++ R200_TXC_ARG_A_TFACTOR_COLOR | ++ R200_TXC_BIAS_ARG_A | ++ R200_TXC_SCALE_ARG_A | ++ R200_TXC_ARG_B_R0_COLOR | ++ R200_TXC_BIAS_ARG_B | ++ R200_TXC_ARG_C_R1_COLOR | ++ R200_TXC_OP_MADD); ++ OUT_ACCEL_REG(R200_PP_TXCBLEND2_2, ++ (2 << R200_TXC_TFACTOR_SEL_SHIFT) | ++ R200_TXC_SCALE_2X | ++ (R200_TXC_REPL_RED << R200_TXC_REPL_ARG_B_SHIFT) | ++ R200_TXC_CLAMP_0_1 | R200_TXC_OUTPUT_REG_R0); ++ OUT_ACCEL_REG(R200_PP_TXABLEND_2, ++ R200_TXA_ARG_A_ZERO | ++ R200_TXA_ARG_B_ZERO | ++ R200_TXA_ARG_C_ZERO | ++ R200_TXA_COMP_ARG_C | ++ R200_TXA_OP_MADD); ++ OUT_ACCEL_REG(R200_PP_TXABLEND2_2, ++ R200_TXA_CLAMP_0_1 | R200_TXA_OUTPUT_REG_R0); ++ ++ /* shader constants */ ++ OUT_ACCEL_REG(R200_PP_TFACTOR_0, float4touint(1.0, /* src range [1, 2] */ ++ yco - 1.0, ++ -yoff, /* range [-1, 0] */ ++ 0.0)); ++ OUT_ACCEL_REG(R200_PP_TFACTOR_1, float4touint(uco[0] * 0.125 + 0.5, /* range [-4, 4] */ ++ uco[1] * 0.125 + 0.5, ++ uco[2] * 0.125 + 0.5, ++ 0.0)); ++ OUT_ACCEL_REG(R200_PP_TFACTOR_2, float4touint(vco[0] * 0.25 + 0.5, /* range [-2, 2] */ ++ vco[1] * 0.25 + 0.5, ++ vco[2] * 0.25 + 0.5, ++ 0.0)); ++ ++ FINISH_ACCEL(); + } - break; - case ATOM_DEVICE_DFP2_SUPPORT: -- if (connected) -+ if (connected) { - save->bios_4_scratch |= RADEON_DFP2_ATTACHED; -- else -+ save->bios_5_scratch |= RADEON_DFP2_ON; -+ } else { - save->bios_4_scratch &= ~RADEON_DFP2_ATTACHED; -+ save->bios_5_scratch &= ~RADEON_DFP2_ON; ++ else { ++ BEGIN_ACCEL(13); ++ OUT_ACCEL_REG(RADEON_PP_CNTL, ++ RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE); ++ ++ OUT_ACCEL_REG(R200_SE_VTX_FMT_0, R200_VTX_XY); ++ OUT_ACCEL_REG(R200_SE_VTX_FMT_1, ++ (2 << R200_VTX_TEX0_COMP_CNT_SHIFT)); ++ ++ OUT_ACCEL_REG(R200_PP_TXFILTER_0, ++ R200_MAG_FILTER_LINEAR | ++ R200_MIN_FILTER_LINEAR | ++ R200_CLAMP_S_CLAMP_LAST | ++ R200_CLAMP_T_CLAMP_LAST | ++ R200_YUV_TO_RGB); ++ OUT_ACCEL_REG(R200_PP_TXFORMAT_0, txformat); ++ OUT_ACCEL_REG(R200_PP_TXFORMAT_X_0, 0); ++ OUT_ACCEL_REG(R200_PP_TXSIZE_0, ++ (pPriv->w - 1) | ++ ((pPriv->h - 1) << RADEON_TEX_VSIZE_SHIFT)); ++ OUT_ACCEL_REG(R200_PP_TXPITCH_0, pPriv->src_pitch - 32); ++ ++ OUT_ACCEL_REG(R200_PP_TXOFFSET_0, pPriv->src_offset); ++ ++ OUT_ACCEL_REG(R200_PP_TXCBLEND_0, ++ R200_TXC_ARG_A_ZERO | ++ R200_TXC_ARG_B_ZERO | ++ R200_TXC_ARG_C_R0_COLOR | ++ R200_TXC_OP_MADD); ++ OUT_ACCEL_REG(R200_PP_TXCBLEND2_0, ++ R200_TXC_CLAMP_0_1 | R200_TXC_OUTPUT_REG_R0); ++ OUT_ACCEL_REG(R200_PP_TXABLEND_0, ++ R200_TXA_ARG_A_ZERO | ++ R200_TXA_ARG_B_ZERO | ++ R200_TXA_ARG_C_R0_ALPHA | ++ R200_TXA_OP_MADD); ++ OUT_ACCEL_REG(R200_PP_TXABLEND2_0, ++ R200_TXA_CLAMP_0_1 | R200_TXA_OUTPUT_REG_R0); ++ FINISH_ACCEL(); + } - break; - } - OUTREG(RADEON_BIOS_4_SCRATCH, save->bios_4_scratch); -+ OUTREG(RADEON_BIOS_5_SCRATCH, save->bios_5_scratch); + } else { + + info->accel_state->texW[0] = 1; + info->accel_state->texH[0] = 1; + +- BEGIN_ACCEL(8); ++ BEGIN_ACCEL(9); ++ ++ OUT_ACCEL_REG(RADEON_PP_CNTL, ++ RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE); + + OUT_ACCEL_REG(RADEON_SE_VTX_FMT, (RADEON_SE_VTX_FMT_XY | + RADEON_SE_VTX_FMT_ST0)); +@@ -1672,6 +2180,20 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv + ((float)srcX + (float)srcw * (((float)dsth / (float)dstw) + 1.0)) / info->accel_state->texW[0], + (float)srcY / info->accel_state->texH[0]); + } ++ } else if (isplanar) { ++ /* ++ * Just render a rect (using three coords). ++ * Filter is a bit a misnomer, it's just texcoords... ++ */ ++ VTX_OUT_FILTER((float)dstX, (float)(dstY + dsth), ++ (float)srcX / info->accel_state->texW[0], (float)(srcY + srch) / info->accel_state->texH[0], ++ (float)srcX / info->accel_state->texW[0], (float)(srcY + srch) / info->accel_state->texH[0]); ++ VTX_OUT_FILTER((float)(dstX + dstw), (float)(dstY + dsth), ++ (float)(srcX + srcw) / info->accel_state->texW[0], (float)(srcY + srch) / info->accel_state->texH[0], ++ (float)(srcX + srcw) / info->accel_state->texW[0], (float)(srcY + srch) / info->accel_state->texH[0]); ++ VTX_OUT_FILTER((float)(dstX + dstw), (float)dstY, ++ (float)(srcX + srcw) / info->accel_state->texW[0], (float)srcY / info->accel_state->texH[0], ++ (float)(srcX + srcw) / info->accel_state->texW[0], (float)srcY / info->accel_state->texH[0]); + } else { + /* + * Just render a rect (using three coords). +diff --git a/src/radeon_tv.c b/src/radeon_tv.c +index 98e3b0a..eef45d9 100644 +--- a/src/radeon_tv.c ++++ b/src/radeon_tv.c +@@ -815,7 +815,9 @@ void RADEONInitTVRegisters(xf86OutputPtr output, RADEONSavePtr save, + save->tv_rgb_cntl = (RADEON_RGB_DITHER_EN + | RADEON_TVOUT_SCALE_EN + | (0x0b << RADEON_UVRAM_READ_MARGIN_SHIFT) +- | (0x07 << RADEON_FIFORAM_FFMACRO_READ_MARGIN_SHIFT)); ++ | (0x07 << RADEON_FIFORAM_FFMACRO_READ_MARGIN_SHIFT) ++ | RADEON_RGB_ATTEN_SEL(0x3) ++ | RADEON_RGB_ATTEN_VAL(0xc)); + + if (IsPrimary) { + if (radeon_output->Flags & RADEON_USE_RMX) +diff --git a/src/radeon_video.c b/src/radeon_video.c +index 92d1a71..42aa036 100644 +--- a/src/radeon_video.c ++++ b/src/radeon_video.c +@@ -297,22 +297,19 @@ void RADEONInitVideo(ScreenPtr pScreen) + RADEONInitOffscreenImages(pScreen); } - } +- if (info->ChipFamily != CHIP_FAMILY_RV250) { +- if ((info->ChipFamily < CHIP_FAMILY_RS400) ++ if ((info->ChipFamily < CHIP_FAMILY_RS400) + #ifdef XF86DRI +- || (info->directRenderingEnabled) ++ || (info->directRenderingEnabled) + #endif +- ) { +- texturedAdaptor = RADEONSetupImageTexturedVideo(pScreen); +- if (texturedAdaptor != NULL) { +- adaptors[num_adaptors++] = texturedAdaptor; +- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Set up textured video\n"); +- } else +- xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Failed to set up textured video\n"); ++ ) { ++ texturedAdaptor = RADEONSetupImageTexturedVideo(pScreen); ++ if (texturedAdaptor != NULL) { ++ adaptors[num_adaptors++] = texturedAdaptor; ++ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Set up textured video\n"); + } else +- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Textured video requires CP on R5xx/R6xx/R7xx/IGP\n"); ++ xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Failed to set up textured video\n"); + } else +- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Textured video disabled on RV250 due to HW bug\n"); ++ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Textured video requires CP on R5xx/R6xx/R7xx/IGP\n"); + + if(num_adaptors) + xf86XVScreenInit(pScreen, adaptors, num_adaptors); +@@ -1070,11 +1067,11 @@ static void RADEONSetTransform (ScrnInfoPtr pScrn, + OvGCr = CAdjGCr * gamma_curve_r100[gamma].OvGammaCont; + OvBCb = CAdjBCb * gamma_curve_r100[gamma].OvGammaCont; + OvBCr = CAdjBCr * gamma_curve_r100[gamma].OvGammaCont; +- OvROff = CAdjOff * gamma_curve_r100[gamma].OvGammaCont - ++ OvROff = RedAdj + CAdjOff * gamma_curve_r100[gamma].OvGammaCont - + OvLuma * Loff - (OvRCb + OvRCr) * Coff; +- OvGOff = CAdjOff * gamma_curve_r100[gamma].OvGammaCont - ++ OvGOff = GreenAdj + CAdjOff * gamma_curve_r100[gamma].OvGammaCont - + OvLuma * Loff - (OvGCb + OvGCr) * Coff; +- OvBOff = CAdjOff * gamma_curve_r100[gamma].OvGammaCont - ++ OvBOff = BlueAdj + CAdjOff * gamma_curve_r100[gamma].OvGammaCont - + OvLuma * Loff - (OvBCb + OvBCr) * Coff; + #if 0 /* default constants */ + OvROff = -888.5; +diff --git a/src/radeon_video.h b/src/radeon_video.h +index 7f1891e..34fb07f 100644 +--- a/src/radeon_video.h ++++ b/src/radeon_video.h +@@ -90,6 +90,11 @@ typedef struct { + void *video_memory; + int video_offset; + ++ Bool planar_hw; ++ Bool planar_state; ++ int planeu_offset; ++ int planev_offset; ++ + /* bicubic filtering */ + void *bicubic_memory; + int bicubic_offset; diff --git a/radeon-modeset.patch b/radeon-modeset.patch index ba8b54f..2273a51 100644 --- a/radeon-modeset.patch +++ b/radeon-modeset.patch @@ -1,5 +1,5 @@ diff --git a/configure.ac b/configure.ac -index b094a50..29a19e3 100644 +index 660ea1f..4279b60 100644 --- a/configure.ac +++ b/configure.ac @@ -114,8 +114,19 @@ if test "$DRI" = yes; then @@ -1067,7 +1067,7 @@ index 0000000..5ea904b +#endif +#endif diff --git a/src/radeon.h b/src/radeon.h -index 7bb720a..348ad3f 100644 +index d488429..09e15f4 100644 --- a/src/radeon.h +++ b/src/radeon.h @@ -46,6 +46,8 @@ @@ -1095,7 +1095,7 @@ index 7bb720a..348ad3f 100644 /* Render support */ #ifdef RENDER #include "picturestr.h" -@@ -413,6 +417,14 @@ typedef enum { +@@ -414,6 +418,14 @@ typedef enum { typedef struct _atomBiosHandle *atomBiosHandlePtr; @@ -1110,7 +1110,7 @@ index 7bb720a..348ad3f 100644 typedef struct { uint32_t pci_device_id; RADEONChipFamily chip_family; -@@ -423,7 +435,27 @@ typedef struct { +@@ -424,7 +436,27 @@ typedef struct { int singledac; } RADEONCardInfo; @@ -1138,7 +1138,7 @@ index 7bb720a..348ad3f 100644 struct radeon_cp { Bool CPRuns; /* CP is running */ Bool CPInUse; /* CP has been used by X server */ -@@ -437,6 +469,10 @@ struct radeon_cp { +@@ -438,6 +470,10 @@ struct radeon_cp { drmBufPtr indirectBuffer; int indirectStart; @@ -1149,7 +1149,7 @@ index 7bb720a..348ad3f 100644 /* Debugging info for BEGIN_RING/ADVANCE_RING pairs. */ int dma_begin_count; char *dma_debug_func; -@@ -503,13 +539,13 @@ struct radeon_dri { +@@ -504,13 +540,13 @@ struct radeon_dri { drm_handle_t ringHandle; /* Handle from drmAddMap */ drmSize ringMapSize; /* Size of map */ int ringSize; /* Size of ring (in MB) */ @@ -1165,7 +1165,7 @@ index 7bb720a..348ad3f 100644 /* CP vertex/indirect buffer data */ unsigned long bufStart; /* Offset into GART space */ -@@ -528,7 +564,6 @@ struct radeon_dri { +@@ -529,7 +565,6 @@ struct radeon_dri { drmAddress gartTex; /* Map */ int log2GARTTexGran; @@ -1173,7 +1173,7 @@ index 7bb720a..348ad3f 100644 int fbX; int fbY; int backX; -@@ -784,6 +819,7 @@ typedef struct { +@@ -789,6 +824,7 @@ typedef struct { RADEONCardType cardType; /* Current card is a PCI card */ struct radeon_cp *cp; struct radeon_dri *dri; @@ -1181,7 +1181,7 @@ index 7bb720a..348ad3f 100644 #ifdef USE_EXA Bool accelDFS; #endif -@@ -887,6 +923,45 @@ typedef struct { +@@ -892,6 +928,45 @@ typedef struct { Bool r4xx_atom; @@ -1227,7 +1227,7 @@ index 7bb720a..348ad3f 100644 } RADEONInfoRec, *RADEONInfoPtr; #define RADEONWaitForFifo(pScrn, entries) \ -@@ -1140,6 +1215,24 @@ extern void +@@ -1147,6 +1222,24 @@ extern void radeon_legacy_free_memory(ScrnInfoPtr pScrn, void *mem_struct); @@ -1252,7 +1252,7 @@ index 7bb720a..348ad3f 100644 #ifdef XF86DRI # ifdef USE_XAA /* radeon_accelfuncs.c */ -@@ -1158,7 +1251,9 @@ do { \ +@@ -1165,7 +1258,9 @@ do { \ #define RADEONCP_RELEASE(pScrn, info) \ do { \ @@ -1263,7 +1263,7 @@ index 7bb720a..348ad3f 100644 RADEON_PURGE_CACHE(); \ RADEON_WAIT_UNTIL_IDLE(); \ RADEONCPReleaseIndirect(pScrn); \ -@@ -1193,7 +1288,7 @@ do { \ +@@ -1200,7 +1295,7 @@ do { \ #define RADEONCP_REFRESH(pScrn, info) \ do { \ @@ -1272,7 +1272,7 @@ index 7bb720a..348ad3f 100644 if (info->cp->needCacheFlush) { \ RADEON_PURGE_CACHE(); \ RADEON_PURGE_ZCACHE(); \ -@@ -1220,6 +1315,13 @@ do { \ +@@ -1227,6 +1322,13 @@ do { \ #define RING_LOCALS uint32_t *__head = NULL; int __expected; int __count = 0 #define BEGIN_RING(n) do { \ @@ -1286,7 +1286,7 @@ index 7bb720a..348ad3f 100644 if (RADEON_VERBOSE) { \ xf86DrvMsg(pScrn->scrnIndex, X_INFO, \ "BEGIN_RING(%d) in %s\n", (unsigned int)n, __FUNCTION__);\ -@@ -1232,13 +1334,6 @@ do { \ +@@ -1239,13 +1341,6 @@ do { \ } \ info->cp->dma_debug_func = __FILE__; \ info->cp->dma_debug_lineno = __LINE__; \ @@ -1300,7 +1300,7 @@ index 7bb720a..348ad3f 100644 __expected = n; \ __head = (pointer)((char *)info->cp->indirectBuffer->address + \ info->cp->indirectBuffer->used); \ -@@ -1281,6 +1376,14 @@ do { \ +@@ -1288,6 +1383,14 @@ do { \ OUT_RING(val); \ } while (0) @@ -1316,7 +1316,7 @@ index 7bb720a..348ad3f 100644 do { \ if (RADEON_VERBOSE) \ diff --git a/src/radeon_accel.c b/src/radeon_accel.c -index dffbc57..1531c81 100644 +index a9a4848..9d02ac8 100644 --- a/src/radeon_accel.c +++ b/src/radeon_accel.c @@ -92,6 +92,7 @@ @@ -1590,7 +1590,7 @@ index dffbc57..1531c81 100644 #if 0 /* FIXME: pScrn->pScreen has not been initialized when this is first -@@ -694,6 +817,11 @@ void RADEONCPFlushIndirect(ScrnInfoPtr pScrn, int discard) +@@ -692,6 +815,11 @@ void RADEONCPFlushIndirect(ScrnInfoPtr pScrn, int discard) if (!buffer) return; if (start == buffer->used && !discard) return; @@ -1602,7 +1602,7 @@ index dffbc57..1531c81 100644 if (RADEON_VERBOSE) { xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Flushing buffer %d\n", buffer->idx); -@@ -749,10 +877,16 @@ void RADEONCPReleaseIndirect(ScrnInfoPtr pScrn) +@@ -750,10 +878,16 @@ void RADEONCPReleaseIndirect(ScrnInfoPtr pScrn) } } @@ -1619,7 +1619,7 @@ index dffbc57..1531c81 100644 if (RADEON_VERBOSE) { xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Releasing buffer %d\n", -@@ -879,6 +1013,7 @@ RADEONHostDataBlit( +@@ -880,6 +1014,7 @@ RADEONHostDataBlit( ret = ( uint8_t* )&__head[__count]; __count += dwords; @@ -1627,7 +1627,7 @@ index dffbc57..1531c81 100644 ADVANCE_RING(); *y += *hpass; -@@ -1013,7 +1148,7 @@ Bool RADEONAccelInit(ScreenPtr pScreen) +@@ -1014,7 +1149,7 @@ Bool RADEONAccelInit(ScreenPtr pScreen) #ifdef USE_EXA if (info->useEXA) { # ifdef XF86DRI @@ -1636,7 +1636,7 @@ index dffbc57..1531c81 100644 if (info->ChipFamily >= CHIP_FAMILY_R600) { if (!R600DrawInit(pScreen)) return FALSE; -@@ -1046,7 +1181,7 @@ Bool RADEONAccelInit(ScreenPtr pScreen) +@@ -1047,7 +1182,7 @@ Bool RADEONAccelInit(ScreenPtr pScreen) } #ifdef XF86DRI @@ -1645,7 +1645,7 @@ index dffbc57..1531c81 100644 RADEONAccelInitCP(pScreen, a); else #endif /* XF86DRI */ -@@ -1068,11 +1203,13 @@ void RADEONInit3DEngine(ScrnInfoPtr pScrn) +@@ -1069,11 +1204,13 @@ void RADEONInit3DEngine(ScrnInfoPtr pScrn) RADEONInfoPtr info = RADEONPTR (pScrn); #ifdef XF86DRI @@ -1663,7 +1663,7 @@ index dffbc57..1531c81 100644 RADEONInit3DEngineCP(pScrn); } else #endif -@@ -1080,7 +1217,7 @@ void RADEONInit3DEngine(ScrnInfoPtr pScrn) +@@ -1081,7 +1218,7 @@ void RADEONInit3DEngine(ScrnInfoPtr pScrn) info->accel_state->XInited3D = TRUE; } @@ -2403,7 +2403,7 @@ index 0000000..6d3b6fe +int radeon_bo_gem_name_buffer(dri_bo *bo, uint32_t *name); +#endif diff --git a/src/radeon_commonfuncs.c b/src/radeon_commonfuncs.c -index eabd87d..8712a74 100644 +index a9bc7d2..6c22339 100644 --- a/src/radeon_commonfuncs.c +++ b/src/radeon_commonfuncs.c @@ -62,12 +62,15 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn) @@ -2601,7 +2601,7 @@ index 0fcdcf0..cbc188b 100644 CURSOR_SWAPPING_START(); diff --git a/src/radeon_dri.c b/src/radeon_dri.c -index 9c9fc7f..aa6352e 100644 +index f6c6261..1699d8a 100644 --- a/src/radeon_dri.c +++ b/src/radeon_dri.c @@ -40,6 +40,8 @@ @@ -2845,7 +2845,7 @@ index 9c9fc7f..aa6352e 100644 } /* AGP Mode Quirk List - Certain hostbridge/gfx-card combos don't work with -@@ -990,6 +1146,8 @@ static Bool RADEONDRIAgpInit(RADEONInfoPtr info, ScreenPtr pScreen) +@@ -992,6 +1148,8 @@ static Bool RADEONDRIAgpInit(RADEONInfoPtr info, ScreenPtr pScreen) "[agp] ring handle = 0x%08x\n", (unsigned int)info->dri->ringHandle); @@ -2854,7 +2854,7 @@ index 9c9fc7f..aa6352e 100644 if (drmMap(info->dri->drmFD, info->dri->ringHandle, info->dri->ringMapSize, &info->dri->ring) < 0) { xf86DrvMsg(pScreen->myNum, X_ERROR, "[agp] Could not map ring\n"); -@@ -998,9 +1156,10 @@ static Bool RADEONDRIAgpInit(RADEONInfoPtr info, ScreenPtr pScreen) +@@ -1000,9 +1158,10 @@ static Bool RADEONDRIAgpInit(RADEONInfoPtr info, ScreenPtr pScreen) xf86DrvMsg(pScreen->myNum, X_INFO, "[agp] Ring mapped at 0x%08lx\n", (unsigned long)info->dri->ring); @@ -2866,7 +2866,7 @@ index 9c9fc7f..aa6352e 100644 xf86DrvMsg(pScreen->myNum, X_ERROR, "[agp] Could not add ring read ptr mapping\n"); return FALSE; -@@ -1009,6 +1168,8 @@ static Bool RADEONDRIAgpInit(RADEONInfoPtr info, ScreenPtr pScreen) +@@ -1011,6 +1170,8 @@ static Bool RADEONDRIAgpInit(RADEONInfoPtr info, ScreenPtr pScreen) "[agp] ring read ptr handle = 0x%08x\n", (unsigned int)info->dri->ringReadPtrHandle); @@ -2875,7 +2875,7 @@ index 9c9fc7f..aa6352e 100644 if (drmMap(info->dri->drmFD, info->dri->ringReadPtrHandle, info->dri->ringReadMapSize, &info->dri->ringReadPtr) < 0) { xf86DrvMsg(pScreen->myNum, X_ERROR, -@@ -1018,6 +1179,7 @@ static Bool RADEONDRIAgpInit(RADEONInfoPtr info, ScreenPtr pScreen) +@@ -1020,6 +1181,7 @@ static Bool RADEONDRIAgpInit(RADEONInfoPtr info, ScreenPtr pScreen) xf86DrvMsg(pScreen->myNum, X_INFO, "[agp] Ring read ptr mapped at 0x%08lx\n", (unsigned long)info->dri->ringReadPtr); @@ -2883,7 +2883,7 @@ index 9c9fc7f..aa6352e 100644 if (drmAddMap(info->dri->drmFD, info->dri->bufStart, info->dri->bufMapSize, DRM_AGP, 0, &info->dri->bufHandle) < 0) { -@@ -1095,6 +1257,7 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info, ScreenPtr pScreen) +@@ -1097,6 +1259,7 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info, ScreenPtr pScreen) "[pci] ring handle = 0x%08x\n", (unsigned int)info->dri->ringHandle); @@ -2891,7 +2891,7 @@ index 9c9fc7f..aa6352e 100644 if (drmMap(info->dri->drmFD, info->dri->ringHandle, info->dri->ringMapSize, &info->dri->ring) < 0) { xf86DrvMsg(pScreen->myNum, X_ERROR, "[pci] Could not map ring\n"); -@@ -1106,6 +1269,7 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info, ScreenPtr pScreen) +@@ -1108,6 +1271,7 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info, ScreenPtr pScreen) xf86DrvMsg(pScreen->myNum, X_INFO, "[pci] Ring contents 0x%08lx\n", *(unsigned long *)(pointer)info->dri->ring); @@ -2899,7 +2899,7 @@ index 9c9fc7f..aa6352e 100644 if (drmAddMap(info->dri->drmFD, info->dri->ringReadOffset, info->dri->ringReadMapSize, DRM_SCATTER_GATHER, flags, &info->dri->ringReadPtrHandle) < 0) { -@@ -1117,8 +1281,10 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info, ScreenPtr pScreen) +@@ -1119,8 +1283,10 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info, ScreenPtr pScreen) "[pci] ring read ptr handle = 0x%08x\n", (unsigned int)info->dri->ringReadPtrHandle); @@ -2910,7 +2910,7 @@ index 9c9fc7f..aa6352e 100644 xf86DrvMsg(pScreen->myNum, X_ERROR, "[pci] Could not map ring read ptr\n"); return FALSE; -@@ -1129,6 +1295,7 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info, ScreenPtr pScreen) +@@ -1131,6 +1297,7 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info, ScreenPtr pScreen) xf86DrvMsg(pScreen->myNum, X_INFO, "[pci] Ring read ptr contents 0x%08lx\n", *(unsigned long *)(pointer)info->dri->ringReadPtr); @@ -2918,7 +2918,7 @@ index 9c9fc7f..aa6352e 100644 if (drmAddMap(info->dri->drmFD, info->dri->bufStart, info->dri->bufMapSize, DRM_SCATTER_GATHER, 0, &info->dri->bufHandle) < 0) { -@@ -1181,6 +1348,9 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info, ScreenPtr pScreen) +@@ -1183,6 +1350,9 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info, ScreenPtr pScreen) */ static Bool RADEONDRIMapInit(RADEONInfoPtr info, ScreenPtr pScreen) { @@ -2928,7 +2928,7 @@ index 9c9fc7f..aa6352e 100644 /* Map registers */ info->dri->registerSize = info->MMIOSize; if (drmAddMap(info->dri->drmFD, info->MMIOAddr, info->dri->registerSize, -@@ -1221,20 +1391,23 @@ static int RADEONDRIKernelInit(RADEONInfoPtr info, ScreenPtr pScreen) +@@ -1223,20 +1393,23 @@ static int RADEONDRIKernelInit(RADEONInfoPtr info, ScreenPtr pScreen) drmInfo.fb_bpp = info->CurrentLayout.pixel_code; drmInfo.depth_bpp = (info->dri->depthBits - 8) * 2; @@ -2966,7 +2966,7 @@ index 9c9fc7f..aa6352e 100644 if (drmCommandWrite(info->dri->drmFD, DRM_RADEON_CP_INIT, &drmInfo, sizeof(drm_radeon_init_t)) < 0) return FALSE; -@@ -1243,8 +1416,9 @@ static int RADEONDRIKernelInit(RADEONInfoPtr info, ScreenPtr pScreen) +@@ -1245,8 +1418,9 @@ static int RADEONDRIKernelInit(RADEONInfoPtr info, ScreenPtr pScreen) * registers back to their default values, so we need to restore * those engine register here. */ @@ -2978,7 +2978,7 @@ index 9c9fc7f..aa6352e 100644 return TRUE; } -@@ -1442,12 +1616,11 @@ Bool RADEONDRIGetVersion(ScrnInfoPtr pScrn) +@@ -1444,12 +1618,11 @@ Bool RADEONDRIGetVersion(ScrnInfoPtr pScrn) /* Get DRM version & close DRM */ info->dri->pKernelDRMVersion = drmGetVersion(fd); @@ -2992,7 +2992,7 @@ index 9c9fc7f..aa6352e 100644 } /* Now check if we qualify */ -@@ -1481,10 +1654,29 @@ Bool RADEONDRIGetVersion(ScrnInfoPtr pScrn) +@@ -1483,10 +1656,29 @@ Bool RADEONDRIGetVersion(ScrnInfoPtr pScrn) req_patch); drmFreeVersion(info->dri->pKernelDRMVersion); info->dri->pKernelDRMVersion = NULL; @@ -3023,7 +3023,7 @@ index 9c9fc7f..aa6352e 100644 } Bool RADEONDRISetVBlankInterrupt(ScrnInfoPtr pScrn, Bool on) -@@ -1493,6 +1685,9 @@ Bool RADEONDRISetVBlankInterrupt(ScrnInfoPtr pScrn, Bool on) +@@ -1495,6 +1687,9 @@ Bool RADEONDRISetVBlankInterrupt(ScrnInfoPtr pScrn, Bool on) xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); int value = 0; @@ -3033,7 +3033,7 @@ index 9c9fc7f..aa6352e 100644 if (!info->want_vblank_interrupts) on = FALSE; -@@ -1512,6 +1707,52 @@ Bool RADEONDRISetVBlankInterrupt(ScrnInfoPtr pScrn, Bool on) +@@ -1514,6 +1709,52 @@ Bool RADEONDRISetVBlankInterrupt(ScrnInfoPtr pScrn, Bool on) return TRUE; } @@ -3086,7 +3086,7 @@ index 9c9fc7f..aa6352e 100644 /* Initialize the screen-specific data structures for the DRI and the * Radeon. This is the main entry point to the device-specific -@@ -1575,10 +1816,22 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen) +@@ -1577,10 +1818,22 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen) pDRIInfo->ddxDriverMajorVersion = info->allowColorTiling ? 5 : 4; pDRIInfo->ddxDriverMinorVersion = 3; pDRIInfo->ddxDriverPatchVersion = 0; @@ -3113,7 +3113,7 @@ index 9c9fc7f..aa6352e 100644 pDRIInfo->ddxDrawableTableEntry = RADEON_MAX_DRAWABLES; pDRIInfo->maxDrawableTableEntry = (SAREA_MAX_DRAWABLES < RADEON_MAX_DRAWABLES -@@ -1631,9 +1884,7 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen) +@@ -1633,9 +1886,7 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen) pDRIInfo->TransitionTo3d = RADEONDRITransitionTo3d; pDRIInfo->TransitionSingleToMulti3D = RADEONDRITransitionSingleToMulti3d; pDRIInfo->TransitionMultiToSingle3D = RADEONDRITransitionMultiToSingle3d; @@ -3124,7 +3124,7 @@ index 9c9fc7f..aa6352e 100644 pDRIInfo->ClipNotify = RADEONDRIClipNotify; #endif -@@ -1665,57 +1916,60 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen) +@@ -1667,57 +1918,60 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen) pDRIInfo = NULL; return FALSE; } @@ -3229,7 +3229,7 @@ index 9c9fc7f..aa6352e 100644 static Bool RADEONDRIDoCloseScreen(int scrnIndex, ScreenPtr pScreen) { ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; -@@ -1757,17 +2011,21 @@ Bool RADEONDRIFinishScreenInit(ScreenPtr pScreen) +@@ -1759,17 +2013,21 @@ Bool RADEONDRIFinishScreenInit(ScreenPtr pScreen) return FALSE; } @@ -3259,7 +3259,7 @@ index 9c9fc7f..aa6352e 100644 /* Initialize and start the CP if required */ RADEONDRICPInit(pScrn); -@@ -1776,6 +2034,10 @@ Bool RADEONDRIFinishScreenInit(ScreenPtr pScreen) +@@ -1778,6 +2036,10 @@ Bool RADEONDRIFinishScreenInit(ScreenPtr pScreen) pSAREAPriv = (drm_radeon_sarea_t*)DRIGetSAREAPrivate(pScreen); memset(pSAREAPriv, 0, sizeof(*pSAREAPriv)); @@ -3270,7 +3270,7 @@ index 9c9fc7f..aa6352e 100644 pRADEONDRI = (RADEONDRIPtr)info->dri->pDRIInfo->devPrivate; pRADEONDRI->deviceID = info->Chipset; -@@ -1933,6 +2195,8 @@ void RADEONDRICloseScreen(ScreenPtr pScreen) +@@ -1935,6 +2197,8 @@ void RADEONDRICloseScreen(ScreenPtr pScreen) drmUnmap(info->dri->buf, info->dri->bufMapSize); info->dri->buf = NULL; } @@ -3279,7 +3279,7 @@ index 9c9fc7f..aa6352e 100644 if (info->dri->ringReadPtr) { drmUnmap(info->dri->ringReadPtr, info->dri->ringReadMapSize); info->dri->ringReadPtr = NULL; -@@ -1941,6 +2205,7 @@ void RADEONDRICloseScreen(ScreenPtr pScreen) +@@ -1943,6 +2207,7 @@ void RADEONDRICloseScreen(ScreenPtr pScreen) drmUnmap(info->dri->ring, info->dri->ringMapSize); info->dri->ring = NULL; } @@ -3287,7 +3287,7 @@ index 9c9fc7f..aa6352e 100644 if (info->dri->agpMemHandle != DRM_AGP_NO_HANDLE) { drmAgpUnbind(info->dri->drmFD, info->dri->agpMemHandle); drmAgpFree(info->dri->drmFD, info->dri->agpMemHandle); -@@ -2350,3 +2615,11 @@ int RADEONDRISetParam(ScrnInfoPtr pScrn, unsigned int param, int64_t value) +@@ -2352,3 +2617,11 @@ int RADEONDRISetParam(ScrnInfoPtr pScrn, unsigned int param, int64_t value) &radeonsetparam, sizeof(drm_radeon_setparam_t)); return ret; } @@ -4058,7 +4058,7 @@ index 0000000..a19d7ec + +#endif diff --git a/src/radeon_driver.c b/src/radeon_driver.c -index c0f5e7b..aa60074 100644 +index 8673f5e..8d04d92 100644 --- a/src/radeon_driver.c +++ b/src/radeon_driver.c @@ -67,7 +67,7 @@ @@ -4070,7 +4070,7 @@ index c0f5e7b..aa60074 100644 /* Driver data structures */ #include "radeon.h" #include "radeon_reg.h" -@@ -226,7 +226,10 @@ radeonShadowWindow(ScreenPtr screen, CARD32 row, CARD32 offset, int mode, +@@ -229,7 +229,10 @@ radeonShadowWindow(ScreenPtr screen, CARD32 row, CARD32 offset, int mode, stride = (pScrn->displayWidth * pScrn->bitsPerPixel) / 8; *size = stride; @@ -4082,7 +4082,7 @@ index c0f5e7b..aa60074 100644 } static Bool RADEONCreateScreenResources (ScreenPtr pScreen) -@@ -247,6 +250,13 @@ RADEONCreateScreenResources (ScreenPtr pScreen) +@@ -250,6 +253,13 @@ RADEONCreateScreenResources (ScreenPtr pScreen) radeonShadowWindow, 0, NULL)) return FALSE; } @@ -4096,7 +4096,7 @@ index c0f5e7b..aa60074 100644 return TRUE; } -@@ -1658,6 +1668,7 @@ static Bool RADEONPreInitVRAM(ScrnInfoPtr pScrn) +@@ -1695,6 +1705,7 @@ static Bool RADEONPreInitVRAM(ScrnInfoPtr pScrn) } pScrn->videoRam &= ~1023; @@ -4104,7 +4104,7 @@ index c0f5e7b..aa60074 100644 info->FbMapSize = pScrn->videoRam * 1024; /* if the card is PCI Express reserve the last 32k for the gart table */ -@@ -1787,59 +1798,61 @@ static Bool RADEONPreInitChipType(ScrnInfoPtr pScrn) +@@ -1824,59 +1835,61 @@ static Bool RADEONPreInitChipType(ScrnInfoPtr pScrn) "R500 support is under development. Please report any issues to xorg-driver-ati@lists.x.org\n"); } @@ -4211,7 +4211,7 @@ index c0f5e7b..aa60074 100644 #ifdef XF86DRI /* AGP/PCI */ -@@ -2014,6 +2027,15 @@ static Bool RADEONPreInitAccel(ScrnInfoPtr pScrn) +@@ -2051,6 +2064,15 @@ static Bool RADEONPreInitAccel(ScrnInfoPtr pScrn) } info->accel_state->fifo_slots = 0; @@ -4227,7 +4227,7 @@ index c0f5e7b..aa60074 100644 if ((info->ChipFamily == CHIP_FAMILY_RS100) || (info->ChipFamily == CHIP_FAMILY_RS200) || (info->ChipFamily == CHIP_FAMILY_RS300) || -@@ -2038,6 +2060,9 @@ static Bool RADEONPreInitAccel(ScrnInfoPtr pScrn) +@@ -2075,6 +2097,9 @@ static Bool RADEONPreInitAccel(ScrnInfoPtr pScrn) if (!xf86ReturnOptValBool(info->Options, OPTION_NOACCEL, FALSE)) { int errmaj = 0, errmin = 0; @@ -4237,7 +4237,7 @@ index c0f5e7b..aa60074 100644 from = X_DEFAULT; #if defined(USE_EXA) #if defined(USE_XAA) -@@ -2048,6 +2073,7 @@ static Bool RADEONPreInitAccel(ScrnInfoPtr pScrn) +@@ -2085,6 +2110,7 @@ static Bool RADEONPreInitAccel(ScrnInfoPtr pScrn) info->useEXA = TRUE; } else if (xf86NameCmp(optstr, "XAA") == 0) { from = X_CONFIG; @@ -4245,7 +4245,7 @@ index c0f5e7b..aa60074 100644 } } #else /* USE_XAA */ -@@ -2151,15 +2177,9 @@ static Bool RADEONPreInitInt10(ScrnInfoPtr pScrn, xf86Int10InfoPtr *ppInt10) +@@ -2189,15 +2215,9 @@ static Bool RADEONPreInitInt10(ScrnInfoPtr pScrn, xf86Int10InfoPtr *ppInt10) return TRUE; } @@ -4262,7 +4262,7 @@ index c0f5e7b..aa60074 100644 if (!(info->dri = xcalloc(1, sizeof(struct radeon_dri)))) { xf86DrvMsg(pScrn->scrnIndex, X_ERROR,"Unable to allocate dri rec!\n"); -@@ -2170,6 +2190,22 @@ static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn) +@@ -2208,6 +2228,22 @@ static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn) xf86DrvMsg(pScrn->scrnIndex, X_ERROR,"Unable to allocate cp rec!\n"); return FALSE; } @@ -4285,7 +4285,7 @@ index c0f5e7b..aa60074 100644 info->cp->CPInUse = FALSE; info->cp->CPStarted = FALSE; info->cp->CPusecTimeout = RADEON_DEFAULT_CP_TIMEOUT; -@@ -2727,6 +2763,37 @@ static const xf86CrtcConfigFuncsRec RADEONCRTCResizeFuncs = { +@@ -2771,6 +2807,37 @@ static const xf86CrtcConfigFuncsRec RADEONCRTCResizeFuncs = { RADEONCRTCResize }; @@ -4323,7 +4323,7 @@ index c0f5e7b..aa60074 100644 Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) { xf86CrtcConfigPtr xf86_config; -@@ -2747,6 +2814,8 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) +@@ -2791,6 +2858,8 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) info = RADEONPTR(pScrn); info->MMIO = NULL; @@ -4332,7 +4332,7 @@ index c0f5e7b..aa60074 100644 info->IsSecondary = FALSE; info->IsPrimary = FALSE; -@@ -2781,62 +2850,63 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) +@@ -2825,62 +2894,63 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) } info->PciInfo = xf86GetPciInfoForEntity(info->pEnt->index); @@ -4443,7 +4443,7 @@ index c0f5e7b..aa60074 100644 if (xf86RegisterResources(info->pEnt->index, 0, ResExclusive)) goto fail; -@@ -2846,10 +2916,12 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) +@@ -2890,10 +2960,12 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) pScrn->racMemFlags = RAC_FB | RAC_COLORMAP | RAC_VIEWPORT | RAC_CURSOR; pScrn->monitor = pScrn->confScreen->monitor; @@ -4460,7 +4460,7 @@ index c0f5e7b..aa60074 100644 if (!RADEONPreInitVisual(pScrn)) goto fail; -@@ -2863,164 +2935,224 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) +@@ -2907,167 +2979,227 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) memcpy(info->Options, RADEONOptions, sizeof(RADEONOptions)); xf86ProcessOptions(pScrn->scrnIndex, pScrn->options, info->Options); @@ -4561,6 +4561,11 @@ index c0f5e7b..aa60074 100644 + + RADEONPostInt10Check(pScrn, int10_save); +- /* Save BIOS scratch registers */ +- RADEONSaveBIOSRegisters(pScrn, info->SavedReg); ++ /* Save BIOS scratch registers */ ++ RADEONSaveBIOSRegisters(pScrn, info->SavedReg); + + if (!RADEONPreInitBIOS(pScrn, pInt10)) + goto fail; #ifdef XF86DRI @@ -4812,7 +4817,7 @@ index c0f5e7b..aa60074 100644 /* Get ScreenInit function */ if (!xf86LoadSubModule(pScrn, "fb")) return FALSE; -@@ -3035,10 +3167,12 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) +@@ -3082,10 +3214,12 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) if (!RADEONPreInitXv(pScrn)) goto fail; } @@ -4829,7 +4834,7 @@ index c0f5e7b..aa60074 100644 } if (pScrn->modes == NULL) { -@@ -3191,6 +3325,9 @@ static void RADEONBlockHandler(int i, pointer blockData, +@@ -3238,6 +3372,9 @@ static void RADEONBlockHandler(int i, pointer blockData, #ifdef USE_EXA info->accel_state->engineMode = EXA_ENGINEMODE_UNKNOWN; @@ -4839,7 +4844,7 @@ index c0f5e7b..aa60074 100644 #endif } -@@ -3279,7 +3416,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3326,7 +3463,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, int subPixelOrder = SubPixelUnknown; char* s; #endif @@ -4848,7 +4853,7 @@ index c0f5e7b..aa60074 100644 info->accelOn = FALSE; #ifdef USE_XAA -@@ -3299,58 +3436,61 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3346,58 +3483,61 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, "RADEONScreenInit %lx %ld\n", pScrn->memPhysBase, pScrn->fbOffset); #endif @@ -4949,7 +4954,7 @@ index c0f5e7b..aa60074 100644 /* Visual setup */ miClearVisualTypes(); if (!miSetVisualTypes(pScrn->depth, -@@ -3384,19 +3524,21 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3431,19 +3571,21 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, hasDRI = info->directRenderingEnabled; #endif /* XF86DRI */ @@ -4983,7 +4988,7 @@ index c0f5e7b..aa60074 100644 } } -@@ -3433,7 +3575,10 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3480,7 +3622,10 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, #ifdef XF86DRI if (hasDRI) { info->accelDFS = xf86ReturnOptValBool(info->Options, OPTION_ACCEL_DFS, @@ -4995,7 +5000,7 @@ index c0f5e7b..aa60074 100644 /* Reserve approx. half of offscreen memory for local textures by * default, can be overridden with Option "FBTexPercent". -@@ -3459,7 +3604,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3506,7 +3651,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, #endif #if defined(XF86DRI) && defined(USE_XAA) @@ -5004,7 +5009,7 @@ index c0f5e7b..aa60074 100644 info->dri->textureSize = -1; if (xf86GetOptValInteger(info->Options, OPTION_FBTEX_PERCENT, &(info->dri->textureSize))) { -@@ -3477,7 +3622,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3524,7 +3669,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, #endif #ifdef USE_XAA @@ -5013,7 +5018,7 @@ index c0f5e7b..aa60074 100644 return FALSE; #endif -@@ -3498,7 +3643,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3545,7 +3690,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, info->CurrentLayout.pixel_bytes); int maxy = info->FbMapSize / width_bytes; @@ -5022,7 +5027,7 @@ index c0f5e7b..aa60074 100644 xf86DrvMsg(scrnIndex, X_ERROR, "Static buffer allocation failed. Disabling DRI.\n"); xf86DrvMsg(scrnIndex, X_ERROR, -@@ -3508,19 +3653,54 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3555,19 +3700,54 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, info->CurrentLayout.pixel_bytes * 3 + 1023) / 1024); info->directRenderingEnabled = FALSE; } else { @@ -5081,7 +5086,7 @@ index c0f5e7b..aa60074 100644 #endif xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, "Initializing fb layer\n"); -@@ -3544,7 +3724,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3591,7 +3771,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, if (info->r600_shadow_fb == FALSE) { /* Init fb layer */ @@ -5090,7 +5095,7 @@ index c0f5e7b..aa60074 100644 pScrn->virtualX, pScrn->virtualY, pScrn->xDpi, pScrn->yDpi, pScrn->displayWidth, pScrn->bitsPerPixel)) -@@ -3586,8 +3766,10 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3633,8 +3813,10 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, /* restore the memory map here otherwise we may get a hang when * initializing the drm below */ @@ -5103,7 +5108,7 @@ index c0f5e7b..aa60074 100644 /* Backing store setup */ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, -@@ -3597,7 +3779,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3644,7 +3826,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, /* DRI finalisation */ #ifdef XF86DRI @@ -5112,7 +5117,7 @@ index c0f5e7b..aa60074 100644 info->dri->pKernelDRMVersion->version_minor >= 19) { if (RADEONDRISetParam(pScrn, RADEON_SETPARAM_PCIGART_LOCATION, info->dri->pciGartOffset) < 0) -@@ -3613,14 +3795,24 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3660,14 +3842,24 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, if (info->directRenderingEnabled) { xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, "DRI Finishing init !\n"); @@ -5138,7 +5143,7 @@ index c0f5e7b..aa60074 100644 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Direct rendering enabled\n"); -@@ -3716,10 +3908,16 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3763,10 +3955,16 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, return FALSE; } } @@ -5148,15 +5153,15 @@ index c0f5e7b..aa60074 100644 - if (!xf86SetDesiredModes (pScrn)) + if (info->drm_mode_setting) { + if (!drmmode_set_desired_modes(pScrn, &info->drmmode)) -+ return FALSE; + return FALSE; + } else { + if (!xf86SetDesiredModes (pScrn)) - return FALSE; ++ return FALSE; + } /* Provide SaveScreen & wrap BlockHandler and CloseScreen */ /* Wrap CloseScreen */ -@@ -5296,7 +5494,7 @@ Bool RADEONSwitchMode(int scrnIndex, DisplayModePtr mode, int flags) +@@ -5336,7 +5534,7 @@ Bool RADEONSwitchMode(int scrnIndex, DisplayModePtr mode, int flags) #ifdef XF86DRI Bool CPStarted = info->cp->CPStarted; @@ -5165,7 +5170,7 @@ index c0f5e7b..aa60074 100644 DRILock(pScrn->pScreen, 0); RADEONCP_STOP(pScrn, info); } -@@ -5319,8 +5517,10 @@ Bool RADEONSwitchMode(int scrnIndex, DisplayModePtr mode, int flags) +@@ -5359,8 +5557,10 @@ Bool RADEONSwitchMode(int scrnIndex, DisplayModePtr mode, int flags) #endif } @@ -5178,7 +5183,7 @@ index c0f5e7b..aa60074 100644 ret = xf86SetSingleMode (pScrn, mode, RR_Rotate_0); -@@ -5332,16 +5532,19 @@ Bool RADEONSwitchMode(int scrnIndex, DisplayModePtr mode, int flags) +@@ -5372,16 +5572,19 @@ Bool RADEONSwitchMode(int scrnIndex, DisplayModePtr mode, int flags) /* xf86SetRootClip would do, but can't access that here */ } @@ -5206,7 +5211,7 @@ index c0f5e7b..aa60074 100644 } #endif -@@ -5539,6 +5742,11 @@ void RADEONAdjustFrame(int scrnIndex, int x, int y, int flags) +@@ -5579,6 +5782,11 @@ void RADEONAdjustFrame(int scrnIndex, int x, int y, int flags) xf86OutputPtr output = config->output[config->compat_output]; xf86CrtcPtr crtc = output->crtc; @@ -5218,7 +5223,7 @@ index c0f5e7b..aa60074 100644 /* not handled */ if (IS_AVIVO_VARIANT) return; -@@ -5578,76 +5786,101 @@ Bool RADEONEnterVT(int scrnIndex, int flags) +@@ -5618,76 +5826,101 @@ Bool RADEONEnterVT(int scrnIndex, int flags) xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, "RADEONEnterVT\n"); @@ -5370,7 +5375,7 @@ index c0f5e7b..aa60074 100644 } #endif /* this will get XVideo going again, but only if XVideo was initialised -@@ -5662,7 +5895,7 @@ Bool RADEONEnterVT(int scrnIndex, int flags) +@@ -5702,7 +5935,7 @@ Bool RADEONEnterVT(int scrnIndex, int flags) info->accel_state->XInited3D = FALSE; #ifdef XF86DRI @@ -5379,7 +5384,7 @@ index c0f5e7b..aa60074 100644 if (info->ChipFamily >= CHIP_FAMILY_R600) R600LoadShaders(pScrn); RADEONCP_START(pScrn, info); -@@ -5686,27 +5919,29 @@ void RADEONLeaveVT(int scrnIndex, int flags) +@@ -5726,27 +5959,29 @@ void RADEONLeaveVT(int scrnIndex, int flags) xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, "RADEONLeaveVT\n"); #ifdef XF86DRI @@ -5425,7 +5430,7 @@ index c0f5e7b..aa60074 100644 /* Make sure 3D clients will re-upload textures to video RAM */ if (info->dri->textureSize) { -@@ -5722,6 +5957,11 @@ void RADEONLeaveVT(int scrnIndex, int flags) +@@ -5762,6 +5997,11 @@ void RADEONLeaveVT(int scrnIndex, int flags) i = list[i].next; } while (i != 0); } @@ -5437,7 +5442,7 @@ index c0f5e7b..aa60074 100644 } #endif -@@ -5748,10 +5988,18 @@ void RADEONLeaveVT(int scrnIndex, int flags) +@@ -5788,10 +6028,18 @@ void RADEONLeaveVT(int scrnIndex, int flags) xf86_hide_cursors (pScrn); @@ -5459,7 +5464,7 @@ index c0f5e7b..aa60074 100644 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, "Ok, leaving now...\n"); -@@ -5805,7 +6053,8 @@ static Bool RADEONCloseScreen(int scrnIndex, ScreenPtr pScreen) +@@ -5845,7 +6093,8 @@ static Bool RADEONCloseScreen(int scrnIndex, ScreenPtr pScreen) #endif /* USE_XAA */ if (pScrn->vtSema) { @@ -5469,7 +5474,7 @@ index c0f5e7b..aa60074 100644 } xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, -@@ -5840,6 +6089,12 @@ static Bool RADEONCloseScreen(int scrnIndex, ScreenPtr pScreen) +@@ -5880,6 +6129,12 @@ static Bool RADEONCloseScreen(int scrnIndex, ScreenPtr pScreen) info->DGAModes = NULL; xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, "Unmapping memory\n"); @@ -7965,7 +7970,7 @@ index 0000000..67868cc + + diff --git a/src/radeon_probe.h b/src/radeon_probe.h -index afc8e21..6138f36 100644 +index a0c6b2c..30fee18 100644 --- a/src/radeon_probe.h +++ b/src/radeon_probe.h @@ -146,6 +146,27 @@ typedef struct @@ -8006,7 +8011,7 @@ index afc8e21..6138f36 100644 typedef struct _radeon_encoder { diff --git a/src/radeon_textured_video.c b/src/radeon_textured_video.c -index 2df299f..ff16f26 100644 +index 79671c0..1ef8dc3 100644 --- a/src/radeon_textured_video.c +++ b/src/radeon_textured_video.c @@ -40,6 +40,7 @@ @@ -8017,7 +8022,7 @@ index 2df299f..ff16f26 100644 #include #include "fourcc.h" -@@ -124,6 +125,7 @@ static __inline__ uint32_t F_TO_24(float val) +@@ -133,6 +134,7 @@ static __inline__ uint32_t float4touint(float fr, float fg, float fb, float fa) #define BEGIN_ACCEL(n) RADEONWaitForFifo(pScrn, (n)) #define OUT_ACCEL_REG(reg, val) OUTREG(reg, val) #define OUT_ACCEL_REG_F(reg, val) OUTREG(reg, F_TO_DW(val)) @@ -8025,7 +8030,7 @@ index 2df299f..ff16f26 100644 #define FINISH_ACCEL() #include "radeon_textured_videofuncs.c" -@@ -133,6 +135,7 @@ static __inline__ uint32_t F_TO_24(float val) +@@ -142,6 +144,7 @@ static __inline__ uint32_t float4touint(float fr, float fg, float fb, float fa) #undef BEGIN_ACCEL #undef OUT_ACCEL_REG #undef OUT_ACCEL_REG_F @@ -8033,7 +8038,7 @@ index 2df299f..ff16f26 100644 #undef FINISH_ACCEL #ifdef XF86DRI -@@ -146,6 +149,7 @@ static __inline__ uint32_t F_TO_24(float val) +@@ -155,6 +158,7 @@ static __inline__ uint32_t float4touint(float fr, float fg, float fb, float fa) #define OUT_ACCEL_REG_F(reg, val) OUT_ACCEL_REG(reg, F_TO_DW(val)) #define FINISH_ACCEL() ADVANCE_RING() #define OUT_RING_F(x) OUT_RING(F_TO_DW(x)) @@ -8041,7 +8046,7 @@ index 2df299f..ff16f26 100644 #include "radeon_textured_videofuncs.c" -@@ -374,6 +378,9 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn, +@@ -412,6 +416,9 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn, size * 2, 64); if (pPriv->video_offset == 0) return BadAlloc; @@ -8050,8 +8055,8 @@ index 2df299f..ff16f26 100644 + pPriv->src_bo = pPriv->video_memory; } - /* Bicubic filter setup */ -@@ -397,6 +404,9 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn, + /* Bicubic filter loading */ +@@ -422,6 +429,9 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn, pPriv->bicubic_src_offset = pPriv->bicubic_offset + info->fbLocation + pScrn->fbOffset; if (pPriv->bicubic_offset == 0) pPriv->bicubic_enabled = FALSE; @@ -8061,7 +8066,7 @@ index 2df299f..ff16f26 100644 } if (pDraw->type == DRAWABLE_WINDOW) -@@ -426,11 +436,22 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn, +@@ -451,11 +461,22 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn, left = (x1 >> 16) & ~1; npixels = ((((x2 + 0xffff) >> 16) + 1) & ~1) - left; @@ -8087,9 +8092,9 @@ index 2df299f..ff16f26 100644 + pPriv->src_addr = (uint8_t *)(info->FB + pPriv->video_offset + (top * dstPitch)); + } pPriv->src_pitch = dstPitch; - pPriv->size = size; - pPriv->pDraw = pDraw; -@@ -511,9 +532,24 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn, + pPriv->planeu_offset = dstPitch * dst_height; + pPriv->planev_offset = pPriv->planeu_offset + dstPitch2 * ((dst_height + 1) >> 1); +@@ -566,9 +587,24 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn, /* Upload bicubic filter tex */ if (pPriv->bicubic_enabled) { @@ -8117,7 +8122,7 @@ index 2df299f..ff16f26 100644 } /* update cliplist */ -@@ -531,10 +567,12 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn, +@@ -586,10 +622,12 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn, pPriv->w = width; pPriv->h = height; @@ -8132,10 +8137,24 @@ index 2df299f..ff16f26 100644 else #endif diff --git a/src/radeon_textured_videofuncs.c b/src/radeon_textured_videofuncs.c -index f55ae12..5d23ad9 100644 +index 05acb93..b7a8513 100644 --- a/src/radeon_textured_videofuncs.c +++ b/src/radeon_textured_videofuncs.c -@@ -92,6 +92,11 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv +@@ -87,11 +87,25 @@ do { \ + + #endif /* !ACCEL_CP */ + ++#define OUT_TEXTURE_REG(reg, offset, bo) do { \ ++ if (info->new_cs) { \ ++ OUT_ACCEL_REG((reg), (offset)); \ ++ OUT_RELOC((bo), RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0); \ ++ } else { \ ++ OUT_ACCEL_REG((reg), (offset) + info->fbLocation + pScrn->fbOffset);} \ ++ } while(0) ++ ++ + static void + FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) { RADEONInfoPtr info = RADEONPTR(pScrn); PixmapPtr pPixmap = pPriv->pPixmap; @@ -8147,7 +8166,7 @@ index f55ae12..5d23ad9 100644 uint32_t txformat; uint32_t txfilter, txformat0, txformat1, txoffset, txpitch; uint32_t dst_offset, dst_pitch, dst_format; -@@ -100,19 +105,57 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv +@@ -101,19 +115,57 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv int dstxoff, dstyoff, pixel_shift, vtx_count; BoxPtr pBox = REGION_RECTS(&pPriv->clip); int nBox = REGION_NUM_RECTS(&pPriv->clip); @@ -8208,7 +8227,7 @@ index f55ae12..5d23ad9 100644 dst_pitch = pPixmap->devKind; } -@@ -143,7 +186,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv +@@ -144,7 +196,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv RADEON_WAIT_DMA_GUI_IDLE); FINISH_ACCEL(); @@ -8217,9 +8236,15 @@ index f55ae12..5d23ad9 100644 RADEONInit3DEngine(pScrn); } -@@ -213,13 +256,20 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv +@@ -222,15 +274,19 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv + if (IS_R500_3D && ((pPriv->h - 1) & 0x800)) + txpitch |= R500_TXHEIGHT_11; - txoffset = pPriv->src_offset; +- txoffset = pPriv->src_offset; ++ if (info->new_cs) ++ txoffset = 0; ++ else ++ txoffset = pPriv->src_offset; - BEGIN_ACCEL(6); + qwords = info->new_cs ? 7 : 6; @@ -8230,17 +8255,37 @@ index f55ae12..5d23ad9 100644 OUT_ACCEL_REG(R300_TX_FORMAT1_0, txformat1); OUT_ACCEL_REG(R300_TX_FORMAT2_0, txpitch); - OUT_ACCEL_REG(R300_TX_OFFSET_0, txoffset); -+ if (info->new_cs) { -+ OUT_ACCEL_REG(R300_TX_OFFSET_0, 0); -+ OUT_RELOC(pPriv->src_bo, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0); -+ } else { -+ txoffset += info->fbLocation + pScrn->fbOffset; -+ OUT_ACCEL_REG(R300_TX_OFFSET_0, txoffset); -+ } ++ OUT_TEXTURE_REG(R300_TX_OFFSET_0, txoffset, pPriv->src_bo); FINISH_ACCEL(); txenable = R300_TEX_0_ENABLE; -@@ -240,13 +290,19 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv +@@ -246,19 +302,22 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv + R300_TX_MIN_FILTER_LINEAR | + R300_TX_MAG_FILTER_LINEAR); + +- BEGIN_ACCEL(12); ++ qwords = info->new_cs ? 14 : 12; ++ BEGIN_ACCEL(qwords); + OUT_ACCEL_REG(R300_TX_FILTER0_1, txfilter | (1 << R300_TX_ID_SHIFT)); + OUT_ACCEL_REG(R300_TX_FILTER1_1, 0); + OUT_ACCEL_REG(R300_TX_FORMAT0_1, txformat0); + OUT_ACCEL_REG(R300_TX_FORMAT1_1, R300_TX_FORMAT_X8 | R300_TX_FORMAT_CACHE_FOURTH_REGION_2); + OUT_ACCEL_REG(R300_TX_FORMAT2_1, txpitch); +- OUT_ACCEL_REG(R300_TX_OFFSET_1, txoffset + pPriv->planeu_offset); ++ OUT_TEXTURE_REG(R300_TX_OFFSET_1, txoffset + pPriv->planeu_offset, pPriv->src_bo); ++ + OUT_ACCEL_REG(R300_TX_FILTER0_2, txfilter | (2 << R300_TX_ID_SHIFT)); + OUT_ACCEL_REG(R300_TX_FILTER1_2, 0); + OUT_ACCEL_REG(R300_TX_FORMAT0_2, txformat0); + OUT_ACCEL_REG(R300_TX_FORMAT1_2, R300_TX_FORMAT_X8 | R300_TX_FORMAT_CACHE_FOURTH_REGION_3); + OUT_ACCEL_REG(R300_TX_FORMAT2_2, txpitch); +- OUT_ACCEL_REG(R300_TX_OFFSET_2, txoffset + pPriv->planev_offset); ++ OUT_TEXTURE_REG(R300_TX_OFFSET_2, txoffset + pPriv->planev_offset, pPriv->src_bo); ++ + FINISH_ACCEL(); + txenable |= R300_TEX_1_ENABLE | R300_TEX_2_ENABLE; + } +@@ -279,13 +338,19 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv R300_TX_MAG_FILTER_NEAREST | (1 << R300_TX_ID_SHIFT)); @@ -8262,12 +8307,12 @@ index f55ae12..5d23ad9 100644 FINISH_ACCEL(); /* Enable tex 1 */ -@@ -1332,11 +1388,18 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv +@@ -1536,11 +1601,18 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv } } - BEGIN_ACCEL(6); -+ qwords = info->new_cs ? 7 : 6; ++ qwords = info->new_cs ? 8 : 6; + BEGIN_ACCEL(qwords); OUT_ACCEL_REG(R300_TX_INVALTAGS, 0); OUT_ACCEL_REG(R300_TX_ENABLE, txenable); @@ -8283,39 +8328,112 @@ index f55ae12..5d23ad9 100644 OUT_ACCEL_REG(R300_RB3D_COLORPITCH0, colorpitch); blendcntl = RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ZERO; -@@ -1381,6 +1444,8 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv - RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE); +@@ -1591,6 +1663,8 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv + OUT_ACCEL_REG(RADEON_RB3D_CNTL, - dst_format | RADEON_ALPHA_BLEND_ENABLE); + dst_format /*| RADEON_ALPHA_BLEND_ENABLE*/); + + dst_offset += info->fbLocation + pScrn->fbOffset; OUT_ACCEL_REG(RADEON_RB3D_COLOROFFSET, dst_offset); OUT_ACCEL_REG(RADEON_RB3D_COLORPITCH, colorpitch); -@@ -1418,7 +1483,8 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv - ((pPriv->h - 1) << RADEON_TEX_VSIZE_SHIFT)); - OUT_ACCEL_REG(R200_PP_TXPITCH_0, pPriv->src_pitch - 32); +@@ -1630,7 +1704,8 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv + R200_CLAMP_S_CLAMP_LAST | + R200_CLAMP_T_CLAMP_LAST; + +- BEGIN_ACCEL(36); ++ qwords = info->new_cs ? 39 : 36; ++ BEGIN_ACCEL(qwords); + + OUT_ACCEL_REG(RADEON_PP_CNTL, + RADEON_TEX_0_ENABLE | RADEON_TEX_1_ENABLE | RADEON_TEX_2_ENABLE | +@@ -1649,21 +1724,22 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv + (pPriv->w - 1) | + ((pPriv->h - 1) << RADEON_TEX_VSIZE_SHIFT)); + OUT_ACCEL_REG(R200_PP_TXPITCH_0, pPriv->src_pitch - 32); +- OUT_ACCEL_REG(R200_PP_TXOFFSET_0, pPriv->src_offset); ++ OUT_TEXTURE_REG(R200_PP_TXOFFSET_0, txoffset, pPriv->src_bo); + + OUT_ACCEL_REG(R200_PP_TXFILTER_1, txfilter); + OUT_ACCEL_REG(R200_PP_TXFORMAT_1, txformat | R200_TXFORMAT_ST_ROUTE_STQ1); + OUT_ACCEL_REG(R200_PP_TXFORMAT_X_1, 0); + OUT_ACCEL_REG(R200_PP_TXSIZE_1, txformat0); + OUT_ACCEL_REG(R200_PP_TXPITCH_1, txpitch); +- OUT_ACCEL_REG(R200_PP_TXOFFSET_1, pPriv->src_offset + pPriv->planeu_offset); ++ OUT_TEXTURE_REG(R200_PP_TXOFFSET_1, txoffset + pPriv->planeu_offset, pPriv->src_bo); + + OUT_ACCEL_REG(R200_PP_TXFILTER_2, txfilter); + OUT_ACCEL_REG(R200_PP_TXFORMAT_2, txformat | R200_TXFORMAT_ST_ROUTE_STQ1); + OUT_ACCEL_REG(R200_PP_TXFORMAT_X_2, 0); + OUT_ACCEL_REG(R200_PP_TXSIZE_2, txformat0); + OUT_ACCEL_REG(R200_PP_TXPITCH_2, txpitch); +- OUT_ACCEL_REG(R200_PP_TXOFFSET_2, pPriv->src_offset + pPriv->planev_offset); ++ ++ OUT_TEXTURE_REG(R200_PP_TXOFFSET_2, txoffset + pPriv->planev_offset, pPriv->src_bo); + + /* similar to r300 code. Note the big problem is that hardware constants + * are 8 bits only, representing 0.0-1.0. We can get that up (using bias +@@ -1799,7 +1875,8 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv + R200_CLAMP_S_CLAMP_LAST | + R200_CLAMP_T_CLAMP_LAST; + +- BEGIN_ACCEL(24); ++ qwords = info->new_cs ? 25 : 24; ++ BEGIN_ACCEL(qwords); + + OUT_ACCEL_REG(RADEON_PP_CNTL, + RADEON_TEX_0_ENABLE | +@@ -1817,7 +1894,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv + (pPriv->w - 1) | + ((pPriv->h - 1) << RADEON_TEX_VSIZE_SHIFT)); + OUT_ACCEL_REG(R200_PP_TXPITCH_0, pPriv->src_pitch - 32); +- OUT_ACCEL_REG(R200_PP_TXOFFSET_0, pPriv->src_offset); ++ OUT_TEXTURE_REG(R200_PP_TXOFFSET_0, txoffset, pPriv->src_bo); + + /* MAD temp1 / 2, const0.a * 2, temp0.ggg, -const0.rgb */ + OUT_ACCEL_REG(R200_PP_TXCBLEND_0, +@@ -1901,7 +1978,8 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv + FINISH_ACCEL(); + } + else { +- BEGIN_ACCEL(13); ++ qwords = info->new_cs ? 14 : 13; ++ BEGIN_ACCEL(qwords); + OUT_ACCEL_REG(RADEON_PP_CNTL, + RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE); + +@@ -1922,7 +2000,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv + ((pPriv->h - 1) << RADEON_TEX_VSIZE_SHIFT)); + OUT_ACCEL_REG(R200_PP_TXPITCH_0, pPriv->src_pitch - 32); + +- OUT_ACCEL_REG(R200_PP_TXOFFSET_0, pPriv->src_offset); ++ OUT_TEXTURE_REG(R200_PP_TXOFFSET_0, txoffset, pPriv->src_bo); + + OUT_ACCEL_REG(R200_PP_TXCBLEND_0, + R200_TXC_ARG_A_ZERO | +@@ -1945,7 +2023,8 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv + info->accel_state->texW[0] = 1; + info->accel_state->texH[0] = 1; -- OUT_ACCEL_REG(R200_PP_TXOFFSET_0, pPriv->src_offset); -+ OUT_ACCEL_REG(R200_PP_TXOFFSET_0, pPriv->src_offset + -+ info->fbLocation + pScrn->fbOffset); +- BEGIN_ACCEL(9); ++ qwords = info->new_cs ? 10 : 9; ++ BEGIN_ACCEL(qwords); - OUT_ACCEL_REG(R200_PP_TXCBLEND_0, - R200_TXC_ARG_A_ZERO | -@@ -1451,8 +1517,10 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv + OUT_ACCEL_REG(RADEON_PP_CNTL, + RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE); +@@ -1959,8 +2038,9 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv RADEON_CLAMP_S_CLAMP_LAST | RADEON_CLAMP_T_CLAMP_LAST | RADEON_YUV_TO_RGB); + OUT_ACCEL_REG(RADEON_PP_TXFORMAT_0, txformat); - OUT_ACCEL_REG(RADEON_PP_TXOFFSET_0, pPriv->src_offset); -+ OUT_ACCEL_REG(RADEON_PP_TXOFFSET_0, pPriv->src_offset + -+ info->fbLocation + pScrn->fbOffset); ++ OUT_TEXTURE_REG(RADEON_PP_TXOFFSET_0, txoffset, pPriv->src_bo); OUT_ACCEL_REG(RADEON_PP_TXCBLEND_0, RADEON_COLOR_ARG_A_ZERO | RADEON_COLOR_ARG_B_ZERO | diff --git a/src/radeon_video.c b/src/radeon_video.c -index 92d1a71..03f42a4 100644 +index 42aa036..bd6408d 100644 --- a/src/radeon_video.c +++ b/src/radeon_video.c @@ -287,7 +287,7 @@ void RADEONInitVideo(ScreenPtr pScreen) @@ -8327,23 +8445,22 @@ index 92d1a71..03f42a4 100644 overlayAdaptor = RADEONSetupImageVideo(pScreen); if (overlayAdaptor != NULL) { adaptors[num_adaptors++] = overlayAdaptor; -@@ -297,10 +297,13 @@ void RADEONInitVideo(ScreenPtr pScreen) +@@ -297,9 +297,12 @@ void RADEONInitVideo(ScreenPtr pScreen) RADEONInitOffscreenImages(pScreen); } -- if (info->ChipFamily != CHIP_FAMILY_RV250) { +- if ((info->ChipFamily < CHIP_FAMILY_RS400) + if (info->ChipFamily >= CHIP_FAMILY_R600 && info->drm_mode_setting) { + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + "Disabling textured video for KMS On R600+\n"); -+ } else if (info->ChipFamily != CHIP_FAMILY_RV250) { - if ((info->ChipFamily < CHIP_FAMILY_RS400) ++ } else if ((info->ChipFamily < CHIP_FAMILY_RS400) #ifdef XF86DRI -- || (info->directRenderingEnabled) -+ || (info->directRenderingEnabled || info->drm_mode_setting) +- || (info->directRenderingEnabled) ++ || (info->directRenderingEnabled || info->drm_mode_setting) #endif - ) { - texturedAdaptor = RADEONSetupImageTexturedVideo(pScreen); -@@ -2203,7 +2206,7 @@ RADEONCopyData( + ) { + texturedAdaptor = RADEONSetupImageTexturedVideo(pScreen); +@@ -2200,7 +2203,7 @@ RADEONCopyData( #ifdef XF86DRI @@ -8353,10 +8470,10 @@ index 92d1a71..03f42a4 100644 uint8_t *buf; uint32_t bufPitch, dstPitchOff; diff --git a/src/radeon_video.h b/src/radeon_video.h -index 7f1891e..7a5f740 100644 +index 34fb07f..7b75ec3 100644 --- a/src/radeon_video.h +++ b/src/radeon_video.h -@@ -116,6 +116,9 @@ typedef struct { +@@ -121,6 +121,9 @@ typedef struct { int w, h; int drw_x, drw_y; int vsync; diff --git a/sources b/sources index 105f04d..eae31e5 100644 --- a/sources +++ b/sources @@ -1 +1 @@ -540b25842f8e09164cf4d2376995dc68 xf86-video-ati-6.12.0.tar.bz2 +2adf5988c5e5b6df5f4cb61006fa2bf1 xf86-video-ati-6.12.1.tar.bz2 diff --git a/xorg-x11-drv-ati.spec b/xorg-x11-drv-ati.spec index 3664c92..8d0c338 100644 --- a/xorg-x11-drv-ati.spec +++ b/xorg-x11-drv-ati.spec @@ -4,8 +4,8 @@ Summary: Xorg X11 ati video driver Name: xorg-x11-drv-ati -Version: 6.12.0 -Release: 3%{?dist} +Version: 6.12.1 +Release: 1%{?dist} URL: http://www.x.org License: MIT Group: User Interface/X Hardware Support @@ -76,8 +76,8 @@ rm -rf $RPM_BUILD_ROOT %{_mandir}/man4/radeon.4* %changelog -* Wed Apr 01 2009 Dave Airlie 6.12.0-3 -- radeon-modeset: fix FUS on DRI22 +* Wed Apr 01 2009 Dave Airlie 6.12.1-1 +- rebase to upstream + fix FUS on DRI2 + video on r100/r200 hopefully * Mon Mar 16 2009 Dave Airlie 6.12.0-2 - radeon-6.12.0-git-fixes: fixes from git upstream