diff --git a/.cvsignore b/.cvsignore index 7d6e9ef..6281a6e 100644 --- a/.cvsignore +++ b/.cvsignore @@ -1 +1 @@ -xf86-video-ati-6.12.1.tar.bz2 +xf86-video-ati-6.12.2.tar.bz2 diff --git a/gen_radeon.xinf b/gen_radeon.xinf deleted file mode 100755 index 531b8bc..0000000 --- a/gen_radeon.xinf +++ /dev/null @@ -1,41 +0,0 @@ -#!/usr/bin/perl -# -# Copyright 2007 Red Hat Inc. -# This crappy script written by Dave Airlie to avoid hassle of adding -# ids in every place. -# -# use perl gen_radeon.xinf xf86-video-ati-6.9.0/src/pcidb/ati_pciids.csv -use strict; -use warnings; -use Text::CSV_XS; - -my $file = $ARGV[0]; - -my $atioutfile = 'radeon.xinf'; - -my $csv = Text::CSV_XS->new(); - -open (CSV, "<", $file) or die $!; - -open (ATIOUT, ">", $atioutfile) or die; - -while () { - if ($csv->parse($_)) { - my @columns = $csv->fields(); - - if ((substr($columns[0], 0, 1) ne "#")) { - - - if (($columns[2] ne "R128") && ($columns[2] ne "MACH64") && ($columns[2] ne "MACH32")) { - my $val = substr($columns[0], 2); - print ATIOUT "alias pcivideo:v00001002d0000".$val."sv*sd*bc*sc*i* radeon # $columns[8]\n" - } - } - } else { - my $err = $csv->error_input; - print "Failed to parse line: $err"; - } -} - -close CSV; -close ATIOUT; diff --git a/import.log b/import.log index 191cc1f..a3ba028 100644 --- a/import.log +++ b/import.log @@ -1 +1,2 @@ xorg-x11-drv-ati-6_9_0-1_fc10:HEAD:xorg-x11-drv-ati-6.9.0-1.fc10.src.rpm:1218428001 +xorg-x11-drv-ati-6_12_2-1_fc11:HEAD:xorg-x11-drv-ati-6.12.2-1.fc11.src.rpm:1239644931 diff --git a/radeon-6.12.0-git-fixes.patch b/radeon-6.12.0-git-fixes.patch deleted file mode 100644 index b86405b..0000000 --- a/radeon-6.12.0-git-fixes.patch +++ /dev/null @@ -1,2857 +0,0 @@ -diff --git a/configure.ac b/configure.ac -index 3848f4c..660ea1f 100644 ---- a/configure.ac -+++ b/configure.ac -@@ -22,7 +22,7 @@ - - AC_PREREQ(2.57) - AC_INIT([xf86-video-ati], -- 6.12.1, -+ 6.12.1.99, - [https://bugs.freedesktop.org/enter_bug.cgi?product=xorg], - xf86-video-ati) - -diff --git a/src/ati_pciids_gen.h b/src/ati_pciids_gen.h -index d532f16..3304e84 100644 ---- a/src/ati_pciids_gen.h -+++ b/src/ati_pciids_gen.h -@@ -345,6 +345,8 @@ - #define PCI_CHIP_RV770_9456 0x9456 - #define PCI_CHIP_RV770_945A 0x945A - #define PCI_CHIP_RV770_945B 0x945B -+#define PCI_CHIP_RV790_9460 0x9460 -+#define PCI_CHIP_RV790_9462 0x9462 - #define PCI_CHIP_RV770_946A 0x946A - #define PCI_CHIP_RV770_946B 0x946B - #define PCI_CHIP_RV770_947A 0x947A -@@ -429,3 +431,10 @@ - #define PCI_CHIP_RS780_9612 0x9612 - #define PCI_CHIP_RS780_9613 0x9613 - #define PCI_CHIP_RS780_9614 0x9614 -+#define PCI_CHIP_RS780_9615 0x9615 -+#define PCI_CHIP_RS780_9616 0x9616 -+#define PCI_CHIP_RS880_9710 0x9710 -+#define PCI_CHIP_RS880_9711 0x9711 -+#define PCI_CHIP_RS880_9712 0x9712 -+#define PCI_CHIP_RS880_9713 0x9713 -+#define PCI_CHIP_RS880_9714 0x9714 -diff --git a/src/atombios_crtc.c b/src/atombios_crtc.c -index 50db578..31c032b 100644 ---- a/src/atombios_crtc.c -+++ b/src/atombios_crtc.c -@@ -517,6 +517,9 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc, - - if (IS_AVIVO_VARIANT) { - uint32_t fb_format; -+#if X_BYTE_ORDER == X_BIG_ENDIAN -+ uint32_t fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE; -+#endif - - switch (crtc->scrn->bitsPerPixel) { - case 15: -@@ -524,10 +527,16 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc, - break; - case 16: - fb_format = AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | AVIVO_D1GRPH_CONTROL_16BPP_RGB565; -+#if X_BYTE_ORDER == X_BIG_ENDIAN -+ fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT; -+#endif - break; - case 24: - case 32: - fb_format = AVIVO_D1GRPH_CONTROL_DEPTH_32BPP | AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888; -+#if X_BYTE_ORDER == X_BIG_ENDIAN -+ fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT; -+#endif - break; - default: - FatalError("Unsupported screen depth: %d\n", xf86GetDepth()); -@@ -555,6 +564,11 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc, - OUTREG(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, fb_location); - OUTREG(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); - -+#if X_BYTE_ORDER == X_BIG_ENDIAN -+ if (info->ChipFamily >= CHIP_FAMILY_R600) -+ OUTREG(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap); -+#endif -+ - OUTREG(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); - OUTREG(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); - OUTREG(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0); -diff --git a/src/atombios_output.c b/src/atombios_output.c -index 35d1767..60d6c10 100644 ---- a/src/atombios_output.c -+++ b/src/atombios_output.c -@@ -61,7 +61,7 @@ const char *device_name[12] = { - }; - - static int --atombios_output_dac_setup(xf86OutputPtr output, DisplayModePtr mode) -+atombios_output_dac_setup(xf86OutputPtr output, int action) - { - RADEONOutputPrivatePtr radeon_output = output->driver_private; - RADEONInfoPtr info = RADEONPTR(output->scrn); -@@ -71,6 +71,7 @@ atombios_output_dac_setup(xf86OutputPtr output, DisplayModePtr mode) - AtomBiosArgRec data; - unsigned char *space; - int index = 0, num = 0; -+ int clock = radeon_output->pixel_clock; - - if (radeon_encoder == NULL) - return ATOM_NOT_IMPLEMENTED; -@@ -90,7 +91,7 @@ atombios_output_dac_setup(xf86OutputPtr output, DisplayModePtr mode) - break; - } - -- disp_data.ucAction = ATOM_ENABLE; -+ disp_data.ucAction =action; - - if (radeon_output->active_device & (ATOM_DEVICE_CRT_SUPPORT)) - disp_data.ucDacStandard = ATOM_DAC1_PS2; -@@ -113,7 +114,7 @@ atombios_output_dac_setup(xf86OutputPtr output, DisplayModePtr mode) - break; - } - } -- disp_data.usPixelClock = cpu_to_le16(mode->Clock / 10); -+ disp_data.usPixelClock = cpu_to_le16(clock / 10); - - data.exec.index = index; - data.exec.dataSpace = (void *)&space; -@@ -130,7 +131,7 @@ atombios_output_dac_setup(xf86OutputPtr output, DisplayModePtr mode) - } - - static int --atombios_output_tv_setup(xf86OutputPtr output, DisplayModePtr mode) -+atombios_output_tv_setup(xf86OutputPtr output, int action) - { - RADEONOutputPrivatePtr radeon_output = output->driver_private; - radeon_tvout_ptr tvout = &radeon_output->tvout; -@@ -138,10 +139,11 @@ atombios_output_tv_setup(xf86OutputPtr output, DisplayModePtr mode) - TV_ENCODER_CONTROL_PS_ALLOCATION disp_data; - AtomBiosArgRec data; - unsigned char *space; -+ int clock = radeon_output->pixel_clock; - - memset(&disp_data,0, sizeof(disp_data)); - -- disp_data.sTVEncoder.ucAction = ATOM_ENABLE; -+ disp_data.sTVEncoder.ucAction = action; - - if (radeon_output->active_device & (ATOM_DEVICE_CV_SUPPORT)) - disp_data.sTVEncoder.ucTvStandard = ATOM_TV_CV; -@@ -177,7 +179,7 @@ atombios_output_tv_setup(xf86OutputPtr output, DisplayModePtr mode) - } - } - -- disp_data.sTVEncoder.usPixelClock = cpu_to_le16(mode->Clock / 10); -+ disp_data.sTVEncoder.usPixelClock = cpu_to_le16(clock / 10); - data.exec.index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl); - data.exec.dataSpace = (void *)&space; - data.exec.pspace = &disp_data; -@@ -193,19 +195,21 @@ atombios_output_tv_setup(xf86OutputPtr output, DisplayModePtr mode) - } - - int --atombios_external_tmds_setup(xf86OutputPtr output, DisplayModePtr mode) -+atombios_external_tmds_setup(xf86OutputPtr output, int action) - { -+ RADEONOutputPrivatePtr radeon_output = output->driver_private; - ScrnInfoPtr pScrn = output->scrn; - RADEONInfoPtr info = RADEONPTR(pScrn); - ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION disp_data; - AtomBiosArgRec data; - unsigned char *space; -+ int clock = radeon_output->pixel_clock; - - memset(&disp_data,0, sizeof(disp_data)); - -- disp_data.sXTmdsEncoder.ucEnable = ATOM_ENABLE; -+ disp_data.sXTmdsEncoder.ucEnable = action; - -- if (mode->Clock > 165000) -+ if (clock > 165000) - disp_data.sXTmdsEncoder.ucMisc = PANEL_ENCODER_MISC_DUAL; - - if (pScrn->rgbBits == 8) -@@ -225,19 +229,21 @@ atombios_external_tmds_setup(xf86OutputPtr output, DisplayModePtr mode) - } - - static int --atombios_output_ddia_setup(xf86OutputPtr output, DisplayModePtr mode) -+atombios_output_ddia_setup(xf86OutputPtr output, int action) - { -+ RADEONOutputPrivatePtr radeon_output = output->driver_private; - RADEONInfoPtr info = RADEONPTR(output->scrn); - DVO_ENCODER_CONTROL_PS_ALLOCATION disp_data; - AtomBiosArgRec data; - unsigned char *space; -+ int clock = radeon_output->pixel_clock; - - memset(&disp_data,0, sizeof(disp_data)); - -- disp_data.sDVOEncoder.ucAction = ATOM_ENABLE; -- disp_data.sDVOEncoder.usPixelClock = cpu_to_le16(mode->Clock / 10); -+ disp_data.sDVOEncoder.ucAction = action; -+ disp_data.sDVOEncoder.usPixelClock = cpu_to_le16(clock / 10); - -- if (mode->Clock > 165000) -+ if (clock > 165000) - disp_data.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute = PANEL_ENCODER_MISC_DUAL; - - data.exec.index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl); -@@ -254,7 +260,7 @@ atombios_output_ddia_setup(xf86OutputPtr output, DisplayModePtr mode) - } - - static int --atombios_output_digital_setup(xf86OutputPtr output, DisplayModePtr mode) -+atombios_output_digital_setup(xf86OutputPtr output, int action) - { - RADEONOutputPrivatePtr radeon_output = output->driver_private; - ScrnInfoPtr pScrn = output->scrn; -@@ -267,6 +273,7 @@ atombios_output_digital_setup(xf86OutputPtr output, DisplayModePtr mode) - int index = 0; - int major, minor; - int lvds_misc = 0; -+ int clock = radeon_output->pixel_clock; - - if (radeon_encoder == NULL) - return ATOM_NOT_IMPLEMENTED; -@@ -308,11 +315,11 @@ atombios_output_digital_setup(xf86OutputPtr output, DisplayModePtr mode) - switch (minor) { - case 1: - disp_data.ucMisc = 0; -- disp_data.ucAction = PANEL_ENCODER_ACTION_ENABLE; -+ disp_data.ucAction = action; - if ((radeon_output->ConnectorType == CONNECTOR_HDMI_TYPE_A) || - (radeon_output->ConnectorType == CONNECTOR_HDMI_TYPE_B)) - disp_data.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; -- disp_data.usPixelClock = cpu_to_le16(mode->Clock / 10); -+ disp_data.usPixelClock = cpu_to_le16(clock / 10); - if (radeon_output->active_device & (ATOM_DEVICE_LCD_SUPPORT)) { - if (lvds_misc & (1 << 0)) - disp_data.ucMisc |= PANEL_ENCODER_MISC_DUAL; -@@ -321,7 +328,7 @@ atombios_output_digital_setup(xf86OutputPtr output, DisplayModePtr mode) - } else { - if (radeon_output->linkb) - disp_data.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; -- if (mode->Clock > 165000) -+ if (clock > 165000) - disp_data.ucMisc |= PANEL_ENCODER_MISC_DUAL; - if (pScrn->rgbBits == 8) - disp_data.ucMisc |= (1 << 1); -@@ -331,7 +338,7 @@ atombios_output_digital_setup(xf86OutputPtr output, DisplayModePtr mode) - case 2: - case 3: - disp_data2.ucMisc = 0; -- disp_data2.ucAction = PANEL_ENCODER_ACTION_ENABLE; -+ disp_data2.ucAction = action; - if (minor == 3) { - if (radeon_output->coherent_mode) { - disp_data2.ucMisc |= PANEL_ENCODER_MISC_COHERENT; -@@ -341,7 +348,7 @@ atombios_output_digital_setup(xf86OutputPtr output, DisplayModePtr mode) - if ((radeon_output->ConnectorType == CONNECTOR_HDMI_TYPE_A) || - (radeon_output->ConnectorType == CONNECTOR_HDMI_TYPE_B)) - disp_data2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; -- disp_data2.usPixelClock = cpu_to_le16(mode->Clock / 10); -+ disp_data2.usPixelClock = cpu_to_le16(clock / 10); - disp_data2.ucTruncate = 0; - disp_data2.ucSpatial = 0; - disp_data2.ucTemporal = 0; -@@ -364,7 +371,7 @@ atombios_output_digital_setup(xf86OutputPtr output, DisplayModePtr mode) - } else { - if (radeon_output->linkb) - disp_data2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; -- if (mode->Clock > 165000) -+ if (clock > 165000) - disp_data2.ucMisc |= PANEL_ENCODER_MISC_DUAL; - } - data.exec.pspace = &disp_data2; -@@ -488,16 +495,17 @@ dp_link_clock_for_mode_clock(int mode_clock) - } - - static int --atombios_output_dig_encoder_setup(xf86OutputPtr output, DisplayModePtr mode) -+atombios_output_dig_encoder_setup(xf86OutputPtr output, int action) - { - RADEONOutputPrivatePtr radeon_output = output->driver_private; -- RADEONCrtcPrivatePtr radeon_crtc = output->crtc->driver_private; - RADEONInfoPtr info = RADEONPTR(output->scrn); - radeon_encoder_ptr radeon_encoder = radeon_get_encoder(output); - DIG_ENCODER_CONTROL_PS_ALLOCATION disp_data; - AtomBiosArgRec data; - unsigned char *space; - int index = 0, major, minor, num = 0; -+ int clock = radeon_output->pixel_clock; -+ int dig_block = radeon_output->dig_block; - - if (radeon_encoder == NULL) - return ATOM_NOT_IMPLEMENTED; -@@ -505,11 +513,11 @@ atombios_output_dig_encoder_setup(xf86OutputPtr output, DisplayModePtr mode) - memset(&disp_data,0, sizeof(disp_data)); - - if (IS_DCE32_VARIANT) { -- if (radeon_crtc->crtc_id) -+ if (dig_block) - index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl); - else - index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl); -- num = radeon_crtc->crtc_id + 1; -+ num = dig_block + 1; - } else { - switch (radeon_encoder->encoder_id) { - case ENCODER_OBJECT_ID_INTERNAL_TMDS1: -@@ -529,8 +537,8 @@ atombios_output_dig_encoder_setup(xf86OutputPtr output, DisplayModePtr mode) - - atombios_get_command_table_version(info->atomBIOS, index, &major, &minor); - -- disp_data.ucAction = ATOM_ENABLE; -- disp_data.usPixelClock = cpu_to_le16(mode->Clock / 10); -+ disp_data.ucAction = action; -+ disp_data.usPixelClock = cpu_to_le16(clock / 10); - - if (IS_DCE32_VARIANT) { - switch (radeon_encoder->encoder_id) { -@@ -569,11 +577,11 @@ atombios_output_dig_encoder_setup(xf86OutputPtr output, DisplayModePtr mode) - else - disp_data.ucConfig |= ATOM_ENCODER_CONFIG_LINKA; - -- if (dp_link_clock_for_mode_clock(mode->Clock) == 27000) -+ if (dp_link_clock_for_mode_clock(clock) == 27000) - disp_data.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; - -- disp_data.ucLaneNum = dp_lanes_for_mode_clock(mode->Clock); -- } else if (mode->Clock > 165000) { -+ disp_data.ucLaneNum = dp_lanes_for_mode_clock(clock); -+ } else if (clock > 165000) { - disp_data.ucConfig |= ATOM_ENCODER_CONFIG_LINKA_B; - disp_data.ucLaneNum = 8; - } else { -@@ -605,10 +613,9 @@ union dig_transmitter_control { - }; - - static int --atombios_output_dig_transmitter_setup(xf86OutputPtr output, DisplayModePtr mode) -+atombios_output_dig_transmitter_setup(xf86OutputPtr output, int action) - { - RADEONOutputPrivatePtr radeon_output = output->driver_private; -- RADEONCrtcPrivatePtr radeon_crtc = output->crtc->driver_private; - RADEONInfoPtr info = RADEONPTR(output->scrn); - radeon_encoder_ptr radeon_encoder = radeon_get_encoder(output); - union dig_transmitter_control disp_data; -@@ -616,6 +623,8 @@ atombios_output_dig_transmitter_setup(xf86OutputPtr output, DisplayModePtr mode) - unsigned char *space; - int index = 0, num = 0; - int major, minor; -+ int clock = radeon_output->pixel_clock; -+ int dig_block = radeon_output->dig_block; - - if (radeon_encoder == NULL) - return ATOM_NOT_IMPLEMENTED; -@@ -641,20 +650,20 @@ atombios_output_dig_transmitter_setup(xf86OutputPtr output, DisplayModePtr mode) - - atombios_get_command_table_version(info->atomBIOS, index, &major, &minor); - -- disp_data.v1.ucAction = ATOM_TRANSMITTER_ACTION_ENABLE; -+ disp_data.v1.ucAction = action; - - if (IS_DCE32_VARIANT) { - if (radeon_output->MonType == MT_DP) { - disp_data.v2.usPixelClock = -- cpu_to_le16(dp_link_clock_for_mode_clock(mode->Clock)); -+ cpu_to_le16(dp_link_clock_for_mode_clock(clock)); - disp_data.v2.acConfig.fDPConnector = 1; -- } else if (mode->Clock > 165000) { -- disp_data.v2.usPixelClock = cpu_to_le16((mode->Clock * 10 * 2) / 100); -+ } else if (clock > 165000) { -+ disp_data.v2.usPixelClock = cpu_to_le16((clock * 10 * 2) / 100); - disp_data.v2.acConfig.fDualLinkConnector = 1; - } else { -- disp_data.v2.usPixelClock = cpu_to_le16((mode->Clock * 10 * 4) / 100); -+ disp_data.v2.usPixelClock = cpu_to_le16((clock * 10 * 4) / 100); - } -- if (radeon_crtc->crtc_id) -+ if (dig_block) - disp_data.v2.acConfig.ucEncoderSel = 1; - - switch (radeon_encoder->encoder_id) { -@@ -684,9 +693,9 @@ atombios_output_dig_transmitter_setup(xf86OutputPtr output, DisplayModePtr mode) - - if (radeon_output->MonType == MT_DP) - disp_data.v1.usPixelClock = -- cpu_to_le16(dp_link_clock_for_mode_clock(mode->Clock)); -+ cpu_to_le16(dp_link_clock_for_mode_clock(clock)); - else -- disp_data.v1.usPixelClock = cpu_to_le16((mode->Clock) / 10); -+ disp_data.v1.usPixelClock = cpu_to_le16((clock) / 10); - - switch (radeon_encoder->encoder_id) { - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: -@@ -704,7 +713,7 @@ atombios_output_dig_transmitter_setup(xf86OutputPtr output, DisplayModePtr mode) - case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: - disp_data.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER; - if (info->IsIGP) { -- if (mode->Clock > 165000) { -+ if (clock > 165000) { - disp_data.v1.ucConfig |= (ATOM_TRANSMITTER_CONFIG_8LANE_LINK | - ATOM_TRANSMITTER_CONFIG_LINKA_B); - /* guess */ -@@ -724,7 +733,7 @@ atombios_output_dig_transmitter_setup(xf86OutputPtr output, DisplayModePtr mode) - disp_data.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15; - } - } else { -- if (mode->Clock > 165000) -+ if (clock > 165000) - disp_data.v1.ucConfig |= (ATOM_TRANSMITTER_CONFIG_8LANE_LINK | - ATOM_TRANSMITTER_CONFIG_LINKA_B | - ATOM_TRANSMITTER_CONFIG_LANE_0_7); -@@ -741,7 +750,7 @@ atombios_output_dig_transmitter_setup(xf86OutputPtr output, DisplayModePtr mode) - case ENCODER_OBJECT_ID_INTERNAL_LVTM1: - case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: - disp_data.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER; -- if (mode->Clock > 165000) -+ if (clock > 165000) - disp_data.v1.ucConfig |= (ATOM_TRANSMITTER_CONFIG_8LANE_LINK | - ATOM_TRANSMITTER_CONFIG_LINKA_B | - ATOM_TRANSMITTER_CONFIG_LANE_0_7); -@@ -767,7 +776,6 @@ atombios_output_dig_transmitter_setup(xf86OutputPtr output, DisplayModePtr mode) - } - } - } -- radeon_output->transmitter_config = disp_data.v1.ucConfig; - - data.exec.index = index; - data.exec.dataSpace = (void *)&space; -@@ -1125,7 +1133,7 @@ atombios_output_overscan_setup(xf86OutputPtr output, DisplayModePtr mode, Displa - } - - static int --atombios_output_scaler_setup(xf86OutputPtr output, DisplayModePtr mode) -+atombios_output_scaler_setup(xf86OutputPtr output) - { - RADEONInfoPtr info = RADEONPTR(output->scrn); - RADEONOutputPrivatePtr radeon_output = output->driver_private; -@@ -1213,63 +1221,6 @@ atombios_output_scaler_setup(xf86OutputPtr output, DisplayModePtr mode) - - } - --static int --atombios_dig_dpms(xf86OutputPtr output, int mode) --{ -- RADEONOutputPrivatePtr radeon_output = output->driver_private; -- RADEONInfoPtr info = RADEONPTR(output->scrn); -- radeon_encoder_ptr radeon_encoder = radeon_get_encoder(output); -- DIG_TRANSMITTER_CONTROL_PS_ALLOCATION disp_data; -- AtomBiosArgRec data; -- unsigned char *space; -- -- if (radeon_encoder == NULL) -- return ATOM_NOT_IMPLEMENTED; -- -- memset(&disp_data, 0, sizeof(disp_data)); -- -- switch (mode) { -- case DPMSModeOn: -- disp_data.ucAction = ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT; -- break; -- case DPMSModeStandby: -- case DPMSModeSuspend: -- case DPMSModeOff: -- disp_data.ucAction = ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT; -- break; -- } -- -- disp_data.ucConfig = radeon_output->transmitter_config; -- -- if (IS_DCE32_VARIANT) -- data.exec.index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl); -- else { -- switch (radeon_encoder->encoder_id) { -- case ENCODER_OBJECT_ID_INTERNAL_TMDS1: -- case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: -- case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: -- data.exec.index = GetIndexIntoMasterTable(COMMAND, DIG1TransmitterControl); -- break; -- case ENCODER_OBJECT_ID_INTERNAL_LVDS: -- case ENCODER_OBJECT_ID_INTERNAL_LVTM1: -- case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: -- data.exec.index = GetIndexIntoMasterTable(COMMAND, DIG2TransmitterControl); -- break; -- } -- } -- data.exec.dataSpace = (void *)&space; -- data.exec.pspace = &disp_data; -- -- if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) { -- ErrorF("Output DIG dpms success\n"); -- return ATOM_SUCCESS; -- } -- -- ErrorF("Output DIG dpms failed\n"); -- return ATOM_NOT_IMPLEMENTED; -- --} -- - void - atombios_output_dpms(xf86OutputPtr output, int mode) - { -@@ -1334,7 +1285,7 @@ atombios_output_dpms(xf86OutputPtr output, int mode) - case DPMSModeOn: - radeon_encoder->devices |= radeon_output->active_device; - if (is_dig) -- (void)atombios_dig_dpms(output, mode); -+ atombios_output_dig_transmitter_setup(output, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT); - else { - disp_data.ucAction = ATOM_ENABLE; - data.exec.index = index; -@@ -1355,7 +1306,7 @@ atombios_output_dpms(xf86OutputPtr output, int mode) - radeon_encoder->devices &= ~(radeon_output->active_device); - if (!radeon_encoder->devices) { - if (is_dig) -- (void)atombios_dig_dpms(output, mode); -+ atombios_output_dig_transmitter_setup(output, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT); - else { - disp_data.ucAction = ATOM_DISABLE; - data.exec.index = index; -@@ -1406,8 +1357,12 @@ atombios_set_output_crtc_source(xf86OutputPtr output) - default: - if (IS_AVIVO_VARIANT) - crtc_src_param.ucCRTC = radeon_crtc->crtc_id; -- else -- crtc_src_param.ucCRTC = radeon_crtc->crtc_id << 2; -+ else { -+ if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) -+ crtc_src_param.ucCRTC = radeon_crtc->crtc_id; -+ else -+ crtc_src_param.ucCRTC = radeon_crtc->crtc_id << 2; -+ } - switch (radeon_encoder->encoder_id) { - case ENCODER_OBJECT_ID_INTERNAL_TMDS1: - case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: -@@ -1559,13 +1514,16 @@ atombios_output_mode_set(xf86OutputPtr output, - DisplayModePtr adjusted_mode) - { - RADEONOutputPrivatePtr radeon_output = output->driver_private; -+ RADEONCrtcPrivatePtr radeon_crtc = output->crtc->driver_private; - radeon_encoder_ptr radeon_encoder = radeon_get_encoder(output); - RADEONInfoPtr info = RADEONPTR(output->scrn); - if (radeon_encoder == NULL) - return; - -+ radeon_output->pixel_clock = adjusted_mode->Clock; -+ radeon_output->dig_block = radeon_crtc->crtc_id; - atombios_output_overscan_setup(output, mode, adjusted_mode); -- atombios_output_scaler_setup(output, adjusted_mode); -+ atombios_output_scaler_setup(output); - atombios_set_output_crtc_source(output); - - if (IS_AVIVO_VARIANT) { -@@ -1580,29 +1538,31 @@ atombios_output_mode_set(xf86OutputPtr output, - case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: - case ENCODER_OBJECT_ID_INTERNAL_LVDS: - case ENCODER_OBJECT_ID_INTERNAL_LVTM1: -- atombios_output_digital_setup(output, adjusted_mode); -+ atombios_output_digital_setup(output, PANEL_ENCODER_ACTION_ENABLE); - break; - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: - case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: -- atombios_output_dig_encoder_setup(output, adjusted_mode); -- atombios_output_dig_transmitter_setup(output, adjusted_mode); -+ atombios_output_dig_encoder_setup(output, ATOM_ENABLE); -+ atombios_output_dig_transmitter_setup(output, ATOM_TRANSMITTER_ACTION_INIT); -+ atombios_output_dig_transmitter_setup(output, ATOM_TRANSMITTER_ACTION_SETUP); -+ atombios_output_dig_transmitter_setup(output, ATOM_TRANSMITTER_ACTION_ENABLE); - break; - case ENCODER_OBJECT_ID_INTERNAL_DDI: -- atombios_output_ddia_setup(output, adjusted_mode); -+ atombios_output_ddia_setup(output, ATOM_ENABLE); - break; - case ENCODER_OBJECT_ID_INTERNAL_DVO1: - case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: -- atombios_external_tmds_setup(output, adjusted_mode); -+ atombios_external_tmds_setup(output, ATOM_ENABLE); - break; - case ENCODER_OBJECT_ID_INTERNAL_DAC1: - case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: - case ENCODER_OBJECT_ID_INTERNAL_DAC2: - case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: -- atombios_output_dac_setup(output, adjusted_mode); -+ atombios_output_dac_setup(output, ATOM_ENABLE); - if (radeon_output->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) -- atombios_output_tv_setup(output, adjusted_mode); -+ atombios_output_tv_setup(output, ATOM_ENABLE); - break; - } - atombios_apply_output_quirks(output, adjusted_mode); -diff --git a/src/legacy_output.c b/src/legacy_output.c -index 6223531..423a3e2 100644 ---- a/src/legacy_output.c -+++ b/src/legacy_output.c -@@ -1589,6 +1589,7 @@ legacy_output_mode_set(xf86OutputPtr output, DisplayModePtr mode, - if (radeon_encoder == NULL) - return; - -+ radeon_output->pixel_clock = adjusted_mode->Clock; - if (radeon_crtc->crtc_id == 0) { - ErrorF("set RMX\n"); - is_primary = TRUE; -@@ -1614,7 +1615,7 @@ legacy_output_mode_set(xf86OutputPtr output, DisplayModePtr mode, - unsigned char *RADEONMMIO = info->MMIO; - uint32_t fp2_gen_cntl; - -- atombios_external_tmds_setup(output, mode); -+ atombios_external_tmds_setup(output, ATOM_ENABLE); - fp2_gen_cntl = INREG(RADEON_FP2_GEN_CNTL) & ~R200_FP2_SOURCE_SEL_MASK; - if (radeon_crtc->crtc_id == 1) - fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2; -diff --git a/src/pcidb/ati_pciids.csv b/src/pcidb/ati_pciids.csv -index 4d4e625..b361d9d 100644 ---- a/src/pcidb/ati_pciids.csv -+++ b/src/pcidb/ati_pciids.csv -@@ -346,6 +346,8 @@ - "0x9456","RV770_9456","RV770",,,,,,"ATI FirePro V8700 (FireGL)" - "0x945A","RV770_945A","RV770",1,,,,,"ATI Mobility RADEON HD 4870" - "0x945B","RV770_945B","RV770",1,,,,,"ATI Mobility RADEON M98" -+"0x9460","RV790_9460","RV770",,,,,,"ATI Radeon 4800 Series" -+"0x9462","RV790_9462","RV770",,,,,,"ATI Radeon 4800 Series" - "0x946A","RV770_946A","RV770",1,,,,,"ATI FirePro M7750" - "0x946B","RV770_946B","RV770",1,,,,,"ATI M98" - "0x947A","RV770_947A","RV770",1,,,,,"ATI M98" -@@ -430,3 +432,10 @@ - "0x9612","RS780_9612","RS780",,1,,,1,"ATI Radeon HD 3200 Graphics" - "0x9613","RS780_9613","RS780",,1,,,1,"ATI Radeon 3100 Graphics" - "0x9614","RS780_9614","RS780",,1,,,1,"ATI Radeon HD 3300 Graphics" -+"0x9615","RS780_9615","RS780",,1,,,1,"ATI Radeon HD 3200 Graphics" -+"0x9616","RS780_9616","RS780",,1,,,1,"ATI Radeon 3000 Graphics" -+"0x9710","RS880_9710","RS880",,1,,,1,"ATI Radeon HD Graphics" -+"0x9711","RS880_9711","RS880",,1,,,1,"ATI Radeon Graphics" -+"0x9712","RS880_9712","RS880",1,1,,,1,"ATI Mobility Radeon HD Graphics" -+"0x9713","RS880_9713","RS880",1,1,,,1,"ATI Mobility Radeon Graphics" -+"0x9714","RS880_9714","RS880",,1,,,1,"ATI Radeon Graphics" -diff --git a/src/r600_exa.c b/src/r600_exa.c -index 40f02e1..2dc33a8 100644 ---- a/src/r600_exa.c -+++ b/src/r600_exa.c -@@ -1098,6 +1098,7 @@ static Bool R600TextureSetup(PicturePtr pPict, PixmapPtr pPix, - unsigned int i; - tex_resource_t tex_res; - tex_sampler_t tex_samp; -+ int pix_r, pix_g, pix_b, pix_a; - - CLEAR (tex_res); - CLEAR (tex_samp); -@@ -1142,46 +1143,102 @@ static Bool R600TextureSetup(PicturePtr pPict, PixmapPtr pPix, - switch (pPict->format) { - case PICT_a1r5g5b5: - case PICT_a8r8g8b8: -- tex_res.dst_sel_x = SQ_SEL_Z; /* R */ -- tex_res.dst_sel_y = SQ_SEL_Y; /* G */ -- tex_res.dst_sel_z = SQ_SEL_X; /* B */ -- tex_res.dst_sel_w = SQ_SEL_W; /* A */ -+ pix_r = SQ_SEL_Z; /* R */ -+ pix_g = SQ_SEL_Y; /* G */ -+ pix_b = SQ_SEL_X; /* B */ -+ pix_a = SQ_SEL_W; /* A */ - break; - case PICT_a8b8g8r8: -- tex_res.dst_sel_x = SQ_SEL_X; /* R */ -- tex_res.dst_sel_y = SQ_SEL_Y; /* G */ -- tex_res.dst_sel_z = SQ_SEL_Z; /* B */ -- tex_res.dst_sel_w = SQ_SEL_W; /* A */ -+ pix_r = SQ_SEL_X; /* R */ -+ pix_g = SQ_SEL_Y; /* G */ -+ pix_b = SQ_SEL_Z; /* B */ -+ pix_a = SQ_SEL_W; /* A */ - break; - case PICT_x8b8g8r8: -- tex_res.dst_sel_x = SQ_SEL_X; /* R */ -- tex_res.dst_sel_y = SQ_SEL_Y; /* G */ -- tex_res.dst_sel_z = SQ_SEL_Z; /* B */ -- tex_res.dst_sel_w = SQ_SEL_1; /* A */ -+ pix_r = SQ_SEL_X; /* R */ -+ pix_g = SQ_SEL_Y; /* G */ -+ pix_b = SQ_SEL_Z; /* B */ -+ pix_a = SQ_SEL_1; /* A */ - break; - case PICT_x1r5g5b5: - case PICT_x8r8g8b8: -- tex_res.dst_sel_x = SQ_SEL_Z; /* R */ -- tex_res.dst_sel_y = SQ_SEL_Y; /* G */ -- tex_res.dst_sel_z = SQ_SEL_X; /* B */ -- tex_res.dst_sel_w = SQ_SEL_1; /* A */ -- break; - case PICT_r5g6b5: -- tex_res.dst_sel_x = SQ_SEL_Z; /* R */ -- tex_res.dst_sel_y = SQ_SEL_Y; /* G */ -- tex_res.dst_sel_z = SQ_SEL_X; /* B */ -- tex_res.dst_sel_w = SQ_SEL_1; /* A */ -+ pix_r = SQ_SEL_Z; /* R */ -+ pix_g = SQ_SEL_Y; /* G */ -+ pix_b = SQ_SEL_X; /* B */ -+ pix_a = SQ_SEL_1; /* A */ - break; - case PICT_a8: -- tex_res.dst_sel_x = SQ_SEL_0; /* R */ -- tex_res.dst_sel_y = SQ_SEL_0; /* G */ -- tex_res.dst_sel_z = SQ_SEL_0; /* B */ -- tex_res.dst_sel_w = SQ_SEL_X; /* A */ -+ pix_r = SQ_SEL_0; /* R */ -+ pix_g = SQ_SEL_0; /* G */ -+ pix_b = SQ_SEL_0; /* B */ -+ pix_a = SQ_SEL_X; /* A */ - break; - default: - RADEON_FALLBACK(("Bad format 0x%x\n", pPict->format)); - } - -+ if (unit == 0) { -+ if (!accel_state->has_mask) { -+ if (PICT_FORMAT_RGB(pPict->format) == 0) { -+ pix_r = SQ_SEL_0; -+ pix_g = SQ_SEL_0; -+ pix_b = SQ_SEL_0; -+ } -+ -+ if (PICT_FORMAT_A(pPict->format) == 0) -+ pix_a = SQ_SEL_1; -+ } else { -+ if (accel_state->component_alpha) { -+ if (accel_state->src_alpha) { -+ if (PICT_FORMAT_A(pPict->format) == 0) { -+ pix_r = SQ_SEL_1; -+ pix_g = SQ_SEL_1; -+ pix_b = SQ_SEL_1; -+ pix_a = SQ_SEL_1; -+ } else { -+ pix_r = pix_a; -+ pix_g = pix_a; -+ pix_b = pix_a; -+ } -+ } else { -+ if (PICT_FORMAT_A(pPict->format) == 0) -+ pix_a = SQ_SEL_1; -+ } -+ } else { -+ if (PICT_FORMAT_RGB(pPict->format) == 0) { -+ pix_r = SQ_SEL_0; -+ pix_g = SQ_SEL_0; -+ pix_b = SQ_SEL_0; -+ } -+ -+ if (PICT_FORMAT_A(pPict->format) == 0) -+ pix_a = SQ_SEL_1; -+ } -+ } -+ } else { -+ if (accel_state->component_alpha) { -+ if (PICT_FORMAT_A(pPict->format) == 0) -+ pix_a = SQ_SEL_1; -+ } else { -+ if (PICT_FORMAT_A(pPict->format) == 0) { -+ pix_r = SQ_SEL_1; -+ pix_g = SQ_SEL_1; -+ pix_b = SQ_SEL_1; -+ pix_a = SQ_SEL_1; -+ } else { -+ pix_r = pix_a; -+ pix_g = pix_a; -+ pix_b = pix_a; -+ } -+ } -+ } -+ -+ tex_res.dst_sel_x = pix_r; /* R */ -+ tex_res.dst_sel_y = pix_g; /* G */ -+ tex_res.dst_sel_z = pix_b; /* B */ -+ tex_res.dst_sel_w = pix_a; /* A */ -+ - tex_res.base_level = 0; - tex_res.last_level = 0; - tex_res.perf_modulation = 0; -@@ -1324,14 +1381,26 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture, - uint32_t blendcntl, dst_format; - cb_config_t cb_conf; - shader_config_t vs_conf, ps_conf; -- uint32_t ps[24]; - - /* return FALSE; */ - -- if (pMask) -+ if (pMask) { - accel_state->has_mask = TRUE; -- else -+ if (pMaskPicture->componentAlpha) { -+ accel_state->component_alpha = TRUE; -+ if (R600BlendOp[op].src_alpha) -+ accel_state->src_alpha = TRUE; -+ else -+ accel_state->src_alpha = FALSE; -+ } else { -+ accel_state->component_alpha = FALSE; -+ accel_state->src_alpha = FALSE; -+ } -+ } else { - accel_state->has_mask = FALSE; -+ accel_state->component_alpha = FALSE; -+ accel_state->src_alpha = FALSE; -+ } - - accel_state->dst_mc_addr = exaGetPixmapOffset(pDst) + info->fbLocation + pScrn->fbOffset; - accel_state->dst_pitch = exaGetPixmapPitch(pDst) / (pDst->drawable.bitsPerPixel / 8); -@@ -1346,116 +1415,6 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture, - if (!R600GetDestFormat(pDstPicture, &dst_format)) - return FALSE; - -- if (pMask) { -- int src_a, src_r, src_g, src_b; -- int mask_a, mask_r, mask_g, mask_b; -- -- /* setup pixel shader */ -- if (PICT_FORMAT_RGB(pSrcPicture->format) == 0) { -- src_r = SQ_SEL_0; -- src_g = SQ_SEL_0; -- src_b = SQ_SEL_0; -- } else { -- src_r = SQ_SEL_X; -- src_g = SQ_SEL_Y; -- src_b = SQ_SEL_Z; -- } -- -- if (PICT_FORMAT_A(pSrcPicture->format) == 0) { -- src_a = SQ_SEL_1; -- } else { -- src_a = SQ_SEL_W; -- } -- -- if (pMaskPicture->componentAlpha) { -- if (R600BlendOp[op].src_alpha) { -- if (PICT_FORMAT_A(pSrcPicture->format) == 0) { -- src_r = SQ_SEL_1; -- src_g = SQ_SEL_1; -- src_b = SQ_SEL_1; -- src_a = SQ_SEL_1; -- } else { -- src_r = SQ_SEL_W; -- src_g = SQ_SEL_W; -- src_b = SQ_SEL_W; -- src_a = SQ_SEL_W; -- } -- -- mask_r = SQ_SEL_X; -- mask_g = SQ_SEL_Y; -- mask_b = SQ_SEL_Z; -- -- if (PICT_FORMAT_A(pMaskPicture->format) == 0) { -- mask_a = SQ_SEL_1; -- } else { -- mask_a = SQ_SEL_W; -- } -- } else { -- src_r = SQ_SEL_X; -- src_g = SQ_SEL_Y; -- src_b = SQ_SEL_Z; -- -- if (PICT_FORMAT_A(pSrcPicture->format) == 0) { -- src_a = SQ_SEL_1; -- } else { -- src_a = SQ_SEL_W; -- } -- -- mask_r = SQ_SEL_X; -- mask_g = SQ_SEL_Y; -- mask_b = SQ_SEL_Z; -- -- if (PICT_FORMAT_A(pMaskPicture->format) == 0) { -- mask_a = SQ_SEL_1; -- } else { -- mask_a = SQ_SEL_W; -- } -- } -- } else { -- if (PICT_FORMAT_A(pMaskPicture->format) == 0) { -- mask_r = SQ_SEL_1; -- mask_g = SQ_SEL_1; -- mask_b = SQ_SEL_1; -- } else { -- mask_r = SQ_SEL_W; -- mask_g = SQ_SEL_W; -- mask_b = SQ_SEL_W; -- } -- if (PICT_FORMAT_A(pMaskPicture->format) == 0) { -- mask_a = SQ_SEL_1; -- } else { -- mask_a = SQ_SEL_W; -- } -- } -- -- R600_comp_mask_ps(info->ChipFamily, ps, -- src_a, src_r, src_g, src_b, -- mask_a, mask_r, mask_g, mask_b); -- -- } else { -- int src_a, src_r, src_g, src_b; -- /* setup pixel shader */ -- if (PICT_FORMAT_RGB(pSrcPicture->format) == 0) { -- src_r = SQ_SEL_0; -- src_g = SQ_SEL_0; -- src_b = SQ_SEL_0; -- } else { -- src_r = SQ_SEL_X; -- src_g = SQ_SEL_Y; -- src_b = SQ_SEL_Z; -- } -- -- if (PICT_FORMAT_A(pSrcPicture->format) == 0) { -- src_a = SQ_SEL_1; -- } else { -- src_a = SQ_SEL_W; -- } -- -- R600_comp_ps(info->ChipFamily, ps, -- src_a, src_r, src_g, src_b); -- -- } -- - CLEAR (cb_conf); - CLEAR (vs_conf); - CLEAR (ps_conf); -@@ -1484,19 +1443,19 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture, - } else - accel_state->is_transform[1] = FALSE; - -- /* VS bool constant */ -- if (pMask) -- set_bool_const(pScrn, accel_state->ib, 1, 1); -- else -- set_bool_const(pScrn, accel_state->ib, 1, 0); -+ if (pMask) { -+ set_bool_consts(pScrn, accel_state->ib, SQ_BOOL_CONST_vs, (1 << 0)); -+ accel_state->ps_mc_addr = info->fbLocation + pScrn->fbOffset + accel_state->shaders->offset + -+ accel_state->comp_mask_ps_offset; -+ } else { -+ set_bool_consts(pScrn, accel_state->ib, SQ_BOOL_CONST_vs, (0 << 0)); -+ accel_state->ps_mc_addr = info->fbLocation + pScrn->fbOffset + accel_state->shaders->offset + -+ accel_state->comp_ps_offset; -+ } - - accel_state->vs_mc_addr = info->fbLocation + pScrn->fbOffset + accel_state->shaders->offset + - accel_state->comp_vs_offset; - -- memcpy ((char *)accel_state->ib->address + (accel_state->ib->total / 2) - 256, ps, sizeof(ps)); -- accel_state->ps_mc_addr = info->gartLocation + info->dri->bufStart + -- (accel_state->ib->idx * accel_state->ib->total) + (accel_state->ib->total / 2) - 256; -- - accel_state->vs_size = 512; - accel_state->ps_size = 512; - -@@ -2013,11 +1972,11 @@ R600LoadShaders(ScrnInfoPtr pScrn) - - /* comp ps --------------------------------------- */ - accel_state->comp_ps_offset = 2560; -- /* not yet */ -+ R600_comp_ps(ChipSet, shader + accel_state->comp_ps_offset / 4); - - /* comp mask ps --------------------------------------- */ - accel_state->comp_mask_ps_offset = 3072; -- /* not yet */ -+ R600_comp_mask_ps(ChipSet, shader + accel_state->comp_mask_ps_offset / 4); - - /* xv vs --------------------------------------- */ - accel_state->xv_vs_offset = 3584; -@@ -2105,10 +2064,10 @@ R600DrawInit(ScreenPtr pScreen) - #if EXA_VERSION_MAJOR > 2 || (EXA_VERSION_MAJOR == 2 && EXA_VERSION_MINOR >= 3) - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Setting EXA maxPitchBytes\n"); - -- info->accel_state->exa->maxPitchBytes = 16320; -+ info->accel_state->exa->maxPitchBytes = 32768; - info->accel_state->exa->maxX = 8192; - #else -- info->accel_state->exa->maxX = 16320 / 4; -+ info->accel_state->exa->maxX = 8192; - #endif - info->accel_state->exa->maxY = 8192; - -diff --git a/src/r600_reg.h b/src/r600_reg.h -index 9036e2a..937926b 100644 ---- a/src/r600_reg.h -+++ b/src/r600_reg.h -@@ -51,8 +51,8 @@ enum { - SET_LOOP_CONST_offset = 0x0003e200, - SET_LOOP_CONST_end = 0x0003e380, - SET_BOOL_CONST_offset = 0x0003e380, -- SET_BOOL_CONST_end = 0x00040000, --} ; -+ SET_BOOL_CONST_end = 0x0003e38c, -+}; - - /* packet3 IT_SURFACE_BASE_UPDATE bits */ - enum { -diff --git a/src/r600_reg_r6xx.h b/src/r600_reg_r6xx.h -index 2e7dfa9..b4cc639 100644 ---- a/src/r600_reg_r6xx.h -+++ b/src/r600_reg_r6xx.h -@@ -488,7 +488,16 @@ enum { - SQ_LOOP_CONST_ps = 0, - SQ_LOOP_CONST_vs = SQ_LOOP_CONST_ps + SQ_LOOP_CONST_ps_num, - SQ_LOOP_CONST_gs = SQ_LOOP_CONST_vs + SQ_LOOP_CONST_vs_num, --} ; -+ SQ_BOOL_CONST = SQ_BOOL_CONST_0, /* 32 bits per PS, VS, GS */ -+ SQ_BOOL_CONST_ps_num = 1, -+ SQ_BOOL_CONST_vs_num = 1, -+ SQ_BOOL_CONST_gs_num = 1, -+ SQ_BOOL_CONST_all_num = 3, -+ SQ_BOOL_CONST_offset = 4, -+ SQ_BOOL_CONST_ps = 0, -+ SQ_BOOL_CONST_vs = SQ_BOOL_CONST_ps + SQ_BOOL_CONST_ps_num, -+ SQ_BOOL_CONST_gs = SQ_BOOL_CONST_vs + SQ_BOOL_CONST_vs_num, -+}; - - - #endif -diff --git a/src/r600_shader.c b/src/r600_shader.c -index 21c4c68..addba36 100644 ---- a/src/r600_shader.c -+++ b/src/r600_shader.c -@@ -1245,10 +1245,7 @@ int R600_xv_ps(RADEONChipFamily ChipSet, uint32_t* shader) - } - - /* comp mask ps --------------------------------------- */ --int R600_comp_mask_ps(RADEONChipFamily ChipSet, -- uint32_t* shader, -- int src_a, int src_r, int src_g, int src_b, -- int mask_a, int mask_r, int mask_g, int mask_b) -+int R600_comp_mask_ps(RADEONChipFamily ChipSet, uint32_t* shader) - { - int i = 0; - -@@ -1421,10 +1418,10 @@ int R600_comp_mask_ps(RADEONChipFamily ChipSet, - R7xx_ALT_CONST(0)); - shader[i++] = TEX_DWORD1(DST_GPR(0), - DST_REL(ABSOLUTE), -- DST_SEL_X(src_r), -- DST_SEL_Y(src_g), -- DST_SEL_Z(src_b), -- DST_SEL_W(src_a), -+ DST_SEL_X(SQ_SEL_X), -+ DST_SEL_Y(SQ_SEL_Y), -+ DST_SEL_Z(SQ_SEL_Z), -+ DST_SEL_W(SQ_SEL_W), - LOD_BIAS(0), - COORD_TYPE_X(TEX_NORMALIZED), - COORD_TYPE_Y(TEX_NORMALIZED), -@@ -1449,10 +1446,10 @@ int R600_comp_mask_ps(RADEONChipFamily ChipSet, - R7xx_ALT_CONST(0)); - shader[i++] = TEX_DWORD1(DST_GPR(1), - DST_REL(ABSOLUTE), -- DST_SEL_X(mask_r), -- DST_SEL_Y(mask_g), -- DST_SEL_Z(mask_b), -- DST_SEL_W(mask_a), -+ DST_SEL_X(SQ_SEL_X), -+ DST_SEL_Y(SQ_SEL_Y), -+ DST_SEL_Z(SQ_SEL_Z), -+ DST_SEL_W(SQ_SEL_W), - LOD_BIAS(0), - COORD_TYPE_X(TEX_NORMALIZED), - COORD_TYPE_Y(TEX_NORMALIZED), -@@ -1781,10 +1778,7 @@ int R600_comp_vs(RADEONChipFamily ChipSet, uint32_t* shader) - } - - /* comp ps --------------------------------------- */ --int R600_comp_ps(RADEONChipFamily ChipSet, -- uint32_t* shader, -- int src_a, int src_r, int src_g, int src_b --) -+int R600_comp_ps(RADEONChipFamily ChipSet, uint32_t* shader) - { - int i = 0; - -@@ -1831,10 +1825,10 @@ int R600_comp_ps(RADEONChipFamily ChipSet, - R7xx_ALT_CONST(0)); - shader[i++] = TEX_DWORD1(DST_GPR(0), - DST_REL(ABSOLUTE), -- DST_SEL_X(src_r), -- DST_SEL_Y(src_g), -- DST_SEL_Z(src_b), -- DST_SEL_W(src_a), -+ DST_SEL_X(SQ_SEL_X), -+ DST_SEL_Y(SQ_SEL_Y), -+ DST_SEL_Z(SQ_SEL_Z), -+ DST_SEL_W(SQ_SEL_W), - LOD_BIAS(0), - COORD_TYPE_X(TEX_NORMALIZED), - COORD_TYPE_Y(TEX_NORMALIZED), -diff --git a/src/r600_shader.h b/src/r600_shader.h -index 67b64ff..6c12614 100644 ---- a/src/r600_shader.h -+++ b/src/r600_shader.h -@@ -352,15 +352,8 @@ extern int R600_copy_ps(RADEONChipFamily ChipSet, uint32_t* ps); - extern int R600_xv_vs(RADEONChipFamily ChipSet, uint32_t* shader); - extern int R600_xv_ps(RADEONChipFamily ChipSet, uint32_t* shader); - --extern int R600_comp_mask_vs(RADEONChipFamily ChipSet, uint32_t* vs); --extern int R600_comp_mask_ps(RADEONChipFamily ChipSet, -- uint32_t* ps, -- int src_a, int src_r, int src_g, int src_b, -- int mask_a, int mask_r, int mask_g, int mask_b); -- - extern int R600_comp_vs(RADEONChipFamily ChipSet, uint32_t* vs); --extern int R600_comp_ps(RADEONChipFamily ChipSet, -- uint32_t* ps, -- int src_a, int src_r, int src_g, int src_b); -+extern int R600_comp_mask_ps(RADEONChipFamily ChipSet, uint32_t* ps); -+extern int R600_comp_ps(RADEONChipFamily ChipSet, uint32_t* ps); - - #endif -diff --git a/src/r600_state.h b/src/r600_state.h -index c903ded..181e167 100644 ---- a/src/r600_state.h -+++ b/src/r600_state.h -@@ -255,7 +255,7 @@ ps_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *ps_conf); - void - set_alu_consts(ScrnInfoPtr pScrn, drmBufPtr ib, int offset, int count, float *const_buf); - void --set_bool_const(ScrnInfoPtr pScrn, drmBufPtr ib, int offset, uint32_t val); -+set_bool_consts(ScrnInfoPtr pScrn, drmBufPtr ib, int offset, uint32_t val); - void - set_vtx_resource(ScrnInfoPtr pScrn, drmBufPtr ib, vtx_resource_t *res); - void -diff --git a/src/r600_textured_videofuncs.c b/src/r600_textured_videofuncs.c -index 735231b..3dfe151 100644 ---- a/src/r600_textured_videofuncs.c -+++ b/src/r600_textured_videofuncs.c -@@ -172,12 +172,12 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) - switch(pPriv->id) { - case FOURCC_YV12: - case FOURCC_I420: -- set_bool_const(pScrn, accel_state->ib, 0, 1); -+ set_bool_consts(pScrn, accel_state->ib, SQ_BOOL_CONST_ps, (1 << 0)); - break; - case FOURCC_UYVY: - case FOURCC_YUY2: - default: -- set_bool_const(pScrn, accel_state->ib, 0, 0); -+ set_bool_consts(pScrn, accel_state->ib, SQ_BOOL_CONST_ps, (0 << 0)); - break; - } - -diff --git a/src/r6xx_accel.c b/src/r6xx_accel.c -index f93ca01..bce597b 100644 ---- a/src/r6xx_accel.c -+++ b/src/r6xx_accel.c -@@ -153,8 +153,10 @@ reset_bool_loop_const(ScrnInfoPtr pScrn, drmBufPtr ib) - { - int i; - -- for (i = 0; i < SQ_BOOL_CONST_0_num; i++) -- EREG(ib, SQ_BOOL_CONST_0 + (i << 2), 0); -+ -+ PACK0(ib, SQ_BOOL_CONST, SQ_BOOL_CONST_all_num); -+ for (i = 0; i < SQ_BOOL_CONST_all_num; i++) -+ E32(ib, 0); - - PACK0(ib, SQ_LOOP_CONST, SQ_LOOP_CONST_all_num); - -@@ -430,10 +432,12 @@ set_alu_consts(ScrnInfoPtr pScrn, drmBufPtr ib, int offset, int count, float *co - } - - void --set_bool_const(ScrnInfoPtr pScrn, drmBufPtr ib, int offset, uint32_t val) -+set_bool_consts(ScrnInfoPtr pScrn, drmBufPtr ib, int offset, uint32_t val) - { -- /* bool order is: ps, vs, gs, ps, vs, gs, ... */ -- EREG(ib, SQ_BOOL_CONST_0 + (offset << 2), val); -+ /* bool register order is: ps, vs, gs; one register each -+ * 1 bits per bool; 32 bools each for ps, vs, gs. -+ */ -+ EREG(ib, SQ_BOOL_CONST + offset * SQ_BOOL_CONST_offset, val); - } - - void -diff --git a/src/radeon.h b/src/radeon.h -index 7bb720a..d488429 100644 ---- a/src/radeon.h -+++ b/src/radeon.h -@@ -325,6 +325,7 @@ typedef enum { - CHIP_FAMILY_RV620, - CHIP_FAMILY_RV635, - CHIP_FAMILY_RS780, -+ CHIP_FAMILY_RS880, - CHIP_FAMILY_RV770, - CHIP_FAMILY_RV730, - CHIP_FAMILY_RV710, -@@ -655,6 +656,10 @@ struct radeon_accel_state { - Bool same_surface; - int rop; - uint32_t planemask; -+ -+ // composite -+ Bool component_alpha; -+ Bool src_alpha; - #endif - - #ifdef USE_XAA -@@ -1051,8 +1056,10 @@ extern RADEONEntPtr RADEONEntPriv(ScrnInfoPtr pScrn); - extern int RADEONMinBits(int val); - extern unsigned RADEONINMC(ScrnInfoPtr pScrn, int addr); - extern unsigned RADEONINPLL(ScrnInfoPtr pScrn, int addr); -+extern unsigned RADEONINPCIE(ScrnInfoPtr pScrn, int addr); - extern void RADEONOUTMC(ScrnInfoPtr pScrn, int addr, uint32_t data); - extern void RADEONOUTPLL(ScrnInfoPtr pScrn, int addr, uint32_t data); -+extern void RADEONOUTPCIE(ScrnInfoPtr pScrn, int addr, uint32_t data); - extern void RADEONPllErrataAfterData(RADEONInfoPtr info); - extern void RADEONPllErrataAfterIndex(RADEONInfoPtr info); - extern void RADEONWaitForVerticalSync(ScrnInfoPtr pScrn); -diff --git a/src/radeon_atombios.c b/src/radeon_atombios.c -index 0b17cbd..47f5103 100644 ---- a/src/radeon_atombios.c -+++ b/src/radeon_atombios.c -@@ -1784,7 +1784,7 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn) - continue; - } - -- if ((info->ChipFamily == CHIP_FAMILY_RS780) && -+ if (info->IsIGP && - (con_obj_id == CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) { - uint32_t slot_config, ct; - -diff --git a/src/radeon_atombios.h b/src/radeon_atombios.h -index efebc62..b9a5398 100644 ---- a/src/radeon_atombios.h -+++ b/src/radeon_atombios.h -@@ -126,7 +126,7 @@ extern Bool - RADEONGetATOMTVInfo(xf86OutputPtr output); - - extern int --atombios_external_tmds_setup(xf86OutputPtr output, DisplayModePtr mode); -+atombios_external_tmds_setup(xf86OutputPtr output, int action); - - extern void - atombios_get_command_table_version(atomBiosHandlePtr atomBIOS, int index, int *major, int *minor); -diff --git a/src/radeon_bios.c b/src/radeon_bios.c -index 6fc0cf4..9b5cb88 100644 ---- a/src/radeon_bios.c -+++ b/src/radeon_bios.c -@@ -740,6 +740,9 @@ static Bool RADEONGetLegacyConnectorInfoFromBIOS (ScrnInfoPtr pScrn) - if (tmp1) { - DDCType = tmp1; - switch (DDCType) { -+ case DDC_NONE_DETECTED: -+ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "No DDC for LCD\n"); -+ break; - case DDC_MONID: - info->BiosConnector[4].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_MONID); - break; -@@ -973,8 +976,8 @@ Bool RADEONGetClockInfoFromBIOS (ScrnInfoPtr pScrn) - - pll->xclk = RADEON_BIOS16(pll_info_block + 0x08); - -- info->sclk = RADEON_BIOS16(pll_info_block + 8) / 100.0; -- info->mclk = RADEON_BIOS16(pll_info_block + 10) / 100.0; -+ info->sclk = RADEON_BIOS16(pll_info_block + 10) / 100.0; -+ info->mclk = RADEON_BIOS16(pll_info_block + 8) / 100.0; - } - - if (info->sclk == 0) info->sclk = 200; -diff --git a/src/radeon_chipinfo_gen.h b/src/radeon_chipinfo_gen.h -index eb2df17..6321246 100644 ---- a/src/radeon_chipinfo_gen.h -+++ b/src/radeon_chipinfo_gen.h -@@ -265,6 +265,8 @@ RADEONCardInfo RADEONCards[] = { - { 0x9456, CHIP_FAMILY_RV770, 0, 0, 0, 0, 0 }, - { 0x945A, CHIP_FAMILY_RV770, 1, 0, 0, 0, 0 }, - { 0x945B, CHIP_FAMILY_RV770, 1, 0, 0, 0, 0 }, -+ { 0x9460, CHIP_FAMILY_RV770, 0, 0, 0, 0, 0 }, -+ { 0x9462, CHIP_FAMILY_RV770, 0, 0, 0, 0, 0 }, - { 0x946A, CHIP_FAMILY_RV770, 1, 0, 0, 0, 0 }, - { 0x946B, CHIP_FAMILY_RV770, 1, 0, 0, 0, 0 }, - { 0x947A, CHIP_FAMILY_RV770, 1, 0, 0, 0, 0 }, -@@ -349,4 +351,11 @@ RADEONCardInfo RADEONCards[] = { - { 0x9612, CHIP_FAMILY_RS780, 0, 1, 0, 0, 1 }, - { 0x9613, CHIP_FAMILY_RS780, 0, 1, 0, 0, 1 }, - { 0x9614, CHIP_FAMILY_RS780, 0, 1, 0, 0, 1 }, -+ { 0x9615, CHIP_FAMILY_RS780, 0, 1, 0, 0, 1 }, -+ { 0x9616, CHIP_FAMILY_RS780, 0, 1, 0, 0, 1 }, -+ { 0x9710, CHIP_FAMILY_RS880, 0, 1, 0, 0, 1 }, -+ { 0x9711, CHIP_FAMILY_RS880, 0, 1, 0, 0, 1 }, -+ { 0x9712, CHIP_FAMILY_RS880, 1, 1, 0, 0, 1 }, -+ { 0x9713, CHIP_FAMILY_RS880, 1, 1, 0, 0, 1 }, -+ { 0x9714, CHIP_FAMILY_RS880, 0, 1, 0, 0, 1 }, - }; -diff --git a/src/radeon_chipset_gen.h b/src/radeon_chipset_gen.h -index 3c86ae6..631eda8 100644 ---- a/src/radeon_chipset_gen.h -+++ b/src/radeon_chipset_gen.h -@@ -265,6 +265,8 @@ static SymTabRec RADEONChipsets[] = { - { PCI_CHIP_RV770_9456, "ATI FirePro V8700 (FireGL)" }, - { PCI_CHIP_RV770_945A, "ATI Mobility RADEON HD 4870" }, - { PCI_CHIP_RV770_945B, "ATI Mobility RADEON M98" }, -+ { PCI_CHIP_RV790_9460, "ATI Radeon 4800 Series" }, -+ { PCI_CHIP_RV790_9462, "ATI Radeon 4800 Series" }, - { PCI_CHIP_RV770_946A, "ATI FirePro M7750" }, - { PCI_CHIP_RV770_946B, "ATI M98" }, - { PCI_CHIP_RV770_947A, "ATI M98" }, -@@ -349,5 +351,12 @@ static SymTabRec RADEONChipsets[] = { - { PCI_CHIP_RS780_9612, "ATI Radeon HD 3200 Graphics" }, - { PCI_CHIP_RS780_9613, "ATI Radeon 3100 Graphics" }, - { PCI_CHIP_RS780_9614, "ATI Radeon HD 3300 Graphics" }, -+ { PCI_CHIP_RS780_9615, "ATI Radeon HD 3200 Graphics" }, -+ { PCI_CHIP_RS780_9616, "ATI Radeon 3000 Graphics" }, -+ { PCI_CHIP_RS880_9710, "ATI Radeon HD Graphics" }, -+ { PCI_CHIP_RS880_9711, "ATI Radeon Graphics" }, -+ { PCI_CHIP_RS880_9712, "ATI Mobility Radeon HD Graphics" }, -+ { PCI_CHIP_RS880_9713, "ATI Mobility Radeon Graphics" }, -+ { PCI_CHIP_RS880_9714, "ATI Radeon Graphics" }, - { -1, NULL } - }; -diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c -index cd0d55e..4b508ce 100644 ---- a/src/radeon_crtc.c -+++ b/src/radeon_crtc.c -@@ -115,6 +115,9 @@ radeon_crtc_mode_prepare(xf86CrtcPtr crtc) - { - RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; - -+ if (radeon_crtc->initialized) -+ radeon_crtc_dpms(crtc, DPMSModeOff); -+ - if (radeon_crtc->enabled) - crtc->funcs->hide_cursor(crtc); - } -@@ -283,6 +286,8 @@ radeon_crtc_mode_commit(xf86CrtcPtr crtc) - { - if (crtc->scrn->pScreen != NULL) - xf86_reload_cursors(crtc->scrn->pScreen); -+ -+ radeon_crtc_dpms(crtc, DPMSModeOn); - } - - void -diff --git a/src/radeon_driver.c b/src/radeon_driver.c -index 5a15c70..8673f5e 100644 ---- a/src/radeon_driver.c -+++ b/src/radeon_driver.c -@@ -668,7 +668,30 @@ void RADEONOUTMC(ScrnInfoPtr pScrn, int addr, uint32_t data) - } - } - --static Bool avivo_get_mc_idle(ScrnInfoPtr pScrn) -+/* Read PCIE register */ -+unsigned RADEONINPCIE(ScrnInfoPtr pScrn, int addr) -+{ -+ RADEONInfoPtr info = RADEONPTR(pScrn); -+ unsigned char *RADEONMMIO = info->MMIO; -+ CARD32 data; -+ -+ OUTREG(RADEON_PCIE_INDEX, addr & 0xff); -+ data = INREG(RADEON_PCIE_DATA); -+ -+ return data; -+} -+ -+/* Write PCIE register */ -+void RADEONOUTPCIE(ScrnInfoPtr pScrn, int addr, uint32_t data) -+{ -+ RADEONInfoPtr info = RADEONPTR(pScrn); -+ unsigned char *RADEONMMIO = info->MMIO; -+ -+ OUTREG(RADEON_PCIE_INDEX, ((addr) & 0xff)); -+ OUTREG(RADEON_PCIE_DATA, data); -+} -+ -+static Bool radeon_get_mc_idle(ScrnInfoPtr pScrn) - { - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; -@@ -694,11 +717,21 @@ static Bool avivo_get_mc_idle(ScrnInfoPtr pScrn) - return TRUE; - else - return FALSE; -- } else { -+ } else if (info->ChipFamily >= CHIP_FAMILY_R520) { - if (INMC(pScrn, R520_MC_STATUS) & R520_MC_STATUS_IDLE) - return TRUE; - else - return FALSE; -+ } else if (IS_R300_VARIANT) { -+ if (INREG(RADEON_MC_STATUS) & R300_MC_IDLE) -+ return TRUE; -+ else -+ return FALSE; -+ } else { -+ if (INREG(RADEON_MC_STATUS) & RADEON_MC_IDLE) -+ return TRUE; -+ else -+ return FALSE; - } - } - -@@ -1333,7 +1366,8 @@ static void RADEONInitMemoryMap(ScrnInfoPtr pScrn) - if ((info->ChipFamily != CHIP_FAMILY_RS600) && - (info->ChipFamily != CHIP_FAMILY_RS690) && - (info->ChipFamily != CHIP_FAMILY_RS740) && -- (info->ChipFamily != CHIP_FAMILY_RS780)) { -+ (info->ChipFamily != CHIP_FAMILY_RS780) && -+ (info->ChipFamily != CHIP_FAMILY_RS880)) { - if (info->IsIGP) - info->mc_fb_location = INREG(RADEON_NB_TOM); - else -@@ -2204,6 +2238,8 @@ static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn) - } - } - -+ if (info->ChipFamily == CHIP_FAMILY_RS880) -+ return FALSE; - - if (!xf86ReturnOptValBool(info->Options, OPTION_DRI, TRUE)) { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, -@@ -3818,7 +3854,7 @@ void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn, - - usleep(10000); - timeout = 0; -- while (!(avivo_get_mc_idle(pScrn))) { -+ while (!(radeon_get_mc_idle(pScrn))) { - if (++timeout > 1000000) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "Timeout trying to update memory controller settings !\n"); -@@ -3858,7 +3894,7 @@ void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn, - if (mc_fb_loc != restore->mc_fb_location || - mc_agp_loc != restore->mc_agp_location) { - uint32_t crtc_ext_cntl, crtc_gen_cntl, crtc2_gen_cntl=0, ov0_scale_cntl; -- uint32_t old_mc_status, status_idle; -+ uint32_t old_mc_status; - - xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, - " Map Changed ! Applying ...\n"); -@@ -3897,15 +3933,8 @@ void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn, - - /* Make sure the chip settles down (paranoid !) */ - usleep(100000); -- -- /* Wait for MC idle */ -- if (IS_R300_VARIANT) -- status_idle = R300_MC_IDLE; -- else -- status_idle = RADEON_MC_IDLE; -- - timeout = 0; -- while (!(INREG(RADEON_MC_STATUS) & status_idle)) { -+ while (!(radeon_get_mc_idle(pScrn))) { - if (++timeout > 1000000) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "Timeout trying to update memory controller settings !\n"); -diff --git a/src/radeon_macros.h b/src/radeon_macros.h -index 387e5f5..b7056b0 100644 ---- a/src/radeon_macros.h -+++ b/src/radeon_macros.h -@@ -152,7 +152,9 @@ do { \ - } while (0) - - #define INMC(pScrn, addr) RADEONINMC(pScrn, addr) -- - #define OUTMC(pScrn, addr, val) RADEONOUTMC(pScrn, addr, val) - -+#define INPCIE(pScrn, addr) RADEONINPCIE(pScrn, addr) -+#define OUTPCIE(pScrn, addr, val) RADEONOUTPCIE(pScrn, addr, val -+ - #endif -diff --git a/src/radeon_output.c b/src/radeon_output.c -index 3931db4..712ac5f 100644 ---- a/src/radeon_output.c -+++ b/src/radeon_output.c -@@ -110,7 +110,6 @@ extern void atombios_output_mode_set(xf86OutputPtr output, - DisplayModePtr adjusted_mode); - extern void atombios_output_dpms(xf86OutputPtr output, int mode); - extern RADEONMonitorType atombios_dac_detect(xf86OutputPtr output); --extern int atombios_external_tmds_setup(xf86OutputPtr output, DisplayModePtr mode); - extern AtomBiosResult - atombios_lock_crtc(atomBiosHandlePtr atomBIOS, int crtc, int lock); - static void -@@ -521,32 +520,8 @@ radeon_mode_fixup(xf86OutputPtr output, DisplayModePtr mode, - static void - radeon_mode_prepare(xf86OutputPtr output) - { -- RADEONInfoPtr info = RADEONPTR(output->scrn); -- xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR (output->scrn); -- int o; -- -- for (o = 0; o < config->num_output; o++) { -- xf86OutputPtr loop_output = config->output[o]; -- if (loop_output == output) -- continue; -- else if (loop_output->crtc) { -- xf86CrtcPtr other_crtc = loop_output->crtc; -- RADEONCrtcPrivatePtr other_radeon_crtc = other_crtc->driver_private; -- if (other_crtc->enabled) { -- if (other_radeon_crtc->initialized) { -- radeon_crtc_dpms(other_crtc, DPMSModeOff); -- if (IS_AVIVO_VARIANT || info->r4xx_atom) -- atombios_lock_crtc(info->atomBIOS, other_radeon_crtc->crtc_id, 1); -- radeon_dpms(loop_output, DPMSModeOff); -- } -- } -- } -- } -- - radeon_bios_output_lock(output, TRUE); - radeon_dpms(output, DPMSModeOff); -- radeon_crtc_dpms(output->crtc, DPMSModeOff); -- - } - - static void -@@ -566,30 +541,7 @@ radeon_mode_set(xf86OutputPtr output, DisplayModePtr mode, - static void - radeon_mode_commit(xf86OutputPtr output) - { -- RADEONInfoPtr info = RADEONPTR(output->scrn); -- xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR (output->scrn); -- int o; -- -- for (o = 0; o < config->num_output; o++) { -- xf86OutputPtr loop_output = config->output[o]; -- if (loop_output == output) -- continue; -- else if (loop_output->crtc) { -- xf86CrtcPtr other_crtc = loop_output->crtc; -- RADEONCrtcPrivatePtr other_radeon_crtc = other_crtc->driver_private; -- if (other_crtc->enabled) { -- if (other_radeon_crtc->initialized) { -- radeon_crtc_dpms(other_crtc, DPMSModeOn); -- if (IS_AVIVO_VARIANT || info->r4xx_atom) -- atombios_lock_crtc(info->atomBIOS, other_radeon_crtc->crtc_id, 0); -- radeon_dpms(loop_output, DPMSModeOn); -- } -- } -- } -- } -- - radeon_dpms(output, DPMSModeOn); -- radeon_crtc_dpms(output->crtc, DPMSModeOn); - radeon_bios_output_lock(output, FALSE); - } - -@@ -1263,10 +1215,21 @@ radeon_create_resources(xf86OutputPtr output) - "RRConfigureOutputProperty error, %d\n", err); - } - /* Set the current value of the property */ -- if (radeon_output->devices & (ATOM_DEVICE_LCD_SUPPORT)) -- s = "full"; -- else -+ switch (radeon_output->rmx_type) { -+ case RMX_OFF: -+ default: - s = "off"; -+ break; -+ case RMX_FULL: -+ s = "full"; -+ break; -+ case RMX_CENTER: -+ s = "center"; -+ break; -+ case RMX_ASPECT: -+ s = "aspect"; -+ break; -+ } - err = RRChangeOutputProperty(output->randr_output, rmx_atom, - XA_STRING, 8, PropModeReplace, strlen(s), (pointer)s, - FALSE, FALSE); -@@ -1884,6 +1847,10 @@ void RADEONInitConnector(xf86OutputPtr output) - else - radeon_output->rmx_type = RMX_OFF; - -+ /* dce 3.2 chips have problems with low dot clocks, so use the scaler */ -+ if (IS_DCE32_VARIANT && (radeon_output->devices & (ATOM_DEVICE_DFP_SUPPORT))) -+ radeon_output->rmx_type = RMX_FULL; -+ - if (!IS_AVIVO_VARIANT) { - if (radeon_output->devices & (ATOM_DEVICE_CRT2_SUPPORT)) { - if (xf86ReturnOptValBool(info->Options, OPTION_TVDAC_LOAD_DETECT, FALSE)) -@@ -2067,12 +2034,12 @@ static Bool RADEONSetupAppleConnectors(ScrnInfoPtr pScrn) - info->BiosConnector[0].load_detection = FALSE; - info->BiosConnector[0].ConnectorType = CONNECTOR_DVI_I; - info->BiosConnector[0].valid = TRUE; -- info->BiosConnector[0].devices = ATOM_DEVICE_CRT1_SUPPORT | ATOM_DEVICE_DFP2_SUPPORT; -+ info->BiosConnector[0].devices = ATOM_DEVICE_CRT2_SUPPORT | ATOM_DEVICE_DFP2_SUPPORT; - if (!radeon_add_encoder(pScrn, - radeon_get_encoder_id_from_supported_device(pScrn, -- ATOM_DEVICE_CRT1_SUPPORT, -- 1), -- ATOM_DEVICE_CRT1_SUPPORT)) -+ ATOM_DEVICE_CRT2_SUPPORT, -+ 2), -+ ATOM_DEVICE_CRT2_SUPPORT)) - return FALSE; - if (!radeon_add_encoder(pScrn, - radeon_get_encoder_id_from_supported_device(pScrn, -@@ -2098,12 +2065,12 @@ static Bool RADEONSetupAppleConnectors(ScrnInfoPtr pScrn) - info->BiosConnector[0].load_detection = FALSE; - info->BiosConnector[0].ConnectorType = CONNECTOR_DVI_I; - info->BiosConnector[0].valid = TRUE; -- info->BiosConnector[0].devices = ATOM_DEVICE_CRT1_SUPPORT | ATOM_DEVICE_DFP1_SUPPORT; -+ info->BiosConnector[0].devices = ATOM_DEVICE_CRT2_SUPPORT | ATOM_DEVICE_DFP1_SUPPORT; - if (!radeon_add_encoder(pScrn, - radeon_get_encoder_id_from_supported_device(pScrn, -- ATOM_DEVICE_CRT1_SUPPORT, -- 1), -- ATOM_DEVICE_CRT1_SUPPORT)) -+ ATOM_DEVICE_CRT2_SUPPORT, -+ 2), -+ ATOM_DEVICE_CRT2_SUPPORT)) - return FALSE; - if (!radeon_add_encoder(pScrn, - radeon_get_encoder_id_from_supported_device(pScrn, -@@ -2502,11 +2469,16 @@ static RADEONMacModel RADEONDetectMacModel(ScrnInfoPtr pScrn) - static int - radeon_output_clones (ScrnInfoPtr pScrn, xf86OutputPtr output) - { -+ RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONOutputPrivatePtr radeon_output = output->driver_private; - xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR (pScrn); - int o; - int index_mask = 0; - -+ /* DIG routing gets problematic */ -+ if (IS_DCE32_VARIANT) -+ return index_mask; -+ - /* LVDS is too wacky */ - if (radeon_output->devices & (ATOM_DEVICE_LCD_SUPPORT)) - return index_mask; -diff --git a/src/radeon_pci_chipset_gen.h b/src/radeon_pci_chipset_gen.h -index 31b032a..d61c57d 100644 ---- a/src/radeon_pci_chipset_gen.h -+++ b/src/radeon_pci_chipset_gen.h -@@ -265,6 +265,8 @@ PciChipsets RADEONPciChipsets[] = { - { PCI_CHIP_RV770_9456, PCI_CHIP_RV770_9456, RES_SHARED_VGA }, - { PCI_CHIP_RV770_945A, PCI_CHIP_RV770_945A, RES_SHARED_VGA }, - { PCI_CHIP_RV770_945B, PCI_CHIP_RV770_945B, RES_SHARED_VGA }, -+ { PCI_CHIP_RV790_9460, PCI_CHIP_RV790_9460, RES_SHARED_VGA }, -+ { PCI_CHIP_RV790_9462, PCI_CHIP_RV790_9462, RES_SHARED_VGA }, - { PCI_CHIP_RV770_946A, PCI_CHIP_RV770_946A, RES_SHARED_VGA }, - { PCI_CHIP_RV770_946B, PCI_CHIP_RV770_946B, RES_SHARED_VGA }, - { PCI_CHIP_RV770_947A, PCI_CHIP_RV770_947A, RES_SHARED_VGA }, -@@ -349,5 +351,12 @@ PciChipsets RADEONPciChipsets[] = { - { PCI_CHIP_RS780_9612, PCI_CHIP_RS780_9612, RES_SHARED_VGA }, - { PCI_CHIP_RS780_9613, PCI_CHIP_RS780_9613, RES_SHARED_VGA }, - { PCI_CHIP_RS780_9614, PCI_CHIP_RS780_9614, RES_SHARED_VGA }, -+ { PCI_CHIP_RS780_9615, PCI_CHIP_RS780_9615, RES_SHARED_VGA }, -+ { PCI_CHIP_RS780_9616, PCI_CHIP_RS780_9616, RES_SHARED_VGA }, -+ { PCI_CHIP_RS880_9710, PCI_CHIP_RS880_9710, RES_SHARED_VGA }, -+ { PCI_CHIP_RS880_9711, PCI_CHIP_RS880_9711, RES_SHARED_VGA }, -+ { PCI_CHIP_RS880_9712, PCI_CHIP_RS880_9712, RES_SHARED_VGA }, -+ { PCI_CHIP_RS880_9713, PCI_CHIP_RS880_9713, RES_SHARED_VGA }, -+ { PCI_CHIP_RS880_9714, PCI_CHIP_RS880_9714, RES_SHARED_VGA }, - { -1, -1, RES_UNDEFINED } - }; -diff --git a/src/radeon_pci_device_match_gen.h b/src/radeon_pci_device_match_gen.h -index b310ce8..a06b4a6 100644 ---- a/src/radeon_pci_device_match_gen.h -+++ b/src/radeon_pci_device_match_gen.h -@@ -265,6 +265,8 @@ static const struct pci_id_match radeon_device_match[] = { - ATI_DEVICE_MATCH( PCI_CHIP_RV770_9456, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV770_945A, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV770_945B, 0 ), -+ ATI_DEVICE_MATCH( PCI_CHIP_RV790_9460, 0 ), -+ ATI_DEVICE_MATCH( PCI_CHIP_RV790_9462, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV770_946A, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV770_946B, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV770_947A, 0 ), -@@ -349,5 +351,12 @@ static const struct pci_id_match radeon_device_match[] = { - ATI_DEVICE_MATCH( PCI_CHIP_RS780_9612, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RS780_9613, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RS780_9614, 0 ), -+ ATI_DEVICE_MATCH( PCI_CHIP_RS780_9615, 0 ), -+ ATI_DEVICE_MATCH( PCI_CHIP_RS780_9616, 0 ), -+ ATI_DEVICE_MATCH( PCI_CHIP_RS880_9710, 0 ), -+ ATI_DEVICE_MATCH( PCI_CHIP_RS880_9711, 0 ), -+ ATI_DEVICE_MATCH( PCI_CHIP_RS880_9712, 0 ), -+ ATI_DEVICE_MATCH( PCI_CHIP_RS880_9713, 0 ), -+ ATI_DEVICE_MATCH( PCI_CHIP_RS880_9714, 0 ), - { 0, 0, 0 } - }; -diff --git a/src/radeon_probe.h b/src/radeon_probe.h -index a0c6b2c..6479972 100644 ---- a/src/radeon_probe.h -+++ b/src/radeon_probe.h -@@ -271,8 +271,10 @@ typedef struct _RADEONOutputPrivateRec { - radeon_tvout_rec tvout; - - /* dce 3.x dig block */ -- int transmitter_config; - int igp_lane_info; -+ int dig_block; -+ -+ int pixel_clock; - } RADEONOutputPrivateRec, *RADEONOutputPrivatePtr; - - struct avivo_pll_state { -diff --git a/src/radeon_reg.h b/src/radeon_reg.h -index 0af8859..d74a30a 100644 ---- a/src/radeon_reg.h -+++ b/src/radeon_reg.h -@@ -274,6 +274,9 @@ - #define RADEON_BUS_CNTL1 0x0034 - # define RADEON_BUS_WAIT_ON_LOCK_EN (1 << 4) - -+#define RADEON_PCIE_INDEX 0x0030 -+#define RADEON_PCIE_DATA 0x0034 -+ - #define RADEON_CACHE_CNTL 0x1724 - #define RADEON_CACHE_LINE 0x0f0c /* PCI */ - #define RADEON_CAPABILITIES_ID 0x0f50 /* PCI */ -@@ -3027,6 +3030,18 @@ - # define R200_TXA_REPL_ARG_B_MASK (3 << 28) - # define R200_TXA_REPL_ARG_C_SHIFT 30 - # define R200_TXA_REPL_ARG_C_MASK (3 << 30) -+#define R200_PP_TXCBLEND_1 0x2f10 -+#define R200_PP_TXCBLEND2_1 0x2f14 -+#define R200_PP_TXABLEND_1 0x2f18 -+#define R200_PP_TXABLEND2_1 0x2f1c -+#define R200_PP_TXCBLEND_2 0x2f20 -+#define R200_PP_TXCBLEND2_2 0x2f24 -+#define R200_PP_TXABLEND_2 0x2f28 -+#define R200_PP_TXABLEND2_2 0x2f2c -+#define R200_PP_TXCBLEND_3 0x2f30 -+#define R200_PP_TXCBLEND2_3 0x2f34 -+#define R200_PP_TXABLEND_3 0x2f38 -+#define R200_PP_TXABLEND2_3 0x2f3c - - #define R200_SE_VTX_FMT_0 0x2088 - # define R200_VTX_XY 0 /* always have xy */ -@@ -3291,7 +3306,9 @@ - # define RADEON_RGB_CONVERT_BY_PASS (1 << 10) - # define RADEON_UVRAM_READ_MARGIN_SHIFT 16 - # define RADEON_FIFORAM_FFMACRO_READ_MARGIN_SHIFT 20 -+# define RADEON_RGB_ATTEN_SEL(x) ((x) << 24) - # define RADEON_TVOUT_SCALE_EN (1 << 26) -+# define RADEON_RGB_ATTEN_VAL(x) ((x) << 28) - #define RADEON_TV_SYNC_CNTL 0x0808 - # define RADEON_SYNC_OE (1 << 0) - # define RADEON_SYNC_OUT (1 << 1) -@@ -3610,6 +3627,13 @@ - # define AVIVO_D1GRPH_MACRO_ADDRESS_MODE (1<<21) - - #define AVIVO_D1GRPH_LUT_SEL 0x6108 -+ -+#define R600_D1GRPH_SWAP_CONTROL 0x610C -+# define R600_D1GRPH_SWAP_ENDIAN_NONE (0 << 0) -+# define R600_D1GRPH_SWAP_ENDIAN_16BIT (1 << 0) -+# define R600_D1GRPH_SWAP_ENDIAN_32BIT (2 << 0) -+# define R600_D1GRPH_SWAP_ENDIAN_64BIT (3 << 0) -+ - #define AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS 0x6110 - #define AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS 0x6118 - #define AVIVO_D1GRPH_PITCH 0x6120 -@@ -4406,6 +4430,7 @@ - #define R300_TX_INVALTAGS 0x4100 - #define R300_TX_FILTER0_0 0x4400 - #define R300_TX_FILTER0_1 0x4404 -+#define R300_TX_FILTER0_2 0x4408 - # define R300_TX_CLAMP_S(x) ((x) << 0) - # define R300_TX_CLAMP_T(x) ((x) << 3) - # define R300_TX_CLAMP_R(x) ((x) << 6) -@@ -4424,8 +4449,10 @@ - # define R300_TX_ID_SHIFT 28 - #define R300_TX_FILTER1_0 0x4440 - #define R300_TX_FILTER1_1 0x4444 -+#define R300_TX_FILTER1_2 0x4448 - #define R300_TX_FORMAT0_0 0x4480 - #define R300_TX_FORMAT0_1 0x4484 -+#define R300_TX_FORMAT0_2 0x4488 - # define R300_TXWIDTH_SHIFT 0 - # define R300_TXHEIGHT_SHIFT 11 - # define R300_NUM_LEVELS_SHIFT 26 -@@ -4434,6 +4461,7 @@ - # define R300_TXPITCH_EN (1 << 31) - #define R300_TX_FORMAT1_0 0x44c0 - #define R300_TX_FORMAT1_1 0x44c4 -+#define R300_TX_FORMAT1_2 0x44c8 - # define R300_TX_FORMAT_X8 0x0 - # define R300_TX_FORMAT_X16 0x1 - # define R300_TX_FORMAT_Y4X4 0x2 -@@ -4506,13 +4534,23 @@ - # define R300_TX_FORMAT_YUV_TO_RGB_NO_CLAMP (2 << 22) - # define R300_TX_FORMAT_SWAP_YUV (1 << 24) - -+# define R300_TX_FORMAT_CACHE_WHOLE (0 << 27) -+# define R300_TX_FORMAT_CACHE_HALF_REGION_0 (2 << 27) -+# define R300_TX_FORMAT_CACHE_HALF_REGION_1 (3 << 27) -+# define R300_TX_FORMAT_CACHE_FOURTH_REGION_0 (4 << 27) -+# define R300_TX_FORMAT_CACHE_FOURTH_REGION_1 (5 << 27) -+# define R300_TX_FORMAT_CACHE_FOURTH_REGION_2 (6 << 27) -+# define R300_TX_FORMAT_CACHE_FOURTH_REGION_3 (7 << 27) -+ - #define R300_TX_FORMAT2_0 0x4500 - #define R300_TX_FORMAT2_1 0x4504 -+#define R300_TX_FORMAT2_2 0x4508 - # define R500_TXWIDTH_11 (1 << 15) - # define R500_TXHEIGHT_11 (1 << 16) - - #define R300_TX_OFFSET_0 0x4540 - #define R300_TX_OFFSET_1 0x4544 -+#define R300_TX_OFFSET_2 0x4548 - # define R300_ENDIAN_SWAP_16_BIT (1 << 0) - # define R300_ENDIAN_SWAP_32_BIT (2 << 0) - # define R300_ENDIAN_SWAP_HALF_DWORD (3 << 0) -@@ -4523,6 +4561,7 @@ - #define R300_TX_ENABLE 0x4104 - # define R300_TEX_0_ENABLE (1 << 0) - # define R300_TEX_1_ENABLE (1 << 1) -+# define R300_TEX_2_ENABLE (1 << 2) - - #define R300_US_W_FMT 0x46b4 - #define R300_US_OUT_FMT_1 0x46a8 -diff --git a/src/radeon_textured_video.c b/src/radeon_textured_video.c -index 2df299f..79671c0 100644 ---- a/src/radeon_textured_video.c -+++ b/src/radeon_textured_video.c -@@ -119,6 +119,15 @@ static __inline__ uint32_t F_TO_24(float val) - return float24; - } - -+static __inline__ uint32_t float4touint(float fr, float fg, float fb, float fa) -+{ -+ unsigned ur = fr * 255.0 + 0.5; -+ unsigned ug = fg * 255.0 + 0.5; -+ unsigned ub = fb * 255.0 + 0.5; -+ unsigned ua = fa * 255.0 + 0.5; -+ return (ua << 24) | (ur << 16) | (ug << 8) | ub; -+} -+ - #define ACCEL_MMIO - #define ACCEL_PREAMBLE() unsigned char *RADEONMMIO = info->MMIO - #define BEGIN_ACCEL(n) RADEONWaitForFifo(pScrn, (n)) -@@ -304,8 +313,9 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn, - RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONPortPrivPtr pPriv = (RADEONPortPrivPtr)data; - INT32 x1, x2, y1, y2; -- int srcPitch, srcPitch2, dstPitch; -+ int srcPitch, srcPitch2, dstPitch, dstPitch2 = 0; - int s2offset, s3offset, tmp; -+ int d2line, d3line; - int top, left, npixels, nlines, size; - BoxRec dstBox; - int dst_width = width, dst_height = height; -@@ -327,36 +337,64 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn, - if (!xf86XVClipVideoHelper(&dstBox, &x1, &x2, &y1, &y2, clipBoxes, width, height)) - return Success; - -- src_w = (x2 - x1) >> 16; -+/* src_w = (x2 - x1) >> 16; - src_h = (y2 - y1) >> 16; - drw_w = dstBox.x2 - dstBox.x1; -- drw_h = dstBox.y2 - dstBox.y1; -+ drw_h = dstBox.y2 - dstBox.y1;*/ - - if ((x1 >= x2) || (y1 >= y2)) - return Success; - -+ /* Bicubic filter setup */ -+ pPriv->bicubic_enabled = (pPriv->bicubic_state != BICUBIC_OFF); -+ if (!(IS_R300_3D || IS_R500_3D || IS_R600_3D)) -+ pPriv->bicubic_enabled = FALSE; -+ if (pPriv->bicubic_enabled && (pPriv->bicubic_state == BICUBIC_AUTO)) { -+ /* -+ * Applying the bicubic filter with a scale of less than 200% -+ * results in a blurred picture, so disable the filter. -+ */ -+ if ((src_w > drw_w / 2) || (src_h > drw_h / 2)) -+ pPriv->bicubic_enabled = FALSE; -+ } -+ -+ pPriv->planar_hw = pPriv->planar_state; -+ if (pPriv->bicubic_enabled || !( IS_R300_3D || -+ (info->ChipFamily == CHIP_FAMILY_RV250) || -+ (info->ChipFamily == CHIP_FAMILY_RV280) || -+ (info->ChipFamily == CHIP_FAMILY_RS300) || -+ (info->ChipFamily == CHIP_FAMILY_R200) )) -+ pPriv->planar_hw = 0; -+ - switch(id) { - case FOURCC_YV12: - case FOURCC_I420: -- dstPitch = ((dst_width << 1) + 15) & ~15; - srcPitch = (width + 3) & ~3; - srcPitch2 = ((width >> 1) + 3) & ~3; -- size = dstPitch * dst_height; -+ if (pPriv->planar_hw) { -+ dstPitch = (dst_width + 15) & ~15; -+ dstPitch = (dstPitch + 63) & ~63; -+ dstPitch2 = ((dst_width >> 1) + 15) & ~15; -+ dstPitch2 = (dstPitch2 + 63) & ~63; -+ } else { -+ dstPitch = ((dst_width << 1) + 15) & ~15; -+ dstPitch = (dstPitch + 63) & ~63; -+ } - break; - case FOURCC_UYVY: - case FOURCC_YUY2: - default: - dstPitch = ((dst_width << 1) + 15) & ~15; -+ dstPitch = (dstPitch + 63) & ~63; - srcPitch = (width << 1); - srcPitch2 = 0; -- size = dstPitch * dst_height; - break; - } - - if (info->ChipFamily >= CHIP_FAMILY_R600) - dstPitch = (dstPitch + 255) & ~255; -- else -- dstPitch = (dstPitch + 63) & ~63; -+ -+ size = dstPitch * dst_height + 2 * dstPitch2 * ((dst_height + 1) >> 1); - - if (pPriv->video_memory != NULL && size != pPriv->size) { - radeon_legacy_free_memory(pScrn, pPriv->video_memory); -@@ -376,19 +414,6 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn, - return BadAlloc; - } - -- /* Bicubic filter setup */ -- pPriv->bicubic_enabled = (pPriv->bicubic_state != BICUBIC_OFF); -- if (!(IS_R300_3D || IS_R500_3D || IS_R600_3D)) -- pPriv->bicubic_enabled = FALSE; -- if (pPriv->bicubic_enabled && (pPriv->bicubic_state == BICUBIC_AUTO)) { -- /* -- * Applying the bicubic filter with a scale of less than 200% -- * results in a blurred picture, so disable the filter. -- */ -- if ((src_w > drw_w / 2) || (src_h > drw_h / 2)) -- pPriv->bicubic_enabled = FALSE; -- } -- - /* Bicubic filter loading */ - if (pPriv->bicubic_memory == NULL && pPriv->bicubic_enabled) { - pPriv->bicubic_offset = radeon_legacy_allocate_memory(pScrn, -@@ -432,10 +457,16 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn, - else - pPriv->src_addr = (uint8_t *)(info->FB + pPriv->video_offset + (top * dstPitch)); - pPriv->src_pitch = dstPitch; -+ pPriv->planeu_offset = dstPitch * dst_height; -+ pPriv->planev_offset = pPriv->planeu_offset + dstPitch2 * ((dst_height + 1) >> 1); - pPriv->size = size; - pPriv->pDraw = pDraw; - -+ - #if 0 -+ ErrorF("planeu_offset: 0x%x\n", pPriv->planeu_offset); -+ ErrorF("planev_offset: 0x%x\n", pPriv->planev_offset); -+ ErrorF("dstPitch2: 0x%x\n", dstPitch2); - ErrorF("src_offset: 0x%x\n", pPriv->src_offset); - ErrorF("src_addr: 0x%x\n", pPriv->src_addr); - ErrorF("src_pitch: 0x%x\n", pPriv->src_pitch); -@@ -470,12 +501,34 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn, - srcPitch, srcPitch2, pPriv->src_pitch, - width, height); - } -+ } -+ else if (pPriv->planar_hw) { -+ top &= ~1; -+ s2offset = srcPitch * ((height + 1) & ~1); -+ s3offset = s2offset + srcPitch2 * ((height + 1) >> 1); -+ s2offset += (top >> 1) * srcPitch2 + (left >> 1); -+ s3offset += (top >> 1) * srcPitch2 + (left >> 1); -+ d2line = pPriv->planeu_offset; -+ d3line = pPriv->planev_offset; -+ d2line += (top >> 1) * dstPitch2 - (top * dstPitch); -+ d3line += (top >> 1) * dstPitch2 - (top * dstPitch); -+ nlines = ((y2 + 0xffff) >> 16) - top; -+ if(id == FOURCC_YV12) { -+ tmp = s2offset; -+ s2offset = s3offset; -+ s3offset = tmp; -+ } -+ RADEONCopyData(pScrn, buf + (top * srcPitch) + left, pPriv->src_addr + left, -+ srcPitch, dstPitch, nlines, npixels, 1); -+ RADEONCopyData(pScrn, buf + s2offset, pPriv->src_addr + d2line + (left >> 1), -+ srcPitch2, dstPitch2, (nlines + 1) >> 1, npixels >> 1, 1); -+ RADEONCopyData(pScrn, buf + s3offset, pPriv->src_addr + d3line + (left >> 1), -+ srcPitch2, dstPitch2, (nlines + 1) >> 1, npixels >> 1, 1); - } else { - top &= ~1; - nlines = ((((y2 + 0xffff) >> 16) + 1) & ~1) - top; - s2offset = srcPitch * height; - s3offset = (srcPitch2 * (height >> 1)) + s2offset; -- top &= ~1; - pPriv->src_addr += left << 1; - tmp = ((top >> 1) * srcPitch2) + (left >> 1); - s2offset += tmp; -@@ -504,7 +557,9 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn, - width, height); - } else { - nlines = ((y2 + 0xffff) >> 16) - top; -- RADEONCopyData(pScrn, buf, pPriv->src_addr, srcPitch, dstPitch, nlines, npixels, 2); -+ pPriv->src_addr += left << 1; -+ RADEONCopyData(pScrn, buf + (top * srcPitch) + (left << 1), -+ pPriv->src_addr, srcPitch, dstPitch, nlines, npixels, 2); - } - break; - } -@@ -581,25 +636,28 @@ static XF86VideoFormatRec Formats[NUM_FORMATS] = - {15, TrueColor}, {16, TrueColor}, {24, TrueColor} - }; - --#define NUM_ATTRIBUTES 1 -+#define NUM_ATTRIBUTES 2 - - static XF86AttributeRec Attributes[NUM_ATTRIBUTES+1] = - { - {XvSettable | XvGettable, 0, 1, "XV_VSYNC"}, -+ {XvSettable | XvGettable, 0, 1, "XV_HWPLANAR"}, - {0, 0, 0, NULL} - }; - --#define NUM_ATTRIBUTES_R300 2 -+#define NUM_ATTRIBUTES_R300 3 - - static XF86AttributeRec Attributes_r300[NUM_ATTRIBUTES_R300+1] = - { - {XvSettable | XvGettable, 0, 2, "XV_BICUBIC"}, - {XvSettable | XvGettable, 0, 1, "XV_VSYNC"}, -+ {XvSettable | XvGettable, 0, 1, "XV_HWPLANAR"}, - {0, 0, 0, NULL} - }; - - static Atom xvBicubic; - static Atom xvVSync; -+static Atom xvHWPlanar; - - #define NUM_IMAGES 4 - -@@ -626,6 +684,8 @@ RADEONGetTexPortAttribute(ScrnInfoPtr pScrn, - *value = pPriv->bicubic_state; - else if (attribute == xvVSync) - *value = pPriv->vsync; -+ else if (attribute == xvHWPlanar) -+ *value = pPriv->planar_state; - else - return BadMatch; - -@@ -647,6 +707,8 @@ RADEONSetTexPortAttribute(ScrnInfoPtr pScrn, - pPriv->bicubic_state = ClipValue (value, 0, 2); - else if (attribute == xvVSync) - pPriv->vsync = ClipValue (value, 0, 1); -+ else if (attribute == xvHWPlanar) -+ pPriv->planar_state = ClipValue (value, 0, 1); - else - return BadMatch; - -@@ -670,6 +732,7 @@ RADEONSetupImageTexturedVideo(ScreenPtr pScreen) - - xvBicubic = MAKE_ATOM("XV_BICUBIC"); - xvVSync = MAKE_ATOM("XV_VSYNC"); -+ xvHWPlanar = MAKE_ATOM("XV_HWPLANAR"); - - adapt->type = XvWindowMask | XvInputMask | XvImageMask; - adapt->flags = 0; -@@ -719,6 +782,7 @@ RADEONSetupImageTexturedVideo(ScreenPtr pScreen) - pPriv->doubleBuffer = 0; - pPriv->bicubic_state = BICUBIC_AUTO; - pPriv->vsync = TRUE; -+ pPriv->planar_state = 1; - - /* gotta uninit this someplace, XXX: shouldn't be necessary for textured */ - REGION_NULL(pScreen, &pPriv->clip); -diff --git a/src/radeon_textured_videofuncs.c b/src/radeon_textured_videofuncs.c -index f55ae12..05acb93 100644 ---- a/src/radeon_textured_videofuncs.c -+++ b/src/radeon_textured_videofuncs.c -@@ -97,6 +97,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv - uint32_t dst_offset, dst_pitch, dst_format; - uint32_t txenable, colorpitch; - uint32_t blendcntl; -+ Bool isplanar = FALSE; - int dstxoff, dstyoff, pixel_shift, vtx_count; - BoxPtr pBox = REGION_RECTS(&pPriv->clip); - int nBox = REGION_NUM_RECTS(&pPriv->clip); -@@ -181,16 +182,29 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv - if (RADEONTilingEnabled(pScrn, pPixmap)) - colorpitch |= R300_COLORTILE; - -- if (pPriv->id == FOURCC_UYVY) -- txformat1 = R300_TX_FORMAT_YVYU422; -- else -- txformat1 = R300_TX_FORMAT_VYUY422; -+ if (pPriv->planar_hw && (pPriv->id == FOURCC_I420 || pPriv->id == FOURCC_YV12)) { -+ isplanar = TRUE; -+ } -+ -+ if (isplanar) { -+ txformat1 = R300_TX_FORMAT_X8 | R300_TX_FORMAT_CACHE_HALF_REGION_0; -+ txpitch = pPriv->src_pitch; -+ } else { -+ if (pPriv->id == FOURCC_UYVY) -+ txformat1 = R300_TX_FORMAT_YVYU422; -+ else -+ txformat1 = R300_TX_FORMAT_VYUY422; -+ -+ txformat1 |= R300_TX_FORMAT_YUV_TO_RGB_CLAMP; - -- txformat1 |= R300_TX_FORMAT_YUV_TO_RGB_CLAMP; -+ /* pitch is in pixels */ -+ txpitch = pPriv->src_pitch / 2; -+ } -+ txpitch -= 1; - - txformat0 = ((((pPriv->w - 1) & 0x7ff) << R300_TXWIDTH_SHIFT) | -- (((pPriv->h - 1) & 0x7ff) << R300_TXHEIGHT_SHIFT) | -- R300_TXPITCH_EN); -+ (((pPriv->h - 1) & 0x7ff) << R300_TXHEIGHT_SHIFT) | -+ R300_TXPITCH_EN); - - info->accel_state->texW[0] = pPriv->w; - info->accel_state->texH[0] = pPriv->h; -@@ -201,9 +215,6 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv - R300_TX_MIN_FILTER_LINEAR | - (0 << R300_TX_ID_SHIFT)); - -- /* pitch is in pixels */ -- txpitch = pPriv->src_pitch / 2; -- txpitch -= 1; - - if (IS_R500_3D && ((pPriv->w - 1) & 0x800)) - txpitch |= R500_TXWIDTH_11; -@@ -224,6 +235,34 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv - - txenable = R300_TEX_0_ENABLE; - -+ if (isplanar) { -+ txformat0 = ((((((pPriv->w + 1 ) >> 1) - 1) & 0x7ff) << R300_TXWIDTH_SHIFT) | -+ (((((pPriv->h + 1 ) >> 1 ) - 1) & 0x7ff) << R300_TXHEIGHT_SHIFT) | -+ R300_TXPITCH_EN); -+ txpitch = ((pPriv->src_pitch >> 1) + 63) & ~63; -+ txpitch -= 1; -+ txfilter = (R300_TX_CLAMP_S(R300_TX_CLAMP_CLAMP_LAST) | -+ R300_TX_CLAMP_T(R300_TX_CLAMP_CLAMP_LAST) | -+ R300_TX_MIN_FILTER_LINEAR | -+ R300_TX_MAG_FILTER_LINEAR); -+ -+ BEGIN_ACCEL(12); -+ OUT_ACCEL_REG(R300_TX_FILTER0_1, txfilter | (1 << R300_TX_ID_SHIFT)); -+ OUT_ACCEL_REG(R300_TX_FILTER1_1, 0); -+ OUT_ACCEL_REG(R300_TX_FORMAT0_1, txformat0); -+ OUT_ACCEL_REG(R300_TX_FORMAT1_1, R300_TX_FORMAT_X8 | R300_TX_FORMAT_CACHE_FOURTH_REGION_2); -+ OUT_ACCEL_REG(R300_TX_FORMAT2_1, txpitch); -+ OUT_ACCEL_REG(R300_TX_OFFSET_1, txoffset + pPriv->planeu_offset); -+ OUT_ACCEL_REG(R300_TX_FILTER0_2, txfilter | (2 << R300_TX_ID_SHIFT)); -+ OUT_ACCEL_REG(R300_TX_FILTER1_2, 0); -+ OUT_ACCEL_REG(R300_TX_FORMAT0_2, txformat0); -+ OUT_ACCEL_REG(R300_TX_FORMAT1_2, R300_TX_FORMAT_X8 | R300_TX_FORMAT_CACHE_FOURTH_REGION_3); -+ OUT_ACCEL_REG(R300_TX_FORMAT2_2, txpitch); -+ OUT_ACCEL_REG(R300_TX_OFFSET_2, txoffset + pPriv->planev_offset); -+ FINISH_ACCEL(); -+ txenable |= R300_TEX_1_ENABLE | R300_TEX_2_ENABLE; -+ } -+ - if (pPriv->bicubic_enabled) { - /* Size is 128x1 */ - txformat0 = ((0x7f << R300_TXWIDTH_SHIFT) | -@@ -691,6 +730,171 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv - OUT_ACCEL_REG(R300_US_ALU_CONST_A(1), 0); - - FINISH_ACCEL(); -+ } else if (isplanar) { -+ /* -+ * y' = y - .0625 -+ * u' = u - .5 -+ * v' = v - .5; -+ * -+ * r = 1.1643 * y' + 0.0 * u' + 1.5958 * v' -+ * g = 1.1643 * y' - 0.39173 * u' - 0.81290 * v' -+ * b = 1.1643 * y' + 2.017 * u' + 0.0 * v' -+ * -+ * DP3 might look like the straightforward solution -+ * but we'd need to move the texture yuv values in -+ * the same reg for this to work. Therefore use MADs. -+ * Without changing the shader at all (only the constants) -+ * could also provide hue/saturation/brightness/contrast control. -+ * -+ * yco = 1.1643 -+ * uco = 0, -0.39173, 2.017 -+ * vco = 1.5958, -0.8129, 0 -+ * off = -0.0625 * yco + -0.5 * uco[r] + -0.5 * vco[r], -+ * -0.0625 * yco + -0.5 * uco[g] + -0.5 * vco[g], -+ * -0.0625 * yco + -0.5 * uco[b] + -0.5 * vco[b], -+ * -+ * temp = MAD(yco, yuv.yyyy, off) -+ * temp = MAD(uco, yuv.uuuu, temp) -+ * result = MAD(vco, yuv.vvvv, temp) -+ */ -+ float yco = 1.1643; -+ float uco[3] = {0.0, -0.39173, 2.018}; -+ float vco[3] = {1.5958, -0.8129, 0.0}; -+ float off[3] = {-0.0625 * yco + -0.5 * uco[0] + -0.5 * vco[0], -+ -0.0625 * yco + -0.5 * uco[1] + -0.5 * vco[1], -+ -0.0625 * yco + -0.5 * uco[2] + -0.5 * vco[2]}; -+ -+ BEGIN_ACCEL(33); -+ /* 2 components: same 2 for tex0/1/2 */ -+ OUT_ACCEL_REG(R300_RS_COUNT, -+ ((2 << R300_RS_COUNT_IT_COUNT_SHIFT) | -+ R300_RS_COUNT_HIRES_EN)); -+ /* R300_INST_COUNT_RS - highest RS instruction used */ -+ OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(0) | R300_TX_OFFSET_RS(6)); -+ -+ OUT_ACCEL_REG(R300_US_PIXSIZE, 2); /* highest temp used */ -+ -+ /* Indirection levels */ -+ OUT_ACCEL_REG(R300_US_CONFIG, ((0 << R300_NLEVEL_SHIFT) | -+ R300_FIRST_TEX)); -+ -+ OUT_ACCEL_REG(R300_US_CODE_OFFSET, (R300_ALU_CODE_OFFSET(0) | -+ R300_ALU_CODE_SIZE(3) | -+ R300_TEX_CODE_OFFSET(0) | -+ R300_TEX_CODE_SIZE(3))); -+ -+ OUT_ACCEL_REG(R300_US_CODE_ADDR_3, (R300_ALU_START(0) | -+ R300_ALU_SIZE(2) | -+ R300_TEX_START(0) | -+ R300_TEX_SIZE(2) | -+ R300_RGBA_OUT)); -+ -+ /* tex inst */ -+ OUT_ACCEL_REG(R300_US_TEX_INST_0, (R300_TEX_SRC_ADDR(0) | -+ R300_TEX_DST_ADDR(0) | -+ R300_TEX_ID(0) | -+ R300_TEX_INST(R300_TEX_INST_LD))); -+ OUT_ACCEL_REG(R300_US_TEX_INST_1, (R300_TEX_SRC_ADDR(0) | -+ R300_TEX_DST_ADDR(1) | -+ R300_TEX_ID(1) | -+ R300_TEX_INST(R300_TEX_INST_LD))); -+ OUT_ACCEL_REG(R300_US_TEX_INST_2, (R300_TEX_SRC_ADDR(0) | -+ R300_TEX_DST_ADDR(2) | -+ R300_TEX_ID(2) | -+ R300_TEX_INST(R300_TEX_INST_LD))); -+ -+ /* ALU inst */ -+ /* MAD temp0, const0.a, temp0, const0.rgb */ -+ OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR(0), (R300_ALU_RGB_ADDR0(R300_ALU_RGB_CONST(0)) | -+ R300_ALU_RGB_ADDR1(0) | -+ R300_ALU_RGB_ADDR2(0) | -+ R300_ALU_RGB_ADDRD(0) | -+ R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_RGB))); -+ OUT_ACCEL_REG(R300_US_ALU_RGB_INST(0), (R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_AAA) | -+ R300_ALU_RGB_MOD_A(R300_ALU_RGB_MOD_NOP) | -+ R300_ALU_RGB_SEL_B(R300_ALU_RGB_SRC1_RGB) | -+ R300_ALU_RGB_MOD_B(R300_ALU_RGB_MOD_NOP) | -+ R300_ALU_RGB_SEL_C(R300_ALU_RGB_SRC0_RGB) | -+ R300_ALU_RGB_MOD_C(R300_ALU_RGB_MOD_NOP) | -+ R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) | -+ R300_ALU_RGB_OMOD(R300_ALU_RGB_OMOD_NONE))); -+ /* alpha nop, but need to set up alpha source for rgb usage */ -+ OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(0), (R300_ALU_ALPHA_ADDR0(R300_ALU_ALPHA_CONST(0)) | -+ R300_ALU_ALPHA_ADDR1(0) | -+ R300_ALU_ALPHA_ADDR2(0) | -+ R300_ALU_ALPHA_ADDRD(0) | -+ R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE))); -+ OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST(0), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) | -+ R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_0_0) | -+ R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) | -+ R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0))); -+ -+ /* MAD const1, temp1, temp0 */ -+ OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR(1), (R300_ALU_RGB_ADDR0(R300_ALU_RGB_CONST(1)) | -+ R300_ALU_RGB_ADDR1(1) | -+ R300_ALU_RGB_ADDR2(0) | -+ R300_ALU_RGB_ADDRD(0) | -+ R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_RGB))); -+ OUT_ACCEL_REG(R300_US_ALU_RGB_INST(1), (R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_RGB) | -+ R300_ALU_RGB_MOD_A(R300_ALU_RGB_MOD_NOP) | -+ R300_ALU_RGB_SEL_B(R300_ALU_RGB_SRC1_RGB) | -+ R300_ALU_RGB_MOD_B(R300_ALU_RGB_MOD_NOP) | -+ R300_ALU_RGB_SEL_C(R300_ALU_RGB_SRC2_RGB) | -+ R300_ALU_RGB_MOD_C(R300_ALU_RGB_MOD_NOP) | -+ R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) | -+ R300_ALU_RGB_OMOD(R300_ALU_RGB_OMOD_NONE))); -+ /* alpha nop */ -+ OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(1), (R300_ALU_ALPHA_ADDRD(0) | -+ R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE))); -+ OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST(1), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) | -+ R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_0_0) | -+ R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) | -+ R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0))); -+ -+ /* MAD result, const2, temp2, temp0 */ -+ OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR(2), (R300_ALU_RGB_ADDR0(R300_ALU_RGB_CONST(2)) | -+ R300_ALU_RGB_ADDR1(2) | -+ R300_ALU_RGB_ADDR2(0) | -+ R300_ALU_RGB_ADDRD(0) | -+ R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_RGB) | -+ R300_ALU_RGB_OMASK(R300_ALU_RGB_MASK_RGB))); -+ OUT_ACCEL_REG(R300_US_ALU_RGB_INST(2), (R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_RGB) | -+ R300_ALU_RGB_MOD_A(R300_ALU_RGB_MOD_NOP) | -+ R300_ALU_RGB_SEL_B(R300_ALU_RGB_SRC1_RGB) | -+ R300_ALU_RGB_MOD_B(R300_ALU_RGB_MOD_NOP) | -+ R300_ALU_RGB_SEL_C(R300_ALU_RGB_SRC2_RGB) | -+ R300_ALU_RGB_MOD_C(R300_ALU_RGB_MOD_NOP) | -+ R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) | -+ R300_ALU_RGB_OMOD(R300_ALU_RGB_OMOD_NONE) | -+ R300_ALU_RGB_CLAMP)); -+ /* write alpha 1 */ -+ OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(4), (R300_ALU_ALPHA_ADDRD(0) | -+ R300_ALU_ALPHA_OMASK(R300_ALU_ALPHA_MASK_A) | -+ R300_ALU_ALPHA_TARGET_A)); -+ OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST(4), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) | -+ R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_0_0) | -+ R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) | -+ R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_1_0))); -+ -+ /* Shader constants. */ -+ /* constant 0: off, yco */ -+ OUT_ACCEL_REG(R300_US_ALU_CONST_R(0), F_TO_24(off[0])); -+ OUT_ACCEL_REG(R300_US_ALU_CONST_G(0), F_TO_24(off[1])); -+ OUT_ACCEL_REG(R300_US_ALU_CONST_B(0), F_TO_24(off[2])); -+ OUT_ACCEL_REG(R300_US_ALU_CONST_A(0), F_TO_24(yco)); -+ /* constant 1: uco */ -+ OUT_ACCEL_REG(R300_US_ALU_CONST_R(1), F_TO_24(uco[0])); -+ OUT_ACCEL_REG(R300_US_ALU_CONST_G(1), F_TO_24(uco[1])); -+ OUT_ACCEL_REG(R300_US_ALU_CONST_B(1), F_TO_24(uco[2])); -+ OUT_ACCEL_REG(R300_US_ALU_CONST_A(1), F_TO_24(0.0)); -+ /* constant 2: vco */ -+ OUT_ACCEL_REG(R300_US_ALU_CONST_R(2), F_TO_24(vco[0])); -+ OUT_ACCEL_REG(R300_US_ALU_CONST_G(2), F_TO_24(vco[1])); -+ OUT_ACCEL_REG(R300_US_ALU_CONST_B(2), F_TO_24(vco[2])); -+ OUT_ACCEL_REG(R300_US_ALU_CONST_A(2), F_TO_24(0.0)); -+ -+ FINISH_ACCEL(); -+ - } else { - BEGIN_ACCEL(11); - /* 2 components: 2 for tex0 */ -@@ -760,7 +964,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv - R300_ALU_ALPHA_OMOD(R300_ALU_ALPHA_OMOD_NONE) | - R300_ALU_ALPHA_CLAMP)); - FINISH_ACCEL(); -- } -+ } - } else { - if (pPriv->bicubic_enabled) { - BEGIN_ACCEL(7); -@@ -1363,10 +1567,18 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv - return; - } - -- if (pPriv->id == FOURCC_UYVY) -- txformat = RADEON_TXFORMAT_YVYU422; -- else -- txformat = RADEON_TXFORMAT_VYUY422; -+ if (pPriv->planar_hw && (pPriv->id == FOURCC_I420 || pPriv->id == FOURCC_YV12)) { -+ isplanar = TRUE; -+ } -+ -+ if (isplanar) { -+ txformat = RADEON_TXFORMAT_I8; -+ } else { -+ if (pPriv->id == FOURCC_UYVY) -+ txformat = RADEON_TXFORMAT_YVYU422; -+ else -+ txformat = RADEON_TXFORMAT_VYUY422; -+ } - - txformat |= RADEON_TXFORMAT_NON_POWER2; - -@@ -1375,12 +1587,10 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv - if (RADEONTilingEnabled(pScrn, pPixmap)) - colorpitch |= RADEON_COLOR_TILE_ENABLE; - -- BEGIN_ACCEL(5); -+ BEGIN_ACCEL(4); - -- OUT_ACCEL_REG(RADEON_PP_CNTL, -- RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE); - OUT_ACCEL_REG(RADEON_RB3D_CNTL, -- dst_format | RADEON_ALPHA_BLEND_ENABLE); -+ dst_format /*| RADEON_ALPHA_BLEND_ENABLE*/); - OUT_ACCEL_REG(RADEON_RB3D_COLOROFFSET, dst_offset); - - OUT_ACCEL_REG(RADEON_RB3D_COLORPITCH, colorpitch); -@@ -1399,48 +1609,346 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv - info->accel_state->texW[0] = pPriv->w; - info->accel_state->texH[0] = pPriv->h; - -- BEGIN_ACCEL(12); -- -- OUT_ACCEL_REG(R200_SE_VTX_FMT_0, R200_VTX_XY); -- OUT_ACCEL_REG(R200_SE_VTX_FMT_1, -- (2 << R200_VTX_TEX0_COMP_CNT_SHIFT)); -- -- OUT_ACCEL_REG(R200_PP_TXFILTER_0, -- R200_MAG_FILTER_LINEAR | -- R200_MIN_FILTER_LINEAR | -- R200_CLAMP_S_CLAMP_LAST | -- R200_CLAMP_T_CLAMP_LAST | -- R200_YUV_TO_RGB); -- OUT_ACCEL_REG(R200_PP_TXFORMAT_0, txformat); -- OUT_ACCEL_REG(R200_PP_TXFORMAT_X_0, 0); -- OUT_ACCEL_REG(R200_PP_TXSIZE_0, -- (pPriv->w - 1) | -- ((pPriv->h - 1) << RADEON_TEX_VSIZE_SHIFT)); -- OUT_ACCEL_REG(R200_PP_TXPITCH_0, pPriv->src_pitch - 32); -- -- OUT_ACCEL_REG(R200_PP_TXOFFSET_0, pPriv->src_offset); -- -- OUT_ACCEL_REG(R200_PP_TXCBLEND_0, -- R200_TXC_ARG_A_ZERO | -- R200_TXC_ARG_B_ZERO | -- R200_TXC_ARG_C_R0_COLOR | -- R200_TXC_OP_MADD); -- OUT_ACCEL_REG(R200_PP_TXCBLEND2_0, -- R200_TXC_CLAMP_0_1 | R200_TXC_OUTPUT_REG_R0); -- OUT_ACCEL_REG(R200_PP_TXABLEND_0, -- R200_TXA_ARG_A_ZERO | -- R200_TXA_ARG_B_ZERO | -- R200_TXA_ARG_C_R0_ALPHA | -- R200_TXA_OP_MADD); -- OUT_ACCEL_REG(R200_PP_TXABLEND2_0, -- R200_TXA_CLAMP_0_1 | R200_TXA_OUTPUT_REG_R0); -- FINISH_ACCEL(); -+ if (isplanar) { -+ /* note: in contrast to r300, use input biasing on uv components */ -+ float yco = 1.1643; -+ float yoff = -0.0625 * yco; -+ float uco[3] = {0.0, -0.39173, 2.018}; -+ float vco[3] = {1.5958, -0.8129, 0.0}; -+ -+ /* need 2 texcoord sets (even though they are identical) due -+ to denormalization! hw apparently can't premultiply -+ same coord set by different texture size */ -+ vtx_count = 6; -+ -+ txformat0 = (((((pPriv->w + 1 ) >> 1) - 1) & 0x7ff) | -+ (((((pPriv->h + 1 ) >> 1) - 1) & 0x7ff) << RADEON_TEX_VSIZE_SHIFT)); -+ txpitch = ((pPriv->src_pitch >> 1) + 63) & ~63; -+ txpitch -= 32; -+ txfilter = R200_MAG_FILTER_LINEAR | -+ R200_MIN_FILTER_LINEAR | -+ R200_CLAMP_S_CLAMP_LAST | -+ R200_CLAMP_T_CLAMP_LAST; -+ -+ BEGIN_ACCEL(36); -+ -+ OUT_ACCEL_REG(RADEON_PP_CNTL, -+ RADEON_TEX_0_ENABLE | RADEON_TEX_1_ENABLE | RADEON_TEX_2_ENABLE | -+ RADEON_TEX_BLEND_0_ENABLE | RADEON_TEX_BLEND_1_ENABLE | -+ RADEON_TEX_BLEND_2_ENABLE); -+ -+ OUT_ACCEL_REG(R200_SE_VTX_FMT_0, R200_VTX_XY); -+ OUT_ACCEL_REG(R200_SE_VTX_FMT_1, -+ (2 << R200_VTX_TEX0_COMP_CNT_SHIFT) | -+ (2 << R200_VTX_TEX1_COMP_CNT_SHIFT)); -+ -+ OUT_ACCEL_REG(R200_PP_TXFILTER_0, txfilter); -+ OUT_ACCEL_REG(R200_PP_TXFORMAT_0, txformat); -+ OUT_ACCEL_REG(R200_PP_TXFORMAT_X_0, 0); -+ OUT_ACCEL_REG(R200_PP_TXSIZE_0, -+ (pPriv->w - 1) | -+ ((pPriv->h - 1) << RADEON_TEX_VSIZE_SHIFT)); -+ OUT_ACCEL_REG(R200_PP_TXPITCH_0, pPriv->src_pitch - 32); -+ OUT_ACCEL_REG(R200_PP_TXOFFSET_0, pPriv->src_offset); -+ -+ OUT_ACCEL_REG(R200_PP_TXFILTER_1, txfilter); -+ OUT_ACCEL_REG(R200_PP_TXFORMAT_1, txformat | R200_TXFORMAT_ST_ROUTE_STQ1); -+ OUT_ACCEL_REG(R200_PP_TXFORMAT_X_1, 0); -+ OUT_ACCEL_REG(R200_PP_TXSIZE_1, txformat0); -+ OUT_ACCEL_REG(R200_PP_TXPITCH_1, txpitch); -+ OUT_ACCEL_REG(R200_PP_TXOFFSET_1, pPriv->src_offset + pPriv->planeu_offset); -+ -+ OUT_ACCEL_REG(R200_PP_TXFILTER_2, txfilter); -+ OUT_ACCEL_REG(R200_PP_TXFORMAT_2, txformat | R200_TXFORMAT_ST_ROUTE_STQ1); -+ OUT_ACCEL_REG(R200_PP_TXFORMAT_X_2, 0); -+ OUT_ACCEL_REG(R200_PP_TXSIZE_2, txformat0); -+ OUT_ACCEL_REG(R200_PP_TXPITCH_2, txpitch); -+ OUT_ACCEL_REG(R200_PP_TXOFFSET_2, pPriv->src_offset + pPriv->planev_offset); -+ -+ /* similar to r300 code. Note the big problem is that hardware constants -+ * are 8 bits only, representing 0.0-1.0. We can get that up (using bias -+ * + scale) to -1.0-1.0 (but precision will suffer). AFAIK the hw actually -+ * has 12 bits fractional precision (plus 1 sign bit, 3 range bits) but -+ * the constants not. To get larger range can use output scale, but for -+ * that 2.018 value we need a total scale by 8, which means the constants -+ * really have no accuracy whatsoever (5 fractional bits only). -+ * The only direct way to get high precision "constants" into the fragment -+ * pipe I know of is to use the texcoord interpolator (not color, this one -+ * is 8 bit only too), which seems a bit expensive. We're lucky though it -+ * seems the values we need seem to fit better than worst case (get about -+ * 6 fractional bits for this instead of 5, at least when not correcting for -+ * hue/saturation/contrast/brightness, which is the same as for vco - yco and -+ * yoff get 8 fractional bits). -+ * -+ * A higher precision (8 fractional bits) version might just put uco into -+ * a texcoord, and calculate a new vcoconst in the shader, like so: -+ * cohelper = {1.0, 0.0, 0.0} - shouldn't use 0.5 since not exactly representable -+ * vco = {1.5958 - 1.0, -0.8129 + 1.0, 1.0} -+ * vcocalc = ADD temp, bias/scale(cohelper), vco -+ * would in total use 4 tex units, 4 instructions which seems fairly -+ * balanced for this architecture (instead of 3 + 3 for the solution here) -+ * -+ * temp = MAD(yco, yuv.yyyy, yoff) -+ * temp = MAD(uco, yuv.uuuu, temp) -+ * result = MAD(vco, yuv.vvvv, temp) -+ * -+ * note first mad produces actually scalar, hence we transform -+ * it into a dp2a to get 8 bit precision of yco instead of 7 - -+ * That's assuming hw correctly expands consts to internal precision. -+ * (y * 1 + y * (yco - 1) + yoff) -+ * temp = DP2A / 2 (yco, yuv.yyyy, yoff) -+ * temp = MAD (uco / 4, yuv.uuuu * 2, temp) -+ * result = MAD x2 (vco / 2, yuv.vvvv, temp) -+ * -+ * vco, uco need bias (and hence scale too) -+ * -+ */ -+ -+ /* MAD temp0 / 2, const0.a * 2, temp0, -const0.rgb */ -+ OUT_ACCEL_REG(R200_PP_TXCBLEND_0, -+ R200_TXC_ARG_A_TFACTOR_COLOR | -+ R200_TXC_ARG_B_R0_COLOR | -+ R200_TXC_ARG_C_TFACTOR_COLOR | -+ R200_TXC_NEG_ARG_C | -+ R200_TXC_OP_DOT2_ADD); -+ OUT_ACCEL_REG(R200_PP_TXCBLEND2_0, -+ (0 << R200_TXC_TFACTOR_SEL_SHIFT) | -+ R200_TXC_SCALE_INV2 | -+ R200_TXC_CLAMP_8_8 | R200_TXC_OUTPUT_REG_R0); -+ OUT_ACCEL_REG(R200_PP_TXABLEND_0, -+ R200_TXA_ARG_A_ZERO | -+ R200_TXA_ARG_B_ZERO | -+ R200_TXA_ARG_C_ZERO | -+ R200_TXA_OP_MADD); -+ OUT_ACCEL_REG(R200_PP_TXABLEND2_0, -+ R200_TXA_OUTPUT_REG_NONE); -+ -+ /* MAD temp0, (const1 - 0.5) * 2, (temp1 - 0.5) * 2, temp0 */ -+ OUT_ACCEL_REG(R200_PP_TXCBLEND_1, -+ R200_TXC_ARG_A_TFACTOR_COLOR | -+ R200_TXC_BIAS_ARG_A | -+ R200_TXC_SCALE_ARG_A | -+ R200_TXC_ARG_B_R1_COLOR | -+ R200_TXC_BIAS_ARG_B | -+ R200_TXC_SCALE_ARG_B | -+ R200_TXC_ARG_C_R0_COLOR | -+ R200_TXC_OP_MADD); -+ OUT_ACCEL_REG(R200_PP_TXCBLEND2_1, -+ (1 << R200_TXC_TFACTOR_SEL_SHIFT) | -+ R200_TXC_CLAMP_8_8 | R200_TXC_OUTPUT_REG_R0); -+ OUT_ACCEL_REG(R200_PP_TXABLEND_1, -+ R200_TXA_ARG_A_ZERO | -+ R200_TXA_ARG_B_ZERO | -+ R200_TXA_ARG_C_ZERO | -+ R200_TXA_OP_MADD); -+ OUT_ACCEL_REG(R200_PP_TXABLEND2_1, -+ R200_TXA_OUTPUT_REG_NONE); -+ -+ /* MAD temp0 x 2, (const2 - 0.5) * 2, (temp2 - 0.5), temp0 */ -+ OUT_ACCEL_REG(R200_PP_TXCBLEND_2, -+ R200_TXC_ARG_A_TFACTOR_COLOR | -+ R200_TXC_BIAS_ARG_A | -+ R200_TXC_SCALE_ARG_A | -+ R200_TXC_ARG_B_R2_COLOR | -+ R200_TXC_BIAS_ARG_B | -+ R200_TXC_ARG_C_R0_COLOR | -+ R200_TXC_OP_MADD); -+ OUT_ACCEL_REG(R200_PP_TXCBLEND2_2, -+ (2 << R200_TXC_TFACTOR_SEL_SHIFT) | -+ R200_TXC_SCALE_2X | -+ R200_TXC_CLAMP_0_1 | R200_TXC_OUTPUT_REG_R0); -+ OUT_ACCEL_REG(R200_PP_TXABLEND_2, -+ R200_TXA_ARG_A_ZERO | -+ R200_TXA_ARG_B_ZERO | -+ R200_TXA_ARG_C_ZERO | -+ R200_TXA_COMP_ARG_C | -+ R200_TXA_OP_MADD); -+ OUT_ACCEL_REG(R200_PP_TXABLEND2_2, -+ R200_TXA_CLAMP_0_1 | R200_TXA_OUTPUT_REG_R0); -+ -+ /* shader constants */ -+ OUT_ACCEL_REG(R200_PP_TFACTOR_0, float4touint(1.0, /* src range [1, 2] */ -+ yco - 1.0, -+ -yoff, /* range [-1, 0] */ -+ 0.0)); -+ OUT_ACCEL_REG(R200_PP_TFACTOR_1, float4touint(uco[0] * 0.125 + 0.5, /* range [-4, 4] */ -+ uco[1] * 0.125 + 0.5, -+ uco[2] * 0.125 + 0.5, -+ 0.0)); -+ OUT_ACCEL_REG(R200_PP_TFACTOR_2, float4touint(vco[0] * 0.25 + 0.5, /* range [-2, 2] */ -+ vco[1] * 0.25 + 0.5, -+ vco[2] * 0.25 + 0.5, -+ 0.0)); -+ -+ FINISH_ACCEL(); -+ } -+ else if (info->ChipFamily == CHIP_FAMILY_RV250) { -+ /* fix up broken packed yuv - shader same as above except -+ yuv compoents are all in same reg */ -+ float yco = 1.1643; -+ float yoff = -0.0625 * yco; -+ float uco[3] = {0.0, -0.39173, 2.018}; -+ float vco[3] = {1.5958, -0.8129, 0.0}; -+ -+ txformat0 = (((((pPriv->w + 1 ) >> 1) - 1) & 0x7ff) | -+ (((((pPriv->h + 1 ) >> 1 ) - 1) & 0x7ff) << RADEON_TEX_VSIZE_SHIFT)); -+ txpitch = ((pPriv->src_pitch >> 1) + 63) & ~63; -+ txpitch -= 32; -+ txfilter = R200_MAG_FILTER_LINEAR | -+ R200_MIN_FILTER_LINEAR | -+ R200_CLAMP_S_CLAMP_LAST | -+ R200_CLAMP_T_CLAMP_LAST; -+ -+ BEGIN_ACCEL(24); -+ -+ OUT_ACCEL_REG(RADEON_PP_CNTL, -+ RADEON_TEX_0_ENABLE | -+ RADEON_TEX_BLEND_0_ENABLE | RADEON_TEX_BLEND_1_ENABLE | -+ RADEON_TEX_BLEND_2_ENABLE); -+ -+ OUT_ACCEL_REG(R200_SE_VTX_FMT_0, R200_VTX_XY); -+ OUT_ACCEL_REG(R200_SE_VTX_FMT_1, -+ (2 << R200_VTX_TEX0_COMP_CNT_SHIFT)); -+ -+ OUT_ACCEL_REG(R200_PP_TXFILTER_0, txfilter); -+ OUT_ACCEL_REG(R200_PP_TXFORMAT_0, txformat); -+ OUT_ACCEL_REG(R200_PP_TXFORMAT_X_0, 0); -+ OUT_ACCEL_REG(R200_PP_TXSIZE_0, -+ (pPriv->w - 1) | -+ ((pPriv->h - 1) << RADEON_TEX_VSIZE_SHIFT)); -+ OUT_ACCEL_REG(R200_PP_TXPITCH_0, pPriv->src_pitch - 32); -+ OUT_ACCEL_REG(R200_PP_TXOFFSET_0, pPriv->src_offset); -+ -+ /* MAD temp1 / 2, const0.a * 2, temp0.ggg, -const0.rgb */ -+ OUT_ACCEL_REG(R200_PP_TXCBLEND_0, -+ R200_TXC_ARG_A_TFACTOR_COLOR | -+ R200_TXC_ARG_B_R0_COLOR | -+ R200_TXC_ARG_C_TFACTOR_COLOR | -+ R200_TXC_NEG_ARG_C | -+ R200_TXC_OP_DOT2_ADD); -+ OUT_ACCEL_REG(R200_PP_TXCBLEND2_0, -+ (0 << R200_TXC_TFACTOR_SEL_SHIFT) | -+ R200_TXC_SCALE_INV2 | -+ (R200_TXC_REPL_GREEN << R200_TXC_REPL_ARG_B_SHIFT) | -+ R200_TXC_CLAMP_8_8 | R200_TXC_OUTPUT_REG_R1); -+ OUT_ACCEL_REG(R200_PP_TXABLEND_0, -+ R200_TXA_ARG_A_ZERO | -+ R200_TXA_ARG_B_ZERO | -+ R200_TXA_ARG_C_ZERO | -+ R200_TXA_OP_MADD); -+ OUT_ACCEL_REG(R200_PP_TXABLEND2_0, -+ R200_TXA_OUTPUT_REG_NONE); -+ -+ /* MAD temp1, (const1 - 0.5) * 2, (temp0.rrr - 0.5) * 2, temp1 */ -+ OUT_ACCEL_REG(R200_PP_TXCBLEND_1, -+ R200_TXC_ARG_A_TFACTOR_COLOR | -+ R200_TXC_BIAS_ARG_A | -+ R200_TXC_SCALE_ARG_A | -+ R200_TXC_ARG_B_R0_COLOR | -+ R200_TXC_BIAS_ARG_B | -+ R200_TXC_SCALE_ARG_B | -+ R200_TXC_ARG_C_R1_COLOR | -+ R200_TXC_OP_MADD); -+ OUT_ACCEL_REG(R200_PP_TXCBLEND2_1, -+ (1 << R200_TXC_TFACTOR_SEL_SHIFT) | -+ (R200_TXC_REPL_BLUE << R200_TXC_REPL_ARG_B_SHIFT) | -+ R200_TXC_CLAMP_8_8 | R200_TXC_OUTPUT_REG_R1); -+ OUT_ACCEL_REG(R200_PP_TXABLEND_1, -+ R200_TXA_ARG_A_ZERO | -+ R200_TXA_ARG_B_ZERO | -+ R200_TXA_ARG_C_ZERO | -+ R200_TXA_OP_MADD); -+ OUT_ACCEL_REG(R200_PP_TXABLEND2_1, -+ R200_TXA_OUTPUT_REG_NONE); -+ -+ /* MAD temp0 x 2, (const2 - 0.5) * 2, (temp0.bbb - 0.5), temp1 */ -+ OUT_ACCEL_REG(R200_PP_TXCBLEND_2, -+ R200_TXC_ARG_A_TFACTOR_COLOR | -+ R200_TXC_BIAS_ARG_A | -+ R200_TXC_SCALE_ARG_A | -+ R200_TXC_ARG_B_R0_COLOR | -+ R200_TXC_BIAS_ARG_B | -+ R200_TXC_ARG_C_R1_COLOR | -+ R200_TXC_OP_MADD); -+ OUT_ACCEL_REG(R200_PP_TXCBLEND2_2, -+ (2 << R200_TXC_TFACTOR_SEL_SHIFT) | -+ R200_TXC_SCALE_2X | -+ (R200_TXC_REPL_RED << R200_TXC_REPL_ARG_B_SHIFT) | -+ R200_TXC_CLAMP_0_1 | R200_TXC_OUTPUT_REG_R0); -+ OUT_ACCEL_REG(R200_PP_TXABLEND_2, -+ R200_TXA_ARG_A_ZERO | -+ R200_TXA_ARG_B_ZERO | -+ R200_TXA_ARG_C_ZERO | -+ R200_TXA_COMP_ARG_C | -+ R200_TXA_OP_MADD); -+ OUT_ACCEL_REG(R200_PP_TXABLEND2_2, -+ R200_TXA_CLAMP_0_1 | R200_TXA_OUTPUT_REG_R0); -+ -+ /* shader constants */ -+ OUT_ACCEL_REG(R200_PP_TFACTOR_0, float4touint(1.0, /* src range [1, 2] */ -+ yco - 1.0, -+ -yoff, /* range [-1, 0] */ -+ 0.0)); -+ OUT_ACCEL_REG(R200_PP_TFACTOR_1, float4touint(uco[0] * 0.125 + 0.5, /* range [-4, 4] */ -+ uco[1] * 0.125 + 0.5, -+ uco[2] * 0.125 + 0.5, -+ 0.0)); -+ OUT_ACCEL_REG(R200_PP_TFACTOR_2, float4touint(vco[0] * 0.25 + 0.5, /* range [-2, 2] */ -+ vco[1] * 0.25 + 0.5, -+ vco[2] * 0.25 + 0.5, -+ 0.0)); -+ -+ FINISH_ACCEL(); -+ } -+ else { -+ BEGIN_ACCEL(13); -+ OUT_ACCEL_REG(RADEON_PP_CNTL, -+ RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE); -+ -+ OUT_ACCEL_REG(R200_SE_VTX_FMT_0, R200_VTX_XY); -+ OUT_ACCEL_REG(R200_SE_VTX_FMT_1, -+ (2 << R200_VTX_TEX0_COMP_CNT_SHIFT)); -+ -+ OUT_ACCEL_REG(R200_PP_TXFILTER_0, -+ R200_MAG_FILTER_LINEAR | -+ R200_MIN_FILTER_LINEAR | -+ R200_CLAMP_S_CLAMP_LAST | -+ R200_CLAMP_T_CLAMP_LAST | -+ R200_YUV_TO_RGB); -+ OUT_ACCEL_REG(R200_PP_TXFORMAT_0, txformat); -+ OUT_ACCEL_REG(R200_PP_TXFORMAT_X_0, 0); -+ OUT_ACCEL_REG(R200_PP_TXSIZE_0, -+ (pPriv->w - 1) | -+ ((pPriv->h - 1) << RADEON_TEX_VSIZE_SHIFT)); -+ OUT_ACCEL_REG(R200_PP_TXPITCH_0, pPriv->src_pitch - 32); -+ -+ OUT_ACCEL_REG(R200_PP_TXOFFSET_0, pPriv->src_offset); -+ -+ OUT_ACCEL_REG(R200_PP_TXCBLEND_0, -+ R200_TXC_ARG_A_ZERO | -+ R200_TXC_ARG_B_ZERO | -+ R200_TXC_ARG_C_R0_COLOR | -+ R200_TXC_OP_MADD); -+ OUT_ACCEL_REG(R200_PP_TXCBLEND2_0, -+ R200_TXC_CLAMP_0_1 | R200_TXC_OUTPUT_REG_R0); -+ OUT_ACCEL_REG(R200_PP_TXABLEND_0, -+ R200_TXA_ARG_A_ZERO | -+ R200_TXA_ARG_B_ZERO | -+ R200_TXA_ARG_C_R0_ALPHA | -+ R200_TXA_OP_MADD); -+ OUT_ACCEL_REG(R200_PP_TXABLEND2_0, -+ R200_TXA_CLAMP_0_1 | R200_TXA_OUTPUT_REG_R0); -+ FINISH_ACCEL(); -+ } - } else { - - info->accel_state->texW[0] = 1; - info->accel_state->texH[0] = 1; - -- BEGIN_ACCEL(8); -+ BEGIN_ACCEL(9); -+ -+ OUT_ACCEL_REG(RADEON_PP_CNTL, -+ RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE); - - OUT_ACCEL_REG(RADEON_SE_VTX_FMT, (RADEON_SE_VTX_FMT_XY | - RADEON_SE_VTX_FMT_ST0)); -@@ -1672,6 +2180,20 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv - ((float)srcX + (float)srcw * (((float)dsth / (float)dstw) + 1.0)) / info->accel_state->texW[0], - (float)srcY / info->accel_state->texH[0]); - } -+ } else if (isplanar) { -+ /* -+ * Just render a rect (using three coords). -+ * Filter is a bit a misnomer, it's just texcoords... -+ */ -+ VTX_OUT_FILTER((float)dstX, (float)(dstY + dsth), -+ (float)srcX / info->accel_state->texW[0], (float)(srcY + srch) / info->accel_state->texH[0], -+ (float)srcX / info->accel_state->texW[0], (float)(srcY + srch) / info->accel_state->texH[0]); -+ VTX_OUT_FILTER((float)(dstX + dstw), (float)(dstY + dsth), -+ (float)(srcX + srcw) / info->accel_state->texW[0], (float)(srcY + srch) / info->accel_state->texH[0], -+ (float)(srcX + srcw) / info->accel_state->texW[0], (float)(srcY + srch) / info->accel_state->texH[0]); -+ VTX_OUT_FILTER((float)(dstX + dstw), (float)dstY, -+ (float)(srcX + srcw) / info->accel_state->texW[0], (float)srcY / info->accel_state->texH[0], -+ (float)(srcX + srcw) / info->accel_state->texW[0], (float)srcY / info->accel_state->texH[0]); - } else { - /* - * Just render a rect (using three coords). -diff --git a/src/radeon_tv.c b/src/radeon_tv.c -index 98e3b0a..eef45d9 100644 ---- a/src/radeon_tv.c -+++ b/src/radeon_tv.c -@@ -815,7 +815,9 @@ void RADEONInitTVRegisters(xf86OutputPtr output, RADEONSavePtr save, - save->tv_rgb_cntl = (RADEON_RGB_DITHER_EN - | RADEON_TVOUT_SCALE_EN - | (0x0b << RADEON_UVRAM_READ_MARGIN_SHIFT) -- | (0x07 << RADEON_FIFORAM_FFMACRO_READ_MARGIN_SHIFT)); -+ | (0x07 << RADEON_FIFORAM_FFMACRO_READ_MARGIN_SHIFT) -+ | RADEON_RGB_ATTEN_SEL(0x3) -+ | RADEON_RGB_ATTEN_VAL(0xc)); - - if (IsPrimary) { - if (radeon_output->Flags & RADEON_USE_RMX) -diff --git a/src/radeon_video.c b/src/radeon_video.c -index 92d1a71..42aa036 100644 ---- a/src/radeon_video.c -+++ b/src/radeon_video.c -@@ -297,22 +297,19 @@ void RADEONInitVideo(ScreenPtr pScreen) - RADEONInitOffscreenImages(pScreen); - } - -- if (info->ChipFamily != CHIP_FAMILY_RV250) { -- if ((info->ChipFamily < CHIP_FAMILY_RS400) -+ if ((info->ChipFamily < CHIP_FAMILY_RS400) - #ifdef XF86DRI -- || (info->directRenderingEnabled) -+ || (info->directRenderingEnabled) - #endif -- ) { -- texturedAdaptor = RADEONSetupImageTexturedVideo(pScreen); -- if (texturedAdaptor != NULL) { -- adaptors[num_adaptors++] = texturedAdaptor; -- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Set up textured video\n"); -- } else -- xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Failed to set up textured video\n"); -+ ) { -+ texturedAdaptor = RADEONSetupImageTexturedVideo(pScreen); -+ if (texturedAdaptor != NULL) { -+ adaptors[num_adaptors++] = texturedAdaptor; -+ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Set up textured video\n"); - } else -- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Textured video requires CP on R5xx/R6xx/R7xx/IGP\n"); -+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Failed to set up textured video\n"); - } else -- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Textured video disabled on RV250 due to HW bug\n"); -+ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Textured video requires CP on R5xx/R6xx/R7xx/IGP\n"); - - if(num_adaptors) - xf86XVScreenInit(pScreen, adaptors, num_adaptors); -@@ -1070,11 +1067,11 @@ static void RADEONSetTransform (ScrnInfoPtr pScrn, - OvGCr = CAdjGCr * gamma_curve_r100[gamma].OvGammaCont; - OvBCb = CAdjBCb * gamma_curve_r100[gamma].OvGammaCont; - OvBCr = CAdjBCr * gamma_curve_r100[gamma].OvGammaCont; -- OvROff = CAdjOff * gamma_curve_r100[gamma].OvGammaCont - -+ OvROff = RedAdj + CAdjOff * gamma_curve_r100[gamma].OvGammaCont - - OvLuma * Loff - (OvRCb + OvRCr) * Coff; -- OvGOff = CAdjOff * gamma_curve_r100[gamma].OvGammaCont - -+ OvGOff = GreenAdj + CAdjOff * gamma_curve_r100[gamma].OvGammaCont - - OvLuma * Loff - (OvGCb + OvGCr) * Coff; -- OvBOff = CAdjOff * gamma_curve_r100[gamma].OvGammaCont - -+ OvBOff = BlueAdj + CAdjOff * gamma_curve_r100[gamma].OvGammaCont - - OvLuma * Loff - (OvBCb + OvBCr) * Coff; - #if 0 /* default constants */ - OvROff = -888.5; -diff --git a/src/radeon_video.h b/src/radeon_video.h -index 7f1891e..34fb07f 100644 ---- a/src/radeon_video.h -+++ b/src/radeon_video.h -@@ -90,6 +90,11 @@ typedef struct { - void *video_memory; - int video_offset; - -+ Bool planar_hw; -+ Bool planar_state; -+ int planeu_offset; -+ int planev_offset; -+ - /* bicubic filtering */ - void *bicubic_memory; - int bicubic_offset; diff --git a/radeon-6.9.0-panel-size-sanity.patch b/radeon-6.9.0-panel-size-sanity.patch deleted file mode 100644 index 7f3acac..0000000 --- a/radeon-6.9.0-panel-size-sanity.patch +++ /dev/null @@ -1,27 +0,0 @@ -diff -up xf86-video-ati-6.9.0/src/radeon_output.c.jx xf86-video-ati-6.9.0/src/radeon_output.c ---- xf86-video-ati-6.9.0/src/radeon_output.c.jx 2008-09-11 15:31:28.000000000 -0400 -+++ xf86-video-ati-6.9.0/src/radeon_output.c 2008-09-11 15:41:33.000000000 -0400 -@@ -1972,14 +1972,18 @@ RADEONGetLVDSInfo (xf86OutputPtr output) - RADEONOutputPrivatePtr radeon_output = output->driver_private; - char* s; - -- if (!RADEONGetLVDSInfoFromBIOS(output)) -- RADEONGetPanelInfoFromReg(output); -- - if ((s = xf86GetOptValString(info->Options, OPTION_PANEL_SIZE))) { - radeon_output->PanelPwrDly = 200; - if (sscanf (s, "%dx%d", &radeon_output->PanelXRes, &radeon_output->PanelYRes) != 2) { -- xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Invalid PanelSize option: %s\n", s); -- RADEONGetPanelInfoFromReg(output); -+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Invalid PanelSize option: %s, disabling the panel\n", s); -+ return FALSE; -+ } -+ } else if (!RADEONGetLVDSInfoFromBIOS(output)) { -+ RADEONGetPanelInfoFromReg(output); -+ if (radeon_output->PanelXRes < 800 || radeon_output->PanelYRes < 480) { -+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING, -+ "Implausible panel size, disabling\n"); -+ return FALSE; - } - } - diff --git a/radeon-6.9.0-remove-limit-heuristics.patch b/radeon-6.9.0-remove-limit-heuristics.patch deleted file mode 100644 index 3fbd9c8..0000000 --- a/radeon-6.9.0-remove-limit-heuristics.patch +++ /dev/null @@ -1,69 +0,0 @@ -diff --git a/src/radeon_driver.c b/src/radeon_driver.c -index d5bb24d..7992646 100644 ---- a/src/radeon_driver.c -+++ b/src/radeon_driver.c -@@ -2935,32 +2935,41 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) - if (crtc_max_Y > 8192) - crtc_max_Y = 8192; - } else { -+ - /* -- * note that these aren't really the CRTC limits, they're just -- * heuristics until we have a better memory manager. -+ * In radeon_driver.c it says: -+ * * -+ * * note that these aren't really the CRTC limits, they're just -+ * * heuristics until we have a better memory manager. -+ * * -+ * then it goes on to heuristically assign numbers to crtc_max_X/Y -+ * I think that's wrong because xf86InitialConfiguration will already pick a -+ * reasonable value for xf86CrtcSetSizeRange() - there is no need for driver -+ * heuristics. So I think it should just set the size range to whatever the crtc -+ * limits are. Does anyone know the actual values? -+ * depends on whether your front buffer is tiled -+ * Ah, so info->MaxSurfaceWidth would be a resonable setting -+ * 3968 if it is. otherwise i think it's 8k for r500+ and 4k for previous -+ * Cool, I'll patch it to do something like that in Fedora then -+ * ta -+ * - */ -- if (pScrn->videoRam <= 16384) { -- crtc_max_X = 1600; -- crtc_max_Y = 1200; -- } else if (IS_R300_VARIANT) { -- crtc_max_X = 2560; -- crtc_max_Y = 1200; -- } else if (IS_AVIVO_VARIANT) { -- crtc_max_X = 2560; -- crtc_max_Y = 1600; -- } else { -- crtc_max_X = 2048; -- crtc_max_Y = 1200; -- } -+ if (info->allowColorTiling) { -+ crtc_max_X = info->MaxSurfaceWidth; -+ crtc_max_Y = info->MaxLines; -+ } -+ else { -+ if (IS_AVIVO_VARIANT) { -+ crtc_max_X = 8192; -+ crtc_max_Y = 8192; -+ } -+ else { -+ crtc_max_X = 4096; -+ crtc_max_Y = 4096; -+ } -+ } - } -- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Max desktop size set to %dx%d\n", -- crtc_max_X, crtc_max_Y); -- xf86DrvMsg(pScrn->scrnIndex, X_INFO, -- "For a larger or smaller max desktop size, add a Virtual line to your xorg.conf\n"); -- xf86DrvMsg(pScrn->scrnIndex, X_INFO, -- "If you are having trouble with 3D, " -- "reduce the desktop size by adjusting the Virtual line to your xorg.conf\n"); -- -+ - /*xf86CrtcSetSizeRange (pScrn, 320, 200, info->MaxSurfaceWidth, info->MaxLines);*/ - xf86CrtcSetSizeRange (pScrn, 320, 200, crtc_max_X, crtc_max_Y); - diff --git a/radeon-modeset.patch b/radeon-modeset.patch index 3c3f732..2b26976 100644 --- a/radeon-modeset.patch +++ b/radeon-modeset.patch @@ -1,7 +1,6 @@ -diff --git a/configure.ac b/configure.ac -index 660ea1f..4ddec1c 100644 ---- a/configure.ac -+++ b/configure.ac +diff -up xf86-video-ati-6.12.2/configure.ac.modeset xf86-video-ati-6.12.2/configure.ac +--- xf86-video-ati-6.12.2/configure.ac.modeset 2009-04-08 10:29:53.000000000 -0400 ++++ xf86-video-ati-6.12.2/configure.ac 2009-04-13 13:24:51.000000000 -0400 @@ -31,6 +31,7 @@ AM_CONFIG_HEADER([config.h]) AC_CONFIG_AUX_DIR(.) @@ -30,48 +29,9 @@ index 660ea1f..4ddec1c 100644 save_CFLAGS="$CFLAGS" CFLAGS="$XORG_CFLAGS" AC_CHECK_HEADER(xf86Modes.h,[XMODES=yes],[XMODES=no],[#include "xorg-server.h"]) -diff --git a/src/Makefile.am b/src/Makefile.am -index 7cc2a6f..8a55d1c 100644 ---- a/src/Makefile.am -+++ b/src/Makefile.am -@@ -90,12 +90,14 @@ radeon_drv_ladir = @moduledir@/drivers - radeon_drv_la_SOURCES = \ - radeon_accel.c radeon_cursor.c radeon_dga.c radeon_legacy_memory.c \ - radeon_driver.c radeon_video.c radeon_bios.c radeon_mm_i2c.c \ -- radeon_vip.c radeon_misc.c radeon_probe.c \ -+ radeon_vip.c radeon_misc.c radeon_probe.c radeon_memory.c \ - legacy_crtc.c legacy_output.c \ - radeon_textured_video.c \ - radeon_crtc.c radeon_output.c radeon_modes.c radeon_tv.c \ - $(RADEON_ATOMBIOS_SOURCES) radeon_atombios.c radeon_atomwrapper.c \ -- $(RADEON_DRI_SRCS) $(RADEON_EXA_SOURCES) atombios_output.c atombios_crtc.c -+ $(RADEON_DRI_SRCS) $(RADEON_EXA_SOURCES) atombios_output.c \ -+ atombios_crtc.c drmmode_display.c radeon_bufmgr_gem.c \ -+ radeon_dri_bufmgr.c radeon_dri2.c - - if XMODES - radeon_drv_la_SOURCES += \ -@@ -144,6 +146,7 @@ EXTRA_DIST = \ - radeon_exa_render.c \ - radeon_exa_funcs.c \ - radeon.h \ -+ radeon_dri2.h \ - radeon_macros.h \ - radeon_probe.h \ - radeon_reg.h \ -@@ -164,4 +167,6 @@ EXTRA_DIST = \ - radeon_pci_device_match_gen.h \ - pcidb/ati_pciids.csv \ - pcidb/parse_pci_ids.pl \ -- radeon_atombios.h -+ radeon_atombios.h \ -+ drmmode_display.h \ -+ radeon_dri_bufmgr.h -diff --git a/src/drmmode_display.c b/src/drmmode_display.c -new file mode 100644 -index 0000000..14384ba ---- /dev/null -+++ b/src/drmmode_display.c +diff -up /dev/null xf86-video-ati-6.12.2/src/drmmode_display.c +--- /dev/null 2009-04-02 14:26:50.181076715 -0400 ++++ xf86-video-ati-6.12.2/src/drmmode_display.c 2009-04-13 13:24:51.000000000 -0400 @@ -0,0 +1,921 @@ +/* + * Copyright © 2007 Red Hat, Inc. @@ -994,11 +954,9 @@ index 0000000..14384ba + return TRUE; +} +#endif -diff --git a/src/drmmode_display.h b/src/drmmode_display.h -new file mode 100644 -index 0000000..5ea904b ---- /dev/null -+++ b/src/drmmode_display.h +diff -up /dev/null xf86-video-ati-6.12.2/src/drmmode_display.h +--- /dev/null 2009-04-02 14:26:50.181076715 -0400 ++++ xf86-video-ati-6.12.2/src/drmmode_display.h 2009-04-13 13:24:51.000000000 -0400 @@ -0,0 +1,74 @@ +/* + * Copyright © 2007 Red Hat, Inc. @@ -1074,11 +1032,46 @@ index 0000000..5ea904b +extern Bool drmmode_set_desired_modes(ScrnInfoPtr pScrn, drmmode_ptr drmmode); +#endif +#endif -diff --git a/src/r600_textured_videofuncs.c b/src/r600_textured_videofuncs.c -index 3dfe151..04b6457 100644 ---- a/src/r600_textured_videofuncs.c -+++ b/src/r600_textured_videofuncs.c -@@ -215,7 +215,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) +diff -up xf86-video-ati-6.12.2/src/Makefile.am.modeset xf86-video-ati-6.12.2/src/Makefile.am +--- xf86-video-ati-6.12.2/src/Makefile.am.modeset 2009-03-31 15:11:10.000000000 -0400 ++++ xf86-video-ati-6.12.2/src/Makefile.am 2009-04-13 13:24:51.000000000 -0400 +@@ -90,12 +90,14 @@ radeon_drv_ladir = @moduledir@/drivers + radeon_drv_la_SOURCES = \ + radeon_accel.c radeon_cursor.c radeon_dga.c radeon_legacy_memory.c \ + radeon_driver.c radeon_video.c radeon_bios.c radeon_mm_i2c.c \ +- radeon_vip.c radeon_misc.c radeon_probe.c \ ++ radeon_vip.c radeon_misc.c radeon_probe.c radeon_memory.c \ + legacy_crtc.c legacy_output.c \ + radeon_textured_video.c \ + radeon_crtc.c radeon_output.c radeon_modes.c radeon_tv.c \ + $(RADEON_ATOMBIOS_SOURCES) radeon_atombios.c radeon_atomwrapper.c \ +- $(RADEON_DRI_SRCS) $(RADEON_EXA_SOURCES) atombios_output.c atombios_crtc.c ++ $(RADEON_DRI_SRCS) $(RADEON_EXA_SOURCES) atombios_output.c \ ++ atombios_crtc.c drmmode_display.c radeon_bufmgr_gem.c \ ++ radeon_dri_bufmgr.c radeon_dri2.c + + if XMODES + radeon_drv_la_SOURCES += \ +@@ -144,6 +146,7 @@ EXTRA_DIST = \ + radeon_exa_render.c \ + radeon_exa_funcs.c \ + radeon.h \ ++ radeon_dri2.h \ + radeon_macros.h \ + radeon_probe.h \ + radeon_reg.h \ +@@ -164,4 +167,6 @@ EXTRA_DIST = \ + radeon_pci_device_match_gen.h \ + pcidb/ati_pciids.csv \ + pcidb/parse_pci_ids.pl \ +- radeon_atombios.h ++ radeon_atombios.h \ ++ drmmode_display.h \ ++ radeon_dri_bufmgr.h +diff -up xf86-video-ati-6.12.2/src/r600_textured_videofuncs.c.modeset xf86-video-ati-6.12.2/src/r600_textured_videofuncs.c +--- xf86-video-ati-6.12.2/src/r600_textured_videofuncs.c.modeset 2009-04-07 11:32:33.000000000 -0400 ++++ xf86-video-ati-6.12.2/src/r600_textured_videofuncs.c 2009-04-13 13:24:51.000000000 -0400 +@@ -215,7 +215,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pSc switch(pPriv->id) { case FOURCC_YV12: case FOURCC_I420: @@ -1087,7 +1080,7 @@ index 3dfe151..04b6457 100644 accel_state->src_size[0] = accel_state->src_pitch[0] * pPriv->h; /* flush texture cache */ -@@ -316,7 +316,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) +@@ -316,7 +316,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pSc case FOURCC_UYVY: case FOURCC_YUY2: default: @@ -1096,325 +1089,77 @@ index 3dfe151..04b6457 100644 accel_state->src_size[0] = accel_state->src_pitch[0] * pPriv->h; /* flush texture cache */ -diff --git a/src/radeon.h b/src/radeon.h -index d488429..d1bca2e 100644 ---- a/src/radeon.h -+++ b/src/radeon.h -@@ -46,6 +46,8 @@ - #include "compiler.h" - #include "xf86fbman.h" - -+#include "drmmode_display.h" -+ - /* PCI support */ - #include "xf86Pci.h" - -@@ -75,6 +77,7 @@ - #include "dri.h" - #include "GL/glxint.h" - #include "xf86drm.h" -+#include "radeon_dri2.h" +diff -up xf86-video-ati-6.12.2/src/radeon_accel.c.modeset xf86-video-ati-6.12.2/src/radeon_accel.c +--- xf86-video-ati-6.12.2/src/radeon_accel.c.modeset 2009-04-07 02:39:04.000000000 -0400 ++++ xf86-video-ati-6.12.2/src/radeon_accel.c 2009-04-13 13:24:51.000000000 -0400 +@@ -92,6 +92,7 @@ - #ifdef DAMAGE - #include "damage.h" -@@ -85,6 +88,7 @@ - #include "xf86Crtc.h" - #include "X11/Xatom.h" + /* X and server generic header files */ + #include "xf86.h" ++#include "radeon_bufmgr_gem.h" -+#include "radeon_bufmgr.h" - /* Render support */ - #ifdef RENDER - #include "picturestr.h" -@@ -414,6 +418,14 @@ typedef enum { + static void R600EngineReset(ScrnInfoPtr pScrn); - typedef struct _atomBiosHandle *atomBiosHandlePtr; +@@ -373,6 +374,9 @@ void RADEONEngineRestore(ScrnInfoPtr pSc + RADEONInfoPtr info = RADEONPTR(pScrn); + unsigned char *RADEONMMIO = info->MMIO; -+#define RADEON_POOL_GART 0 -+#define RADEON_POOL_VRAM 1 ++ if (info->drm_mode_setting) ++ return; + -+struct radeon_exa_pixmap_priv { -+ dri_bo *bo; -+ int flags; -+}; -+ - typedef struct { - uint32_t pci_device_id; - RADEONChipFamily chip_family; -@@ -424,7 +436,27 @@ typedef struct { - int singledac; - } RADEONCardInfo; + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "EngineRestore (%d/%d)\n", + info->CurrentLayout.pixel_code, +@@ -433,8 +437,8 @@ void RADEONEngineInit(ScrnInfoPtr pScrn) + info->CurrentLayout.bitsPerPixel); -+#define RADEON_2D_EXA_COPY 1 -+#define RADEON_2D_EXA_SOLID 2 -+ -+struct radeon_2d_state { -+ int op; // -+ uint32_t dst_pitch_offset; -+ uint32_t src_pitch_offset; -+ uint32_t dp_gui_master_cntl; -+ uint32_t dp_cntl; -+ uint32_t dp_write_mask; -+ uint32_t dp_brush_frgd_clr; -+ uint32_t dp_brush_bkgd_clr; -+ uint32_t dp_src_frgd_clr; -+ uint32_t dp_src_bkgd_clr; -+ uint32_t default_sc_bottom_right; -+ dri_bo *dst_bo; -+ dri_bo *src_bo; -+}; -+ #ifdef XF86DRI -+ - struct radeon_cp { - Bool CPRuns; /* CP is running */ - Bool CPInUse; /* CP has been used by X server */ -@@ -438,6 +470,10 @@ struct radeon_cp { - drmBufPtr indirectBuffer; - int indirectStart; - -+ drmBuf ib_gem_fake; -+ void *ib_ptr; -+ -+ struct radeon_relocs_info relocs; - /* Debugging info for BEGIN_RING/ADVANCE_RING pairs. */ - int dma_begin_count; - char *dma_debug_func; -@@ -504,13 +540,13 @@ struct radeon_dri { - drm_handle_t ringHandle; /* Handle from drmAddMap */ - drmSize ringMapSize; /* Size of map */ - int ringSize; /* Size of ring (in MB) */ -- drmAddress ring; /* Map */ -+ // drmAddress ring; /* Map */ - int ringSizeLog2QW; - - unsigned long ringReadOffset; /* Offset into GART space */ - drm_handle_t ringReadPtrHandle; /* Handle from drmAddMap */ - drmSize ringReadMapSize; /* Size of map */ -- drmAddress ringReadPtr; /* Map */ -+ // drmAddress ringReadPtr; /* Map */ - - /* CP vertex/indirect buffer data */ - unsigned long bufStart; /* Offset into GART space */ -@@ -529,7 +565,6 @@ struct radeon_dri { - drmAddress gartTex; /* Map */ - int log2GARTTexGran; +- if (info->directRenderingEnabled && (IS_R300_3D || IS_R500_3D)) { +- drm_radeon_getparam_t np; ++ if ((info->directRenderingEnabled || info->drm_mode_setting) && (IS_R300_3D || IS_R500_3D)) { ++ drm_radeon_getparam_t np; + int num_pipes; -- /* DRI screen private data */ - int fbX; - int fbY; - int backX; -@@ -789,6 +824,7 @@ typedef struct { - RADEONCardType cardType; /* Current card is a PCI card */ - struct radeon_cp *cp; - struct radeon_dri *dri; -+ struct radeon_dri2 dri2; - #ifdef USE_EXA - Bool accelDFS; + memset(&np, 0, sizeof(np)); +@@ -453,59 +457,62 @@ void RADEONEngineInit(ScrnInfoPtr pScrn) + } #endif -@@ -892,6 +928,43 @@ typedef struct { - - Bool r4xx_atom; -+ Bool new_cs; // new command submission routine -+ struct radeon_2d_state state_2d; -+ void (*reemit_current2d)(ScrnInfoPtr pScrn, int op); // emit the current 2D state into the IB -+ Bool cs_used_depth; -+ Bool drm_mm; // the drm memory manager exists and is initialised -+ struct { -+ uint64_t vram_size; -+ uint64_t gart_size; -+ -+ struct radeon_memory *bo_list[2]; -+ struct radeon_memory *front_buffer; -+ struct radeon_memory *back_buffer; -+ struct radeon_memory *depth_buffer; -+ -+#if 0 -+ struct radeon_memory *exa_buffer; -+#endif -+ struct radeon_memory *texture_buffer; -+ -+ struct radeon_memory *dma_buffer; -+ struct radeon_memory *gart_texture_buffer; -+ struct radeon_memory *rotate_buffer; -+ struct radeon_memory *cursor[2]; -+ -+ /* indirect buffer for accel */ -+ struct radeon_memory *gem_ib_memory; -+ -+ } mm; -+ -+ drm_handle_t fb_map_handle; -+ Bool drm_mode_setting; -+#ifdef XF86DRM_MODE -+ drmmode_rec drmmode; -+#endif -+ -+ int can_resize; -+ dri_bufmgr *bufmgr; - } RADEONInfoRec, *RADEONInfoPtr; - - #define RADEONWaitForFifo(pScrn, entries) \ -@@ -1147,6 +1220,24 @@ extern void - radeon_legacy_free_memory(ScrnInfoPtr pScrn, - void *mem_struct); - -+/* radeon_memory.c */ -+extern uint32_t radeon_name_buffer(ScrnInfoPtr pScrn, struct radeon_memory *mem); -+extern Bool radeon_bind_all_memory(ScrnInfoPtr pScrn); -+extern Bool radeon_unbind_all_memory(ScrnInfoPtr pScrn); -+extern struct radeon_memory *radeon_allocate_memory(ScrnInfoPtr pScrn, int pool, int size, int alignment, Bool no_backing_store, char *name, -+ int need_bind); -+int radeon_map_memory(ScrnInfoPtr pScrn, struct radeon_memory *mem); -+void radeon_unmap_memory(ScrnInfoPtr pScrn, struct radeon_memory *mem); -+void radeon_free_memory(ScrnInfoPtr pScrn, struct radeon_memory *mem); -+Bool radeon_bind_memory(ScrnInfoPtr pScrn, struct radeon_memory *mem); -+Bool radeon_free_all_memory(ScrnInfoPtr pScrn); -+Bool radeon_setup_kernel_mem(ScreenPtr pScreen); -+Bool RADEONDRIDoMappings(ScreenPtr pScreen); -+Bool radeon_update_dri_buffers(ScreenPtr pScreen); -+ -+dri_bo *radeon_get_pixmap_bo(PixmapPtr pPix); -+void radeon_set_pixmap_mem(PixmapPtr pPix, struct radeon_memory *mem); -+void radeon_set_pixmap_bo(PixmapPtr pPix, dri_bo *bo); - #ifdef XF86DRI - # ifdef USE_XAA - /* radeon_accelfuncs.c */ -@@ -1165,7 +1256,9 @@ do { \ - - #define RADEONCP_RELEASE(pScrn, info) \ - do { \ -- if (info->cp->CPInUse) { \ -+ if (info->new_cs) { \ -+ RADEONCPReleaseIndirect(pScrn); \ -+ } else if (info->cp->CPInUse) { \ - RADEON_PURGE_CACHE(); \ - RADEON_WAIT_UNTIL_IDLE(); \ - RADEONCPReleaseIndirect(pScrn); \ -@@ -1200,7 +1293,7 @@ do { \ - - #define RADEONCP_REFRESH(pScrn, info) \ - do { \ -- if (!info->cp->CPInUse) { \ -+ if (!info->cp->CPInUse && !info->new_cs) { \ - if (info->cp->needCacheFlush) { \ - RADEON_PURGE_CACHE(); \ - RADEON_PURGE_ZCACHE(); \ -@@ -1227,6 +1320,13 @@ do { \ - #define RING_LOCALS uint32_t *__head = NULL; int __expected; int __count = 0 - - #define BEGIN_RING(n) do { \ -+ if (!info->cp->indirectBuffer) { \ -+ info->cp->indirectBuffer = RADEONCPGetBuffer(pScrn); \ -+ info->cp->indirectStart = 0; \ -+ } else if (info->cp->indirectBuffer->used + (n) * (int)sizeof(uint32_t) > \ -+ info->cp->indirectBuffer->total) { \ -+ RADEONCPFlushIndirect(pScrn, 1); \ -+ } \ - if (RADEON_VERBOSE) { \ - xf86DrvMsg(pScrn->scrnIndex, X_INFO, \ - "BEGIN_RING(%d) in %s\n", (unsigned int)n, __FUNCTION__);\ -@@ -1239,13 +1339,6 @@ do { \ - } \ - info->cp->dma_debug_func = __FILE__; \ - info->cp->dma_debug_lineno = __LINE__; \ -- if (!info->cp->indirectBuffer) { \ -- info->cp->indirectBuffer = RADEONCPGetBuffer(pScrn); \ -- info->cp->indirectStart = 0; \ -- } else if (info->cp->indirectBuffer->used + (n) * (int)sizeof(uint32_t) > \ -- info->cp->indirectBuffer->total) { \ -- RADEONCPFlushIndirect(pScrn, 1); \ -- } \ - __expected = n; \ - __head = (pointer)((char *)info->cp->indirectBuffer->address + \ - info->cp->indirectBuffer->used); \ -@@ -1288,6 +1381,14 @@ do { \ - OUT_RING(val); \ - } while (0) - -+/* TODO - VRAM is wrong in general but true for now - all EXA stuff -+ is in VRAM */ -+#define OUT_RING_RELOC(x, read_domains, write_domains) \ -+ do { \ -+ radeon_bufmgr_emit_reloc(x, &info->cp->relocs, __head, &__count, read_domains, write_domains); \ -+ } while(0) -+ -+ - #define FLUSH_RING() \ - do { \ - if (RADEON_VERBOSE) \ -diff --git a/src/radeon_accel.c b/src/radeon_accel.c -index a9a4848..9d02ac8 100644 ---- a/src/radeon_accel.c -+++ b/src/radeon_accel.c -@@ -92,6 +92,7 @@ - - /* X and server generic header files */ - #include "xf86.h" -+#include "radeon_bufmgr_gem.h" - - static void R600EngineReset(ScrnInfoPtr pScrn); - -@@ -373,6 +374,9 @@ void RADEONEngineRestore(ScrnInfoPtr pScrn) - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - -+ if (info->drm_mode_setting) -+ return; -+ - xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, - "EngineRestore (%d/%d)\n", - info->CurrentLayout.pixel_code, -@@ -433,8 +437,8 @@ void RADEONEngineInit(ScrnInfoPtr pScrn) - info->CurrentLayout.bitsPerPixel); - - #ifdef XF86DRI -- if (info->directRenderingEnabled && (IS_R300_3D || IS_R500_3D)) { -- drm_radeon_getparam_t np; -+ if ((info->directRenderingEnabled || info->drm_mode_setting) && (IS_R300_3D || IS_R500_3D)) { -+ drm_radeon_getparam_t np; - int num_pipes; - - memset(&np, 0, sizeof(np)); -@@ -453,59 +457,62 @@ void RADEONEngineInit(ScrnInfoPtr pScrn) - } - #endif - -- if ((info->ChipFamily == CHIP_FAMILY_RV410) || -- (info->ChipFamily == CHIP_FAMILY_R420) || -- (info->ChipFamily == CHIP_FAMILY_RS600) || -- (info->ChipFamily == CHIP_FAMILY_RS690) || -- (info->ChipFamily == CHIP_FAMILY_RS740) || -- (info->ChipFamily == CHIP_FAMILY_RS400) || -- (info->ChipFamily == CHIP_FAMILY_RS480) || -- IS_R500_3D) { -- if (info->accel_state->num_gb_pipes == 0) { -- uint32_t gb_pipe_sel = INREG(R400_GB_PIPE_SELECT); -- -- info->accel_state->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1; -- if (IS_R500_3D) -- OUTPLL(pScrn, R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4)); -- } -- } else { -- if (info->accel_state->num_gb_pipes == 0) { -- if ((info->ChipFamily == CHIP_FAMILY_R300) || -- (info->ChipFamily == CHIP_FAMILY_R350)) { -- /* R3xx chips */ -- info->accel_state->num_gb_pipes = 2; -- } else { -- /* RV3xx chips */ -- info->accel_state->num_gb_pipes = 1; -+ if (!info->drm_mode_setting) { -+ if ((info->ChipFamily == CHIP_FAMILY_RV410) || -+ (info->ChipFamily == CHIP_FAMILY_R420) || -+ (info->ChipFamily == CHIP_FAMILY_RS600) || -+ (info->ChipFamily == CHIP_FAMILY_RS690) || -+ (info->ChipFamily == CHIP_FAMILY_RS740) || -+ (info->ChipFamily == CHIP_FAMILY_RS400) || -+ (info->ChipFamily == CHIP_FAMILY_RS480) || -+ IS_R500_3D) { -+ if (info->accel_state->num_gb_pipes == 0) { -+ uint32_t gb_pipe_sel = INREG(R400_GB_PIPE_SELECT); +- if ((info->ChipFamily == CHIP_FAMILY_RV410) || +- (info->ChipFamily == CHIP_FAMILY_R420) || +- (info->ChipFamily == CHIP_FAMILY_RS600) || +- (info->ChipFamily == CHIP_FAMILY_RS690) || +- (info->ChipFamily == CHIP_FAMILY_RS740) || +- (info->ChipFamily == CHIP_FAMILY_RS400) || +- (info->ChipFamily == CHIP_FAMILY_RS480) || +- IS_R500_3D) { +- if (info->accel_state->num_gb_pipes == 0) { +- uint32_t gb_pipe_sel = INREG(R400_GB_PIPE_SELECT); +- +- info->accel_state->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1; +- if (IS_R500_3D) +- OUTPLL(pScrn, R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4)); +- } +- } else { +- if (info->accel_state->num_gb_pipes == 0) { +- if ((info->ChipFamily == CHIP_FAMILY_R300) || +- (info->ChipFamily == CHIP_FAMILY_R350)) { +- /* R3xx chips */ +- info->accel_state->num_gb_pipes = 2; +- } else { +- /* RV3xx chips */ +- info->accel_state->num_gb_pipes = 1; ++ if (!info->drm_mode_setting) { ++ if ((info->ChipFamily == CHIP_FAMILY_RV410) || ++ (info->ChipFamily == CHIP_FAMILY_R420) || ++ (info->ChipFamily == CHIP_FAMILY_RS600) || ++ (info->ChipFamily == CHIP_FAMILY_RS690) || ++ (info->ChipFamily == CHIP_FAMILY_RS740) || ++ (info->ChipFamily == CHIP_FAMILY_RS400) || ++ (info->ChipFamily == CHIP_FAMILY_RS480) || ++ IS_R500_3D) { ++ if (info->accel_state->num_gb_pipes == 0) { ++ uint32_t gb_pipe_sel = INREG(R400_GB_PIPE_SELECT); + + info->accel_state->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1; + if (IS_R500_3D) @@ -1431,9 +1176,9 @@ index a9a4848..9d02ac8 100644 + info->accel_state->num_gb_pipes = 1; + } } -- } + } - } -- + - if (IS_R300_3D || IS_R500_3D) - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "num quad-pipes is %d\n", info->accel_state->num_gb_pipes); @@ -1447,8 +1192,8 @@ index a9a4848..9d02ac8 100644 - case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break; - default: - case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break; - } - +- } +- - OUTREG(R300_GB_TILE_CONFIG, gb_tile_config); - OUTREG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); - OUTREG(R300_DST_PIPE_CONFIG, INREG(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG); @@ -1488,7 +1233,7 @@ index a9a4848..9d02ac8 100644 switch (info->CurrentLayout.pixel_code) { case 8: datatype = 2; break; -@@ -613,6 +620,119 @@ int RADEONCPStop(ScrnInfoPtr pScrn, RADEONInfoPtr info) +@@ -613,6 +620,119 @@ int RADEONCPStop(ScrnInfoPtr pScrn, RADE } } @@ -1608,7 +1353,7 @@ index a9a4848..9d02ac8 100644 /* Get an indirect buffer for the CP 2D acceleration commands */ drmBufPtr RADEONCPGetBuffer(ScrnInfoPtr pScrn) { -@@ -623,6 +743,9 @@ drmBufPtr RADEONCPGetBuffer(ScrnInfoPtr pScrn) +@@ -623,6 +743,9 @@ drmBufPtr RADEONCPGetBuffer(ScrnInfoPtr int size = 0; int i = 0; int ret; @@ -1618,7 +1363,7 @@ index a9a4848..9d02ac8 100644 #if 0 /* FIXME: pScrn->pScreen has not been initialized when this is first -@@ -692,6 +815,11 @@ void RADEONCPFlushIndirect(ScrnInfoPtr pScrn, int discard) +@@ -692,6 +815,11 @@ void RADEONCPFlushIndirect(ScrnInfoPtr p if (!buffer) return; if (start == buffer->used && !discard) return; @@ -1630,7 +1375,7 @@ index a9a4848..9d02ac8 100644 if (RADEON_VERBOSE) { xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Flushing buffer %d\n", buffer->idx); -@@ -750,10 +878,16 @@ void RADEONCPReleaseIndirect(ScrnInfoPtr pScrn) +@@ -750,10 +878,16 @@ void RADEONCPReleaseIndirect(ScrnInfoPtr } } @@ -1673,7 +1418,7 @@ index a9a4848..9d02ac8 100644 RADEONAccelInitCP(pScreen, a); else #endif /* XF86DRI */ -@@ -1069,11 +1204,13 @@ void RADEONInit3DEngine(ScrnInfoPtr pScrn) +@@ -1069,11 +1204,13 @@ void RADEONInit3DEngine(ScrnInfoPtr pScr RADEONInfoPtr info = RADEONPTR (pScrn); #ifdef XF86DRI @@ -1691,7 +1436,7 @@ index a9a4848..9d02ac8 100644 RADEONInit3DEngineCP(pScrn); } else #endif -@@ -1081,7 +1218,7 @@ void RADEONInit3DEngine(ScrnInfoPtr pScrn) +@@ -1081,7 +1218,7 @@ void RADEONInit3DEngine(ScrnInfoPtr pScr info->accel_state->XInited3D = TRUE; } @@ -1700,42 +1445,9 @@ index a9a4848..9d02ac8 100644 #ifdef USE_XAA #ifdef XF86DRI Bool -diff --git a/src/radeon_bufmgr.h b/src/radeon_bufmgr.h -new file mode 100644 -index 0000000..481c5cf ---- /dev/null -+++ b/src/radeon_bufmgr.h -@@ -0,0 +1,25 @@ -+/** -+ * @file intel_bufmgr.h -+ * -+ * Public definitions of Intel-specific bufmgr functions. -+ */ -+ -+#ifndef RADEON_BUFMGR_H -+#define RADEON_BUFMGR_H -+ -+#include "radeon_dri_bufmgr.h" -+ -+struct radeon_bufmgr { -+ void (*emit_reloc)(dri_bo *buf, struct radeon_relocs_info *relocs, uint32_t *head, uint32_t *count_p, uint32_t read_domains, uint32_t write_domain); -+}; -+ -+dri_bufmgr *radeon_bufmgr_gem_init(int fd); -+dri_bo *radeon_bo_gem_create_from_name(dri_bufmgr *bufmgr, const char *name, -+ unsigned int handle); -+dri_bo *radeon_bo_gem_create_from_handle(dri_bufmgr *bufmgr, -+ uint32_t handle, unsigned long size); -+ -+void radeon_bufmgr_emit_reloc(dri_bo *buf, struct radeon_relocs_info *relocs, uint32_t *head, uint32_t *count_p, uint32_t read_domains, uint32_t write_domain); -+ -+void radeon_bufmgr_post_submit(dri_bufmgr *bufmgr); -+#endif -diff --git a/src/radeon_bufmgr_gem.c b/src/radeon_bufmgr_gem.c -new file mode 100644 -index 0000000..6005e51 ---- /dev/null -+++ b/src/radeon_bufmgr_gem.c +diff -up /dev/null xf86-video-ati-6.12.2/src/radeon_bufmgr_gem.c +--- /dev/null 2009-04-02 14:26:50.181076715 -0400 ++++ xf86-video-ati-6.12.2/src/radeon_bufmgr_gem.c 2009-04-13 13:24:51.000000000 -0400 @@ -0,0 +1,635 @@ +/************************************************************************** + * @@ -2372,11 +2084,9 @@ index 0000000..6005e51 + *name = flink.name; + return 0; +} -diff --git a/src/radeon_bufmgr_gem.h b/src/radeon_bufmgr_gem.h -new file mode 100644 -index 0000000..6d3b6fe ---- /dev/null -+++ b/src/radeon_bufmgr_gem.h +diff -up /dev/null xf86-video-ati-6.12.2/src/radeon_bufmgr_gem.h +--- /dev/null 2009-04-02 14:26:50.181076715 -0400 ++++ xf86-video-ati-6.12.2/src/radeon_bufmgr_gem.h 2009-04-13 13:24:51.000000000 -0400 @@ -0,0 +1,19 @@ +#ifndef RADEON_BUFMGR_GEM_H +#define RADEON_BUFMGR_GEM_H @@ -2397,11 +2107,39 @@ index 0000000..6d3b6fe +int radeon_bufmgr_gem_in_vram(dri_bo *buf); +int radeon_bo_gem_name_buffer(dri_bo *bo, uint32_t *name); +#endif -diff --git a/src/radeon_commonfuncs.c b/src/radeon_commonfuncs.c -index a9bc7d2..6c22339 100644 ---- a/src/radeon_commonfuncs.c -+++ b/src/radeon_commonfuncs.c -@@ -62,12 +62,15 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn) +diff -up /dev/null xf86-video-ati-6.12.2/src/radeon_bufmgr.h +--- /dev/null 2009-04-02 14:26:50.181076715 -0400 ++++ xf86-video-ati-6.12.2/src/radeon_bufmgr.h 2009-04-13 13:24:51.000000000 -0400 +@@ -0,0 +1,25 @@ ++/** ++ * @file intel_bufmgr.h ++ * ++ * Public definitions of Intel-specific bufmgr functions. ++ */ ++ ++#ifndef RADEON_BUFMGR_H ++#define RADEON_BUFMGR_H ++ ++#include "radeon_dri_bufmgr.h" ++ ++struct radeon_bufmgr { ++ void (*emit_reloc)(dri_bo *buf, struct radeon_relocs_info *relocs, uint32_t *head, uint32_t *count_p, uint32_t read_domains, uint32_t write_domain); ++}; ++ ++dri_bufmgr *radeon_bufmgr_gem_init(int fd); ++dri_bo *radeon_bo_gem_create_from_name(dri_bufmgr *bufmgr, const char *name, ++ unsigned int handle); ++dri_bo *radeon_bo_gem_create_from_handle(dri_bufmgr *bufmgr, ++ uint32_t handle, unsigned long size); ++ ++void radeon_bufmgr_emit_reloc(dri_bo *buf, struct radeon_relocs_info *relocs, uint32_t *head, uint32_t *count_p, uint32_t read_domains, uint32_t write_domain); ++ ++void radeon_bufmgr_post_submit(dri_bufmgr *bufmgr); ++#endif +diff -up xf86-video-ati-6.12.2/src/radeon_commonfuncs.c.modeset xf86-video-ati-6.12.2/src/radeon_commonfuncs.c +--- xf86-video-ati-6.12.2/src/radeon_commonfuncs.c.modeset 2009-03-13 18:24:21.000000000 -0400 ++++ xf86-video-ati-6.12.2/src/radeon_commonfuncs.c 2009-04-13 13:24:51.000000000 -0400 +@@ -62,12 +62,15 @@ static void FUNC_NAME(RADEONInit3DEngine info->accel_state->texW[1] = info->accel_state->texH[1] = 1; if (IS_R300_3D || IS_R500_3D) { @@ -2422,7 +2160,7 @@ index a9bc7d2..6c22339 100644 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 | R300_SUBPIXEL_1_16); -@@ -79,10 +82,12 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn) +@@ -79,10 +82,12 @@ static void FUNC_NAME(RADEONInit3DEngine case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break; } @@ -2437,7 +2175,7 @@ index a9bc7d2..6c22339 100644 OUT_ACCEL_REG(R300_GB_SELECT, 0); OUT_ACCEL_REG(R300_GB_ENABLE, 0); FINISH_ACCEL(); -@@ -626,6 +631,39 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn) +@@ -626,6 +631,39 @@ static void FUNC_NAME(RADEONInit3DEngine } @@ -2477,7 +2215,7 @@ index a9bc7d2..6c22339 100644 /* inserts a wait for vline in the command stream */ void FUNC_NAME(RADEONWaitForVLine)(ScrnInfoPtr pScrn, PixmapPtr pPix, int crtc, int start, int stop) -@@ -644,16 +682,19 @@ void FUNC_NAME(RADEONWaitForVLine)(ScrnInfoPtr pScrn, PixmapPtr pPix, +@@ -644,16 +682,19 @@ void FUNC_NAME(RADEONWaitForVLine)(ScrnI if (!xf86_config->crtc[crtc]->enabled) return; @@ -2505,7 +2243,7 @@ index a9bc7d2..6c22339 100644 start = max(start, 0); stop = min(stop, xf86_config->crtc[crtc]->mode.VDisplay); -@@ -661,6 +702,13 @@ void FUNC_NAME(RADEONWaitForVLine)(ScrnInfoPtr pScrn, PixmapPtr pPix, +@@ -661,6 +702,13 @@ void FUNC_NAME(RADEONWaitForVLine)(ScrnI if (start > xf86_config->crtc[crtc]->mode.VDisplay) return; @@ -2519,7 +2257,7 @@ index a9bc7d2..6c22339 100644 BEGIN_ACCEL(2); if (IS_AVIVO_VARIANT) { -@@ -712,7 +760,7 @@ void FUNC_NAME(RADEONWaitForIdle)(ScrnInfoPtr pScrn) +@@ -712,7 +760,7 @@ void FUNC_NAME(RADEONWaitForIdle)(ScrnIn #ifdef ACCEL_CP /* Make sure the CP is idle first */ @@ -2528,11 +2266,10 @@ index a9bc7d2..6c22339 100644 int ret; FLUSH_RING(); -diff --git a/src/radeon_cursor.c b/src/radeon_cursor.c -index 0fcdcf0..cbc188b 100644 ---- a/src/radeon_cursor.c -+++ b/src/radeon_cursor.c -@@ -96,12 +96,16 @@ avivo_setup_cursor(xf86CrtcPtr crtc, Bool enable) +diff -up xf86-video-ati-6.12.2/src/radeon_cursor.c.modeset xf86-video-ati-6.12.2/src/radeon_cursor.c +--- xf86-video-ati-6.12.2/src/radeon_cursor.c.modeset 2008-11-25 02:20:03.000000000 -0500 ++++ xf86-video-ati-6.12.2/src/radeon_cursor.c 2009-04-13 13:24:51.000000000 -0400 +@@ -96,12 +96,16 @@ avivo_setup_cursor(xf86CrtcPtr crtc, Boo RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; RADEONInfoPtr info = RADEONPTR(crtc->scrn); unsigned char *RADEONMMIO = info->MMIO; @@ -2551,7 +2288,7 @@ index 0fcdcf0..cbc188b 100644 OUTREG(AVIVO_D1CUR_SIZE + radeon_crtc->crtc_offset, ((CURSOR_WIDTH - 1) << 16) | (CURSOR_HEIGHT - 1)); OUTREG(AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset, -@@ -203,6 +207,7 @@ radeon_crtc_set_cursor_position (xf86CrtcPtr crtc, int x, int y) +@@ -203,6 +207,7 @@ radeon_crtc_set_cursor_position (xf86Crt int xorigin = 0, yorigin = 0; int stride = 256; DisplayModePtr mode = &crtc->mode; @@ -2559,7 +2296,7 @@ index 0fcdcf0..cbc188b 100644 if (x < 0) xorigin = -x+1; if (y < 0) yorigin = -y+1; -@@ -233,8 +238,9 @@ radeon_crtc_set_cursor_position (xf86CrtcPtr crtc, int x, int y) +@@ -233,8 +238,9 @@ radeon_crtc_set_cursor_position (xf86Crt | (yorigin ? 0 : y))); RADEONCTRACE(("cursor_offset: 0x%x, yorigin: %d, stride: %d, temp %08X\n", radeon_crtc->cursor_offset + pScrn->fbOffset, yorigin, stride, temp)); @@ -2570,7 +2307,7 @@ index 0fcdcf0..cbc188b 100644 } else if (crtc_id == 1) { OUTREG(RADEON_CUR2_HORZ_VERT_OFF, (RADEON_CUR2_LOCK | (xorigin << 16) -@@ -244,8 +250,9 @@ radeon_crtc_set_cursor_position (xf86CrtcPtr crtc, int x, int y) +@@ -244,8 +250,9 @@ radeon_crtc_set_cursor_position (xf86Crt | (yorigin ? 0 : y))); RADEONCTRACE(("cursor_offset2: 0x%x, yorigin: %d, stride: %d, temp %08X\n", radeon_crtc->cursor_offset + pScrn->fbOffset, yorigin, stride, temp)); @@ -2581,7 +2318,7 @@ index 0fcdcf0..cbc188b 100644 } } } -@@ -299,10 +306,12 @@ radeon_crtc_load_cursor_argb (xf86CrtcPtr crtc, CARD32 *image) +@@ -299,10 +306,12 @@ radeon_crtc_load_cursor_argb (xf86CrtcPt RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; RADEONInfoPtr info = RADEONPTR(pScrn); CURSOR_SWAPPING_DECL_MMIO @@ -2595,1443 +2332,1432 @@ index 0fcdcf0..cbc188b 100644 info->cursor_argb = TRUE; CURSOR_SWAPPING_START(); -diff --git a/src/radeon_dri.c b/src/radeon_dri.c -index f6c6261..64b5937 100644 ---- a/src/radeon_dri.c -+++ b/src/radeon_dri.c -@@ -40,6 +40,8 @@ - - #include - #include -+#include -+#include - - /* Driver data structures */ - #include "radeon.h" -@@ -53,6 +55,8 @@ - - #include "atipciids.h" - -+#include "radeon_drm.h" -+ - /* X and server generic header files */ - #include "xf86.h" - #include "xf86PciInfo.h" -@@ -70,16 +74,31 @@ static size_t radeon_drm_page_size; - extern void GlxSetVisualConfigs(int nconfigs, __GLXvisualConfig *configs, - void **configprivs); - -+#if defined(DAMAGE) && (DRIINFO_MAJOR_VERSION > 5 || \ -+ (DRIINFO_MAJOR_VERSION == 5 && DRIINFO_MINOR_VERSION >= 1)) -+#define DRI_SUPPORTS_CLIP_NOTIFY 1 -+#else -+#define DRI_SUPPORTS_CLIP_NOTIFY 0 -+#endif -+ -+#if (DRIINFO_MAJOR_VERSION > 5 || \ -+ (DRIINFO_MAJOR_VERSION == 5 && DRIINFO_MINOR_VERSION >= 4)) -+#define DRI_DRIVER_FRAMEBUFFER_MAP 1 -+#else -+#define DRI_DRIVER_FRAMEBUFFER_MAP 0 +diff -up /dev/null xf86-video-ati-6.12.2/src/radeon_dri2.c +--- /dev/null 2009-04-02 14:26:50.181076715 -0400 ++++ xf86-video-ati-6.12.2/src/radeon_dri2.c 2009-04-13 13:24:51.000000000 -0400 +@@ -0,0 +1,224 @@ ++/* ++ * Copyright 2008 Kristian Høgsberg ++ * Copyright 2008 Jérôme Glisse ++ * ++ * All Rights Reserved. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining ++ * a copy of this software and associated documentation files (the ++ * "Software"), to deal in the Software without restriction, including ++ * without limitation on the rights to use, copy, modify, merge, ++ * publish, distribute, sublicense, and/or sell copies of the Software, ++ * and to permit persons to whom the Software is furnished to do so, ++ * subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice (including the ++ * next paragraph) shall be included in all copies or substantial ++ * portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF ++ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR ++ * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, ++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, ++ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER ++ * DEALINGS IN THE SOFTWARE. ++ */ ++#ifdef HAVE_CONFIG_H ++#include "config.h" +#endif + - static void RADEONDRITransitionTo2d(ScreenPtr pScreen); - static void RADEONDRITransitionTo3d(ScreenPtr pScreen); - static void RADEONDRITransitionMultiToSingle3d(ScreenPtr pScreen); - static void RADEONDRITransitionSingleToMulti3d(ScreenPtr pScreen); - -+static Bool radeon_dri_gart_init(ScreenPtr pScreen); ++#include ++#include ++#include ++#include + - #ifdef DAMAGE - static void RADEONDRIRefreshArea(ScrnInfoPtr pScrn, RegionPtr pReg); - --#if (DRIINFO_MAJOR_VERSION > 5 || \ -- (DRIINFO_MAJOR_VERSION == 5 && DRIINFO_MINOR_VERSION >= 1)) -+#if DRI_SUPPORTS_CLIP_NOTIFY - static void RADEONDRIClipNotify(ScreenPtr pScreen, WindowPtr *ppWin, int num); - #endif - #endif -@@ -352,6 +371,111 @@ static void RADEONDestroyContext(ScreenPtr pScreen, drm_context_t hwContext, - #endif - } - ++#include "radeon.h" ++#include "radeon_dri2.h" ++#include "radeon_version.h" + -+uint32_t radeon_name_buffer(ScrnInfoPtr pScrn, struct radeon_memory *mem) ++#ifdef DRI2 ++ ++struct dri2_buffer_priv { ++ PixmapPtr pixmap; ++}; ++ ++ ++static DRI2BufferPtr ++radeon_dri2_create_buffers(DrawablePtr drawable, ++ unsigned int *attachments, ++ int count) +{ -+ RADEONInfoPtr info = RADEONPTR(pScrn); -+ struct drm_gem_flink flink; -+ int ret; -+ -+ if (mem && mem->kernel_bo_handle) { -+ if (!mem->kernel_name) { -+ flink.handle = mem->kernel_bo_handle; -+ ret = ioctl(info->dri->drmFD, DRM_IOCTL_GEM_FLINK, &flink); -+ if (ret != 0) { -+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR, -+ "[drm] failed to name buffer %d\n", -errno); -+ return -1; -+ } -+ mem->kernel_name = flink.name; -+ } -+ return mem->kernel_name; ++ ScreenPtr pScreen = drawable->pScreen; ++ DRI2BufferPtr buffers; ++ struct dri2_buffer_priv *privates; ++ PixmapPtr pixmap, depth_pixmap; ++ struct radeon_exa_pixmap_priv *driver_priv; ++ int i, r; ++ ++ buffers = xcalloc(count, sizeof *buffers); ++ if (buffers == NULL) { ++ return NULL; ++ } ++ privates = xcalloc(count, sizeof(struct dri2_buffer_priv)); ++ if (privates == NULL) { ++ xfree(buffers); ++ return NULL; + } -+ return -1; -+} + -+/* so we need to add a frontbuffer map no matter what */ -+#define ROUND_TO(x, y) (((x) + (y) - 1) / (y) * (y)) -+#define ROUND_TO_PAGE(x) ROUND_TO((x), radeon_drm_page_size) ++ depth_pixmap = NULL; ++ for (i = 0; i < count; i++) { ++ if (attachments[i] == DRI2BufferFrontLeft) { ++ if (drawable->type == DRAWABLE_PIXMAP) { ++ pixmap = (Pixmap*)drawable; ++ } else { ++ pixmap = (*pScreen->GetWindowPixmap)((WindowPtr)drawable); ++ } ++ pixmap->refcnt++; ++ } else if (attachments[i] == DRI2BufferStencil && depth_pixmap) { ++ pixmap = depth_pixmap; ++ pixmap->refcnt++; ++ } else { ++ pixmap = (*pScreen->CreatePixmap)(pScreen, ++ drawable->width, ++ drawable->height, ++ drawable->depth, ++ 0); ++ } ++ ++ if (attachments[i] == DRI2BufferDepth) { ++ depth_pixmap = pixmap; ++ } ++ driver_priv = exaGetPixmapDriverPrivate(pixmap); ++ r = radeon_bo_gem_name_buffer(driver_priv->bo, &buffers[i].name); ++ if (r) { ++ /* FIXME: cleanup */ ++ fprintf(stderr, "flink error: %d %s\n", r, strerror(r)); ++ xfree(buffers); ++ xfree(privates); ++ return NULL; ++ } ++ buffers[i].attachment = attachments[i]; ++ buffers[i].pitch = pixmap->devKind; ++ buffers[i].cpp = pixmap->drawable.bitsPerPixel / 8; ++ buffers[i].driverPrivate = &privates[i]; ++ buffers[i].flags = 0; /* not tiled */ ++ privates[i].pixmap = pixmap; ++ } ++ return buffers; ++} + +static void -+radeon_update_screen_private(ScrnInfoPtr pScrn, drm_radeon_sarea_t * sarea) ++radeon_dri2_destroy_buffers(DrawablePtr drawable, ++ DRI2BufferPtr buffers, ++ int count) +{ -+ RADEONInfoPtr info = RADEONPTR(pScrn); -+ RADEONDRIPtr pRADEONDRI; ++ ScreenPtr pScreen = drawable->pScreen; ++ struct dri2_buffer_priv *private; ++ int i; + -+ pRADEONDRI = (RADEONDRIPtr)info->dri->pDRIInfo->devPrivate; -+ info->dri->pDRIInfo->frameBufferPhysicalAddress = (char *) info->LinearAddr; -+ info->dri->pDRIInfo->frameBufferStride = pScrn->displayWidth * info->CurrentLayout.pixel_bytes; -+ info->dri->pDRIInfo->frameBufferSize = ROUND_TO_PAGE(pScrn->displayWidth * pScrn->virtualY * info->CurrentLayout.pixel_bytes); -+#if DRI_DRIVER_FRAMEBUFFER_MAP -+ info->dri->pDRIInfo->hFrameBuffer = info->fb_map_handle; -+#endif -+ /* overload these */ -+ pRADEONDRI->gartTexHandle = radeon_name_buffer(pScrn, info->mm.gart_texture_buffer); -+ pRADEONDRI->textureOffset = radeon_name_buffer(pScrn, info->mm.texture_buffer); -+ pRADEONDRI->frontOffset = radeon_name_buffer(pScrn, info->mm.front_buffer); -+ pRADEONDRI->backOffset = radeon_name_buffer(pScrn, info->mm.back_buffer); -+ pRADEONDRI->depthOffset = radeon_name_buffer(pScrn, info->mm.depth_buffer); ++ for (i = 0; i < count; i++) { ++ private = buffers[i].driverPrivate; ++ (*pScreen->DestroyPixmap)(private->pixmap); ++ } ++ if (buffers) { ++ xfree(buffers[0].driverPrivate); ++ xfree(buffers); ++ } +} + -+static Bool -+radeon_update_dri_mappings(ScrnInfoPtr pScrn, drm_radeon_sarea_t * sarea) ++static void ++radeon_dri2_copy_region(DrawablePtr drawable, ++ RegionPtr region, ++ DRI2BufferPtr dest_buffer, ++ DRI2BufferPtr src_buffer) +{ -+ RADEONInfoPtr info = RADEONPTR(pScrn); -+ uint32_t fb_addr, fb_size; -+ int ret; -+ -+ if (!info->drm_mm) -+ return TRUE; ++ struct dri2_buffer_priv *private = src_buffer->driverPrivate; ++ ScreenPtr pScreen = drawable->pScreen; ++ ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; ++ PixmapPtr pixmap = private->pixmap; ++ RegionPtr copy_clip; ++ GCPtr gc; + ++ gc = GetScratchGC(drawable->depth, pScreen); ++ copy_clip = REGION_CREATE(pScreen, NULL, 0); ++ REGION_COPY(pScreen, copy_clip, region); ++ (*gc->funcs->ChangeClip) (gc, CT_REGION, copy_clip, 0); ++ ValidateGC(drawable, gc); ++ (*gc->ops->CopyArea)(&pixmap->drawable, drawable, gc, ++ 0, 0, drawable->width, drawable->height, 0, 0); ++ FreeScratchGC(gc); ++ RADEONCPReleaseIndirect(pScrn); ++} + -+ fb_addr = info->mm.front_buffer->offset + info->LinearAddr; -+ fb_size = ROUND_TO_PAGE(pScrn->displayWidth * pScrn->virtualY * info->CurrentLayout.pixel_bytes); ++Bool ++radeon_dri2_screen_init(ScreenPtr pScreen) ++{ ++ ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; ++ RADEONInfoPtr info = RADEONPTR(pScrn); ++ DRI2InfoRec dri2_info; ++ int fd; ++ char *bus_id; ++ char *tmp_bus_id; ++ int cmp; ++ int i; + -+ if (info->fb_map_handle) { -+ drmRmMap(info->dri->drmFD, info->fb_map_handle); -+ info->fb_map_handle = 0; ++ if (!info->useEXA) { ++ xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "DRI2 requires EXA\n"); ++ return FALSE; + } -+ -+ ret = drmAddMap(info->dri->drmFD, fb_addr, fb_size, DRM_FRAME_BUFFER, 0, -+ &info->fb_map_handle); + -+ ErrorF("adding fb map from %x for %x ret %d %x\n", fb_addr, fb_size, ret, info->fb_map_handle); ++ /* The whole drmOpen thing is a fiasco and we need to find a way ++ * back to just using open(2). For now, however, lets just make ++ * things worse with even more ad hoc directory walking code to ++ * discover the device file name. */ ++ bus_id = DRICreatePCIBusID(info->PciInfo); ++ for (i = 0; i < DRM_MAX_MINOR; i++) { ++ sprintf(info->dri2.device_name, DRM_DEV_NAME, DRM_DIR_NAME, i); ++ fd = open(info->dri2.device_name, O_RDWR); ++ if (fd < 0) ++ continue; + -+ if (ret < 0) -+ return FALSE; ++ tmp_bus_id = drmGetBusid(fd); ++ close(fd); ++ if (tmp_bus_id == NULL) ++ continue; + -+ return TRUE; -+} ++ cmp = strcmp(tmp_bus_id, bus_id); ++ drmFree(tmp_bus_id); ++ if (cmp == 0) ++ break; ++ } ++ xfree(bus_id); + -+Bool radeon_update_dri_buffers(ScreenPtr pScreen) ++ if (i == DRM_MAX_MINOR) { ++ xf86DrvMsg(pScrn->scrnIndex, X_WARNING, ++ "DRI2: failed to open drm device\n"); ++ return FALSE; ++ } ++ ++ if ( (info->ChipFamily >= CHIP_FAMILY_R300) ) { ++ dri2_info.driverName = R300_DRIVER_NAME; ++ } else if ( info->ChipFamily >= CHIP_FAMILY_R200 ) { ++ dri2_info.driverName = R200_DRIVER_NAME; ++ } else { ++ dri2_info.driverName = RADEON_DRIVER_NAME; ++ } ++ dri2_info.fd = info->dri2.drm_fd; ++ dri2_info.deviceName = info->dri2.device_name; ++ dri2_info.version = 1; ++ dri2_info.CreateBuffers = radeon_dri2_create_buffers; ++ dri2_info.DestroyBuffers = radeon_dri2_destroy_buffers; ++ dri2_info.CopyRegion = radeon_dri2_copy_region; ++ info->dri2.enabled = DRI2ScreenInit(pScreen, &dri2_info); ++ return info->dri2.enabled; ++} ++ ++void ++radeon_dri2_close_screen(ScreenPtr pScreen) +{ -+ ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; -+ RADEONInfoPtr info = RADEONPTR(pScrn); -+ Bool success; -+ drm_radeon_sarea_t *sarea; ++ DRI2CloseScreen(pScreen); ++} + -+ if (info->ChipFamily >= CHIP_FAMILY_R600) -+ return TRUE; ++#endif +diff -up /dev/null xf86-video-ati-6.12.2/src/radeon_dri2.h +--- /dev/null 2009-04-02 14:26:50.181076715 -0400 ++++ xf86-video-ati-6.12.2/src/radeon_dri2.h 2009-04-13 13:24:51.000000000 -0400 +@@ -0,0 +1,42 @@ ++/* ++ * Copyright 2008 Jerome Glisse ++ * ++ * All Rights Reserved. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining ++ * a copy of this software and associated documentation files (the ++ * "Software"), to deal in the Software without restriction, including ++ * without limitation on the rights to use, copy, modify, merge, ++ * publish, distribute, sublicense, and/or sell copies of the Software, ++ * and to permit persons to whom the Software is furnished to do so, ++ * subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice (including the ++ * next paragraph) shall be included in all copies or substantial ++ * portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF ++ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR ++ * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, ++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, ++ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER ++ * DEALINGS IN THE SOFTWARE. ++ */ ++#ifndef RADEON_DRI2_H ++#define RADEON_DRI2_H + -+ if (!info->drm_mm) -+ return TRUE; ++struct radeon_dri2 { ++ int drm_fd; ++ Bool enabled; ++ char device_name[64]; ++}; + -+ if (info->dri2.enabled) -+ return TRUE; ++#ifdef DRI2 ++#include "dri2.h" ++Bool radeon_dri2_screen_init(ScreenPtr pScreen); ++void radeon_dri2_close_screen(ScreenPtr pScreen); ++#endif + -+ sarea = DRIGetSAREAPrivate(pScreen); -+ success = radeon_update_dri_mappings(pScrn, sarea); ++#endif +diff -up /dev/null xf86-video-ati-6.12.2/src/radeon_dri_bufmgr.c +--- /dev/null 2009-04-02 14:26:50.181076715 -0400 ++++ xf86-video-ati-6.12.2/src/radeon_dri_bufmgr.c 2009-04-13 13:24:51.000000000 -0400 +@@ -0,0 +1,177 @@ ++/* ++ * Copyright © 2007 Intel Corporation ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice (including the next ++ * paragraph) shall be included in all copies or substantial portions of the ++ * Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER ++ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS ++ * IN THE SOFTWARE. ++ * ++ * Authors: ++ * Eric Anholt ++ * ++ */ + -+ if (!success) -+ return FALSE; ++#include ++#include ++#include ++#include "radeon_dri_bufmgr.h" + -+ radeon_update_sarea(pScrn, sarea); -+ radeon_update_screen_private(pScrn, sarea); -+ return TRUE; ++/** @file dri_bufmgr.c ++ * ++ * Convenience functions for buffer management methods. ++ */ ++ ++dri_bo * ++dri_bo_alloc(dri_bufmgr *bufmgr, const char *name, unsigned long size, ++ unsigned int alignment, uint64_t location_mask) ++{ ++ return bufmgr->bo_alloc(bufmgr, name, size, alignment, location_mask); +} + - /* Called when the X server is woken up to allow the last client's - * context to be saved and the X server's context to be loaded. This is - * not necessary for the Radeon since the client detects when it's -@@ -701,25 +825,35 @@ static void RADEONDRIInitGARTValues(RADEONInfoPtr info) - - info->dri->gartOffset = 0; - -- /* Initialize the CP ring buffer data */ -- info->dri->ringStart = info->dri->gartOffset; -- info->dri->ringMapSize = info->dri->ringSize*1024*1024 + radeon_drm_page_size; -- info->dri->ringSizeLog2QW = RADEONMinBits(info->dri->ringSize*1024*1024/8)-1; -- -- info->dri->ringReadOffset = info->dri->ringStart + info->dri->ringMapSize; -- info->dri->ringReadMapSize = radeon_drm_page_size; -- -- /* Reserve space for vertex/indirect buffers */ -- info->dri->bufStart = info->dri->ringReadOffset + info->dri->ringReadMapSize; -- info->dri->bufMapSize = info->dri->bufSize*1024*1024; -- -- /* Reserve the rest for GART textures */ -- info->dri->gartTexStart = info->dri->bufStart + info->dri->bufMapSize; -- s = (info->dri->gartSize*1024*1024 - info->dri->gartTexStart); -- l = RADEONMinBits((s-1) / RADEON_NR_TEX_REGIONS); -- if (l < RADEON_LOG_TEX_GRANULARITY) l = RADEON_LOG_TEX_GRANULARITY; -- info->dri->gartTexMapSize = (s >> l) << l; -- info->dri->log2GARTTexGran = l; -+ if (!info->drm_mm) { -+ /* Initialize the CP ring buffer data */ -+ info->dri->ringStart = info->dri->gartOffset; -+ info->dri->ringMapSize = info->dri->ringSize*1024*1024 + radeon_drm_page_size; -+ info->dri->ringSizeLog2QW = RADEONMinBits(info->dri->ringSize*1024*1024/8)-1; ++dri_bo * ++dri_bo_alloc_static(dri_bufmgr *bufmgr, const char *name, unsigned long offset, ++ unsigned long size, void *virtual, ++ uint64_t location_mask) ++{ ++ return bufmgr->bo_alloc_static(bufmgr, name, offset, size, virtual, ++ location_mask); ++} + -+ info->dri->ringReadOffset = info->dri->ringStart + info->dri->ringMapSize; -+ info->dri->ringReadMapSize = radeon_drm_page_size; ++void ++dri_bo_reference(dri_bo *bo) ++{ ++ bo->bufmgr->bo_reference(bo); ++} + -+ /* Reserve space for vertex/indirect buffers */ -+ info->dri->bufStart = info->dri->ringReadOffset + info->dri->ringReadMapSize; -+ info->dri->bufMapSize = info->dri->bufSize*1024*1024; ++void ++dri_bo_unreference(dri_bo *bo) ++{ ++ if (bo == NULL) ++ return; + -+ /* Reserve the rest for GART textures */ -+ info->dri->gartTexStart = info->dri->bufStart + info->dri->bufMapSize; -+ s = (info->dri->gartSize*1024*1024 - info->dri->gartTexStart); -+ l = RADEONMinBits((s-1) / RADEON_NR_TEX_REGIONS); -+ if (l < RADEON_LOG_TEX_GRANULARITY) l = RADEON_LOG_TEX_GRANULARITY; -+ info->dri->gartTexMapSize = (s >> l) << l; -+ info->dri->log2GARTTexGran = l; -+ } else { -+ s = (8*1024*1024); -+ l = RADEONMinBits((s-1) / RADEON_NR_TEX_REGIONS); -+ l = RADEONMinBits((s-1) / RADEON_NR_TEX_REGIONS); -+ if (l < RADEON_LOG_TEX_GRANULARITY) l = RADEON_LOG_TEX_GRANULARITY; -+ info->dri->gartTexMapSize = (s >> l) << l; -+ info->dri->log2GARTTexGran = l; -+ } ++ bo->bufmgr->bo_unreference(bo); ++} + - } - - /* AGP Mode Quirk List - Certain hostbridge/gfx-card combos don't work with -@@ -992,6 +1126,8 @@ static Bool RADEONDRIAgpInit(RADEONInfoPtr info, ScreenPtr pScreen) - "[agp] ring handle = 0x%08x\n", - (unsigned int)info->dri->ringHandle); - ++int ++dri_bo_map(dri_bo *buf, int write_enable) ++{ ++ return buf->bufmgr->bo_map(buf, write_enable); ++} + -+#if 0 - if (drmMap(info->dri->drmFD, info->dri->ringHandle, info->dri->ringMapSize, - &info->dri->ring) < 0) { - xf86DrvMsg(pScreen->myNum, X_ERROR, "[agp] Could not map ring\n"); -@@ -1000,9 +1136,10 @@ static Bool RADEONDRIAgpInit(RADEONInfoPtr info, ScreenPtr pScreen) - xf86DrvMsg(pScreen->myNum, X_INFO, - "[agp] Ring mapped at 0x%08lx\n", - (unsigned long)info->dri->ring); -- -+#endif - if (drmAddMap(info->dri->drmFD, info->dri->ringReadOffset, info->dri->ringReadMapSize, - DRM_AGP, DRM_READ_ONLY, &info->dri->ringReadPtrHandle) < 0) { ++int ++dri_bo_unmap(dri_bo *buf) ++{ ++ return buf->bufmgr->bo_unmap(buf); ++} + - xf86DrvMsg(pScreen->myNum, X_ERROR, - "[agp] Could not add ring read ptr mapping\n"); - return FALSE; -@@ -1011,6 +1148,8 @@ static Bool RADEONDRIAgpInit(RADEONInfoPtr info, ScreenPtr pScreen) - "[agp] ring read ptr handle = 0x%08x\n", - (unsigned int)info->dri->ringReadPtrHandle); - ++void ++dri_fence_wait(dri_fence *fence) ++{ ++ fence->bufmgr->fence_wait(fence); ++} + -+#if 0 - if (drmMap(info->dri->drmFD, info->dri->ringReadPtrHandle, info->dri->ringReadMapSize, - &info->dri->ringReadPtr) < 0) { - xf86DrvMsg(pScreen->myNum, X_ERROR, -@@ -1020,6 +1159,7 @@ static Bool RADEONDRIAgpInit(RADEONInfoPtr info, ScreenPtr pScreen) - xf86DrvMsg(pScreen->myNum, X_INFO, - "[agp] Ring read ptr mapped at 0x%08lx\n", - (unsigned long)info->dri->ringReadPtr); -+#endif - - if (drmAddMap(info->dri->drmFD, info->dri->bufStart, info->dri->bufMapSize, - DRM_AGP, 0, &info->dri->bufHandle) < 0) { -@@ -1097,6 +1237,7 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info, ScreenPtr pScreen) - "[pci] ring handle = 0x%08x\n", - (unsigned int)info->dri->ringHandle); - -+#if 0 - if (drmMap(info->dri->drmFD, info->dri->ringHandle, info->dri->ringMapSize, - &info->dri->ring) < 0) { - xf86DrvMsg(pScreen->myNum, X_ERROR, "[pci] Could not map ring\n"); -@@ -1108,6 +1249,7 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info, ScreenPtr pScreen) - xf86DrvMsg(pScreen->myNum, X_INFO, - "[pci] Ring contents 0x%08lx\n", - *(unsigned long *)(pointer)info->dri->ring); -+#endif - - if (drmAddMap(info->dri->drmFD, info->dri->ringReadOffset, info->dri->ringReadMapSize, - DRM_SCATTER_GATHER, flags, &info->dri->ringReadPtrHandle) < 0) { -@@ -1119,8 +1261,10 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info, ScreenPtr pScreen) - "[pci] ring read ptr handle = 0x%08x\n", - (unsigned int)info->dri->ringReadPtrHandle); - -+#if 0 - if (drmMap(info->dri->drmFD, info->dri->ringReadPtrHandle, info->dri->ringReadMapSize, - &info->dri->ringReadPtr) < 0) { ++void ++dri_fence_reference(dri_fence *fence) ++{ ++ fence->bufmgr->fence_reference(fence); ++} + - xf86DrvMsg(pScreen->myNum, X_ERROR, - "[pci] Could not map ring read ptr\n"); - return FALSE; -@@ -1131,6 +1275,7 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info, ScreenPtr pScreen) - xf86DrvMsg(pScreen->myNum, X_INFO, - "[pci] Ring read ptr contents 0x%08lx\n", - *(unsigned long *)(pointer)info->dri->ringReadPtr); -+#endif - - if (drmAddMap(info->dri->drmFD, info->dri->bufStart, info->dri->bufMapSize, - DRM_SCATTER_GATHER, 0, &info->dri->bufHandle) < 0) { -@@ -1183,6 +1328,9 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info, ScreenPtr pScreen) - */ - static Bool RADEONDRIMapInit(RADEONInfoPtr info, ScreenPtr pScreen) - { ++void ++dri_fence_unreference(dri_fence *fence) ++{ ++ if (fence == NULL) ++ return; + -+ if (info->drm_mm) -+ return TRUE; - /* Map registers */ - info->dri->registerSize = info->MMIOSize; - if (drmAddMap(info->dri->drmFD, info->MMIOAddr, info->dri->registerSize, -@@ -1223,20 +1371,23 @@ static int RADEONDRIKernelInit(RADEONInfoPtr info, ScreenPtr pScreen) - drmInfo.fb_bpp = info->CurrentLayout.pixel_code; - drmInfo.depth_bpp = (info->dri->depthBits - 8) * 2; - -- drmInfo.front_offset = info->dri->frontOffset; -- drmInfo.front_pitch = info->dri->frontPitch * cpp; -- drmInfo.back_offset = info->dri->backOffset; -- drmInfo.back_pitch = info->dri->backPitch * cpp; -- drmInfo.depth_offset = info->dri->depthOffset; -- drmInfo.depth_pitch = info->dri->depthPitch * drmInfo.depth_bpp / 8; -- -- drmInfo.fb_offset = info->dri->fbHandle; -- drmInfo.mmio_offset = info->dri->registerHandle; -- drmInfo.ring_offset = info->dri->ringHandle; -- drmInfo.ring_rptr_offset = info->dri->ringReadPtrHandle; -- drmInfo.buffers_offset = info->dri->bufHandle; -- drmInfo.gart_textures_offset= info->dri->gartTexHandle; -- -+ if (!info->drm_mm) { -+ drmInfo.front_offset = info->dri->frontOffset; -+ drmInfo.front_pitch = info->dri->frontPitch * cpp; -+ drmInfo.back_offset = info->dri->backOffset; -+ drmInfo.back_pitch = info->dri->backPitch * cpp; -+ drmInfo.depth_offset = info->dri->depthOffset; -+ drmInfo.depth_pitch = info->dri->depthPitch * drmInfo.depth_bpp / 8; ++ fence->bufmgr->fence_unreference(fence); ++} + -+ drmInfo.fb_offset = info->dri->fbHandle; -+ drmInfo.mmio_offset = info->dri->registerHandle; -+ drmInfo.ring_offset = info->dri->ringHandle; -+ drmInfo.ring_rptr_offset = info->dri->ringReadPtrHandle; -+ drmInfo.buffers_offset = info->dri->bufHandle; -+ drmInfo.gart_textures_offset= info->dri->gartTexHandle; -+ } else { -+ } -+ - if (drmCommandWrite(info->dri->drmFD, DRM_RADEON_CP_INIT, - &drmInfo, sizeof(drm_radeon_init_t)) < 0) - return FALSE; -@@ -1245,8 +1396,9 @@ static int RADEONDRIKernelInit(RADEONInfoPtr info, ScreenPtr pScreen) - * registers back to their default values, so we need to restore - * those engine register here. - */ -- if (info->ChipFamily < CHIP_FAMILY_R600) -- RADEONEngineRestore(pScrn); -+ if (!info->drm_mm) -+ if (info->ChipFamily < CHIP_FAMILY_R600) -+ RADEONEngineRestore(pScrn); - - return TRUE; - } -@@ -1444,12 +1596,11 @@ Bool RADEONDRIGetVersion(ScrnInfoPtr pScrn) - - /* Get DRM version & close DRM */ - info->dri->pKernelDRMVersion = drmGetVersion(fd); -- drmClose(fd); - if (info->dri->pKernelDRMVersion == NULL) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "[dri] RADEONDRIGetVersion failed to get the DRM version\n" - "[dri] Disabling DRI.\n"); -- return FALSE; -+ goto fail; - } - - /* Now check if we qualify */ -@@ -1483,10 +1634,27 @@ Bool RADEONDRIGetVersion(ScrnInfoPtr pScrn) - req_patch); - drmFreeVersion(info->dri->pKernelDRMVersion); - info->dri->pKernelDRMVersion = NULL; -- return FALSE; -+ goto fail; -+ } ++void ++dri_bo_subdata(dri_bo *bo, unsigned long offset, ++ unsigned long size, const void *data) ++{ ++ if (size == 0 || data == NULL) ++ return; + -+ if (info->dri->pKernelDRMVersion->version_minor >= 30) { -+ struct drm_radeon_gem_info mminfo; ++ dri_bo_map(bo, 1); ++ memcpy((unsigned char *)bo->virtual + offset, data, size); ++ dri_bo_unmap(bo); ++} + -+ if (!drmCommandWriteRead(fd, DRM_RADEON_GEM_INFO, &mminfo, sizeof(mminfo))) -+ { -+ info->drm_mm = TRUE; -+ info->mm.vram_size = mminfo.vram_size; -+ info->mm.gart_size = mminfo.gart_size; -+ ErrorF("initing %llx %llx %llx %llx\n", -+ mminfo.gart_size, mminfo.vram_size); -+ } - } - -+ drmClose(fd); - return TRUE; -+fail: -+ drmClose(fd); -+ return FALSE; - } - - Bool RADEONDRISetVBlankInterrupt(ScrnInfoPtr pScrn, Bool on) -@@ -1495,6 +1663,9 @@ Bool RADEONDRISetVBlankInterrupt(ScrnInfoPtr pScrn, Bool on) - xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); - int value = 0; - -+ if (info->drm_mode_setting) -+ return TRUE; ++void ++dri_bo_get_subdata(dri_bo *bo, unsigned long offset, ++ unsigned long size, void *data) ++{ ++ if (size == 0 || data == NULL) ++ return; + - if (!info->want_vblank_interrupts) - on = FALSE; - -@@ -1514,6 +1685,52 @@ Bool RADEONDRISetVBlankInterrupt(ScrnInfoPtr pScrn, Bool on) - return TRUE; - } - -+Bool RADEONDRIDoMappings(ScreenPtr pScreen) ++ dri_bo_map(bo, 0); ++ memcpy(data, (unsigned char *)bo->virtual + offset, size); ++ dri_bo_unmap(bo); ++} ++ ++void ++dri_bufmgr_destroy(dri_bufmgr *bufmgr) +{ -+ ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; -+ RADEONInfoPtr info = RADEONPTR(pScrn); -+ drm_radeon_sarea_t * pSAREAPriv = DRIGetSAREAPrivate(pScreen); -+ /* DRIScreenInit doesn't add all the -+ * common mappings. Add additional -+ * mappings here. -+ */ ++ bufmgr->destroy(bufmgr); ++} + -+ if (info->ChipFamily >= CHIP_FAMILY_R600) -+ return TRUE; + -+ if (info->dri2.enabled) -+ return TRUE; ++int dri_emit_reloc(dri_bo *reloc_buf, uint64_t flags, uint32_t delta, ++ uint32_t offset, dri_bo *target_buf) ++{ ++ return reloc_buf->bufmgr->emit_reloc(reloc_buf, flags, delta, offset, target_buf); ++} + -+ pSAREAPriv = DRIGetSAREAPrivate(pScreen); -+ if (!RADEONDRIMapInit(info, pScreen)) { -+ RADEONDRICloseScreen(pScreen); -+ return FALSE; -+ } -+ -+ radeon_update_sarea(pScrn, pSAREAPriv); -+ -+ /* DRIScreenInit adds the frame buffer -+ map, but we need it as well */ -+ { -+ void *scratch_ptr; -+ int scratch_int; ++void *dri_process_relocs(dri_bo *batch_buf, uint32_t *count) ++{ ++ return batch_buf->bufmgr->process_relocs(batch_buf, count); ++} + -+ DRIGetDeviceInfo(pScreen, &info->dri->fbHandle, -+ &scratch_int, &scratch_int, -+ &scratch_int, &scratch_int, -+ &scratch_ptr); -+ } ++void dri_post_submit(dri_bo *batch_buf, dri_fence **last_fence) ++{ ++ batch_buf->bufmgr->post_submit(batch_buf, last_fence); ++} + -+ /* FIXME: When are these mappings unmapped? */ ++void ++dri_bufmgr_set_debug(dri_bufmgr *bufmgr, int enable_debug) ++{ ++ bufmgr->debug = enable_debug; ++} + -+ if (!RADEONInitVisualConfigs(pScreen)) { -+ RADEONDRICloseScreen(pScreen); -+ return FALSE; -+ } -+ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "[dri] Visual configs initialized\n"); -+ return TRUE; ++int ++dri_bufmgr_check_aperture_space(struct radeon_space_check *bos, int num_bo) ++{ ++ if (num_bo == 0) ++ return BUFMGR_SPACE_OK; + ++ return bos[0].buf->bufmgr->check_aperture_space(bos, num_bo); +} - - /* Initialize the screen-specific data structures for the DRI and the - * Radeon. This is the main entry point to the device-specific -@@ -1577,10 +1794,22 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen) - pDRIInfo->ddxDriverMajorVersion = info->allowColorTiling ? 5 : 4; - pDRIInfo->ddxDriverMinorVersion = 3; - pDRIInfo->ddxDriverPatchVersion = 0; -- pDRIInfo->frameBufferPhysicalAddress = (void *)info->LinearAddr + info->dri->frontOffset; -- pDRIInfo->frameBufferSize = info->FbMapSize - info->FbSecureSize; -- pDRIInfo->frameBufferStride = (pScrn->displayWidth * -- info->CurrentLayout.pixel_bytes); + -+#if DRI_DRIVER_FRAMEBUFFER_MAP -+ if (info->drm_mm) { -+ pDRIInfo->frameBufferPhysicalAddress = 0; -+ pDRIInfo->frameBufferSize = 0; -+ pDRIInfo->frameBufferStride = 0; -+ pDRIInfo->dontMapFrameBuffer = TRUE; -+ } else -+#endif -+ { -+ pDRIInfo->frameBufferPhysicalAddress = (void *)info->LinearAddr + info->dri->frontOffset; -+ pDRIInfo->frameBufferSize = info->FbMapSize - info->FbSecureSize; -+ pDRIInfo->frameBufferStride = (pScrn->displayWidth * -+ info->CurrentLayout.pixel_bytes); -+ } ++int dri_bo_pin(dri_bo *bo, int domain) ++{ ++ return bo->bufmgr->pin(bo, domain); ++} + - pDRIInfo->ddxDrawableTableEntry = RADEON_MAX_DRAWABLES; - pDRIInfo->maxDrawableTableEntry = (SAREA_MAX_DRAWABLES - < RADEON_MAX_DRAWABLES -@@ -1633,9 +1862,7 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen) - pDRIInfo->TransitionTo3d = RADEONDRITransitionTo3d; - pDRIInfo->TransitionSingleToMulti3D = RADEONDRITransitionSingleToMulti3d; - pDRIInfo->TransitionMultiToSingle3D = RADEONDRITransitionMultiToSingle3d; --#if defined(DAMAGE) && (DRIINFO_MAJOR_VERSION > 5 || \ -- (DRIINFO_MAJOR_VERSION == 5 && \ -- DRIINFO_MINOR_VERSION >= 1)) -+#if DRI_SUPPORT_CLIP_NOTIFY - pDRIInfo->ClipNotify = RADEONDRIClipNotify; - #endif - -@@ -1667,57 +1894,60 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen) - pDRIInfo = NULL; - return FALSE; - } -- /* Initialize AGP */ -- if (info->cardType==CARD_AGP && !RADEONDRIAgpInit(info, pScreen)) { -- xf86DrvMsg(pScreen->myNum, X_ERROR, -- "[agp] AGP failed to initialize. Disabling the DRI.\n" ); -- xf86DrvMsg(pScreen->myNum, X_INFO, -- "[agp] You may want to make sure the agpgart kernel " -- "module\nis loaded before the radeon kernel module.\n"); -- RADEONDRICloseScreen(pScreen); -- return FALSE; -- } -- -- /* Initialize PCI */ -- if ((info->cardType!=CARD_AGP) && !RADEONDRIPciInit(info, pScreen)) { -- xf86DrvMsg(pScreen->myNum, X_ERROR, -- "[pci] PCI failed to initialize. Disabling the DRI.\n" ); -- RADEONDRICloseScreen(pScreen); -- return FALSE; -- } -- -- /* DRIScreenInit doesn't add all the -- * common mappings. Add additional -- * mappings here. -- */ -- if (!RADEONDRIMapInit(info, pScreen)) { -- RADEONDRICloseScreen(pScreen); -- return FALSE; -- } - -- /* DRIScreenInit adds the frame buffer -- map, but we need it as well */ -- { -- void *scratch_ptr; -- int scratch_int; -+ /* Now, nuke dri.c's dummy frontbuffer map setup if we did that. */ -+ if (pDRIInfo->frameBufferSize != 0 && info->drm_mm) { -+ int tmp; -+ drm_handle_t fb_handle; -+ void *ptmp; - -- DRIGetDeviceInfo(pScreen, &info->dri->fbHandle, -- &scratch_int, &scratch_int, -- &scratch_int, &scratch_int, -- &scratch_ptr); -- } -- -- /* FIXME: When are these mappings unmapped? */ -- -- if (!RADEONInitVisualConfigs(pScreen)) { -- RADEONDRICloseScreen(pScreen); -- return FALSE; -+ /* With the compat method, it will continue to report -+ * the wrong map out of GetDeviceInfo, which will break AIGLX. -+ */ -+ DRIGetDeviceInfo(pScreen, &fb_handle, &tmp, &tmp, &tmp, &tmp, &ptmp); -+ drmRmMap(info->dri->drmFD, fb_handle); -+ -+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING, -+ "Removed DRI frontbuffer mapping in compatibility mode.\n"); -+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING, -+ "DRIGetDeviceInfo will report incorrect frontbuffer " -+ "handle.\n"); -+ } -+ -+ if (info->drm_mm) { -+ int ret; -+ ret = radeon_dri_gart_init(pScreen); -+ if (!ret) { -+ xf86DrvMsg(pScreen->myNum, X_ERROR, -+ "[gart] GART failed to initialize. Disabling the DRI.\n" ); -+ RADEONDRICloseScreen(pScreen); -+ return FALSE; -+ } -+ } else { -+ if (info->cardType==CARD_AGP && !RADEONDRIAgpInit(info, pScreen)) { -+ /* Initialize AGP */ -+ xf86DrvMsg(pScreen->myNum, X_ERROR, -+ "[agp] AGP failed to initialize. Disabling the DRI.\n" ); -+ xf86DrvMsg(pScreen->myNum, X_INFO, -+ "[agp] You may want to make sure the agpgart kernel " -+ "module\nis loaded before the radeon kernel module.\n"); -+ RADEONDRICloseScreen(pScreen); -+ return FALSE; -+ } -+ -+ /* Initialize PCI */ -+ if ((info->cardType!=CARD_AGP) && !RADEONDRIPciInit(info, pScreen)) { -+ xf86DrvMsg(pScreen->myNum, X_ERROR, -+ "[pci] PCI failed to initialize. Disabling the DRI.\n" ); -+ RADEONDRICloseScreen(pScreen); -+ return FALSE; -+ } - } -- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "[dri] Visual configs initialized\n"); - - return TRUE; - } - -+ - static Bool RADEONDRIDoCloseScreen(int scrnIndex, ScreenPtr pScreen) - { - ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; -@@ -1759,17 +1989,21 @@ Bool RADEONDRIFinishScreenInit(ScreenPtr pScreen) - return FALSE; - } - -- /* Initialize the vertex buffers list */ -- if (!RADEONDRIBufInit(info, pScreen)) { -- RADEONDRICloseScreen(pScreen); -- return FALSE; -+ if (!info->drm_mm) { -+ /* Initialize the vertex buffers list */ -+ if (!RADEONDRIBufInit(info, pScreen)) { -+ RADEONDRICloseScreen(pScreen); -+ return FALSE; -+ } - } - -- /* Initialize IRQ */ -- RADEONDRIIrqInit(info, pScreen); -+ if (!info->drm_mode_setting) { -+ /* Initialize IRQ */ -+ RADEONDRIIrqInit(info, pScreen); -+ /* Initialize kernel GART memory manager */ -+ RADEONDRIGartHeapInit(info, pScreen); -+ } - -- /* Initialize kernel GART memory manager */ -- RADEONDRIGartHeapInit(info, pScreen); - - /* Initialize and start the CP if required */ - RADEONDRICPInit(pScrn); -@@ -1778,6 +2012,10 @@ Bool RADEONDRIFinishScreenInit(ScreenPtr pScreen) - pSAREAPriv = (drm_radeon_sarea_t*)DRIGetSAREAPrivate(pScreen); - memset(pSAREAPriv, 0, sizeof(*pSAREAPriv)); - -+ if (info->drm_mm) { -+ /* init the handles into the sarea */ -+ -+ } - pRADEONDRI = (RADEONDRIPtr)info->dri->pDRIInfo->devPrivate; - - pRADEONDRI->deviceID = info->Chipset; -@@ -1935,6 +2173,8 @@ void RADEONDRICloseScreen(ScreenPtr pScreen) - drmUnmap(info->dri->buf, info->dri->bufMapSize); - info->dri->buf = NULL; - } -+ -+#if 0 - if (info->dri->ringReadPtr) { - drmUnmap(info->dri->ringReadPtr, info->dri->ringReadMapSize); - info->dri->ringReadPtr = NULL; -@@ -1943,6 +2183,7 @@ void RADEONDRICloseScreen(ScreenPtr pScreen) - drmUnmap(info->dri->ring, info->dri->ringMapSize); - info->dri->ring = NULL; - } -+#endif - if (info->dri->agpMemHandle != DRM_AGP_NO_HANDLE) { - drmAgpUnbind(info->dri->drmFD, info->dri->agpMemHandle); - drmAgpFree(info->dri->drmFD, info->dri->agpMemHandle); -@@ -2352,3 +2593,11 @@ int RADEONDRISetParam(ScrnInfoPtr pScrn, unsigned int param, int64_t value) - &radeonsetparam, sizeof(drm_radeon_setparam_t)); - return ret; - } -+ -+static Bool radeon_dri_gart_init(ScreenPtr pScreen) ++void dri_bo_unpin(dri_bo *bo) +{ -+ ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; -+ RADEONInfoPtr info = RADEONPTR(pScrn); ++ bo->bufmgr->unpin(bo); ++} + -+ RADEONDRIInitGARTValues(info); ++uint32_t dri_bo_get_handle(dri_bo *bo) ++{ ++ return bo->bufmgr->get_handle(bo); +} -diff --git a/src/radeon_dri2.c b/src/radeon_dri2.c -new file mode 100644 -index 0000000..eb15ff2 ---- /dev/null -+++ b/src/radeon_dri2.c -@@ -0,0 +1,224 @@ -+/* -+ * Copyright 2008 Kristian Høgsberg -+ * Copyright 2008 Jérôme Glisse -+ * +diff -up /dev/null xf86-video-ati-6.12.2/src/radeon_dri_bufmgr.h +--- /dev/null 2009-04-02 14:26:50.181076715 -0400 ++++ xf86-video-ati-6.12.2/src/radeon_dri_bufmgr.h 2009-04-13 13:24:51.000000000 -0400 +@@ -0,0 +1,291 @@ ++/************************************************************************** ++ * ++ * Copyright � 2007 Intel Corporation ++ * Copyright 2006 Tungsten Graphics, Inc., Bismarck, ND., USA + * All Rights Reserved. -+ * -+ * Permission is hereby granted, free of charge, to any person obtaining -+ * a copy of this software and associated documentation files (the ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including -+ * without limitation on the rights to use, copy, modify, merge, -+ * publish, distribute, sublicense, and/or sell copies of the Software, -+ * and to permit persons to whom the Software is furnished to do so, -+ * subject to the following conditions: ++ * without limitation the rights to use, copy, modify, merge, publish, ++ * distribute, sub license, and/or sell copies of the Software, and to ++ * permit persons to whom the Software is furnished to do so, subject to ++ * the following conditions: ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, ++ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR ++ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE ++ * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * The above copyright notice and this permission notice (including the -+ * next paragraph) shall be included in all copies or substantial -+ * portions of the Software. -+ * -+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -+ * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR -+ * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER -+ * DEALINGS IN THE SOFTWARE. ++ * next paragraph) shall be included in all copies or substantial portions ++ * of the Software. ++ * ++ * ++ **************************************************************************/ ++/* ++ * Authors: Thomas Hellstr�m ++ * Keith Whitwell ++ * Eric Anholt + */ -+#ifdef HAVE_CONFIG_H -+#include "config.h" -+#endif + -+#include -+#include -+#include -+#include -+ -+#include "radeon.h" -+#include "radeon_dri2.h" -+#include "radeon_version.h" ++#ifndef _DRI_BUFMGR_H_ ++#define _DRI_BUFMGR_H_ ++#include + -+#ifdef DRI2 ++typedef struct _dri_bufmgr dri_bufmgr; ++typedef struct _dri_bo dri_bo; ++typedef struct _dri_fence dri_fence; + -+struct dri2_buffer_priv { -+ PixmapPtr pixmap; ++#define BUFMGR_SPACE_OK 0 ++#define BUFMGR_SPACE_OP_TO_BIG 1 ++#define BUFMGR_SPACE_FLUSH 2 ++struct radeon_space_check { ++ dri_bo *buf; ++ uint32_t read_domains; ++ uint32_t write_domain; ++ uint32_t new_accounted; +}; + ++/* reloc format */ ++/* gem handle, read_domains, write_domain, reloc_count */ ++#define RADEON_RELOC_SIZE 4 ++struct radeon_relocs_info { ++ uint32_t *buf; ++ dri_bo **bo_list; ++ int size; ++ int max_bo; ++ int num_reloc; ++}; + -+static DRI2BufferPtr -+radeon_dri2_create_buffers(DrawablePtr drawable, -+ unsigned int *attachments, -+ int count) -+{ -+ ScreenPtr pScreen = drawable->pScreen; -+ DRI2BufferPtr buffers; -+ struct dri2_buffer_priv *privates; -+ PixmapPtr pixmap, depth_pixmap; -+ struct radeon_exa_pixmap_priv *driver_priv; -+ int i, r; -+ -+ buffers = xcalloc(count, sizeof *buffers); -+ if (buffers == NULL) { -+ return NULL; -+ } -+ privates = xcalloc(count, sizeof(struct dri2_buffer_priv)); -+ if (privates == NULL) { -+ xfree(buffers); -+ return NULL; -+ } -+ -+ depth_pixmap = NULL; -+ for (i = 0; i < count; i++) { -+ if (attachments[i] == DRI2BufferFrontLeft) { -+ if (drawable->type == DRAWABLE_PIXMAP) { -+ pixmap = (Pixmap*)drawable; -+ } else { -+ pixmap = (*pScreen->GetWindowPixmap)((WindowPtr)drawable); -+ } -+ pixmap->refcnt++; -+ } else if (attachments[i] == DRI2BufferStencil && depth_pixmap) { -+ pixmap = depth_pixmap; -+ pixmap->refcnt++; -+ } else { -+ pixmap = (*pScreen->CreatePixmap)(pScreen, -+ drawable->width, -+ drawable->height, -+ drawable->depth, -+ 0); -+ } -+ -+ if (attachments[i] == DRI2BufferDepth) { -+ depth_pixmap = pixmap; -+ } -+ driver_priv = exaGetPixmapDriverPrivate(pixmap); -+ r = radeon_bo_gem_name_buffer(driver_priv->bo, &buffers[i].name); -+ if (r) { -+ /* FIXME: cleanup */ -+ fprintf(stderr, "flink error: %d %s\n", r, strerror(r)); -+ xfree(buffers); -+ xfree(privates); -+ return NULL; -+ } -+ buffers[i].attachment = attachments[i]; -+ buffers[i].pitch = pixmap->devKind; -+ buffers[i].cpp = pixmap->drawable.bitsPerPixel / 8; -+ buffers[i].driverPrivate = &privates[i]; -+ buffers[i].flags = 0; /* not tiled */ -+ privates[i].pixmap = pixmap; -+ } -+ return buffers; -+} -+ -+static void -+radeon_dri2_destroy_buffers(DrawablePtr drawable, -+ DRI2BufferPtr buffers, -+ int count) -+{ -+ ScreenPtr pScreen = drawable->pScreen; -+ struct dri2_buffer_priv *private; -+ int i; -+ -+ for (i = 0; i < count; i++) { -+ private = buffers[i].driverPrivate; -+ (*pScreen->DestroyPixmap)(private->pixmap); -+ } -+ if (buffers) { -+ xfree(buffers[0].driverPrivate); -+ xfree(buffers); -+ } -+} ++struct _dri_bo { ++ /** Size in bytes of the buffer object. */ ++ unsigned long size; ++ /** ++ * Card virtual address (offset from the beginning of the aperture) for the ++ * object. Only valid while validated. ++ */ ++ unsigned long offset; ++ /** ++ * Virtual address for accessing the buffer data. Only valid while mapped. ++ */ ++ void *virtual; ++ /** Buffer manager context associated with this buffer object */ ++ dri_bufmgr *bufmgr; ++}; + -+static void -+radeon_dri2_copy_region(DrawablePtr drawable, -+ RegionPtr region, -+ DRI2BufferPtr dest_buffer, -+ DRI2BufferPtr src_buffer) -+{ -+ struct dri2_buffer_priv *private = src_buffer->driverPrivate; -+ ScreenPtr pScreen = drawable->pScreen; -+ ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; -+ PixmapPtr pixmap = private->pixmap; -+ RegionPtr copy_clip; -+ GCPtr gc; ++struct _dri_fence { ++ /** ++ * This is an ORed mask of DRM_BO_FLAG_READ, DRM_BO_FLAG_WRITE, and ++ * DRM_FLAG_EXE indicating the operations associated with this fence. ++ * ++ * It is constant for the life of the fence object. ++ */ ++ unsigned int type; ++ /** Buffer manager context associated with this fence */ ++ dri_bufmgr *bufmgr; ++}; + -+ gc = GetScratchGC(drawable->depth, pScreen); -+ copy_clip = REGION_CREATE(pScreen, NULL, 0); -+ REGION_COPY(pScreen, copy_clip, region); -+ (*gc->funcs->ChangeClip) (gc, CT_REGION, copy_clip, 0); -+ ValidateGC(drawable, gc); -+ (*gc->ops->CopyArea)(&pixmap->drawable, drawable, gc, -+ 0, 0, drawable->width, drawable->height, 0, 0); -+ FreeScratchGC(gc); -+ RADEONCPReleaseIndirect(pScrn); -+} ++/** ++ * Context for a buffer manager instance. ++ * ++ * Contains public methods followed by private storage for the buffer manager. ++ */ ++struct _dri_bufmgr { ++ /** ++ * Allocate a buffer object. ++ * ++ * Buffer objects are not necessarily initially mapped into CPU virtual ++ * address space or graphics device aperture. They must be mapped using ++ * bo_map() to be used by the CPU, and validated for use using bo_validate() ++ * to be used from the graphics device. ++ */ ++ dri_bo *(*bo_alloc)(dri_bufmgr *bufmgr_ctx, const char *name, ++ unsigned long size, unsigned int alignment, ++ uint64_t location_mask); + -+Bool -+radeon_dri2_screen_init(ScreenPtr pScreen) -+{ -+ ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; -+ RADEONInfoPtr info = RADEONPTR(pScrn); -+ DRI2InfoRec dri2_info; -+ int fd; -+ char *bus_id; -+ char *tmp_bus_id; -+ int cmp; -+ int i; ++ /** ++ * Allocates a buffer object for a static allocation. ++ * ++ * Static allocations are ones such as the front buffer that are offered by ++ * the X Server, which are never evicted and never moved. ++ */ ++ dri_bo *(*bo_alloc_static)(dri_bufmgr *bufmgr_ctx, const char *name, ++ unsigned long offset, unsigned long size, ++ void *virtual, uint64_t location_mask); + -+ if (!info->useEXA) { -+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "DRI2 requires EXA\n"); -+ return FALSE; -+ } ++ /** Takes a reference on a buffer object */ ++ void (*bo_reference)(dri_bo *bo); + -+ /* The whole drmOpen thing is a fiasco and we need to find a way -+ * back to just using open(2). For now, however, lets just make -+ * things worse with even more ad hoc directory walking code to -+ * discover the device file name. */ -+ bus_id = DRICreatePCIBusID(info->PciInfo); -+ for (i = 0; i < DRM_MAX_MINOR; i++) { -+ sprintf(info->dri2.device_name, DRM_DEV_NAME, DRM_DIR_NAME, i); -+ fd = open(info->dri2.device_name, O_RDWR); -+ if (fd < 0) -+ continue; ++ /** ++ * Releases a reference on a buffer object, freeing the data if ++ * rerefences remain. ++ */ ++ void (*bo_unreference)(dri_bo *bo); + -+ tmp_bus_id = drmGetBusid(fd); -+ close(fd); -+ if (tmp_bus_id == NULL) -+ continue; ++ /** ++ * Maps the buffer into userspace. ++ * ++ * This function will block waiting for any existing fence on the buffer to ++ * clear, first. The resulting mapping is available at buf->virtual. ++\ */ ++ int (*bo_map)(dri_bo *buf, int write_enable); + -+ cmp = strcmp(tmp_bus_id, bus_id); -+ drmFree(tmp_bus_id); -+ if (cmp == 0) -+ break; -+ } -+ xfree(bus_id); ++ /** Reduces the refcount on the userspace mapping of the buffer object. */ ++ int (*bo_unmap)(dri_bo *buf); + -+ if (i == DRM_MAX_MINOR) { -+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING, -+ "DRI2: failed to open drm device\n"); -+ return FALSE; -+ } ++ /** Takes a reference on a fence object */ ++ void (*fence_reference)(dri_fence *fence); + -+ if ( (info->ChipFamily >= CHIP_FAMILY_R300) ) { -+ dri2_info.driverName = R300_DRIVER_NAME; -+ } else if ( info->ChipFamily >= CHIP_FAMILY_R200 ) { -+ dri2_info.driverName = R200_DRIVER_NAME; -+ } else { -+ dri2_info.driverName = RADEON_DRIVER_NAME; -+ } -+ dri2_info.fd = info->dri2.drm_fd; -+ dri2_info.deviceName = info->dri2.device_name; -+ dri2_info.version = 1; -+ dri2_info.CreateBuffers = radeon_dri2_create_buffers; -+ dri2_info.DestroyBuffers = radeon_dri2_destroy_buffers; -+ dri2_info.CopyRegion = radeon_dri2_copy_region; -+ info->dri2.enabled = DRI2ScreenInit(pScreen, &dri2_info); -+ return info->dri2.enabled; -+} ++ /** ++ * Releases a reference on a fence object, freeing the data if ++ * rerefences remain. ++ */ ++ void (*fence_unreference)(dri_fence *fence); + -+void -+radeon_dri2_close_screen(ScreenPtr pScreen) -+{ -+ DRI2CloseScreen(pScreen); -+} ++ /** ++ * Blocks until the given fence is signaled. ++ */ ++ void (*fence_wait)(dri_fence *fence); + -+#endif -diff --git a/src/radeon_dri2.h b/src/radeon_dri2.h -new file mode 100644 -index 0000000..9ad9cee ---- /dev/null -+++ b/src/radeon_dri2.h -@@ -0,0 +1,42 @@ -+/* -+ * Copyright 2008 Jerome Glisse -+ * -+ * All Rights Reserved. -+ * -+ * Permission is hereby granted, free of charge, to any person obtaining -+ * a copy of this software and associated documentation files (the -+ * "Software"), to deal in the Software without restriction, including -+ * without limitation on the rights to use, copy, modify, merge, -+ * publish, distribute, sublicense, and/or sell copies of the Software, -+ * and to permit persons to whom the Software is furnished to do so, -+ * subject to the following conditions: -+ * -+ * The above copyright notice and this permission notice (including the -+ * next paragraph) shall be included in all copies or substantial -+ * portions of the Software. -+ * -+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -+ * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR -+ * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER -+ * DEALINGS IN THE SOFTWARE. -+ */ -+#ifndef RADEON_DRI2_H -+#define RADEON_DRI2_H ++ /** ++ * Tears down the buffer manager instance. ++ */ ++ void (*destroy)(dri_bufmgr *bufmgr); + -+struct radeon_dri2 { -+ int drm_fd; -+ Bool enabled; -+ char device_name[64]; -+}; ++ /** ++ * Add relocation entry in reloc_buf, which will be updated with the ++ * target buffer's real offset on on command submission. ++ * ++ * Relocations remain in place for the lifetime of the buffer object. ++ * ++ * \param reloc_buf Buffer to write the relocation into. ++ * \param flags BO flags to be used in validating the target buffer. ++ * Applicable flags include: ++ * - DRM_BO_FLAG_READ: The buffer will be read in the process of ++ * command execution. ++ * - DRM_BO_FLAG_WRITE: The buffer will be written in the process of ++ * command execution. ++ * - DRM_BO_FLAG_MEM_TT: The buffer should be validated in TT memory. ++ * - DRM_BO_FLAG_MEM_VRAM: The buffer should be validated in video ++ * memory. ++ * \param delta Constant value to be added to the relocation target's offset. ++ * \param offset Byte offset within batch_buf of the relocated pointer. ++ * \param target Buffer whose offset should be written into the relocation ++ * entry. ++ */ ++ int (*emit_reloc)(dri_bo *reloc_buf, uint64_t flags, uint32_t delta, ++ uint32_t offset, dri_bo *target); + -+#ifdef DRI2 -+#include "dri2.h" -+Bool radeon_dri2_screen_init(ScreenPtr pScreen); -+void radeon_dri2_close_screen(ScreenPtr pScreen); -+#endif ++ /** ++ * Processes the relocations, either in userland or by converting the list ++ * for use in batchbuffer submission. ++ * ++ * Kernel-based implementations will return a pointer to the arguments ++ * to be handed with batchbuffer submission to the kernel. The userland ++ * implementation performs the buffer validation and emits relocations ++ * into them the appopriate order. ++ * ++ * \param batch_buf buffer at the root of the tree of relocations ++ * \param count returns the number of buffers validated. ++ * \return relocation record for use in command submission. ++ * */ ++ void *(*process_relocs)(dri_bo *batch_buf, uint32_t *count); + -+#endif -diff --git a/src/radeon_dri_bufmgr.c b/src/radeon_dri_bufmgr.c -new file mode 100644 -index 0000000..f6154dc ---- /dev/null -+++ b/src/radeon_dri_bufmgr.c -@@ -0,0 +1,177 @@ -+/* -+ * Copyright © 2007 Intel Corporation -+ * -+ * Permission is hereby granted, free of charge, to any person obtaining a -+ * copy of this software and associated documentation files (the "Software"), -+ * to deal in the Software without restriction, including without limitation -+ * the rights to use, copy, modify, merge, publish, distribute, sublicense, -+ * and/or sell copies of the Software, and to permit persons to whom the -+ * Software is furnished to do so, subject to the following conditions: -+ * -+ * The above copyright notice and this permission notice (including the next -+ * paragraph) shall be included in all copies or substantial portions of the -+ * Software. -+ * -+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -+ * IN THE SOFTWARE. -+ * -+ * Authors: -+ * Eric Anholt -+ * -+ */ ++ void (*post_submit)(dri_bo *batch_buf, dri_fence **fence); + -+#include -+#include -+#include -+#include "radeon_dri_bufmgr.h" ++ int (*check_aperture_space)(struct radeon_space_check *bos, int num_bo); + -+/** @file dri_bufmgr.c -+ * -+ * Convenience functions for buffer management methods. -+ */ ++ int (*pin)(dri_bo *bo, int domain); ++ void (*unpin)(dri_bo *bo); + -+dri_bo * -+dri_bo_alloc(dri_bufmgr *bufmgr, const char *name, unsigned long size, -+ unsigned int alignment, uint64_t location_mask) -+{ -+ return bufmgr->bo_alloc(bufmgr, name, size, alignment, location_mask); -+} ++ uint32_t (*get_handle)(dri_bo *bo); ++ int debug; /**< Enables verbose debugging printouts */ ++}; + -+dri_bo * -+dri_bo_alloc_static(dri_bufmgr *bufmgr, const char *name, unsigned long offset, -+ unsigned long size, void *virtual, -+ uint64_t location_mask) -+{ -+ return bufmgr->bo_alloc_static(bufmgr, name, offset, size, virtual, -+ location_mask); -+} ++dri_bo *dri_bo_alloc(dri_bufmgr *bufmgr, const char *name, unsigned long size, ++ unsigned int alignment, uint64_t location_mask); ++dri_bo *dri_bo_alloc_static(dri_bufmgr *bufmgr, const char *name, ++ unsigned long offset, unsigned long size, ++ void *virtual, uint64_t location_mask); ++void dri_bo_reference(dri_bo *bo); ++void dri_bo_unreference(dri_bo *bo); ++int dri_bo_map(dri_bo *buf, int write_enable); ++int dri_bo_unmap(dri_bo *buf); ++void dri_fence_wait(dri_fence *fence); ++void dri_fence_reference(dri_fence *fence); ++void dri_fence_unreference(dri_fence *fence); + -+void -+dri_bo_reference(dri_bo *bo) -+{ -+ bo->bufmgr->bo_reference(bo); -+} ++void dri_bo_subdata(dri_bo *bo, unsigned long offset, ++ unsigned long size, const void *data); ++void dri_bo_get_subdata(dri_bo *bo, unsigned long offset, ++ unsigned long size, void *data); + -+void -+dri_bo_unreference(dri_bo *bo) -+{ -+ if (bo == NULL) -+ return; ++void dri_bufmgr_fake_contended_lock_take(dri_bufmgr *bufmgr); ++dri_bufmgr *dri_bufmgr_fake_init(unsigned long low_offset, void *low_virtual, ++ unsigned long size, ++ unsigned int (*fence_emit)(void *private), ++ int (*fence_wait)(void *private, ++ unsigned int cookie), ++ void *driver_priv); ++void dri_bufmgr_set_debug(dri_bufmgr *bufmgr, int enable_debug); ++void dri_bo_fake_disable_backing_store(dri_bo *bo, ++ void (*invalidate_cb)(dri_bo *bo, ++ void *ptr), ++ void *ptr); ++void dri_bufmgr_destroy(dri_bufmgr *bufmgr); ++ ++int dri_emit_reloc(dri_bo *reloc_buf, uint64_t flags, uint32_t delta, ++ uint32_t offset, dri_bo *target_buf); ++void *dri_process_relocs(dri_bo *batch_buf, uint32_t *count); ++void dri_post_process_relocs(dri_bo *batch_buf); ++void dri_post_submit(dri_bo *batch_buf, dri_fence **last_fence); ++int dri_bufmgr_check_aperture_space(struct radeon_space_check *bos, int num_bo); + -+ bo->bufmgr->bo_unreference(bo); -+} ++int dri_bo_pin(dri_bo *bo, int domain); ++void dri_bo_unpin(dri_bo *bo); + -+int -+dri_bo_map(dri_bo *buf, int write_enable) -+{ -+ return buf->bufmgr->bo_map(buf, write_enable); -+} ++uint32_t dri_bo_get_handle(dri_bo *bo); + -+int -+dri_bo_unmap(dri_bo *buf) -+{ -+ return buf->bufmgr->bo_unmap(buf); -+} ++#ifndef TTM_API ++/* reuse some TTM API */ + -+void -+dri_fence_wait(dri_fence *fence) -+{ -+ fence->bufmgr->fence_wait(fence); -+} ++#define DRM_BO_MEM_LOCAL 0 ++#define DRM_BO_MEM_TT 1 ++#define DRM_BO_MEM_VRAM 2 ++#define DRM_BO_MEM_PRIV0 3 ++#define DRM_BO_MEM_PRIV1 4 ++#define DRM_BO_MEM_PRIV2 5 ++#define DRM_BO_MEM_PRIV3 6 ++#define DRM_BO_MEM_PRIV4 7 + -+void -+dri_fence_reference(dri_fence *fence) -+{ -+ fence->bufmgr->fence_reference(fence); -+} ++#define DRM_BO_FLAG_READ (1ULL << 0) ++#define DRM_BO_FLAG_WRITE (1ULL << 1) ++#define DRM_BO_FLAG_EXE (1ULL << 2) ++#define DRM_BO_MASK_ACCESS (DRM_BO_FLAG_READ | DRM_BO_FLAG_WRITE | DRM_BO_FLAG_EXE) ++#define DRM_BO_FLAG_NO_EVICT (1ULL << 4) + -+void -+dri_fence_unreference(dri_fence *fence) -+{ -+ if (fence == NULL) -+ return; ++#define DRM_BO_FLAG_MAPPABLE (1ULL << 5) ++#define DRM_BO_FLAG_SHAREABLE (1ULL << 6) + -+ fence->bufmgr->fence_unreference(fence); -+} ++#define DRM_BO_FLAG_CACHED (1ULL << 7) + -+void -+dri_bo_subdata(dri_bo *bo, unsigned long offset, -+ unsigned long size, const void *data) -+{ -+ if (size == 0 || data == NULL) -+ return; ++#define DRM_BO_FLAG_NO_MOVE (1ULL << 8) ++#define DRM_BO_FLAG_CACHED_MAPPED (1ULL << 19) ++#define DRM_BO_FLAG_FORCE_CACHING (1ULL << 13) ++#define DRM_BO_FLAG_FORCE_MAPPABLE (1ULL << 14) ++#define DRM_BO_FLAG_TILE (1ULL << 15) + -+ dri_bo_map(bo, 1); -+ memcpy((unsigned char *)bo->virtual + offset, data, size); -+ dri_bo_unmap(bo); -+} ++#define DRM_BO_FLAG_MEM_LOCAL (1ULL << 24) ++#define DRM_BO_FLAG_MEM_TT (1ULL << 25) ++#define DRM_BO_FLAG_MEM_VRAM (1ULL << 26) + -+void -+dri_bo_get_subdata(dri_bo *bo, unsigned long offset, -+ unsigned long size, void *data) -+{ -+ if (size == 0 || data == NULL) -+ return; ++#define DRM_BO_MASK_MEM 0x00000000FF000000ULL + -+ dri_bo_map(bo, 0); -+ memcpy(data, (unsigned char *)bo->virtual + offset, size); -+ dri_bo_unmap(bo); -+} ++#define DRM_FENCE_TYPE_EXE 0x00000001 ++#endif + -+void -+dri_bufmgr_destroy(dri_bufmgr *bufmgr) -+{ -+ bufmgr->destroy(bufmgr); -+} ++#endif +diff -up xf86-video-ati-6.12.2/src/radeon_dri.c.modeset xf86-video-ati-6.12.2/src/radeon_dri.c +--- xf86-video-ati-6.12.2/src/radeon_dri.c.modeset 2009-03-16 13:50:31.000000000 -0400 ++++ xf86-video-ati-6.12.2/src/radeon_dri.c 2009-04-13 13:24:51.000000000 -0400 +@@ -40,6 +40,8 @@ + + #include + #include ++#include ++#include + + /* Driver data structures */ + #include "radeon.h" +@@ -53,6 +55,8 @@ + + #include "atipciids.h" + ++#include "radeon_drm.h" + + /* X and server generic header files */ + #include "xf86.h" + #include "xf86PciInfo.h" +@@ -70,16 +74,31 @@ static size_t radeon_drm_page_size; + extern void GlxSetVisualConfigs(int nconfigs, __GLXvisualConfig *configs, + void **configprivs); + ++#if defined(DAMAGE) && (DRIINFO_MAJOR_VERSION > 5 || \ ++ (DRIINFO_MAJOR_VERSION == 5 && DRIINFO_MINOR_VERSION >= 1)) ++#define DRI_SUPPORTS_CLIP_NOTIFY 1 ++#else ++#define DRI_SUPPORTS_CLIP_NOTIFY 0 ++#endif + -+int dri_emit_reloc(dri_bo *reloc_buf, uint64_t flags, uint32_t delta, -+ uint32_t offset, dri_bo *target_buf) -+{ -+ return reloc_buf->bufmgr->emit_reloc(reloc_buf, flags, delta, offset, target_buf); -+} ++#if (DRIINFO_MAJOR_VERSION > 5 || \ ++ (DRIINFO_MAJOR_VERSION == 5 && DRIINFO_MINOR_VERSION >= 4)) ++#define DRI_DRIVER_FRAMEBUFFER_MAP 1 ++#else ++#define DRI_DRIVER_FRAMEBUFFER_MAP 0 ++#endif + -+void *dri_process_relocs(dri_bo *batch_buf, uint32_t *count) -+{ -+ return batch_buf->bufmgr->process_relocs(batch_buf, count); -+} + static void RADEONDRITransitionTo2d(ScreenPtr pScreen); + static void RADEONDRITransitionTo3d(ScreenPtr pScreen); + static void RADEONDRITransitionMultiToSingle3d(ScreenPtr pScreen); + static void RADEONDRITransitionSingleToMulti3d(ScreenPtr pScreen); + ++static Bool radeon_dri_gart_init(ScreenPtr pScreen); + -+void dri_post_submit(dri_bo *batch_buf, dri_fence **last_fence) -+{ -+ batch_buf->bufmgr->post_submit(batch_buf, last_fence); -+} + #ifdef DAMAGE + static void RADEONDRIRefreshArea(ScrnInfoPtr pScrn, RegionPtr pReg); + +-#if (DRIINFO_MAJOR_VERSION > 5 || \ +- (DRIINFO_MAJOR_VERSION == 5 && DRIINFO_MINOR_VERSION >= 1)) ++#if DRI_SUPPORTS_CLIP_NOTIFY + static void RADEONDRIClipNotify(ScreenPtr pScreen, WindowPtr *ppWin, int num); + #endif + #endif +@@ -352,6 +371,111 @@ static void RADEONDestroyContext(ScreenP + #endif + } + + -+void -+dri_bufmgr_set_debug(dri_bufmgr *bufmgr, int enable_debug) ++uint32_t radeon_name_buffer(ScrnInfoPtr pScrn, struct radeon_memory *mem) +{ -+ bufmgr->debug = enable_debug; ++ RADEONInfoPtr info = RADEONPTR(pScrn); ++ struct drm_gem_flink flink; ++ int ret; ++ ++ if (mem && mem->kernel_bo_handle) { ++ if (!mem->kernel_name) { ++ flink.handle = mem->kernel_bo_handle; ++ ret = ioctl(info->dri->drmFD, DRM_IOCTL_GEM_FLINK, &flink); ++ if (ret != 0) { ++ xf86DrvMsg(pScrn->scrnIndex, X_ERROR, ++ "[drm] failed to name buffer %d\n", -errno); ++ return -1; ++ } ++ mem->kernel_name = flink.name; ++ } ++ return mem->kernel_name; ++ } ++ return -1; +} + -+int -+dri_bufmgr_check_aperture_space(struct radeon_space_check *bos, int num_bo) ++/* so we need to add a frontbuffer map no matter what */ ++#define ROUND_TO(x, y) (((x) + (y) - 1) / (y) * (y)) ++#define ROUND_TO_PAGE(x) ROUND_TO((x), radeon_drm_page_size) ++ ++static void ++radeon_update_screen_private(ScrnInfoPtr pScrn, drm_radeon_sarea_t * sarea) +{ -+ if (num_bo == 0) -+ return BUFMGR_SPACE_OK; ++ RADEONInfoPtr info = RADEONPTR(pScrn); ++ RADEONDRIPtr pRADEONDRI; + -+ return bos[0].buf->bufmgr->check_aperture_space(bos, num_bo); ++ pRADEONDRI = (RADEONDRIPtr)info->dri->pDRIInfo->devPrivate; ++ info->dri->pDRIInfo->frameBufferPhysicalAddress = (char *) info->LinearAddr; ++ info->dri->pDRIInfo->frameBufferStride = pScrn->displayWidth * info->CurrentLayout.pixel_bytes; ++ info->dri->pDRIInfo->frameBufferSize = ROUND_TO_PAGE(pScrn->displayWidth * pScrn->virtualY * info->CurrentLayout.pixel_bytes); ++#if DRI_DRIVER_FRAMEBUFFER_MAP ++ info->dri->pDRIInfo->hFrameBuffer = info->fb_map_handle; ++#endif ++ /* overload these */ ++ pRADEONDRI->gartTexHandle = radeon_name_buffer(pScrn, info->mm.gart_texture_buffer); ++ pRADEONDRI->textureOffset = radeon_name_buffer(pScrn, info->mm.texture_buffer); ++ pRADEONDRI->frontOffset = radeon_name_buffer(pScrn, info->mm.front_buffer); ++ pRADEONDRI->backOffset = radeon_name_buffer(pScrn, info->mm.back_buffer); ++ pRADEONDRI->depthOffset = radeon_name_buffer(pScrn, info->mm.depth_buffer); +} + -+int dri_bo_pin(dri_bo *bo, int domain) ++static Bool ++radeon_update_dri_mappings(ScrnInfoPtr pScrn, drm_radeon_sarea_t * sarea) +{ -+ return bo->bufmgr->pin(bo, domain); -+} ++ RADEONInfoPtr info = RADEONPTR(pScrn); ++ uint32_t fb_addr, fb_size; ++ int ret; + -+void dri_bo_unpin(dri_bo *bo) -+{ -+ bo->bufmgr->unpin(bo); -+} ++ if (!info->drm_mm) ++ return TRUE; + -+uint32_t dri_bo_get_handle(dri_bo *bo) -+{ -+ return bo->bufmgr->get_handle(bo); -+} -diff --git a/src/radeon_dri_bufmgr.h b/src/radeon_dri_bufmgr.h -new file mode 100644 -index 0000000..a19d7ec ---- /dev/null -+++ b/src/radeon_dri_bufmgr.h -@@ -0,0 +1,291 @@ -+/************************************************************************** -+ * -+ * Copyright � 2007 Intel Corporation -+ * Copyright 2006 Tungsten Graphics, Inc., Bismarck, ND., USA -+ * All Rights Reserved. -+ * -+ * Permission is hereby granted, free of charge, to any person obtaining a -+ * copy of this software and associated documentation files (the -+ * "Software"), to deal in the Software without restriction, including -+ * without limitation the rights to use, copy, modify, merge, publish, -+ * distribute, sub license, and/or sell copies of the Software, and to -+ * permit persons to whom the Software is furnished to do so, subject to -+ * the following conditions: -+ * -+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL -+ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, -+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR -+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE -+ * USE OR OTHER DEALINGS IN THE SOFTWARE. -+ * -+ * The above copyright notice and this permission notice (including the -+ * next paragraph) shall be included in all copies or substantial portions -+ * of the Software. -+ * -+ * -+ **************************************************************************/ -+/* -+ * Authors: Thomas Hellstr�m -+ * Keith Whitwell -+ * Eric Anholt -+ */ + -+#ifndef _DRI_BUFMGR_H_ -+#define _DRI_BUFMGR_H_ -+#include ++ fb_addr = info->mm.front_buffer->offset + info->LinearAddr; ++ fb_size = ROUND_TO_PAGE(pScrn->displayWidth * pScrn->virtualY * info->CurrentLayout.pixel_bytes); + -+typedef struct _dri_bufmgr dri_bufmgr; -+typedef struct _dri_bo dri_bo; -+typedef struct _dri_fence dri_fence; ++ if (info->fb_map_handle) { ++ drmRmMap(info->dri->drmFD, info->fb_map_handle); ++ info->fb_map_handle = 0; ++ } ++ ++ ret = drmAddMap(info->dri->drmFD, fb_addr, fb_size, DRM_FRAME_BUFFER, 0, ++ &info->fb_map_handle); + -+#define BUFMGR_SPACE_OK 0 -+#define BUFMGR_SPACE_OP_TO_BIG 1 -+#define BUFMGR_SPACE_FLUSH 2 -+struct radeon_space_check { -+ dri_bo *buf; -+ uint32_t read_domains; -+ uint32_t write_domain; -+ uint32_t new_accounted; -+}; ++ ErrorF("adding fb map from %x for %x ret %d %x\n", fb_addr, fb_size, ret, info->fb_map_handle); + -+/* reloc format */ -+/* gem handle, read_domains, write_domain, reloc_count */ -+#define RADEON_RELOC_SIZE 4 -+struct radeon_relocs_info { -+ uint32_t *buf; -+ dri_bo **bo_list; -+ int size; -+ int max_bo; -+ int num_reloc; -+}; ++ if (ret < 0) ++ return FALSE; + -+struct _dri_bo { -+ /** Size in bytes of the buffer object. */ -+ unsigned long size; -+ /** -+ * Card virtual address (offset from the beginning of the aperture) for the -+ * object. Only valid while validated. -+ */ -+ unsigned long offset; -+ /** -+ * Virtual address for accessing the buffer data. Only valid while mapped. -+ */ -+ void *virtual; -+ /** Buffer manager context associated with this buffer object */ -+ dri_bufmgr *bufmgr; -+}; ++ return TRUE; ++} + -+struct _dri_fence { -+ /** -+ * This is an ORed mask of DRM_BO_FLAG_READ, DRM_BO_FLAG_WRITE, and -+ * DRM_FLAG_EXE indicating the operations associated with this fence. -+ * -+ * It is constant for the life of the fence object. -+ */ -+ unsigned int type; -+ /** Buffer manager context associated with this fence */ -+ dri_bufmgr *bufmgr; -+}; ++Bool radeon_update_dri_buffers(ScreenPtr pScreen) ++{ ++ ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; ++ RADEONInfoPtr info = RADEONPTR(pScrn); ++ Bool success; ++ drm_radeon_sarea_t *sarea; + -+/** -+ * Context for a buffer manager instance. -+ * -+ * Contains public methods followed by private storage for the buffer manager. -+ */ -+struct _dri_bufmgr { -+ /** -+ * Allocate a buffer object. -+ * -+ * Buffer objects are not necessarily initially mapped into CPU virtual -+ * address space or graphics device aperture. They must be mapped using -+ * bo_map() to be used by the CPU, and validated for use using bo_validate() -+ * to be used from the graphics device. -+ */ -+ dri_bo *(*bo_alloc)(dri_bufmgr *bufmgr_ctx, const char *name, -+ unsigned long size, unsigned int alignment, -+ uint64_t location_mask); ++ if (info->ChipFamily >= CHIP_FAMILY_R600) ++ return TRUE; + -+ /** -+ * Allocates a buffer object for a static allocation. -+ * -+ * Static allocations are ones such as the front buffer that are offered by -+ * the X Server, which are never evicted and never moved. -+ */ -+ dri_bo *(*bo_alloc_static)(dri_bufmgr *bufmgr_ctx, const char *name, -+ unsigned long offset, unsigned long size, -+ void *virtual, uint64_t location_mask); ++ if (!info->drm_mm) ++ return TRUE; + -+ /** Takes a reference on a buffer object */ -+ void (*bo_reference)(dri_bo *bo); ++ if (info->dri2.enabled) ++ return TRUE; + -+ /** -+ * Releases a reference on a buffer object, freeing the data if -+ * rerefences remain. -+ */ -+ void (*bo_unreference)(dri_bo *bo); ++ sarea = DRIGetSAREAPrivate(pScreen); ++ success = radeon_update_dri_mappings(pScrn, sarea); + -+ /** -+ * Maps the buffer into userspace. -+ * -+ * This function will block waiting for any existing fence on the buffer to -+ * clear, first. The resulting mapping is available at buf->virtual. -+\ */ -+ int (*bo_map)(dri_bo *buf, int write_enable); ++ if (!success) ++ return FALSE; + -+ /** Reduces the refcount on the userspace mapping of the buffer object. */ -+ int (*bo_unmap)(dri_bo *buf); ++ radeon_update_sarea(pScrn, sarea); ++ radeon_update_screen_private(pScrn, sarea); ++ return TRUE; ++} + -+ /** Takes a reference on a fence object */ -+ void (*fence_reference)(dri_fence *fence); + /* Called when the X server is woken up to allow the last client's + * context to be saved and the X server's context to be loaded. This is + * not necessary for the Radeon since the client detects when it's +@@ -701,25 +825,35 @@ static void RADEONDRIInitGARTValues(RADE + + info->dri->gartOffset = 0; + +- /* Initialize the CP ring buffer data */ +- info->dri->ringStart = info->dri->gartOffset; +- info->dri->ringMapSize = info->dri->ringSize*1024*1024 + radeon_drm_page_size; +- info->dri->ringSizeLog2QW = RADEONMinBits(info->dri->ringSize*1024*1024/8)-1; +- +- info->dri->ringReadOffset = info->dri->ringStart + info->dri->ringMapSize; +- info->dri->ringReadMapSize = radeon_drm_page_size; +- +- /* Reserve space for vertex/indirect buffers */ +- info->dri->bufStart = info->dri->ringReadOffset + info->dri->ringReadMapSize; +- info->dri->bufMapSize = info->dri->bufSize*1024*1024; +- +- /* Reserve the rest for GART textures */ +- info->dri->gartTexStart = info->dri->bufStart + info->dri->bufMapSize; +- s = (info->dri->gartSize*1024*1024 - info->dri->gartTexStart); +- l = RADEONMinBits((s-1) / RADEON_NR_TEX_REGIONS); +- if (l < RADEON_LOG_TEX_GRANULARITY) l = RADEON_LOG_TEX_GRANULARITY; +- info->dri->gartTexMapSize = (s >> l) << l; +- info->dri->log2GARTTexGran = l; ++ if (!info->drm_mm) { ++ /* Initialize the CP ring buffer data */ ++ info->dri->ringStart = info->dri->gartOffset; ++ info->dri->ringMapSize = info->dri->ringSize*1024*1024 + radeon_drm_page_size; ++ info->dri->ringSizeLog2QW = RADEONMinBits(info->dri->ringSize*1024*1024/8)-1; + -+ /** -+ * Releases a reference on a fence object, freeing the data if -+ * rerefences remain. -+ */ -+ void (*fence_unreference)(dri_fence *fence); ++ info->dri->ringReadOffset = info->dri->ringStart + info->dri->ringMapSize; ++ info->dri->ringReadMapSize = radeon_drm_page_size; + -+ /** -+ * Blocks until the given fence is signaled. -+ */ -+ void (*fence_wait)(dri_fence *fence); ++ /* Reserve space for vertex/indirect buffers */ ++ info->dri->bufStart = info->dri->ringReadOffset + info->dri->ringReadMapSize; ++ info->dri->bufMapSize = info->dri->bufSize*1024*1024; + -+ /** -+ * Tears down the buffer manager instance. -+ */ -+ void (*destroy)(dri_bufmgr *bufmgr); ++ /* Reserve the rest for GART textures */ ++ info->dri->gartTexStart = info->dri->bufStart + info->dri->bufMapSize; ++ s = (info->dri->gartSize*1024*1024 - info->dri->gartTexStart); ++ l = RADEONMinBits((s-1) / RADEON_NR_TEX_REGIONS); ++ if (l < RADEON_LOG_TEX_GRANULARITY) l = RADEON_LOG_TEX_GRANULARITY; ++ info->dri->gartTexMapSize = (s >> l) << l; ++ info->dri->log2GARTTexGran = l; ++ } else { ++ s = (8*1024*1024); ++ l = RADEONMinBits((s-1) / RADEON_NR_TEX_REGIONS); ++ l = RADEONMinBits((s-1) / RADEON_NR_TEX_REGIONS); ++ if (l < RADEON_LOG_TEX_GRANULARITY) l = RADEON_LOG_TEX_GRANULARITY; ++ info->dri->gartTexMapSize = (s >> l) << l; ++ info->dri->log2GARTTexGran = l; ++ } + -+ /** -+ * Add relocation entry in reloc_buf, which will be updated with the -+ * target buffer's real offset on on command submission. -+ * -+ * Relocations remain in place for the lifetime of the buffer object. -+ * -+ * \param reloc_buf Buffer to write the relocation into. -+ * \param flags BO flags to be used in validating the target buffer. -+ * Applicable flags include: -+ * - DRM_BO_FLAG_READ: The buffer will be read in the process of -+ * command execution. -+ * - DRM_BO_FLAG_WRITE: The buffer will be written in the process of -+ * command execution. -+ * - DRM_BO_FLAG_MEM_TT: The buffer should be validated in TT memory. -+ * - DRM_BO_FLAG_MEM_VRAM: The buffer should be validated in video -+ * memory. -+ * \param delta Constant value to be added to the relocation target's offset. -+ * \param offset Byte offset within batch_buf of the relocated pointer. -+ * \param target Buffer whose offset should be written into the relocation -+ * entry. -+ */ -+ int (*emit_reloc)(dri_bo *reloc_buf, uint64_t flags, uint32_t delta, -+ uint32_t offset, dri_bo *target); + } + + /* AGP Mode Quirk List - Certain hostbridge/gfx-card combos don't work with +@@ -992,6 +1126,8 @@ static Bool RADEONDRIAgpInit(RADEONInfoP + "[agp] ring handle = 0x%08x\n", + (unsigned int)info->dri->ringHandle); + + -+ /** -+ * Processes the relocations, either in userland or by converting the list -+ * for use in batchbuffer submission. -+ * -+ * Kernel-based implementations will return a pointer to the arguments -+ * to be handed with batchbuffer submission to the kernel. The userland -+ * implementation performs the buffer validation and emits relocations -+ * into them the appopriate order. -+ * -+ * \param batch_buf buffer at the root of the tree of relocations -+ * \param count returns the number of buffers validated. -+ * \return relocation record for use in command submission. -+ * */ -+ void *(*process_relocs)(dri_bo *batch_buf, uint32_t *count); ++#if 0 + if (drmMap(info->dri->drmFD, info->dri->ringHandle, info->dri->ringMapSize, + &info->dri->ring) < 0) { + xf86DrvMsg(pScreen->myNum, X_ERROR, "[agp] Could not map ring\n"); +@@ -1000,9 +1136,10 @@ static Bool RADEONDRIAgpInit(RADEONInfoP + xf86DrvMsg(pScreen->myNum, X_INFO, + "[agp] Ring mapped at 0x%08lx\n", + (unsigned long)info->dri->ring); +- ++#endif + if (drmAddMap(info->dri->drmFD, info->dri->ringReadOffset, info->dri->ringReadMapSize, + DRM_AGP, DRM_READ_ONLY, &info->dri->ringReadPtrHandle) < 0) { + -+ void (*post_submit)(dri_bo *batch_buf, dri_fence **fence); + xf86DrvMsg(pScreen->myNum, X_ERROR, + "[agp] Could not add ring read ptr mapping\n"); + return FALSE; +@@ -1011,6 +1148,8 @@ static Bool RADEONDRIAgpInit(RADEONInfoP + "[agp] ring read ptr handle = 0x%08x\n", + (unsigned int)info->dri->ringReadPtrHandle); + + -+ int (*check_aperture_space)(struct radeon_space_check *bos, int num_bo); ++#if 0 + if (drmMap(info->dri->drmFD, info->dri->ringReadPtrHandle, info->dri->ringReadMapSize, + &info->dri->ringReadPtr) < 0) { + xf86DrvMsg(pScreen->myNum, X_ERROR, +@@ -1020,6 +1159,7 @@ static Bool RADEONDRIAgpInit(RADEONInfoP + xf86DrvMsg(pScreen->myNum, X_INFO, + "[agp] Ring read ptr mapped at 0x%08lx\n", + (unsigned long)info->dri->ringReadPtr); ++#endif + + if (drmAddMap(info->dri->drmFD, info->dri->bufStart, info->dri->bufMapSize, + DRM_AGP, 0, &info->dri->bufHandle) < 0) { +@@ -1097,6 +1237,7 @@ static Bool RADEONDRIPciInit(RADEONInfoP + "[pci] ring handle = 0x%08x\n", + (unsigned int)info->dri->ringHandle); + ++#if 0 + if (drmMap(info->dri->drmFD, info->dri->ringHandle, info->dri->ringMapSize, + &info->dri->ring) < 0) { + xf86DrvMsg(pScreen->myNum, X_ERROR, "[pci] Could not map ring\n"); +@@ -1108,6 +1249,7 @@ static Bool RADEONDRIPciInit(RADEONInfoP + xf86DrvMsg(pScreen->myNum, X_INFO, + "[pci] Ring contents 0x%08lx\n", + *(unsigned long *)(pointer)info->dri->ring); ++#endif + + if (drmAddMap(info->dri->drmFD, info->dri->ringReadOffset, info->dri->ringReadMapSize, + DRM_SCATTER_GATHER, flags, &info->dri->ringReadPtrHandle) < 0) { +@@ -1119,8 +1261,10 @@ static Bool RADEONDRIPciInit(RADEONInfoP + "[pci] ring read ptr handle = 0x%08x\n", + (unsigned int)info->dri->ringReadPtrHandle); + ++#if 0 + if (drmMap(info->dri->drmFD, info->dri->ringReadPtrHandle, info->dri->ringReadMapSize, + &info->dri->ringReadPtr) < 0) { + -+ int (*pin)(dri_bo *bo, int domain); -+ void (*unpin)(dri_bo *bo); + xf86DrvMsg(pScreen->myNum, X_ERROR, + "[pci] Could not map ring read ptr\n"); + return FALSE; +@@ -1131,6 +1275,7 @@ static Bool RADEONDRIPciInit(RADEONInfoP + xf86DrvMsg(pScreen->myNum, X_INFO, + "[pci] Ring read ptr contents 0x%08lx\n", + *(unsigned long *)(pointer)info->dri->ringReadPtr); ++#endif + + if (drmAddMap(info->dri->drmFD, info->dri->bufStart, info->dri->bufMapSize, + DRM_SCATTER_GATHER, 0, &info->dri->bufHandle) < 0) { +@@ -1183,6 +1328,9 @@ static Bool RADEONDRIPciInit(RADEONInfoP + */ + static Bool RADEONDRIMapInit(RADEONInfoPtr info, ScreenPtr pScreen) + { + -+ uint32_t (*get_handle)(dri_bo *bo); -+ int debug; /**< Enables verbose debugging printouts */ -+}; ++ if (info->drm_mm) ++ return TRUE; + /* Map registers */ + info->dri->registerSize = info->MMIOSize; + if (drmAddMap(info->dri->drmFD, info->MMIOAddr, info->dri->registerSize, +@@ -1223,20 +1371,23 @@ static int RADEONDRIKernelInit(RADEONInf + drmInfo.fb_bpp = info->CurrentLayout.pixel_code; + drmInfo.depth_bpp = (info->dri->depthBits - 8) * 2; + +- drmInfo.front_offset = info->dri->frontOffset; +- drmInfo.front_pitch = info->dri->frontPitch * cpp; +- drmInfo.back_offset = info->dri->backOffset; +- drmInfo.back_pitch = info->dri->backPitch * cpp; +- drmInfo.depth_offset = info->dri->depthOffset; +- drmInfo.depth_pitch = info->dri->depthPitch * drmInfo.depth_bpp / 8; +- +- drmInfo.fb_offset = info->dri->fbHandle; +- drmInfo.mmio_offset = info->dri->registerHandle; +- drmInfo.ring_offset = info->dri->ringHandle; +- drmInfo.ring_rptr_offset = info->dri->ringReadPtrHandle; +- drmInfo.buffers_offset = info->dri->bufHandle; +- drmInfo.gart_textures_offset= info->dri->gartTexHandle; +- ++ if (!info->drm_mm) { ++ drmInfo.front_offset = info->dri->frontOffset; ++ drmInfo.front_pitch = info->dri->frontPitch * cpp; ++ drmInfo.back_offset = info->dri->backOffset; ++ drmInfo.back_pitch = info->dri->backPitch * cpp; ++ drmInfo.depth_offset = info->dri->depthOffset; ++ drmInfo.depth_pitch = info->dri->depthPitch * drmInfo.depth_bpp / 8; + -+dri_bo *dri_bo_alloc(dri_bufmgr *bufmgr, const char *name, unsigned long size, -+ unsigned int alignment, uint64_t location_mask); -+dri_bo *dri_bo_alloc_static(dri_bufmgr *bufmgr, const char *name, -+ unsigned long offset, unsigned long size, -+ void *virtual, uint64_t location_mask); -+void dri_bo_reference(dri_bo *bo); -+void dri_bo_unreference(dri_bo *bo); -+int dri_bo_map(dri_bo *buf, int write_enable); -+int dri_bo_unmap(dri_bo *buf); -+void dri_fence_wait(dri_fence *fence); -+void dri_fence_reference(dri_fence *fence); -+void dri_fence_unreference(dri_fence *fence); ++ drmInfo.fb_offset = info->dri->fbHandle; ++ drmInfo.mmio_offset = info->dri->registerHandle; ++ drmInfo.ring_offset = info->dri->ringHandle; ++ drmInfo.ring_rptr_offset = info->dri->ringReadPtrHandle; ++ drmInfo.buffers_offset = info->dri->bufHandle; ++ drmInfo.gart_textures_offset= info->dri->gartTexHandle; ++ } else { ++ } ++ + if (drmCommandWrite(info->dri->drmFD, DRM_RADEON_CP_INIT, + &drmInfo, sizeof(drm_radeon_init_t)) < 0) + return FALSE; +@@ -1245,8 +1396,9 @@ static int RADEONDRIKernelInit(RADEONInf + * registers back to their default values, so we need to restore + * those engine register here. + */ +- if (info->ChipFamily < CHIP_FAMILY_R600) +- RADEONEngineRestore(pScrn); ++ if (!info->drm_mm) ++ if (info->ChipFamily < CHIP_FAMILY_R600) ++ RADEONEngineRestore(pScrn); + + return TRUE; + } +@@ -1444,12 +1596,11 @@ Bool RADEONDRIGetVersion(ScrnInfoPtr pSc + + /* Get DRM version & close DRM */ + info->dri->pKernelDRMVersion = drmGetVersion(fd); +- drmClose(fd); + if (info->dri->pKernelDRMVersion == NULL) { + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, + "[dri] RADEONDRIGetVersion failed to get the DRM version\n" + "[dri] Disabling DRI.\n"); +- return FALSE; ++ goto fail; + } + + /* Now check if we qualify */ +@@ -1483,10 +1634,27 @@ Bool RADEONDRIGetVersion(ScrnInfoPtr pSc + req_patch); + drmFreeVersion(info->dri->pKernelDRMVersion); + info->dri->pKernelDRMVersion = NULL; +- return FALSE; ++ goto fail; ++ } + -+void dri_bo_subdata(dri_bo *bo, unsigned long offset, -+ unsigned long size, const void *data); -+void dri_bo_get_subdata(dri_bo *bo, unsigned long offset, -+ unsigned long size, void *data); ++ if (info->dri->pKernelDRMVersion->version_minor >= 30) { ++ struct drm_radeon_gem_info mminfo; + -+void dri_bufmgr_fake_contended_lock_take(dri_bufmgr *bufmgr); -+dri_bufmgr *dri_bufmgr_fake_init(unsigned long low_offset, void *low_virtual, -+ unsigned long size, -+ unsigned int (*fence_emit)(void *private), -+ int (*fence_wait)(void *private, -+ unsigned int cookie), -+ void *driver_priv); -+void dri_bufmgr_set_debug(dri_bufmgr *bufmgr, int enable_debug); -+void dri_bo_fake_disable_backing_store(dri_bo *bo, -+ void (*invalidate_cb)(dri_bo *bo, -+ void *ptr), -+ void *ptr); -+void dri_bufmgr_destroy(dri_bufmgr *bufmgr); ++ if (!drmCommandWriteRead(fd, DRM_RADEON_GEM_INFO, &mminfo, sizeof(mminfo))) ++ { ++ info->drm_mm = TRUE; ++ info->mm.vram_size = mminfo.vram_size; ++ info->mm.gart_size = mminfo.gart_size; ++ ErrorF("initing %llx %llx %llx %llx\n", ++ mminfo.gart_size, mminfo.vram_size); ++ } + } + ++ drmClose(fd); + return TRUE; ++fail: ++ drmClose(fd); ++ return FALSE; + } + + Bool RADEONDRISetVBlankInterrupt(ScrnInfoPtr pScrn, Bool on) +@@ -1495,6 +1663,9 @@ Bool RADEONDRISetVBlankInterrupt(ScrnInf + xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); + int value = 0; + ++ if (info->drm_mode_setting) ++ return TRUE; + -+int dri_emit_reloc(dri_bo *reloc_buf, uint64_t flags, uint32_t delta, -+ uint32_t offset, dri_bo *target_buf); -+void *dri_process_relocs(dri_bo *batch_buf, uint32_t *count); -+void dri_post_process_relocs(dri_bo *batch_buf); -+void dri_post_submit(dri_bo *batch_buf, dri_fence **last_fence); -+int dri_bufmgr_check_aperture_space(struct radeon_space_check *bos, int num_bo); + if (!info->want_vblank_interrupts) + on = FALSE; + +@@ -1514,6 +1685,52 @@ Bool RADEONDRISetVBlankInterrupt(ScrnInf + return TRUE; + } + ++Bool RADEONDRIDoMappings(ScreenPtr pScreen) ++{ ++ ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; ++ RADEONInfoPtr info = RADEONPTR(pScrn); ++ drm_radeon_sarea_t * pSAREAPriv = DRIGetSAREAPrivate(pScreen); ++ /* DRIScreenInit doesn't add all the ++ * common mappings. Add additional ++ * mappings here. ++ */ + -+int dri_bo_pin(dri_bo *bo, int domain); -+void dri_bo_unpin(dri_bo *bo); ++ if (info->ChipFamily >= CHIP_FAMILY_R600) ++ return TRUE; + -+uint32_t dri_bo_get_handle(dri_bo *bo); ++ if (info->dri2.enabled) ++ return TRUE; + -+#ifndef TTM_API -+/* reuse some TTM API */ ++ pSAREAPriv = DRIGetSAREAPrivate(pScreen); ++ if (!RADEONDRIMapInit(info, pScreen)) { ++ RADEONDRICloseScreen(pScreen); ++ return FALSE; ++ } ++ ++ radeon_update_sarea(pScrn, pSAREAPriv); ++ ++ /* DRIScreenInit adds the frame buffer ++ map, but we need it as well */ ++ { ++ void *scratch_ptr; ++ int scratch_int; + -+#define DRM_BO_MEM_LOCAL 0 -+#define DRM_BO_MEM_TT 1 -+#define DRM_BO_MEM_VRAM 2 -+#define DRM_BO_MEM_PRIV0 3 -+#define DRM_BO_MEM_PRIV1 4 -+#define DRM_BO_MEM_PRIV2 5 -+#define DRM_BO_MEM_PRIV3 6 -+#define DRM_BO_MEM_PRIV4 7 ++ DRIGetDeviceInfo(pScreen, &info->dri->fbHandle, ++ &scratch_int, &scratch_int, ++ &scratch_int, &scratch_int, ++ &scratch_ptr); ++ } + -+#define DRM_BO_FLAG_READ (1ULL << 0) -+#define DRM_BO_FLAG_WRITE (1ULL << 1) -+#define DRM_BO_FLAG_EXE (1ULL << 2) -+#define DRM_BO_MASK_ACCESS (DRM_BO_FLAG_READ | DRM_BO_FLAG_WRITE | DRM_BO_FLAG_EXE) -+#define DRM_BO_FLAG_NO_EVICT (1ULL << 4) ++ /* FIXME: When are these mappings unmapped? */ + -+#define DRM_BO_FLAG_MAPPABLE (1ULL << 5) -+#define DRM_BO_FLAG_SHAREABLE (1ULL << 6) ++ if (!RADEONInitVisualConfigs(pScreen)) { ++ RADEONDRICloseScreen(pScreen); ++ return FALSE; ++ } ++ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "[dri] Visual configs initialized\n"); ++ return TRUE; + -+#define DRM_BO_FLAG_CACHED (1ULL << 7) ++} + + /* Initialize the screen-specific data structures for the DRI and the + * Radeon. This is the main entry point to the device-specific +@@ -1577,10 +1794,22 @@ Bool RADEONDRIScreenInit(ScreenPtr pScre + pDRIInfo->ddxDriverMajorVersion = info->allowColorTiling ? 5 : 4; + pDRIInfo->ddxDriverMinorVersion = 3; + pDRIInfo->ddxDriverPatchVersion = 0; +- pDRIInfo->frameBufferPhysicalAddress = (void *)info->LinearAddr + info->dri->frontOffset; +- pDRIInfo->frameBufferSize = info->FbMapSize - info->FbSecureSize; +- pDRIInfo->frameBufferStride = (pScrn->displayWidth * +- info->CurrentLayout.pixel_bytes); + -+#define DRM_BO_FLAG_NO_MOVE (1ULL << 8) -+#define DRM_BO_FLAG_CACHED_MAPPED (1ULL << 19) -+#define DRM_BO_FLAG_FORCE_CACHING (1ULL << 13) -+#define DRM_BO_FLAG_FORCE_MAPPABLE (1ULL << 14) -+#define DRM_BO_FLAG_TILE (1ULL << 15) ++#if DRI_DRIVER_FRAMEBUFFER_MAP ++ if (info->drm_mm) { ++ pDRIInfo->frameBufferPhysicalAddress = 0; ++ pDRIInfo->frameBufferSize = 0; ++ pDRIInfo->frameBufferStride = 0; ++ pDRIInfo->dontMapFrameBuffer = TRUE; ++ } else ++#endif ++ { ++ pDRIInfo->frameBufferPhysicalAddress = (void *)info->LinearAddr + info->dri->frontOffset; ++ pDRIInfo->frameBufferSize = info->FbMapSize - info->FbSecureSize; ++ pDRIInfo->frameBufferStride = (pScrn->displayWidth * ++ info->CurrentLayout.pixel_bytes); ++ } + -+#define DRM_BO_FLAG_MEM_LOCAL (1ULL << 24) -+#define DRM_BO_FLAG_MEM_TT (1ULL << 25) -+#define DRM_BO_FLAG_MEM_VRAM (1ULL << 26) + pDRIInfo->ddxDrawableTableEntry = RADEON_MAX_DRAWABLES; + pDRIInfo->maxDrawableTableEntry = (SAREA_MAX_DRAWABLES + < RADEON_MAX_DRAWABLES +@@ -1633,9 +1862,7 @@ Bool RADEONDRIScreenInit(ScreenPtr pScre + pDRIInfo->TransitionTo3d = RADEONDRITransitionTo3d; + pDRIInfo->TransitionSingleToMulti3D = RADEONDRITransitionSingleToMulti3d; + pDRIInfo->TransitionMultiToSingle3D = RADEONDRITransitionMultiToSingle3d; +-#if defined(DAMAGE) && (DRIINFO_MAJOR_VERSION > 5 || \ +- (DRIINFO_MAJOR_VERSION == 5 && \ +- DRIINFO_MINOR_VERSION >= 1)) ++#if DRI_SUPPORT_CLIP_NOTIFY + pDRIInfo->ClipNotify = RADEONDRIClipNotify; + #endif + +@@ -1667,57 +1894,60 @@ Bool RADEONDRIScreenInit(ScreenPtr pScre + pDRIInfo = NULL; + return FALSE; + } +- /* Initialize AGP */ +- if (info->cardType==CARD_AGP && !RADEONDRIAgpInit(info, pScreen)) { +- xf86DrvMsg(pScreen->myNum, X_ERROR, +- "[agp] AGP failed to initialize. Disabling the DRI.\n" ); +- xf86DrvMsg(pScreen->myNum, X_INFO, +- "[agp] You may want to make sure the agpgart kernel " +- "module\nis loaded before the radeon kernel module.\n"); +- RADEONDRICloseScreen(pScreen); +- return FALSE; +- } +- +- /* Initialize PCI */ +- if ((info->cardType!=CARD_AGP) && !RADEONDRIPciInit(info, pScreen)) { +- xf86DrvMsg(pScreen->myNum, X_ERROR, +- "[pci] PCI failed to initialize. Disabling the DRI.\n" ); +- RADEONDRICloseScreen(pScreen); +- return FALSE; +- } +- +- /* DRIScreenInit doesn't add all the +- * common mappings. Add additional +- * mappings here. +- */ +- if (!RADEONDRIMapInit(info, pScreen)) { +- RADEONDRICloseScreen(pScreen); +- return FALSE; +- } +- +- /* DRIScreenInit adds the frame buffer +- map, but we need it as well */ +- { +- void *scratch_ptr; +- int scratch_int; + +- DRIGetDeviceInfo(pScreen, &info->dri->fbHandle, +- &scratch_int, &scratch_int, +- &scratch_int, &scratch_int, +- &scratch_ptr); +- } ++ /* Now, nuke dri.c's dummy frontbuffer map setup if we did that. */ ++ if (pDRIInfo->frameBufferSize != 0 && info->drm_mm) { ++ int tmp; ++ drm_handle_t fb_handle; ++ void *ptmp; + +- /* FIXME: When are these mappings unmapped? */ ++ /* With the compat method, it will continue to report ++ * the wrong map out of GetDeviceInfo, which will break AIGLX. ++ */ ++ DRIGetDeviceInfo(pScreen, &fb_handle, &tmp, &tmp, &tmp, &tmp, &ptmp); ++ drmRmMap(info->dri->drmFD, fb_handle); + +- if (!RADEONInitVisualConfigs(pScreen)) { +- RADEONDRICloseScreen(pScreen); +- return FALSE; ++ xf86DrvMsg(pScrn->scrnIndex, X_WARNING, ++ "Removed DRI frontbuffer mapping in compatibility mode.\n"); ++ xf86DrvMsg(pScrn->scrnIndex, X_WARNING, ++ "DRIGetDeviceInfo will report incorrect frontbuffer " ++ "handle.\n"); ++ } ++ ++ if (info->drm_mm) { ++ int ret; ++ ret = radeon_dri_gart_init(pScreen); ++ if (!ret) { ++ xf86DrvMsg(pScreen->myNum, X_ERROR, ++ "[gart] GART failed to initialize. Disabling the DRI.\n" ); ++ RADEONDRICloseScreen(pScreen); ++ return FALSE; ++ } ++ } else { ++ if (info->cardType==CARD_AGP && !RADEONDRIAgpInit(info, pScreen)) { ++ /* Initialize AGP */ ++ xf86DrvMsg(pScreen->myNum, X_ERROR, ++ "[agp] AGP failed to initialize. Disabling the DRI.\n" ); ++ xf86DrvMsg(pScreen->myNum, X_INFO, ++ "[agp] You may want to make sure the agpgart kernel " ++ "module\nis loaded before the radeon kernel module.\n"); ++ RADEONDRICloseScreen(pScreen); ++ return FALSE; ++ } ++ ++ /* Initialize PCI */ ++ if ((info->cardType!=CARD_AGP) && !RADEONDRIPciInit(info, pScreen)) { ++ xf86DrvMsg(pScreen->myNum, X_ERROR, ++ "[pci] PCI failed to initialize. Disabling the DRI.\n" ); ++ RADEONDRICloseScreen(pScreen); ++ return FALSE; ++ } + } +- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "[dri] Visual configs initialized\n"); + + return TRUE; + } + + -+#define DRM_BO_MASK_MEM 0x00000000FF000000ULL + static Bool RADEONDRIDoCloseScreen(int scrnIndex, ScreenPtr pScreen) + { + ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; +@@ -1759,17 +1989,21 @@ Bool RADEONDRIFinishScreenInit(ScreenPtr + return FALSE; + } + +- /* Initialize the vertex buffers list */ +- if (!RADEONDRIBufInit(info, pScreen)) { +- RADEONDRICloseScreen(pScreen); +- return FALSE; ++ if (!info->drm_mm) { ++ /* Initialize the vertex buffers list */ ++ if (!RADEONDRIBufInit(info, pScreen)) { ++ RADEONDRICloseScreen(pScreen); ++ return FALSE; ++ } + } + +- /* Initialize IRQ */ +- RADEONDRIIrqInit(info, pScreen); ++ if (!info->drm_mode_setting) { ++ /* Initialize IRQ */ ++ RADEONDRIIrqInit(info, pScreen); ++ /* Initialize kernel GART memory manager */ ++ RADEONDRIGartHeapInit(info, pScreen); ++ } + +- /* Initialize kernel GART memory manager */ +- RADEONDRIGartHeapInit(info, pScreen); + + /* Initialize and start the CP if required */ + RADEONDRICPInit(pScrn); +@@ -1778,6 +2012,10 @@ Bool RADEONDRIFinishScreenInit(ScreenPtr + pSAREAPriv = (drm_radeon_sarea_t*)DRIGetSAREAPrivate(pScreen); + memset(pSAREAPriv, 0, sizeof(*pSAREAPriv)); + ++ if (info->drm_mm) { ++ /* init the handles into the sarea */ ++ ++ } + pRADEONDRI = (RADEONDRIPtr)info->dri->pDRIInfo->devPrivate; + + pRADEONDRI->deviceID = info->Chipset; +@@ -1935,6 +2173,8 @@ void RADEONDRICloseScreen(ScreenPtr pScr + drmUnmap(info->dri->buf, info->dri->bufMapSize); + info->dri->buf = NULL; + } + -+#define DRM_FENCE_TYPE_EXE 0x00000001 ++#if 0 + if (info->dri->ringReadPtr) { + drmUnmap(info->dri->ringReadPtr, info->dri->ringReadMapSize); + info->dri->ringReadPtr = NULL; +@@ -1943,6 +2183,7 @@ void RADEONDRICloseScreen(ScreenPtr pScr + drmUnmap(info->dri->ring, info->dri->ringMapSize); + info->dri->ring = NULL; + } +#endif + if (info->dri->agpMemHandle != DRM_AGP_NO_HANDLE) { + drmAgpUnbind(info->dri->drmFD, info->dri->agpMemHandle); + drmAgpFree(info->dri->drmFD, info->dri->agpMemHandle); +@@ -2352,3 +2593,11 @@ int RADEONDRISetParam(ScrnInfoPtr pScrn, + &radeonsetparam, sizeof(drm_radeon_setparam_t)); + return ret; + } + -+#endif -diff --git a/src/radeon_driver.c b/src/radeon_driver.c -index 8673f5e..1c9d5d9 100644 ---- a/src/radeon_driver.c -+++ b/src/radeon_driver.c ++static Bool radeon_dri_gart_init(ScreenPtr pScreen) ++{ ++ ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; ++ RADEONInfoPtr info = RADEONPTR(pScrn); ++ ++ RADEONDRIInitGARTValues(info); ++} +diff -up xf86-video-ati-6.12.2/src/radeon_driver.c.modeset xf86-video-ati-6.12.2/src/radeon_driver.c +--- xf86-video-ati-6.12.2/src/radeon_driver.c.modeset 2009-04-06 10:50:11.000000000 -0400 ++++ xf86-video-ati-6.12.2/src/radeon_driver.c 2009-04-13 13:24:51.000000000 -0400 @@ -67,7 +67,7 @@ #include @@ -4041,7 +3767,7 @@ index 8673f5e..1c9d5d9 100644 /* Driver data structures */ #include "radeon.h" #include "radeon_reg.h" -@@ -229,7 +229,10 @@ radeonShadowWindow(ScreenPtr screen, CARD32 row, CARD32 offset, int mode, +@@ -229,7 +229,10 @@ radeonShadowWindow(ScreenPtr screen, CAR stride = (pScrn->displayWidth * pScrn->bitsPerPixel) / 8; *size = stride; @@ -4053,7 +3779,7 @@ index 8673f5e..1c9d5d9 100644 } static Bool RADEONCreateScreenResources (ScreenPtr pScreen) -@@ -250,6 +253,13 @@ RADEONCreateScreenResources (ScreenPtr pScreen) +@@ -250,6 +253,13 @@ RADEONCreateScreenResources (ScreenPtr p radeonShadowWindow, 0, NULL)) return FALSE; } @@ -4067,7 +3793,7 @@ index 8673f5e..1c9d5d9 100644 return TRUE; } -@@ -1695,6 +1705,7 @@ static Bool RADEONPreInitVRAM(ScrnInfoPtr pScrn) +@@ -1695,6 +1705,7 @@ static Bool RADEONPreInitVRAM(ScrnInfoPt } pScrn->videoRam &= ~1023; @@ -4075,7 +3801,7 @@ index 8673f5e..1c9d5d9 100644 info->FbMapSize = pScrn->videoRam * 1024; /* if the card is PCI Express reserve the last 32k for the gart table */ -@@ -1824,59 +1835,61 @@ static Bool RADEONPreInitChipType(ScrnInfoPtr pScrn) +@@ -1824,59 +1835,61 @@ static Bool RADEONPreInitChipType(ScrnIn "R500 support is under development. Please report any issues to xorg-driver-ati@lists.x.org\n"); } @@ -4182,7 +3908,7 @@ index 8673f5e..1c9d5d9 100644 #ifdef XF86DRI /* AGP/PCI */ -@@ -2051,6 +2064,15 @@ static Bool RADEONPreInitAccel(ScrnInfoPtr pScrn) +@@ -2051,6 +2064,15 @@ static Bool RADEONPreInitAccel(ScrnInfoP } info->accel_state->fifo_slots = 0; @@ -4198,7 +3924,7 @@ index 8673f5e..1c9d5d9 100644 if ((info->ChipFamily == CHIP_FAMILY_RS100) || (info->ChipFamily == CHIP_FAMILY_RS200) || (info->ChipFamily == CHIP_FAMILY_RS300) || -@@ -2075,6 +2097,9 @@ static Bool RADEONPreInitAccel(ScrnInfoPtr pScrn) +@@ -2075,6 +2097,9 @@ static Bool RADEONPreInitAccel(ScrnInfoP if (!xf86ReturnOptValBool(info->Options, OPTION_NOACCEL, FALSE)) { int errmaj = 0, errmin = 0; @@ -4208,7 +3934,7 @@ index 8673f5e..1c9d5d9 100644 from = X_DEFAULT; #if defined(USE_EXA) #if defined(USE_XAA) -@@ -2085,6 +2110,7 @@ static Bool RADEONPreInitAccel(ScrnInfoPtr pScrn) +@@ -2085,6 +2110,7 @@ static Bool RADEONPreInitAccel(ScrnInfoP info->useEXA = TRUE; } else if (xf86NameCmp(optstr, "XAA") == 0) { from = X_CONFIG; @@ -4216,7 +3942,7 @@ index 8673f5e..1c9d5d9 100644 } } #else /* USE_XAA */ -@@ -2189,15 +2215,9 @@ static Bool RADEONPreInitInt10(ScrnInfoPtr pScrn, xf86Int10InfoPtr *ppInt10) +@@ -2189,15 +2215,9 @@ static Bool RADEONPreInitInt10(ScrnInfoP return TRUE; } @@ -4233,7 +3959,7 @@ index 8673f5e..1c9d5d9 100644 if (!(info->dri = xcalloc(1, sizeof(struct radeon_dri)))) { xf86DrvMsg(pScrn->scrnIndex, X_ERROR,"Unable to allocate dri rec!\n"); -@@ -2208,6 +2228,22 @@ static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn) +@@ -2208,6 +2228,22 @@ static Bool RADEONPreInitDRI(ScrnInfoPtr xf86DrvMsg(pScrn->scrnIndex, X_ERROR,"Unable to allocate cp rec!\n"); return FALSE; } @@ -4256,7 +3982,7 @@ index 8673f5e..1c9d5d9 100644 info->cp->CPInUse = FALSE; info->cp->CPStarted = FALSE; info->cp->CPusecTimeout = RADEON_DEFAULT_CP_TIMEOUT; -@@ -2771,6 +2807,37 @@ static const xf86CrtcConfigFuncsRec RADEONCRTCResizeFuncs = { +@@ -2771,6 +2807,37 @@ static const xf86CrtcConfigFuncsRec RADE RADEONCRTCResize }; @@ -4294,7 +4020,7 @@ index 8673f5e..1c9d5d9 100644 Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) { xf86CrtcConfigPtr xf86_config; -@@ -2791,6 +2858,8 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) +@@ -2791,6 +2858,8 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, in info = RADEONPTR(pScrn); info->MMIO = NULL; @@ -4303,7 +4029,7 @@ index 8673f5e..1c9d5d9 100644 info->IsSecondary = FALSE; info->IsPrimary = FALSE; -@@ -2825,62 +2894,63 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) +@@ -2825,62 +2894,63 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, in } info->PciInfo = xf86GetPciInfoForEntity(info->pEnt->index); @@ -4414,7 +4140,7 @@ index 8673f5e..1c9d5d9 100644 if (xf86RegisterResources(info->pEnt->index, 0, ResExclusive)) goto fail; -@@ -2890,10 +2960,12 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) +@@ -2890,10 +2960,12 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, in pScrn->racMemFlags = RAC_FB | RAC_COLORMAP | RAC_VIEWPORT | RAC_CURSOR; pScrn->monitor = pScrn->confScreen->monitor; @@ -4431,7 +4157,7 @@ index 8673f5e..1c9d5d9 100644 if (!RADEONPreInitVisual(pScrn)) goto fail; -@@ -2907,167 +2979,225 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) +@@ -2907,167 +2979,225 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, in memcpy(info->Options, RADEONOptions, sizeof(RADEONOptions)); xf86ProcessOptions(pScrn->scrnIndex, pScrn->options, info->Options); @@ -4503,7 +4229,8 @@ index 8673f5e..1c9d5d9 100644 - if (!RADEONPreInitChipType(pScrn)) - goto fail; -- ++ goto fail; + - if (!RADEONPreInitInt10(pScrn, &pInt10)) - goto fail; - @@ -4511,8 +4238,6 @@ index 8673f5e..1c9d5d9 100644 - - if (!RADEONPreInitBIOS(pScrn, pInt10)) - goto fail; -+ goto fail; -+ + if (!info->drm_mode_setting) { + info->DispPriority = 1; + if ((s = xf86GetOptValString(info->Options, OPTION_DISP_PRIORITY))) { @@ -4719,7 +4444,9 @@ index 8673f5e..1c9d5d9 100644 + char *bus_id; + if (!radeon_alloc_dri(pScrn)) + return FALSE; -+ + +- for (i = 0; i < xf86_config->num_output; i++) { +- xf86OutputPtr output = xf86_config->output[i]; + bus_id = DRICreatePCIBusID(info->PciInfo); + if (drmmode_pre_init(pScrn, &info->drmmode, bus_id, "radeon", pScrn->bitsPerPixel / 8) == FALSE) { + xfree(bus_id); @@ -4734,7 +4461,10 @@ index 8673f5e..1c9d5d9 100644 + + { + struct drm_radeon_gem_info mminfo; -+ + +- /* XXX: double check crtc mode */ +- if ((output->probed_modes != NULL) && (output->crtc == NULL)) +- output->crtc = xf86_config->crtc[0]; + if (!drmCommandWriteRead(info->dri->drmFD, DRM_RADEON_GEM_INFO, &mminfo, sizeof(mminfo))) + { + info->mm.vram_size = mminfo.vram_visible; @@ -4745,16 +4475,11 @@ index 8673f5e..1c9d5d9 100644 + { + struct drm_radeon_getparam gp; + int value; - -- for (i = 0; i < xf86_config->num_output; i++) { -- xf86OutputPtr output = xf86_config->output[i]; ++ + memset(&gp, 0, sizeof(gp)); + gp.param = RADEON_PARAM_FB_LOCATION; + gp.value = &value; - -- /* XXX: double check crtc mode */ -- if ((output->probed_modes != NULL) && (output->crtc == NULL)) -- output->crtc = xf86_config->crtc[0]; ++ + if (drmCommandWriteRead(info->dri->drmFD, DRM_RADEON_GETPARAM, &gp, + sizeof(gp)) < 0) { + goto fail; @@ -4786,7 +4511,7 @@ index 8673f5e..1c9d5d9 100644 /* Get ScreenInit function */ if (!xf86LoadSubModule(pScrn, "fb")) return FALSE; -@@ -3082,10 +3212,12 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) +@@ -3082,10 +3212,12 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, in if (!RADEONPreInitXv(pScrn)) goto fail; } @@ -4803,7 +4528,7 @@ index 8673f5e..1c9d5d9 100644 } if (pScrn->modes == NULL) { -@@ -3238,6 +3370,9 @@ static void RADEONBlockHandler(int i, pointer blockData, +@@ -3238,6 +3370,9 @@ static void RADEONBlockHandler(int i, po #ifdef USE_EXA info->accel_state->engineMode = EXA_ENGINEMODE_UNKNOWN; @@ -4813,7 +4538,7 @@ index 8673f5e..1c9d5d9 100644 #endif } -@@ -3326,7 +3461,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3326,7 +3461,7 @@ Bool RADEONScreenInit(int scrnIndex, Scr int subPixelOrder = SubPixelUnknown; char* s; #endif @@ -4822,7 +4547,7 @@ index 8673f5e..1c9d5d9 100644 info->accelOn = FALSE; #ifdef USE_XAA -@@ -3346,58 +3481,61 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3346,58 +3481,61 @@ Bool RADEONScreenInit(int scrnIndex, Scr "RADEONScreenInit %lx %ld\n", pScrn->memPhysBase, pScrn->fbOffset); #endif @@ -4923,7 +4648,7 @@ index 8673f5e..1c9d5d9 100644 /* Visual setup */ miClearVisualTypes(); if (!miSetVisualTypes(pScrn->depth, -@@ -3431,19 +3569,21 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3431,19 +3569,21 @@ Bool RADEONScreenInit(int scrnIndex, Scr hasDRI = info->directRenderingEnabled; #endif /* XF86DRI */ @@ -4957,7 +4682,7 @@ index 8673f5e..1c9d5d9 100644 } } -@@ -3480,7 +3620,10 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3480,7 +3620,10 @@ Bool RADEONScreenInit(int scrnIndex, Scr #ifdef XF86DRI if (hasDRI) { info->accelDFS = xf86ReturnOptValBool(info->Options, OPTION_ACCEL_DFS, @@ -4969,7 +4694,7 @@ index 8673f5e..1c9d5d9 100644 /* Reserve approx. half of offscreen memory for local textures by * default, can be overridden with Option "FBTexPercent". -@@ -3506,7 +3649,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3506,7 +3649,7 @@ Bool RADEONScreenInit(int scrnIndex, Scr #endif #if defined(XF86DRI) && defined(USE_XAA) @@ -4978,7 +4703,7 @@ index 8673f5e..1c9d5d9 100644 info->dri->textureSize = -1; if (xf86GetOptValInteger(info->Options, OPTION_FBTEX_PERCENT, &(info->dri->textureSize))) { -@@ -3524,7 +3667,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3524,7 +3667,7 @@ Bool RADEONScreenInit(int scrnIndex, Scr #endif #ifdef USE_XAA @@ -4987,7 +4712,7 @@ index 8673f5e..1c9d5d9 100644 return FALSE; #endif -@@ -3545,7 +3688,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3545,7 +3688,7 @@ Bool RADEONScreenInit(int scrnIndex, Scr info->CurrentLayout.pixel_bytes); int maxy = info->FbMapSize / width_bytes; @@ -4996,7 +4721,7 @@ index 8673f5e..1c9d5d9 100644 xf86DrvMsg(scrnIndex, X_ERROR, "Static buffer allocation failed. Disabling DRI.\n"); xf86DrvMsg(scrnIndex, X_ERROR, -@@ -3555,19 +3698,54 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3555,19 +3698,54 @@ Bool RADEONScreenInit(int scrnIndex, Scr info->CurrentLayout.pixel_bytes * 3 + 1023) / 1024); info->directRenderingEnabled = FALSE; } else { @@ -5055,7 +4780,7 @@ index 8673f5e..1c9d5d9 100644 #endif xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, "Initializing fb layer\n"); -@@ -3591,7 +3769,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3591,7 +3769,7 @@ Bool RADEONScreenInit(int scrnIndex, Scr if (info->r600_shadow_fb == FALSE) { /* Init fb layer */ @@ -5064,7 +4789,7 @@ index 8673f5e..1c9d5d9 100644 pScrn->virtualX, pScrn->virtualY, pScrn->xDpi, pScrn->yDpi, pScrn->displayWidth, pScrn->bitsPerPixel)) -@@ -3633,8 +3811,10 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3633,8 +3811,10 @@ Bool RADEONScreenInit(int scrnIndex, Scr /* restore the memory map here otherwise we may get a hang when * initializing the drm below */ @@ -5077,7 +4802,7 @@ index 8673f5e..1c9d5d9 100644 /* Backing store setup */ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, -@@ -3644,7 +3824,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3644,7 +3824,7 @@ Bool RADEONScreenInit(int scrnIndex, Scr /* DRI finalisation */ #ifdef XF86DRI @@ -5086,7 +4811,7 @@ index 8673f5e..1c9d5d9 100644 info->dri->pKernelDRMVersion->version_minor >= 19) { if (RADEONDRISetParam(pScrn, RADEON_SETPARAM_PCIGART_LOCATION, info->dri->pciGartOffset) < 0) -@@ -3660,14 +3840,24 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3660,14 +3840,24 @@ Bool RADEONScreenInit(int scrnIndex, Scr if (info->directRenderingEnabled) { xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, "DRI Finishing init !\n"); @@ -5112,7 +4837,7 @@ index 8673f5e..1c9d5d9 100644 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Direct rendering enabled\n"); -@@ -3763,10 +3953,16 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3763,10 +3953,16 @@ Bool RADEONScreenInit(int scrnIndex, Scr return FALSE; } } @@ -5122,15 +4847,15 @@ index 8673f5e..1c9d5d9 100644 - if (!xf86SetDesiredModes (pScrn)) + if (info->drm_mode_setting) { + if (!drmmode_set_desired_modes(pScrn, &info->drmmode)) - return FALSE; ++ return FALSE; + } else { + if (!xf86SetDesiredModes (pScrn)) -+ return FALSE; + return FALSE; + } /* Provide SaveScreen & wrap BlockHandler and CloseScreen */ /* Wrap CloseScreen */ -@@ -5336,7 +5532,7 @@ Bool RADEONSwitchMode(int scrnIndex, DisplayModePtr mode, int flags) +@@ -5336,7 +5532,7 @@ Bool RADEONSwitchMode(int scrnIndex, Dis #ifdef XF86DRI Bool CPStarted = info->cp->CPStarted; @@ -5139,7 +4864,7 @@ index 8673f5e..1c9d5d9 100644 DRILock(pScrn->pScreen, 0); RADEONCP_STOP(pScrn, info); } -@@ -5359,8 +5555,10 @@ Bool RADEONSwitchMode(int scrnIndex, DisplayModePtr mode, int flags) +@@ -5359,8 +5555,10 @@ Bool RADEONSwitchMode(int scrnIndex, Dis #endif } @@ -5152,7 +4877,7 @@ index 8673f5e..1c9d5d9 100644 ret = xf86SetSingleMode (pScrn, mode, RR_Rotate_0); -@@ -5372,16 +5570,19 @@ Bool RADEONSwitchMode(int scrnIndex, DisplayModePtr mode, int flags) +@@ -5372,16 +5570,19 @@ Bool RADEONSwitchMode(int scrnIndex, Dis /* xf86SetRootClip would do, but can't access that here */ } @@ -5180,7 +4905,7 @@ index 8673f5e..1c9d5d9 100644 } #endif -@@ -5579,6 +5780,11 @@ void RADEONAdjustFrame(int scrnIndex, int x, int y, int flags) +@@ -5579,6 +5780,11 @@ void RADEONAdjustFrame(int scrnIndex, in xf86OutputPtr output = config->output[config->compat_output]; xf86CrtcPtr crtc = output->crtc; @@ -5192,7 +4917,7 @@ index 8673f5e..1c9d5d9 100644 /* not handled */ if (IS_AVIVO_VARIANT) return; -@@ -5618,76 +5824,100 @@ Bool RADEONEnterVT(int scrnIndex, int flags) +@@ -5618,76 +5824,100 @@ Bool RADEONEnterVT(int scrnIndex, int fl xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, "RADEONEnterVT\n"); @@ -5207,7 +4932,12 @@ index 8673f5e..1c9d5d9 100644 + rhdAtomASICInit(info->atomBIOS); + } else { + xf86Int10InfoPtr pInt; -+ + +- pInt = xf86InitInt10 (info->pEnt->index); +- if (pInt) { +- pInt->num = 0xe6; +- xf86ExecX86int10 (pInt); +- xf86FreeInt10 (pInt); + pInt = xf86InitInt10 (info->pEnt->index); + if (pInt) { + pInt->num = 0xe6; @@ -5221,12 +4951,7 @@ index 8673f5e..1c9d5d9 100644 + } + /* Makes sure the engine is idle before doing anything */ + RADEONWaitForIdleMMIO(pScrn); - -- pInt = xf86InitInt10 (info->pEnt->index); -- if (pInt) { -- pInt->num = 0xe6; -- xf86ExecX86int10 (pInt); -- xf86FreeInt10 (pInt); ++ + if (info->IsMobility && !IS_AVIVO_VARIANT) { + if (xf86ReturnOptValBool(info->Options, OPTION_DYNAMIC_CLOCKS, FALSE)) { + RADEONSetDynamicClock(pScrn, 1); @@ -5343,7 +5068,7 @@ index 8673f5e..1c9d5d9 100644 } #endif /* this will get XVideo going again, but only if XVideo was initialised -@@ -5702,7 +5932,7 @@ Bool RADEONEnterVT(int scrnIndex, int flags) +@@ -5702,7 +5932,7 @@ Bool RADEONEnterVT(int scrnIndex, int fl info->accel_state->XInited3D = FALSE; #ifdef XF86DRI @@ -5352,7 +5077,7 @@ index 8673f5e..1c9d5d9 100644 if (info->ChipFamily >= CHIP_FAMILY_R600) R600LoadShaders(pScrn); RADEONCP_START(pScrn, info); -@@ -5726,27 +5956,29 @@ void RADEONLeaveVT(int scrnIndex, int flags) +@@ -5726,27 +5956,29 @@ void RADEONLeaveVT(int scrnIndex, int fl xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, "RADEONLeaveVT\n"); #ifdef XF86DRI @@ -5398,7 +5123,7 @@ index 8673f5e..1c9d5d9 100644 /* Make sure 3D clients will re-upload textures to video RAM */ if (info->dri->textureSize) { -@@ -5762,6 +5994,11 @@ void RADEONLeaveVT(int scrnIndex, int flags) +@@ -5762,6 +5994,11 @@ void RADEONLeaveVT(int scrnIndex, int fl i = list[i].next; } while (i != 0); } @@ -5410,7 +5135,7 @@ index 8673f5e..1c9d5d9 100644 } #endif -@@ -5788,10 +6025,17 @@ void RADEONLeaveVT(int scrnIndex, int flags) +@@ -5788,10 +6025,17 @@ void RADEONLeaveVT(int scrnIndex, int fl xf86_hide_cursors (pScrn); @@ -5431,7 +5156,7 @@ index 8673f5e..1c9d5d9 100644 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, "Ok, leaving now...\n"); -@@ -5845,7 +6089,8 @@ static Bool RADEONCloseScreen(int scrnIndex, ScreenPtr pScreen) +@@ -5845,7 +6089,8 @@ static Bool RADEONCloseScreen(int scrnIn #endif /* USE_XAA */ if (pScrn->vtSema) { @@ -5441,7 +5166,7 @@ index 8673f5e..1c9d5d9 100644 } xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, -@@ -5880,6 +6125,11 @@ static Bool RADEONCloseScreen(int scrnIndex, ScreenPtr pScreen) +@@ -5880,6 +6125,11 @@ static Bool RADEONCloseScreen(int scrnIn info->DGAModes = NULL; xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, "Unmapping memory\n"); @@ -5453,10 +5178,9 @@ index 8673f5e..1c9d5d9 100644 RADEONUnmapMem(pScrn); pScrn->vtSema = FALSE; -diff --git a/src/radeon_drm.h b/src/radeon_drm.h -index 54bc234..843cfe8 100644 ---- a/src/radeon_drm.h -+++ b/src/radeon_drm.h +diff -up xf86-video-ati-6.12.2/src/radeon_drm.h.modeset xf86-video-ati-6.12.2/src/radeon_drm.h +--- xf86-video-ati-6.12.2/src/radeon_drm.h.modeset 2008-12-01 17:20:59.000000000 -0500 ++++ xf86-video-ati-6.12.2/src/radeon_drm.h 2009-04-13 13:24:51.000000000 -0400 @@ -303,7 +303,8 @@ typedef union { #define RADEON_INDEX_PRIM_OFFSET 20 @@ -5613,7 +5337,7 @@ index 54bc234..843cfe8 100644 } drm_radeon_mem_alloc_t; typedef struct drm_radeon_mem_free { -@@ -715,7 +734,7 @@ typedef struct drm_radeon_mem_init_heap { +@@ -715,7 +734,7 @@ typedef struct drm_radeon_mem_init_heap /* 1.6: Userspace can request & wait on irq's: */ typedef struct drm_radeon_irq_emit { @@ -5743,10 +5467,9 @@ index 54bc234..843cfe8 100644 +}; + #endif -diff --git a/src/radeon_exa.c b/src/radeon_exa.c -index ae68146..d98b654 100644 ---- a/src/radeon_exa.c -+++ b/src/radeon_exa.c +diff -up xf86-video-ati-6.12.2/src/radeon_exa.c.modeset xf86-video-ati-6.12.2/src/radeon_exa.c +--- xf86-video-ati-6.12.2/src/radeon_exa.c.modeset 2009-02-27 11:25:10.000000000 -0500 ++++ xf86-video-ati-6.12.2/src/radeon_exa.c 2009-04-13 13:24:51.000000000 -0400 @@ -44,7 +44,7 @@ #include "radeon_version.h" @@ -5756,7 +5479,7 @@ index ae68146..d98b654 100644 /***********************************************************************/ #define RINFO_FROM_SCREEN(pScr) ScrnInfoPtr pScrn = xf86Screens[pScr->myNum]; \ -@@ -182,12 +182,25 @@ Bool RADEONGetPixmapOffsetPitch(PixmapPtr pPix, uint32_t *pitch_offset) +@@ -182,12 +182,25 @@ Bool RADEONGetPixmapOffsetPitch(PixmapPt RINFO_FROM_SCREEN(pPix->drawable.pScreen); uint32_t pitch, offset; int bpp; @@ -5811,7 +5534,7 @@ index ae68146..d98b654 100644 static Bool RADEONPrepareAccess(PixmapPtr pPix, int index) { RINFO_FROM_SCREEN(pPix->drawable.pScreen); -@@ -231,7 +261,31 @@ static Bool RADEONPrepareAccess(PixmapPtr pPix, int index) +@@ -231,7 +261,31 @@ static Bool RADEONPrepareAccess(PixmapPt uint32_t offset = exaGetPixmapOffset(pPix); int bpp, soff; uint32_t size, flags; @@ -5819,7 +5542,7 @@ index ae68146..d98b654 100644 + + driver_priv = exaGetPixmapDriverPrivate(pPix); + if (driver_priv) { - ++ + if (driver_priv->bo) { + int ret; + @@ -5838,12 +5561,12 @@ index ae68146..d98b654 100644 + pPix->devPrivate.ptr = driver_priv->bo->virtual; + } + } -+ + +#if X_BYTE_ORDER == X_BIG_ENDIAN /* Front buffer is always set with proper swappers */ if (offset == 0) return TRUE; -@@ -287,6 +341,7 @@ static Bool RADEONPrepareAccess(PixmapPtr pPix, int index) +@@ -287,6 +341,7 @@ static Bool RADEONPrepareAccess(PixmapPt OUTREG(RADEON_SURFACE0_LOWER_BOUND + soff, offset); OUTREG(RADEON_SURFACE0_UPPER_BOUND + soff, offset + size - 1); swapper_surfaces[index] = offset; @@ -5851,25 +5574,25 @@ index ae68146..d98b654 100644 return TRUE; } -@@ -296,7 +351,17 @@ static void RADEONFinishAccess(PixmapPtr pPix, int index) +@@ -296,7 +351,17 @@ static void RADEONFinishAccess(PixmapPtr unsigned char *RADEONMMIO = info->MMIO; uint32_t offset = exaGetPixmapOffset(pPix); int soff; + struct radeon_exa_pixmap_priv *driver_priv; + + driver_priv = exaGetPixmapDriverPrivate(pPix); - ++ + if (driver_priv) { + dri_bo_unmap(driver_priv->bo); + pPix->devPrivate.ptr = NULL; + } + -+ + +#if X_BYTE_ORDER == X_BIG_ENDIAN /* Front buffer is always set with proper swappers */ if (offset == 0) return; -@@ -319,9 +384,152 @@ static void RADEONFinishAccess(PixmapPtr pPix, int index) +@@ -319,9 +384,152 @@ static void RADEONFinishAccess(PixmapPtr OUTREG(RADEON_SURFACE0_LOWER_BOUND + soff, 0); OUTREG(RADEON_SURFACE0_UPPER_BOUND + soff, 0); swapper_surfaces[index] = 0; @@ -6023,7 +5746,7 @@ index ae68146..d98b654 100644 #define ENTER_DRAW(x) TRACE #define LEAVE_DRAW(x) TRACE -@@ -332,6 +540,7 @@ static void RADEONFinishAccess(PixmapPtr pPix, int index) +@@ -332,6 +540,7 @@ static void RADEONFinishAccess(PixmapPtr #define BEGIN_ACCEL(n) RADEONWaitForFifo(pScrn, (n)) #define OUT_ACCEL_REG(reg, val) OUTREG(reg, val) #define OUT_ACCEL_REG_F(reg, val) OUTREG(reg, F_TO_DW(val)) @@ -6031,7 +5754,7 @@ index ae68146..d98b654 100644 #define FINISH_ACCEL() #ifdef RENDER -@@ -345,6 +554,7 @@ static void RADEONFinishAccess(PixmapPtr pPix, int index) +@@ -345,6 +554,7 @@ static void RADEONFinishAccess(PixmapPtr #undef OUT_ACCEL_REG #undef OUT_ACCEL_REG_F #undef FINISH_ACCEL @@ -6039,7 +5762,7 @@ index ae68146..d98b654 100644 #ifdef XF86DRI -@@ -355,6 +565,7 @@ static void RADEONFinishAccess(PixmapPtr pPix, int index) +@@ -355,6 +565,7 @@ static void RADEONFinishAccess(PixmapPtr #define BEGIN_ACCEL(n) BEGIN_RING(2*(n)) #define OUT_ACCEL_REG(reg, val) OUT_RING_REG(reg, val) #define FINISH_ACCEL() ADVANCE_RING() @@ -6047,7 +5770,7 @@ index ae68146..d98b654 100644 #define OUT_RING_F(x) OUT_RING(F_TO_DW(x)) -@@ -372,6 +583,8 @@ static void RADEONFinishAccess(PixmapPtr pPix, int index) +@@ -372,6 +583,8 @@ static void RADEONFinishAccess(PixmapPtr #endif /* XF86DRI */ @@ -6056,7 +5779,7 @@ index ae68146..d98b654 100644 /* * Once screen->off_screen_base is set, this function * allocates the remaining memory appropriately -@@ -393,122 +606,126 @@ Bool RADEONSetupMemEXA (ScreenPtr pScreen) +@@ -393,122 +606,126 @@ Bool RADEONSetupMemEXA (ScreenPtr pScree if (info->accel_state->exa == NULL) return FALSE; @@ -6235,7 +5958,9 @@ index ae68146..d98b654 100644 - info->dri->textureSize *= (info->accel_state->exa->memorySize - - info->accel_state->exa->offScreenBase) / 100; -- ++ info->dri->textureSize *= (info->accel_state->exa->memorySize - ++ info->accel_state->exa->offScreenBase) / 100; + - l = RADEONLog2(info->dri->textureSize / RADEON_NR_TEX_REGIONS); - if (l < RADEON_LOG_TEX_GRANULARITY) - l = RADEON_LOG_TEX_GRANULARITY; @@ -6251,9 +5976,6 @@ index ae68146..d98b654 100644 - info->dri->textureSize = 0; - } - } else -+ info->dri->textureSize *= (info->accel_state->exa->memorySize - -+ info->accel_state->exa->offScreenBase) / 100; -+ + l = RADEONLog2(info->dri->textureSize / RADEON_NR_TEX_REGIONS); + if (l < RADEON_LOG_TEX_GRANULARITY) + l = RADEON_LOG_TEX_GRANULARITY; @@ -6292,12 +6014,15 @@ index ae68146..d98b654 100644 unsigned long long offset; - exaMoveInPixmap(pPix); - ExaOffscreenMarkUsed(pPix); -- -- offset = exaGetPixmapOffset(pPix); + struct radeon_exa_pixmap_priv *driver_priv; -+ + +- offset = exaGetPixmapOffset(pPix); + driver_priv = exaGetPixmapDriverPrivate(pPix); -+ + +- if (offset > info->FbMapSize) +- return ~0ULL; +- else +- return info->fbLocation + offset; + if (driver_priv) { + //offset = dri_bo_get_handle(driver_priv->bo); + offset = driver_priv->bo->offset; @@ -6310,19 +6035,14 @@ index ae68146..d98b654 100644 + offset += info->fbLocation; + ExaOffscreenMarkUsed(pPix); + } - -- if (offset > info->FbMapSize) -- return ~0ULL; -- else -- return info->fbLocation + offset; ++ + return offset; } #endif -diff --git a/src/radeon_exa_funcs.c b/src/radeon_exa_funcs.c -index 59cb46f..8d6f085 100644 ---- a/src/radeon_exa_funcs.c -+++ b/src/radeon_exa_funcs.c -@@ -74,21 +74,73 @@ FUNC_NAME(RADEONSync)(ScreenPtr pScreen, int marker) +diff -up xf86-video-ati-6.12.2/src/radeon_exa_funcs.c.modeset xf86-video-ati-6.12.2/src/radeon_exa_funcs.c +--- xf86-video-ati-6.12.2/src/radeon_exa_funcs.c.modeset 2009-04-07 11:19:33.000000000 -0400 ++++ xf86-video-ati-6.12.2/src/radeon_exa_funcs.c 2009-04-13 13:24:51.000000000 -0400 +@@ -74,21 +74,73 @@ FUNC_NAME(RADEONSync)(ScreenPtr pScreen, ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; RADEONInfoPtr info = RADEONPTR(pScrn); @@ -6397,7 +6117,7 @@ index 59cb46f..8d6f085 100644 ACCEL_PREAMBLE(); TRACE; -@@ -97,25 +149,58 @@ FUNC_NAME(RADEONPrepareSolid)(PixmapPtr pPix, int alu, Pixel pm, Pixel fg) +@@ -97,25 +149,58 @@ FUNC_NAME(RADEONPrepareSolid)(PixmapPtr RADEON_FALLBACK(("24bpp unsupported\n")); if (!RADEONGetDatatypeBpp(pPix->drawable.bitsPerPixel, &datatype)) RADEON_FALLBACK(("RADEONGetDatatypeBpp failed\n")); @@ -6471,7 +6191,7 @@ index 59cb46f..8d6f085 100644 return TRUE; } -@@ -146,6 +231,7 @@ FUNC_NAME(RADEONDoneSolid)(PixmapPtr pPix) +@@ -146,6 +231,7 @@ FUNC_NAME(RADEONDoneSolid)(PixmapPtr pPi TRACE; @@ -6479,7 +6199,7 @@ index 59cb46f..8d6f085 100644 BEGIN_ACCEL(2); OUT_ACCEL_REG(RADEON_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL); OUT_ACCEL_REG(RADEON_WAIT_UNTIL, -@@ -153,6 +239,7 @@ FUNC_NAME(RADEONDoneSolid)(PixmapPtr pPix) +@@ -153,6 +239,7 @@ FUNC_NAME(RADEONDoneSolid)(PixmapPtr pPi FINISH_ACCEL(); } @@ -6487,7 +6207,7 @@ index 59cb46f..8d6f085 100644 void FUNC_NAME(RADEONDoPrepareCopy)(ScrnInfoPtr pScrn, uint32_t src_pitch_offset, uint32_t dst_pitch_offset, uint32_t datatype, int rop, -@@ -163,23 +250,28 @@ FUNC_NAME(RADEONDoPrepareCopy)(ScrnInfoPtr pScrn, uint32_t src_pitch_offset, +@@ -163,23 +250,28 @@ FUNC_NAME(RADEONDoPrepareCopy)(ScrnInfoP RADEON_SWITCH_TO_2D(); @@ -6533,7 +6253,7 @@ index 59cb46f..8d6f085 100644 } static Bool -@@ -190,9 +282,46 @@ FUNC_NAME(RADEONPrepareCopy)(PixmapPtr pSrc, PixmapPtr pDst, +@@ -190,9 +282,46 @@ FUNC_NAME(RADEONPrepareCopy)(PixmapPtr p { RINFO_FROM_SCREEN(pDst->drawable.pScreen); uint32_t datatype, src_pitch_offset, dst_pitch_offset; @@ -6581,7 +6301,7 @@ index 59cb46f..8d6f085 100644 info->accel_state->xdir = xdir; info->accel_state->ydir = ydir; -@@ -200,10 +329,11 @@ FUNC_NAME(RADEONPrepareCopy)(PixmapPtr pSrc, PixmapPtr pDst, +@@ -200,10 +329,11 @@ FUNC_NAME(RADEONPrepareCopy)(PixmapPtr p RADEON_FALLBACK(("24bpp unsupported")); if (!RADEONGetDatatypeBpp(pDst->drawable.bitsPerPixel, &datatype)) RADEON_FALLBACK(("RADEONGetDatatypeBpp failed\n")); @@ -6595,7 +6315,7 @@ index 59cb46f..8d6f085 100644 FUNC_NAME(RADEONDoPrepareCopy)(pScrn, src_pitch_offset, dst_pitch_offset, datatype, rop, planemask); -@@ -251,6 +381,7 @@ FUNC_NAME(RADEONDoneCopy)(PixmapPtr pDst) +@@ -251,6 +381,7 @@ FUNC_NAME(RADEONDoneCopy)(PixmapPtr pDst TRACE; @@ -6603,7 +6323,7 @@ index 59cb46f..8d6f085 100644 BEGIN_ACCEL(2); OUT_ACCEL_REG(RADEON_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL); OUT_ACCEL_REG(RADEON_WAIT_UNTIL, -@@ -267,17 +398,27 @@ RADEONUploadToScreenCP(PixmapPtr pDst, int x, int y, int w, int h, +@@ -267,17 +398,27 @@ RADEONUploadToScreenCP(PixmapPtr pDst, i { RINFO_FROM_SCREEN(pDst->drawable.pScreen); unsigned int bpp = pDst->drawable.bitsPerPixel; @@ -6634,7 +6354,7 @@ index 59cb46f..8d6f085 100644 int cpp = bpp / 8; ACCEL_PREAMBLE(); -@@ -297,20 +438,26 @@ RADEONUploadToScreenCP(PixmapPtr pDst, int x, int y, int w, int h, +@@ -297,20 +438,26 @@ RADEONUploadToScreenCP(PixmapPtr pDst, i exaMarkSync(pDst->drawable.pScreen); return TRUE; } @@ -6664,7 +6384,7 @@ index 59cb46f..8d6f085 100644 OUT_ACCEL_REG(RADEON_DP_GUI_MASTER_CNTL, RADEON_GMC_DST_PITCH_OFFSET_CNTL | RADEON_GMC_SRC_PITCH_OFFSET_CNTL | -@@ -321,8 +468,14 @@ RADEONBlitChunk(ScrnInfoPtr pScrn, uint32_t datatype, uint32_t src_pitch_offset, +@@ -321,8 +468,14 @@ RADEONBlitChunk(ScrnInfoPtr pScrn, uint3 RADEON_DP_SRC_SOURCE_MEMORY | RADEON_GMC_CLR_CMP_CNTL_DIS | RADEON_GMC_WR_MSK_DIS); @@ -6679,7 +6399,7 @@ index 59cb46f..8d6f085 100644 OUT_ACCEL_REG(RADEON_SRC_Y_X, (srcY << 16) | srcX); OUT_ACCEL_REG(RADEON_DST_Y_X, (dstY << 16) | dstX); OUT_ACCEL_REG(RADEON_DST_HEIGHT_WIDTH, (h << 16) | w); -@@ -334,6 +487,173 @@ RADEONBlitChunk(ScrnInfoPtr pScrn, uint32_t datatype, uint32_t src_pitch_offset, +@@ -334,6 +487,173 @@ RADEONBlitChunk(ScrnInfoPtr pScrn, uint3 FINISH_ACCEL(); } @@ -6853,7 +6573,7 @@ index 59cb46f..8d6f085 100644 static Bool RADEONDownloadFromScreenCP(PixmapPtr pSrc, int x, int y, int w, int h, -@@ -347,12 +667,17 @@ RADEONDownloadFromScreenCP(PixmapPtr pSrc, int x, int y, int w, int h, +@@ -347,12 +667,17 @@ RADEONDownloadFromScreenCP(PixmapPtr pSr TRACE; @@ -6872,7 +6592,7 @@ index 59cb46f..8d6f085 100644 RADEONGetPixmapOffsetPitch(pSrc, &src_pitch_offset) && (scratch = RADEONCPGetBuffer(pScrn))) { -@@ -367,7 +692,8 @@ RADEONDownloadFromScreenCP(PixmapPtr pSrc, int x, int y, int w, int h, +@@ -367,7 +692,8 @@ RADEONDownloadFromScreenCP(PixmapPtr pSr RADEON_SWITCH_TO_2D(); /* Kick the first blit as early as possible */ @@ -6882,7 +6602,7 @@ index 59cb46f..8d6f085 100644 x, y, 0, 0, w, hpass); FLUSH_RING(); -@@ -394,7 +720,8 @@ RADEONDownloadFromScreenCP(PixmapPtr pSrc, int x, int y, int w, int h, +@@ -394,7 +720,8 @@ RADEONDownloadFromScreenCP(PixmapPtr pSr /* Prepare next blit if anything's left */ if (hpass) { scratch_off = scratch->total/2 - scratch_off; @@ -6892,7 +6612,7 @@ index 59cb46f..8d6f085 100644 x, y, 0, 0, w, hpass); } -@@ -473,10 +800,8 @@ Bool FUNC_NAME(RADEONDrawInit)(ScreenPtr pScreen) +@@ -473,10 +800,8 @@ Bool FUNC_NAME(RADEONDrawInit)(ScreenPtr info->accel_state->exa->DownloadFromScreen = RADEONDownloadFromScreenCP; #endif @@ -6903,7 +6623,7 @@ index 59cb46f..8d6f085 100644 info->accel_state->exa->flags = EXA_OFFSCREEN_PIXMAPS; #ifdef EXA_SUPPORTS_PREPARE_AUX -@@ -485,6 +810,11 @@ Bool FUNC_NAME(RADEONDrawInit)(ScreenPtr pScreen) +@@ -485,6 +810,11 @@ Bool FUNC_NAME(RADEONDrawInit)(ScreenPtr info->accel_state->exa->pixmapOffsetAlign = RADEON_BUFFER_ALIGN + 1; info->accel_state->exa->pixmapPitchAlign = 64; @@ -6915,7 +6635,7 @@ index 59cb46f..8d6f085 100644 #ifdef RENDER if (info->RenderAccel) { if (info->ChipFamily >= CHIP_FAMILY_R600) -@@ -493,7 +823,7 @@ Bool FUNC_NAME(RADEONDrawInit)(ScreenPtr pScreen) +@@ -493,7 +823,7 @@ Bool FUNC_NAME(RADEONDrawInit)(ScreenPtr else if (IS_R300_3D || IS_R500_3D) { if ((info->ChipFamily < CHIP_FAMILY_RS400) #ifdef XF86DRI @@ -6924,7 +6644,7 @@ index 59cb46f..8d6f085 100644 #endif ) { xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Render acceleration " -@@ -528,6 +858,16 @@ Bool FUNC_NAME(RADEONDrawInit)(ScreenPtr pScreen) +@@ -528,6 +858,16 @@ Bool FUNC_NAME(RADEONDrawInit)(ScreenPtr } #endif @@ -6941,10 +6661,9 @@ index 59cb46f..8d6f085 100644 #if EXA_VERSION_MAJOR > 2 || (EXA_VERSION_MAJOR == 2 && EXA_VERSION_MINOR >= 3) xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Setting EXA maxPitchBytes\n"); -diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c -index 571204a..ca46505 100644 ---- a/src/radeon_exa_render.c -+++ b/src/radeon_exa_render.c +diff -up xf86-video-ati-6.12.2/src/radeon_exa_render.c.modeset xf86-video-ati-6.12.2/src/radeon_exa_render.c +--- xf86-video-ati-6.12.2/src/radeon_exa_render.c.modeset 2009-04-02 01:12:43.000000000 -0400 ++++ xf86-video-ati-6.12.2/src/radeon_exa_render.c 2009-04-13 13:24:51.000000000 -0400 @@ -54,6 +54,10 @@ #define ONLY_ONCE #endif @@ -6956,7 +6675,7 @@ index 571204a..ca46505 100644 /* Only include the following (generic) bits once. */ #ifdef ONLY_ONCE -@@ -365,12 +369,14 @@ static Bool FUNC_NAME(R100TextureSetup)(PicturePtr pPict, PixmapPtr pPix, +@@ -365,12 +369,14 @@ static Bool FUNC_NAME(R100TextureSetup)( Bool repeat = pPict->repeat && pPict->repeatType != RepeatPad && !(unit == 0 && (info->accel_state->need_src_tile_x || info->accel_state->need_src_tile_y)); int i; @@ -6973,7 +6692,7 @@ index 571204a..ca46505 100644 RADEON_FALLBACK(("Bad texture offset 0x%x\n", (int)txoffset)); if ((txpitch & 0x1f) != 0) RADEON_FALLBACK(("Bad texture pitch 0x%x\n", (int)txpitch)); -@@ -426,23 +432,43 @@ static Bool FUNC_NAME(R100TextureSetup)(PicturePtr pPict, PixmapPtr pPix, +@@ -426,23 +432,43 @@ static Bool FUNC_NAME(R100TextureSetup)( } } @@ -7020,7 +6739,7 @@ index 571204a..ca46505 100644 } FINISH_ACCEL(); -@@ -551,10 +577,52 @@ static Bool FUNC_NAME(R100PrepareComposite)(int op, +@@ -551,10 +577,52 @@ static Bool FUNC_NAME(R100PrepareComposi uint32_t dst_format, dst_offset, dst_pitch, colorpitch; uint32_t pp_cntl, blendcntl, cblend, ablend; int pixel_shift; @@ -7073,7 +6792,7 @@ index 571204a..ca46505 100644 if (!RADEONGetDestFormat(pDstPicture, &dst_format)) return FALSE; -@@ -568,19 +636,18 @@ static Bool FUNC_NAME(R100PrepareComposite)(int op, +@@ -568,19 +636,18 @@ static Bool FUNC_NAME(R100PrepareComposi pixel_shift = pDst->drawable.bitsPerPixel >> 4; @@ -7096,7 +6815,7 @@ index 571204a..ca46505 100644 if (!RADEONSetupSourceTile(pSrcPicture, pSrc, FALSE, TRUE)) return FALSE; -@@ -598,10 +665,18 @@ static Bool FUNC_NAME(R100PrepareComposite)(int op, +@@ -598,10 +665,18 @@ static Bool FUNC_NAME(R100PrepareComposi info->accel_state->is_transform[1] = FALSE; } @@ -7117,7 +6836,7 @@ index 571204a..ca46505 100644 OUT_ACCEL_REG(RADEON_RB3D_COLORPITCH, colorpitch); /* IN operator: Multiply src by mask components or mask alpha. -@@ -701,13 +776,17 @@ static Bool FUNC_NAME(R200TextureSetup)(PicturePtr pPict, PixmapPtr pPix, +@@ -701,13 +776,17 @@ static Bool FUNC_NAME(R200TextureSetup)( Bool repeat = pPict->repeat && pPict->repeatType != RepeatPad && !(unit == 0 && (info->accel_state->need_src_tile_x || info->accel_state->need_src_tile_y)); int i; @@ -7138,7 +6857,7 @@ index 571204a..ca46505 100644 if ((txpitch & 0x1f) != 0) RADEON_FALLBACK(("Bad texture pitch 0x%x\n", (int)txpitch)); -@@ -764,7 +843,8 @@ static Bool FUNC_NAME(R200TextureSetup)(PicturePtr pPict, PixmapPtr pPix, +@@ -764,7 +843,8 @@ static Bool FUNC_NAME(R200TextureSetup)( } } @@ -7148,7 +6867,7 @@ index 571204a..ca46505 100644 if (unit == 0) { OUT_ACCEL_REG(R200_PP_TXFILTER_0, txfilter); OUT_ACCEL_REG(R200_PP_TXFORMAT_0, txformat); -@@ -772,7 +852,15 @@ static Bool FUNC_NAME(R200TextureSetup)(PicturePtr pPict, PixmapPtr pPix, +@@ -772,7 +852,15 @@ static Bool FUNC_NAME(R200TextureSetup)( OUT_ACCEL_REG(R200_PP_TXSIZE_0, (pPix->drawable.width - 1) | ((pPix->drawable.height - 1) << RADEON_TEX_VSIZE_SHIFT)); OUT_ACCEL_REG(R200_PP_TXPITCH_0, txpitch - 32); @@ -7165,7 +6884,7 @@ index 571204a..ca46505 100644 } else { OUT_ACCEL_REG(R200_PP_TXFILTER_1, txfilter); OUT_ACCEL_REG(R200_PP_TXFORMAT_1, txformat); -@@ -780,7 +868,17 @@ static Bool FUNC_NAME(R200TextureSetup)(PicturePtr pPict, PixmapPtr pPix, +@@ -780,7 +868,17 @@ static Bool FUNC_NAME(R200TextureSetup)( OUT_ACCEL_REG(R200_PP_TXSIZE_1, (pPix->drawable.width - 1) | ((pPix->drawable.height - 1) << RADEON_TEX_VSIZE_SHIFT)); OUT_ACCEL_REG(R200_PP_TXPITCH_1, txpitch - 32); @@ -7184,7 +6903,7 @@ index 571204a..ca46505 100644 } FINISH_ACCEL(); -@@ -873,10 +971,52 @@ static Bool FUNC_NAME(R200PrepareComposite)(int op, PicturePtr pSrcPicture, +@@ -873,10 +971,52 @@ static Bool FUNC_NAME(R200PrepareComposi uint32_t dst_format, dst_offset, dst_pitch; uint32_t pp_cntl, blendcntl, cblend, ablend, colorpitch; int pixel_shift; @@ -7237,7 +6956,7 @@ index 571204a..ca46505 100644 if (!RADEONGetDestFormat(pDstPicture, &dst_format)) return FALSE; -@@ -890,13 +1030,13 @@ static Bool FUNC_NAME(R200PrepareComposite)(int op, PicturePtr pSrcPicture, +@@ -890,13 +1030,13 @@ static Bool FUNC_NAME(R200PrepareComposi pixel_shift = pDst->drawable.bitsPerPixel >> 4; @@ -7253,7 +6972,7 @@ index 571204a..ca46505 100644 RADEON_FALLBACK(("Bad destination offset 0x%x\n", (int)dst_offset)); if (((dst_pitch >> pixel_shift) & 0x7) != 0) RADEON_FALLBACK(("Bad destination pitch 0x%x\n", (int)dst_pitch)); -@@ -918,11 +1058,22 @@ static Bool FUNC_NAME(R200PrepareComposite)(int op, PicturePtr pSrcPicture, +@@ -918,11 +1058,22 @@ static Bool FUNC_NAME(R200PrepareComposi info->accel_state->is_transform[1] = FALSE; } @@ -7278,7 +6997,7 @@ index 571204a..ca46505 100644 OUT_ACCEL_REG(R200_SE_VTX_FMT_0, R200_VTX_XY); if (pMask) -@@ -991,6 +1142,10 @@ static Bool R300CheckCompositeTexture(PicturePtr pPict, +@@ -991,6 +1142,10 @@ static Bool R300CheckCompositeTexture(Pi int unit, Bool is_r500) { @@ -7289,7 +7008,7 @@ index 571204a..ca46505 100644 int w = pPict->pDrawable->width; int h = pPict->pDrawable->height; int i; -@@ -1016,8 +1171,17 @@ static Bool R300CheckCompositeTexture(PicturePtr pPict, +@@ -1016,8 +1171,17 @@ static Bool R300CheckCompositeTexture(Pi RADEON_FALLBACK(("Unsupported picture format 0x%x\n", (int)pPict->format)); @@ -7308,7 +7027,7 @@ index 571204a..ca46505 100644 if (pPict->filter != PictFilterNearest && pPict->filter != PictFilterBilinear) -@@ -1049,15 +1213,19 @@ static Bool FUNC_NAME(R300TextureSetup)(PicturePtr pPict, PixmapPtr pPix, +@@ -1049,15 +1213,19 @@ static Bool FUNC_NAME(R300TextureSetup)( int w = pPict->pDrawable->width; int h = pPict->pDrawable->height; int i, pixel_shift; @@ -7331,7 +7050,7 @@ index 571204a..ca46505 100644 if ((txpitch & 0x1f) != 0) RADEON_FALLBACK(("Bad texture pitch 0x%x\n", (int)txpitch)); -@@ -1139,13 +1307,26 @@ static Bool FUNC_NAME(R300TextureSetup)(PicturePtr pPict, PixmapPtr pPix, +@@ -1139,13 +1307,26 @@ static Bool FUNC_NAME(R300TextureSetup)( RADEON_FALLBACK(("Bad filter 0x%x\n", pPict->filter)); } @@ -7360,7 +7079,7 @@ index 571204a..ca46505 100644 if (!pPict->repeat) OUT_ACCEL_REG(R300_TX_BORDER_COLOR_0 + (unit * 4), 0); FINISH_ACCEL(); -@@ -1244,6 +1425,7 @@ static Bool R300CheckComposite(int op, PicturePtr pSrcPicture, PicturePtr pMaskP +@@ -1244,6 +1425,7 @@ static Bool R300CheckComposite(int op, P return TRUE; } @@ -7368,7 +7087,7 @@ index 571204a..ca46505 100644 #endif /* ONLY_ONCE */ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, -@@ -1255,10 +1437,51 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, +@@ -1255,10 +1437,51 @@ static Bool FUNC_NAME(R300PrepareComposi uint32_t txenable, colorpitch; uint32_t blendcntl; int pixel_shift; @@ -7421,7 +7140,7 @@ index 571204a..ca46505 100644 if (!R300GetDestFormat(pDstPicture, &dst_format)) return FALSE; -@@ -1269,7 +1492,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, +@@ -1269,7 +1492,7 @@ static Bool FUNC_NAME(R300PrepareComposi pixel_shift = pDst->drawable.bitsPerPixel >> 4; @@ -7430,7 +7149,7 @@ index 571204a..ca46505 100644 dst_pitch = exaGetPixmapPitch(pDst); colorpitch = dst_pitch >> pixel_shift; -@@ -1278,7 +1501,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, +@@ -1278,7 +1501,7 @@ static Bool FUNC_NAME(R300PrepareComposi colorpitch |= dst_format; @@ -7439,7 +7158,7 @@ index 571204a..ca46505 100644 RADEON_FALLBACK(("Bad destination offset 0x%x\n", (int)dst_offset)); if (((dst_pitch >> pixel_shift) & 0x7) != 0) RADEON_FALLBACK(("Bad destination pitch 0x%x\n", (int)dst_pitch)); -@@ -1287,6 +1510,9 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, +@@ -1287,6 +1510,9 @@ static Bool FUNC_NAME(R300PrepareComposi return FALSE; RADEON_SWITCH_TO_3D(); @@ -7449,7 +7168,7 @@ index 571204a..ca46505 100644 if (!FUNC_NAME(R300TextureSetup)(pSrcPicture, pSrc, 0)) return FALSE; -@@ -1939,9 +2165,18 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, +@@ -1939,9 +2165,18 @@ static Bool FUNC_NAME(R300PrepareComposi (8191 << R300_SCISSOR_Y_SHIFT))); FINISH_ACCEL(); @@ -7470,7 +7189,7 @@ index 571204a..ca46505 100644 OUT_ACCEL_REG(R300_RB3D_COLORPITCH0, colorpitch); blendcntl = RADEONGetBlendCntl(op, pMaskPicture, pDstPicture->format); -@@ -1959,7 +2194,6 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, +@@ -1959,7 +2194,6 @@ static Bool FUNC_NAME(R300PrepareComposi return TRUE; } @@ -7478,7 +7197,7 @@ index 571204a..ca46505 100644 #ifdef ACCEL_CP #define VTX_OUT_MASK(_dstX, _dstY, _srcX, _srcY, _maskX, _maskY) \ -@@ -2245,14 +2479,23 @@ static void FUNC_NAME(RadeonDoneComposite)(PixmapPtr pDst) +@@ -2245,14 +2479,23 @@ static void FUNC_NAME(RadeonDoneComposit if (IS_R300_3D || IS_R500_3D) { BEGIN_ACCEL(3); @@ -7503,11 +7222,256 @@ index 571204a..ca46505 100644 } #undef ONLY_ONCE -diff --git a/src/radeon_legacy_memory.c b/src/radeon_legacy_memory.c -index 861fd97..c436faf 100644 ---- a/src/radeon_legacy_memory.c -+++ b/src/radeon_legacy_memory.c -@@ -21,6 +21,19 @@ radeon_legacy_allocate_memory(ScrnInfoPtr pScrn, +diff -up xf86-video-ati-6.12.2/src/radeon.h.modeset xf86-video-ati-6.12.2/src/radeon.h +--- xf86-video-ati-6.12.2/src/radeon.h.modeset 2009-03-31 15:48:34.000000000 -0400 ++++ xf86-video-ati-6.12.2/src/radeon.h 2009-04-13 13:24:51.000000000 -0400 +@@ -46,6 +46,8 @@ + #include "compiler.h" + #include "xf86fbman.h" + ++#include "drmmode_display.h" ++ + /* PCI support */ + #include "xf86Pci.h" + +@@ -75,6 +77,7 @@ + #include "dri.h" + #include "GL/glxint.h" + #include "xf86drm.h" ++#include "radeon_dri2.h" + + #ifdef DAMAGE + #include "damage.h" +@@ -85,6 +88,7 @@ + #include "xf86Crtc.h" + #include "X11/Xatom.h" + ++#include "radeon_bufmgr.h" + /* Render support */ + #ifdef RENDER + #include "picturestr.h" +@@ -414,6 +418,14 @@ typedef enum { + + typedef struct _atomBiosHandle *atomBiosHandlePtr; + ++#define RADEON_POOL_GART 0 ++#define RADEON_POOL_VRAM 1 ++ ++struct radeon_exa_pixmap_priv { ++ dri_bo *bo; ++ int flags; ++}; ++ + typedef struct { + uint32_t pci_device_id; + RADEONChipFamily chip_family; +@@ -424,7 +436,27 @@ typedef struct { + int singledac; + } RADEONCardInfo; + ++#define RADEON_2D_EXA_COPY 1 ++#define RADEON_2D_EXA_SOLID 2 ++ ++struct radeon_2d_state { ++ int op; // ++ uint32_t dst_pitch_offset; ++ uint32_t src_pitch_offset; ++ uint32_t dp_gui_master_cntl; ++ uint32_t dp_cntl; ++ uint32_t dp_write_mask; ++ uint32_t dp_brush_frgd_clr; ++ uint32_t dp_brush_bkgd_clr; ++ uint32_t dp_src_frgd_clr; ++ uint32_t dp_src_bkgd_clr; ++ uint32_t default_sc_bottom_right; ++ dri_bo *dst_bo; ++ dri_bo *src_bo; ++}; ++ + #ifdef XF86DRI ++ + struct radeon_cp { + Bool CPRuns; /* CP is running */ + Bool CPInUse; /* CP has been used by X server */ +@@ -438,6 +470,10 @@ struct radeon_cp { + drmBufPtr indirectBuffer; + int indirectStart; + ++ drmBuf ib_gem_fake; ++ void *ib_ptr; ++ ++ struct radeon_relocs_info relocs; + /* Debugging info for BEGIN_RING/ADVANCE_RING pairs. */ + int dma_begin_count; + char *dma_debug_func; +@@ -504,13 +540,13 @@ struct radeon_dri { + drm_handle_t ringHandle; /* Handle from drmAddMap */ + drmSize ringMapSize; /* Size of map */ + int ringSize; /* Size of ring (in MB) */ +- drmAddress ring; /* Map */ ++ // drmAddress ring; /* Map */ + int ringSizeLog2QW; + + unsigned long ringReadOffset; /* Offset into GART space */ + drm_handle_t ringReadPtrHandle; /* Handle from drmAddMap */ + drmSize ringReadMapSize; /* Size of map */ +- drmAddress ringReadPtr; /* Map */ ++ // drmAddress ringReadPtr; /* Map */ + + /* CP vertex/indirect buffer data */ + unsigned long bufStart; /* Offset into GART space */ +@@ -529,7 +565,6 @@ struct radeon_dri { + drmAddress gartTex; /* Map */ + int log2GARTTexGran; + +- /* DRI screen private data */ + int fbX; + int fbY; + int backX; +@@ -789,6 +824,7 @@ typedef struct { + RADEONCardType cardType; /* Current card is a PCI card */ + struct radeon_cp *cp; + struct radeon_dri *dri; ++ struct radeon_dri2 dri2; + #ifdef USE_EXA + Bool accelDFS; + #endif +@@ -892,6 +928,43 @@ typedef struct { + + Bool r4xx_atom; + ++ Bool new_cs; // new command submission routine ++ struct radeon_2d_state state_2d; ++ void (*reemit_current2d)(ScrnInfoPtr pScrn, int op); // emit the current 2D state into the IB ++ Bool cs_used_depth; ++ Bool drm_mm; // the drm memory manager exists and is initialised ++ struct { ++ uint64_t vram_size; ++ uint64_t gart_size; ++ ++ struct radeon_memory *bo_list[2]; ++ struct radeon_memory *front_buffer; ++ struct radeon_memory *back_buffer; ++ struct radeon_memory *depth_buffer; ++ ++#if 0 ++ struct radeon_memory *exa_buffer; ++#endif ++ struct radeon_memory *texture_buffer; ++ ++ struct radeon_memory *dma_buffer; ++ struct radeon_memory *gart_texture_buffer; ++ struct radeon_memory *rotate_buffer; ++ struct radeon_memory *cursor[2]; ++ ++ /* indirect buffer for accel */ ++ struct radeon_memory *gem_ib_memory; ++ ++ } mm; ++ ++ drm_handle_t fb_map_handle; ++ Bool drm_mode_setting; ++#ifdef XF86DRM_MODE ++ drmmode_rec drmmode; ++#endif ++ ++ int can_resize; ++ dri_bufmgr *bufmgr; + } RADEONInfoRec, *RADEONInfoPtr; + + #define RADEONWaitForFifo(pScrn, entries) \ +@@ -1147,6 +1220,24 @@ extern void + radeon_legacy_free_memory(ScrnInfoPtr pScrn, + void *mem_struct); + ++/* radeon_memory.c */ ++extern uint32_t radeon_name_buffer(ScrnInfoPtr pScrn, struct radeon_memory *mem); ++extern Bool radeon_bind_all_memory(ScrnInfoPtr pScrn); ++extern Bool radeon_unbind_all_memory(ScrnInfoPtr pScrn); ++extern struct radeon_memory *radeon_allocate_memory(ScrnInfoPtr pScrn, int pool, int size, int alignment, Bool no_backing_store, char *name, ++ int need_bind); ++int radeon_map_memory(ScrnInfoPtr pScrn, struct radeon_memory *mem); ++void radeon_unmap_memory(ScrnInfoPtr pScrn, struct radeon_memory *mem); ++void radeon_free_memory(ScrnInfoPtr pScrn, struct radeon_memory *mem); ++Bool radeon_bind_memory(ScrnInfoPtr pScrn, struct radeon_memory *mem); ++Bool radeon_free_all_memory(ScrnInfoPtr pScrn); ++Bool radeon_setup_kernel_mem(ScreenPtr pScreen); ++Bool RADEONDRIDoMappings(ScreenPtr pScreen); ++Bool radeon_update_dri_buffers(ScreenPtr pScreen); ++ ++dri_bo *radeon_get_pixmap_bo(PixmapPtr pPix); ++void radeon_set_pixmap_mem(PixmapPtr pPix, struct radeon_memory *mem); ++void radeon_set_pixmap_bo(PixmapPtr pPix, dri_bo *bo); + #ifdef XF86DRI + # ifdef USE_XAA + /* radeon_accelfuncs.c */ +@@ -1165,7 +1256,9 @@ do { \ + + #define RADEONCP_RELEASE(pScrn, info) \ + do { \ +- if (info->cp->CPInUse) { \ ++ if (info->new_cs) { \ ++ RADEONCPReleaseIndirect(pScrn); \ ++ } else if (info->cp->CPInUse) { \ + RADEON_PURGE_CACHE(); \ + RADEON_WAIT_UNTIL_IDLE(); \ + RADEONCPReleaseIndirect(pScrn); \ +@@ -1200,7 +1293,7 @@ do { \ + + #define RADEONCP_REFRESH(pScrn, info) \ + do { \ +- if (!info->cp->CPInUse) { \ ++ if (!info->cp->CPInUse && !info->new_cs) { \ + if (info->cp->needCacheFlush) { \ + RADEON_PURGE_CACHE(); \ + RADEON_PURGE_ZCACHE(); \ +@@ -1227,6 +1320,13 @@ do { \ + #define RING_LOCALS uint32_t *__head = NULL; int __expected; int __count = 0 + + #define BEGIN_RING(n) do { \ ++ if (!info->cp->indirectBuffer) { \ ++ info->cp->indirectBuffer = RADEONCPGetBuffer(pScrn); \ ++ info->cp->indirectStart = 0; \ ++ } else if (info->cp->indirectBuffer->used + (n) * (int)sizeof(uint32_t) > \ ++ info->cp->indirectBuffer->total) { \ ++ RADEONCPFlushIndirect(pScrn, 1); \ ++ } \ + if (RADEON_VERBOSE) { \ + xf86DrvMsg(pScrn->scrnIndex, X_INFO, \ + "BEGIN_RING(%d) in %s\n", (unsigned int)n, __FUNCTION__);\ +@@ -1239,13 +1339,6 @@ do { \ + } \ + info->cp->dma_debug_func = __FILE__; \ + info->cp->dma_debug_lineno = __LINE__; \ +- if (!info->cp->indirectBuffer) { \ +- info->cp->indirectBuffer = RADEONCPGetBuffer(pScrn); \ +- info->cp->indirectStart = 0; \ +- } else if (info->cp->indirectBuffer->used + (n) * (int)sizeof(uint32_t) > \ +- info->cp->indirectBuffer->total) { \ +- RADEONCPFlushIndirect(pScrn, 1); \ +- } \ + __expected = n; \ + __head = (pointer)((char *)info->cp->indirectBuffer->address + \ + info->cp->indirectBuffer->used); \ +@@ -1288,6 +1381,14 @@ do { \ + OUT_RING(val); \ + } while (0) + ++/* TODO - VRAM is wrong in general but true for now - all EXA stuff ++ is in VRAM */ ++#define OUT_RING_RELOC(x, read_domains, write_domains) \ ++ do { \ ++ radeon_bufmgr_emit_reloc(x, &info->cp->relocs, __head, &__count, read_domains, write_domains); \ ++ } while(0) ++ ++ + #define FLUSH_RING() \ + do { \ + if (RADEON_VERBOSE) \ +diff -up xf86-video-ati-6.12.2/src/radeon_legacy_memory.c.modeset xf86-video-ati-6.12.2/src/radeon_legacy_memory.c +--- xf86-video-ati-6.12.2/src/radeon_legacy_memory.c.modeset 2009-02-24 09:45:07.000000000 -0500 ++++ xf86-video-ati-6.12.2/src/radeon_legacy_memory.c 2009-04-13 13:24:51.000000000 -0400 +@@ -21,6 +21,19 @@ radeon_legacy_allocate_memory(ScrnInfoPt RADEONInfoPtr info = RADEONPTR(pScrn); uint32_t offset = 0; @@ -7527,7 +7491,7 @@ index 861fd97..c436faf 100644 #ifdef USE_EXA if (info->useEXA) { ExaOffscreenArea *area = *mem_struct; -@@ -94,6 +107,12 @@ radeon_legacy_free_memory(ScrnInfoPtr pScrn, +@@ -94,6 +107,12 @@ radeon_legacy_free_memory(ScrnInfoPtr pS void *mem_struct) { RADEONInfoPtr info = RADEONPTR(pScrn); @@ -7540,11 +7504,9 @@ index 861fd97..c436faf 100644 #ifdef USE_EXA ScreenPtr pScreen = screenInfo.screens[pScrn->scrnIndex]; -diff --git a/src/radeon_memory.c b/src/radeon_memory.c -new file mode 100644 -index 0000000..3d722fb ---- /dev/null -+++ b/src/radeon_memory.c +diff -up /dev/null xf86-video-ati-6.12.2/src/radeon_memory.c +--- /dev/null 2009-04-02 14:26:50.181076715 -0400 ++++ xf86-video-ati-6.12.2/src/radeon_memory.c 2009-04-13 13:24:51.000000000 -0400 @@ -0,0 +1,245 @@ + +#ifdef HAVE_CONFIG_H @@ -7791,10 +7753,9 @@ index 0000000..3d722fb +} + + -diff --git a/src/radeon_probe.h b/src/radeon_probe.h -index a0c6b2c..b0fd23e 100644 ---- a/src/radeon_probe.h -+++ b/src/radeon_probe.h +diff -up xf86-video-ati-6.12.2/src/radeon_probe.h.modeset xf86-video-ati-6.12.2/src/radeon_probe.h +--- xf86-video-ati-6.12.2/src/radeon_probe.h.modeset 2009-04-04 18:44:00.000000000 -0400 ++++ xf86-video-ati-6.12.2/src/radeon_probe.h 2009-04-13 13:24:51.000000000 -0400 @@ -146,6 +146,26 @@ typedef struct Bool hw_capable; } RADEONI2CBusRec, *RADEONI2CBusPtr; @@ -7831,10 +7792,9 @@ index a0c6b2c..b0fd23e 100644 } RADEONCrtcPrivateRec, *RADEONCrtcPrivatePtr; typedef struct _radeon_encoder { -diff --git a/src/radeon_textured_video.c b/src/radeon_textured_video.c -index 79671c0..7a70d2f 100644 ---- a/src/radeon_textured_video.c -+++ b/src/radeon_textured_video.c +diff -up xf86-video-ati-6.12.2/src/radeon_textured_video.c.modeset xf86-video-ati-6.12.2/src/radeon_textured_video.c +--- xf86-video-ati-6.12.2/src/radeon_textured_video.c.modeset 2009-03-27 01:13:04.000000000 -0400 ++++ xf86-video-ati-6.12.2/src/radeon_textured_video.c 2009-04-13 13:24:51.000000000 -0400 @@ -40,6 +40,7 @@ #include "radeon_macros.h" #include "radeon_probe.h" @@ -7843,7 +7803,7 @@ index 79671c0..7a70d2f 100644 #include #include "fourcc.h" -@@ -133,6 +134,7 @@ static __inline__ uint32_t float4touint(float fr, float fg, float fb, float fa) +@@ -133,6 +134,7 @@ static __inline__ uint32_t float4touint( #define BEGIN_ACCEL(n) RADEONWaitForFifo(pScrn, (n)) #define OUT_ACCEL_REG(reg, val) OUTREG(reg, val) #define OUT_ACCEL_REG_F(reg, val) OUTREG(reg, F_TO_DW(val)) @@ -7851,7 +7811,7 @@ index 79671c0..7a70d2f 100644 #define FINISH_ACCEL() #include "radeon_textured_videofuncs.c" -@@ -142,6 +144,7 @@ static __inline__ uint32_t float4touint(float fr, float fg, float fb, float fa) +@@ -142,6 +144,7 @@ static __inline__ uint32_t float4touint( #undef BEGIN_ACCEL #undef OUT_ACCEL_REG #undef OUT_ACCEL_REG_F @@ -7859,7 +7819,7 @@ index 79671c0..7a70d2f 100644 #undef FINISH_ACCEL #ifdef XF86DRI -@@ -155,6 +158,7 @@ static __inline__ uint32_t float4touint(float fr, float fg, float fb, float fa) +@@ -155,6 +158,7 @@ static __inline__ uint32_t float4touint( #define OUT_ACCEL_REG_F(reg, val) OUT_ACCEL_REG(reg, F_TO_DW(val)) #define FINISH_ACCEL() ADVANCE_RING() #define OUT_RING_F(x) OUT_RING(F_TO_DW(x)) @@ -7867,7 +7827,7 @@ index 79671c0..7a70d2f 100644 #include "radeon_textured_videofuncs.c" -@@ -412,6 +416,9 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn, +@@ -412,6 +416,9 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn size * 2, 64); if (pPriv->video_offset == 0) return BadAlloc; @@ -7877,7 +7837,7 @@ index 79671c0..7a70d2f 100644 } /* Bicubic filter loading */ -@@ -422,6 +429,9 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn, +@@ -422,6 +429,9 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn pPriv->bicubic_src_offset = pPriv->bicubic_offset + info->fbLocation + pScrn->fbOffset; if (pPriv->bicubic_offset == 0) pPriv->bicubic_enabled = FALSE; @@ -7887,7 +7847,7 @@ index 79671c0..7a70d2f 100644 } if (pDraw->type == DRAWABLE_WINDOW) -@@ -451,11 +461,22 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn, +@@ -451,11 +461,22 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn left = (x1 >> 16) & ~1; npixels = ((((x2 + 0xffff) >> 16) + 1) & ~1) - left; @@ -7915,7 +7875,7 @@ index 79671c0..7a70d2f 100644 pPriv->src_pitch = dstPitch; pPriv->planeu_offset = dstPitch * dst_height; pPriv->planev_offset = pPriv->planeu_offset + dstPitch2 * ((dst_height + 1) >> 1); -@@ -481,12 +502,12 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn, +@@ -481,12 +502,12 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn if (info->DMAForXv) { if (id == FOURCC_YV12) R600CopyPlanarHW(pScrn, buf, buf + s3offset, buf + s2offset, @@ -7930,7 +7890,7 @@ index 79671c0..7a70d2f 100644 srcPitch, srcPitch2, pPriv->src_pitch, width, height); } else { -@@ -548,7 +569,7 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn, +@@ -548,7 +569,7 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn default: if (info->ChipFamily >= CHIP_FAMILY_R600) { if (info->DMAForXv) @@ -7939,7 +7899,7 @@ index 79671c0..7a70d2f 100644 2 * width, pPriv->src_pitch, width, height); else -@@ -566,9 +587,24 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn, +@@ -566,9 +587,24 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn /* Upload bicubic filter tex */ if (pPriv->bicubic_enabled) { @@ -7967,7 +7927,7 @@ index 79671c0..7a70d2f 100644 } /* update cliplist */ -@@ -586,10 +622,12 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn, +@@ -586,10 +622,12 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn pPriv->w = width; pPriv->h = height; @@ -7981,10 +7941,9 @@ index 79671c0..7a70d2f 100644 RADEONDisplayTexturedVideoCP(pScrn, pPriv); else #endif -diff --git a/src/radeon_textured_videofuncs.c b/src/radeon_textured_videofuncs.c -index 05acb93..852f4ac 100644 ---- a/src/radeon_textured_videofuncs.c -+++ b/src/radeon_textured_videofuncs.c +diff -up xf86-video-ati-6.12.2/src/radeon_textured_videofuncs.c.modeset xf86-video-ati-6.12.2/src/radeon_textured_videofuncs.c +--- xf86-video-ati-6.12.2/src/radeon_textured_videofuncs.c.modeset 2009-04-07 11:32:12.000000000 -0400 ++++ xf86-video-ati-6.12.2/src/radeon_textured_videofuncs.c 2009-04-13 13:24:51.000000000 -0400 @@ -87,11 +87,25 @@ do { \ #endif /* !ACCEL_CP */ @@ -8011,7 +7970,7 @@ index 05acb93..852f4ac 100644 uint32_t txformat; uint32_t txfilter, txformat0, txformat1, txoffset, txpitch; uint32_t dst_offset, dst_pitch, dst_format; -@@ -101,19 +115,57 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv +@@ -101,19 +115,57 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(Sc int dstxoff, dstyoff, pixel_shift, vtx_count; BoxPtr pBox = REGION_RECTS(&pPriv->clip); int nBox = REGION_NUM_RECTS(&pPriv->clip); @@ -8072,7 +8031,7 @@ index 05acb93..852f4ac 100644 dst_pitch = pPixmap->devKind; } -@@ -144,7 +196,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv +@@ -144,7 +196,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(Sc RADEON_WAIT_DMA_GUI_IDLE); FINISH_ACCEL(); @@ -8081,7 +8040,7 @@ index 05acb93..852f4ac 100644 RADEONInit3DEngine(pScrn); } -@@ -222,15 +274,19 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv +@@ -222,15 +274,19 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(Sc if (IS_R500_3D && ((pPriv->h - 1) & 0x800)) txpitch |= R500_TXHEIGHT_11; @@ -8104,7 +8063,7 @@ index 05acb93..852f4ac 100644 FINISH_ACCEL(); txenable = R300_TEX_0_ENABLE; -@@ -246,19 +302,22 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv +@@ -246,19 +302,22 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(Sc R300_TX_MIN_FILTER_LINEAR | R300_TX_MAG_FILTER_LINEAR); @@ -8130,7 +8089,7 @@ index 05acb93..852f4ac 100644 FINISH_ACCEL(); txenable |= R300_TEX_1_ENABLE | R300_TEX_2_ENABLE; } -@@ -279,13 +338,19 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv +@@ -279,13 +338,19 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(Sc R300_TX_MAG_FILTER_NEAREST | (1 << R300_TX_ID_SHIFT)); @@ -8152,7 +8111,7 @@ index 05acb93..852f4ac 100644 FINISH_ACCEL(); /* Enable tex 1 */ -@@ -1536,11 +1601,18 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv +@@ -1536,11 +1601,18 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(Sc } } @@ -8173,7 +8132,7 @@ index 05acb93..852f4ac 100644 OUT_ACCEL_REG(R300_RB3D_COLORPITCH0, colorpitch); blendcntl = RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ZERO; -@@ -1587,11 +1659,19 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv +@@ -1587,11 +1659,19 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(Sc if (RADEONTilingEnabled(pScrn, pPixmap)) colorpitch |= RADEON_COLOR_TILE_ENABLE; @@ -8195,7 +8154,7 @@ index 05acb93..852f4ac 100644 OUT_ACCEL_REG(RADEON_RB3D_COLORPITCH, colorpitch); -@@ -1630,7 +1710,8 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv +@@ -1630,7 +1710,8 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(Sc R200_CLAMP_S_CLAMP_LAST | R200_CLAMP_T_CLAMP_LAST; @@ -8205,7 +8164,7 @@ index 05acb93..852f4ac 100644 OUT_ACCEL_REG(RADEON_PP_CNTL, RADEON_TEX_0_ENABLE | RADEON_TEX_1_ENABLE | RADEON_TEX_2_ENABLE | -@@ -1649,21 +1730,22 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv +@@ -1649,21 +1730,22 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(Sc (pPriv->w - 1) | ((pPriv->h - 1) << RADEON_TEX_VSIZE_SHIFT)); OUT_ACCEL_REG(R200_PP_TXPITCH_0, pPriv->src_pitch - 32); @@ -8231,7 +8190,7 @@ index 05acb93..852f4ac 100644 /* similar to r300 code. Note the big problem is that hardware constants * are 8 bits only, representing 0.0-1.0. We can get that up (using bias -@@ -1799,7 +1881,8 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv +@@ -1799,7 +1881,8 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(Sc R200_CLAMP_S_CLAMP_LAST | R200_CLAMP_T_CLAMP_LAST; @@ -8241,7 +8200,7 @@ index 05acb93..852f4ac 100644 OUT_ACCEL_REG(RADEON_PP_CNTL, RADEON_TEX_0_ENABLE | -@@ -1817,7 +1900,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv +@@ -1817,7 +1900,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(Sc (pPriv->w - 1) | ((pPriv->h - 1) << RADEON_TEX_VSIZE_SHIFT)); OUT_ACCEL_REG(R200_PP_TXPITCH_0, pPriv->src_pitch - 32); @@ -8250,7 +8209,7 @@ index 05acb93..852f4ac 100644 /* MAD temp1 / 2, const0.a * 2, temp0.ggg, -const0.rgb */ OUT_ACCEL_REG(R200_PP_TXCBLEND_0, -@@ -1901,7 +1984,8 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv +@@ -1901,7 +1984,8 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(Sc FINISH_ACCEL(); } else { @@ -8260,7 +8219,7 @@ index 05acb93..852f4ac 100644 OUT_ACCEL_REG(RADEON_PP_CNTL, RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE); -@@ -1922,7 +2006,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv +@@ -1922,7 +2006,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(Sc ((pPriv->h - 1) << RADEON_TEX_VSIZE_SHIFT)); OUT_ACCEL_REG(R200_PP_TXPITCH_0, pPriv->src_pitch - 32); @@ -8269,7 +8228,7 @@ index 05acb93..852f4ac 100644 OUT_ACCEL_REG(R200_PP_TXCBLEND_0, R200_TXC_ARG_A_ZERO | -@@ -1945,7 +2029,8 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv +@@ -1945,7 +2029,8 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(Sc info->accel_state->texW[0] = 1; info->accel_state->texH[0] = 1; @@ -8279,7 +8238,7 @@ index 05acb93..852f4ac 100644 OUT_ACCEL_REG(RADEON_PP_CNTL, RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE); -@@ -1959,8 +2044,9 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv +@@ -1959,8 +2044,9 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(Sc RADEON_CLAMP_S_CLAMP_LAST | RADEON_CLAMP_T_CLAMP_LAST | RADEON_YUV_TO_RGB); @@ -8290,11 +8249,10 @@ index 05acb93..852f4ac 100644 OUT_ACCEL_REG(RADEON_PP_TXCBLEND_0, RADEON_COLOR_ARG_A_ZERO | RADEON_COLOR_ARG_B_ZERO | -diff --git a/src/radeon_video.c b/src/radeon_video.c -index 42aa036..bd6408d 100644 ---- a/src/radeon_video.c -+++ b/src/radeon_video.c -@@ -287,7 +287,7 @@ void RADEONInitVideo(ScreenPtr pScreen) +diff -up xf86-video-ati-6.12.2/src/radeon_video.c.modeset xf86-video-ati-6.12.2/src/radeon_video.c +--- xf86-video-ati-6.12.2/src/radeon_video.c.modeset 2009-04-07 11:31:32.000000000 -0400 ++++ xf86-video-ati-6.12.2/src/radeon_video.c 2009-04-13 13:24:51.000000000 -0400 +@@ -284,7 +284,7 @@ void RADEONInitVideo(ScreenPtr pScreen) memcpy(newAdaptors, adaptors, num_adaptors * sizeof(XF86VideoAdaptorPtr)); adaptors = newAdaptors; @@ -8303,7 +8261,7 @@ index 42aa036..bd6408d 100644 overlayAdaptor = RADEONSetupImageVideo(pScreen); if (overlayAdaptor != NULL) { adaptors[num_adaptors++] = overlayAdaptor; -@@ -297,9 +297,12 @@ void RADEONInitVideo(ScreenPtr pScreen) +@@ -294,9 +294,12 @@ void RADEONInitVideo(ScreenPtr pScreen) RADEONInitOffscreenImages(pScreen); } @@ -8318,7 +8276,7 @@ index 42aa036..bd6408d 100644 #endif ) { texturedAdaptor = RADEONSetupImageTexturedVideo(pScreen); -@@ -2200,7 +2203,7 @@ RADEONCopyData( +@@ -2197,7 +2200,7 @@ RADEONCopyData( #ifdef XF86DRI @@ -8327,10 +8285,9 @@ index 42aa036..bd6408d 100644 { uint8_t *buf; uint32_t bufPitch, dstPitchOff; -diff --git a/src/radeon_video.h b/src/radeon_video.h -index 34fb07f..7b75ec3 100644 ---- a/src/radeon_video.h -+++ b/src/radeon_video.h +diff -up xf86-video-ati-6.12.2/src/radeon_video.h.modeset xf86-video-ati-6.12.2/src/radeon_video.h +--- xf86-video-ati-6.12.2/src/radeon_video.h.modeset 2009-04-07 11:31:53.000000000 -0400 ++++ xf86-video-ati-6.12.2/src/radeon_video.h 2009-04-13 13:31:13.000000000 -0400 @@ -121,6 +121,9 @@ typedef struct { int w, h; int drw_x, drw_y; @@ -8340,4 +8297,4 @@ index 34fb07f..7b75ec3 100644 + dri_bo *bicubic_bo; } RADEONPortPrivRec, *RADEONPortPrivPtr; - int + xf86CrtcPtr diff --git a/sources b/sources index eae31e5..fda057c 100644 --- a/sources +++ b/sources @@ -1 +1 @@ -2adf5988c5e5b6df5f4cb61006fa2bf1 xf86-video-ati-6.12.1.tar.bz2 +2bf50461378771497501ca7f678d36f3 xf86-video-ati-6.12.2.tar.bz2 diff --git a/xorg-x11-drv-ati.spec b/xorg-x11-drv-ati.spec index 5f0632a..504fb48 100644 --- a/xorg-x11-drv-ati.spec +++ b/xorg-x11-drv-ati.spec @@ -4,8 +4,8 @@ Summary: Xorg X11 ati video driver Name: xorg-x11-drv-ati -Version: 6.12.1 -Release: 10%{?dist} +Version: 6.12.2 +Release: 1%{?dist} URL: http://www.x.org License: MIT Group: User Interface/X Hardware Support @@ -14,11 +14,8 @@ BuildRoot: %{_tmppath}/%{name}-%{version}-%{release}-root-%(%{__id_u} -n) Source0: http://www.x.org/pub/individual/driver/%{tarball}-%{version}.tar.bz2 Source1: radeon.xinf -Patch0: radeon-6.12.0-git-fixes.patch Patch1: radeon-modeset.patch Patch2: radeon-modeset-fixes.patch -#Patch4: radeon-6.9.0-remove-limit-heuristics.patch -Patch5: radeon-6.9.0-panel-size-sanity.patch Patch6: radeon-6.9.0-bgnr-enable.patch Patch7: radeon-6.12.1-r600-fb-size.patch @@ -42,11 +39,8 @@ X.Org X11 ati video driver. %prep %setup -q -n %{tarball}-%{version} -%patch0 -p1 -b .fixes %patch1 -p1 -b .modeset %patch2 -p1 -b .modeset-fix -#patch4 -p1 -b .remove-limit-heuristics -#%patch5 -p1 -b .panel-size %patch6 -p1 -b .bgnr %patch7 -p1 -b .r600-fb-size @@ -80,6 +74,9 @@ rm -rf $RPM_BUILD_ROOT %{_mandir}/man4/radeon.4* %changelog +* Mon Apr 13 2009 Adam Jackson 6.12.2-1 +- radeon 6.12.2 + * Thu Apr 09 2009 Adam Jackson 6.12.1-10 - radeon-6.12.1-r600-fb-size.patch: Bump fb size max on R600+ when no KMS so single-link dualhead stands a chance of working.