diff --git a/radeon-6.6.3-renderaccel-buglet.patch b/radeon-6.6.3-renderaccel-buglet.patch deleted file mode 100644 index e959704..0000000 --- a/radeon-6.6.3-renderaccel-buglet.patch +++ /dev/null @@ -1,20 +0,0 @@ ---- xf86-video-ati-6.6.3/src/radeon_render.c.jx 2006-10-03 11:00:42.000000000 -0400 -+++ xf86-video-ati-6.6.3/src/radeon_render.c 2007-06-18 11:27:55.000000000 -0400 -@@ -396,7 +396,7 @@ - if (flags & XAA_RENDER_REPEAT) - return FALSE; - -- if ((width > 2048) || (height > 2048)) -+ if ((width > 2047) || (height > 2047)) - return FALSE; - - txformat = RadeonGetTextureFormat(format); -@@ -424,7 +424,7 @@ - txformat |= ATILog2(width) << RADEON_TXFORMAT_WIDTH_SHIFT; - txformat |= ATILog2(height) << RADEON_TXFORMAT_HEIGHT_SHIFT; - } else { -- tex_size = ((height - 1) << 16) | (width - 1); -+ tex_size = (height << 16) | width; - txformat |= RADEON_TXFORMAT_NON_POWER2; - } - diff --git a/radeon-6.7.196-atombios-support.patch b/radeon-6.7.196-atombios-support.patch index 4a78e0f..35b19d7 100644 --- a/radeon-6.7.196-atombios-support.patch +++ b/radeon-6.7.196-atombios-support.patch @@ -1,3 +1,99 @@ +commit 78fb6c77f88d2ce5d2e1ec925958b97c51955ec6 +Merge: f5e8c18... ce4fa1c... +Author: Dave Airlie +Date: Wed Dec 19 14:45:11 2007 +1000 + + Merge branch 'master' into atombios-support + + Conflicts: + + src/radeon_display.c + +diff --git a/configure.ac b/configure.ac +index 1570e54..d395899 100644 +--- a/configure.ac ++++ b/configure.ac +@@ -62,6 +62,11 @@ AC_ARG_ENABLE(exa, + [EXA="$enableval"], + [EXA=yes]) + ++AC_ARG_WITH(xserver-source,AC_HELP_STRING([--with-xserver-source=XSERVER_SOURCE], ++ [Path to X server source tree]), ++ [ XSERVER_SOURCE="$withval" ], ++ [ XSERVER_SOURCE="" ]) ++ + # Checks for extensions + XORG_DRIVER_CHECK_EXT(XINERAMA, xineramaproto) + XORG_DRIVER_CHECK_EXT(RANDR, randrproto) +@@ -71,7 +76,7 @@ XORG_DRIVER_CHECK_EXT(XF86MISC, xf86miscproto) + XORG_DRIVER_CHECK_EXT(DPMSExtension, xextproto) + + # Checks for pkg-config packages +-PKG_CHECK_MODULES(XORG, [xorg-server >= 1.3 xproto fontsproto $REQUIRED_MODULES]) ++PKG_CHECK_MODULES(XORG, [xorg-server xproto fontsproto $REQUIRED_MODULES]) + sdkdir=$(pkg-config --variable=sdkdir xorg-server) + + # Checks for libraries. +@@ -112,6 +117,10 @@ if test "$DRI" = yes; then + fi + fi + ++CFLAGS="$XORG_CFLAGS" ++AC_CHECK_HEADER(xf86Modes.h,[XMODES=yes],[XMODES=no],[#include "xorg-server.h"]) ++CFLAGS="$save_CFLAGS" ++ + # Note that this is sort of inverted from drivers/ati/Imakefile in + # the monolith. We test for foo, not for !foo (i.e. ATMISC_CPIO, not + # ATIMISC_AVOID_CPIO), but the defines are negative. So beware. Oh yeah, +@@ -208,6 +217,48 @@ AC_CHECK_DECL(XSERVER_LIBPCIACCESS, + [XSERVER_LIBPCIACCESS=yes],[XSERVER_LIBPCIACCESS=no], + [#include "xorg-server.h"]) + ++AM_CONDITIONAL(XMODES, test "x$XMODES" = xno) ++ ++if test "x$XSERVER_SOURCE" = x; then ++ if test -d ../../xserver; then ++ XSERVER_SOURCE="`cd ../../xserver && pwd`" ++ fi ++fi ++ ++if test -d "$XSERVER_SOURCE"; then ++ case "$XSERVER_SOURCE" in ++ /*) ++ ;; ++ *) ++ XSERVER_SOURCE="`cd $XSERVER_SOURCE && pwd`" ++ esac ++ if test -f src/modes/xf86Modes.h; then ++ : ++ else ++ ln -sf $XSERVER_SOURCE/hw/xfree86/modes src/modes ++ fi ++ ++ if test -f src/parser/xf86Parser.h; then ++ : ++ else ++ ln -sf $XSERVER_SOURCE/hw/xfree86/parser src/parser ++ fi ++fi ++if test "x$XMODES" = xyes; then ++ AC_MSG_NOTICE([X server has new mode code]) ++ AC_DEFINE(XMODES, 1,[X server has built-in mode code]) ++ XMODES_CFLAGS= ++else ++ if test -f src/modes/xf86Modes.h -a -f src/parser/xf86Parser.h; then ++ AC_MSG_NOTICE([X server is missing new mode code, using local copy]) ++ else ++ AC_MSG_ERROR([Must have X server >= 1.3 source tree for mode setting code. Please specify --with-xserver-source]) ++ fi ++ XMODES_CFLAGS='-DXF86_MODES_RENAME -I$(top_srcdir)/src -I$(top_srcdir)/src/modes -I$(top_srcdir)/src/parser' ++fi ++ ++AC_SUBST([XMODES_CFLAGS]) ++ + CPPFLAGS="$SAVE_CPPFLAGS" + + AM_CONDITIONAL(USE_EXA, test "x$USE_EXA" = xyes) diff --git a/src/AtomBios/CD_Operations.c b/src/AtomBios/CD_Operations.c new file mode 100644 index 0000000..1e48f81 @@ -7691,10 +7787,10 @@ index 0000000..e557ac0 +//Without this file, compatibility will be broken among ASICs and BIOs vs. driver +//James H. Apr. 22/03 diff --git a/src/Makefile.am b/src/Makefile.am -index 5152577..fd870c4 100644 +index 5152577..3e0352b 100644 --- a/src/Makefile.am +++ b/src/Makefile.am -@@ -32,6 +32,22 @@ R128_DRI_SRCS = r128_dri.c +@@ -32,6 +32,38 @@ R128_DRI_SRCS = r128_dri.c RADEON_DRI_SRCS = radeon_dri.c endif @@ -7713,31 +7809,60 @@ index 5152577..fd870c4 100644 + AtomBios/includes/ObjectID.h \ + AtomBios/includes/regsdef.h + ++XMODE_SRCS=\ ++ local_xf86Rename.h \ ++ parser/xf86Parser.h \ ++ parser/xf86Optrec.h \ ++ modes/xf86Modes.h \ ++ modes/xf86Modes.c \ ++ modes/xf86cvt.c \ ++ modes/xf86Crtc.h \ ++ modes/xf86Crtc.c \ ++ modes/xf86Cursors.c \ ++ modes/xf86EdidModes.c \ ++ modes/xf86RandR12.c \ ++ modes/xf86RandR12.h \ ++ modes/xf86Rename.h \ ++ modes/xf86Rotate.c \ ++ modes/xf86DiDGA.c + if ATIMISC_CPIO ATIMISC_CPIO_SOURCES = ativga.c ativgaio.c atibank.c atiwonder.c atiwonderio.c endif -@@ -45,7 +61,8 @@ ATIMISC_EXA_SOURCES = atimach64exa.c +@@ -45,7 +77,8 @@ ATIMISC_EXA_SOURCES = atimach64exa.c RADEON_EXA_SOURCES = radeon_exa.c endif -AM_CFLAGS = @XORG_CFLAGS@ @DRI_CFLAGS@ -+AM_CFLAGS = @XORG_CFLAGS@ @DRI_CFLAGS@ -DDISABLE_EASF -DENABLE_ALL_SERVICE_FUNCTIONS -DATOM_BIOS -DATOM_BIOS_PARSER ++AM_CFLAGS = @XORG_CFLAGS@ @DRI_CFLAGS@ @XMODES_CFLAGS@ -DDISABLE_EASF -DENABLE_ALL_SERVICE_FUNCTIONS -DATOM_BIOS -DATOM_BIOS_PARSER +INCLUDES = -I$(srcdir)/AtomBios/includes ati_drv_la_LTLIBRARIES = ati_drv.la ati_drv_la_LDFLAGS = -module -avoid-version -@@ -85,7 +102,8 @@ radeon_drv_la_SOURCES = \ +@@ -85,7 +118,13 @@ radeon_drv_la_SOURCES = \ radeon_driver.c radeon_video.c radeon_bios.c radeon_mm_i2c.c \ radeon_vip.c radeon_misc.c radeon_probe.c radeon_display.c \ radeon_crtc.c radeon_output.c radeon_modes.c radeon_tv.c \ - $(RADEON_DRI_SRCS) $(RADEON_EXA_SOURCES) + $(RADEON_ATOMBIOS_SOURCES) radeon_atombios.c radeon_atomwrapper.c \ + $(RADEON_DRI_SRCS) $(RADEON_EXA_SOURCES) atombios_output.c atombios_crtc.c ++ ++if XMODES ++radeon_drv_la_SOURCES += \ ++ $(XMODE_SRCS) ++endif theatre_detect_drv_la_LTLIBRARIES = theatre_detect_drv.la theatre_detect_drv_la_LDFLAGS = -module -avoid-version -@@ -185,6 +203,7 @@ EXTRA_DIST = \ +@@ -109,6 +148,7 @@ theatre200_drv_la_SOURCES = \ + theatre200.c theatre200_module.c + + EXTRA_DIST = \ ++ $(XMODE_SRCS) \ + atimach64render.c \ + radeon_render.c \ + radeon_accelfuncs.c \ +@@ -185,6 +225,7 @@ EXTRA_DIST = \ radeon_version.h \ radeon_video.h \ radeon_tv.h \ @@ -7745,7 +7870,7 @@ index 5152577..fd870c4 100644 theatre200.h \ theatre_detect.h \ theatre.h \ -@@ -196,4 +215,5 @@ EXTRA_DIST = \ +@@ -196,4 +237,5 @@ EXTRA_DIST = \ radeon_chipset_gen.h \ radeon_pci_chipset_gen.h \ pcidb/ati_pciids.csv \ @@ -7914,10 +8039,10 @@ index f24f8fb..2953964 100644 diff --git a/src/atombios_crtc.c b/src/atombios_crtc.c new file mode 100644 -index 0000000..5c2d261 +index 0000000..e7ad4a9 --- /dev/null +++ b/src/atombios_crtc.c -@@ -0,0 +1,433 @@ +@@ -0,0 +1,381 @@ + /* + * Copyright © 2007 Red Hat, Inc. + * @@ -8068,82 +8193,6 @@ index 0000000..5c2d261 + return ATOM_NOT_IMPLEMENTED; +} + -+/* -+ * Calculate the PLL parameters for a given dotclock. -+ */ -+#define RADEON_PLL_DEFAULT_PLLOUT_MIN 64800 /* experimental. - taken from rhd divided by 10 */ -+ -+static Bool -+PLLCalculate(ScrnInfoPtr pScrn, CARD32 PixelClock, -+ CARD16 *RefDivider, CARD16 *FBDivider, CARD8 *PostDivider) -+{ -+/* limited by the number of bits available */ -+#define FB_DIV_LIMIT 1024 /* rv6x0 doesn't like 2048 */ -+#define REF_DIV_LIMIT 1024 -+#define POST_DIV_LIMIT 128 -+ RADEONInfoPtr info = RADEONPTR (pScrn); -+ RADEONPLLPtr pll = &info->pll; -+ CARD32 FBDiv, RefDiv, PostDiv, BestDiff = 0xFFFFFFFF; -+ float Ratio; -+ -+ Ratio = ((float) PixelClock) / ((float) pll->reference_freq * 10); -+ -+ if (pll->min_pll_freq == 0) -+ pll->min_pll_freq = RADEON_PLL_DEFAULT_PLLOUT_MIN; -+ for (PostDiv = 2; PostDiv < POST_DIV_LIMIT; PostDiv++) { -+ CARD32 VCOOut = PixelClock * PostDiv; -+ -+ /* we are conservative and avoid the limits */ -+ if (VCOOut <= pll->min_pll_freq * 10) -+ continue; -+ if (VCOOut >= pll->max_pll_freq * 10) -+ break; -+ -+ for (RefDiv = 1; RefDiv <= REF_DIV_LIMIT; RefDiv++) -+ { -+ CARD32 Diff; -+ -+ FBDiv = (CARD32) ((Ratio * PostDiv * RefDiv) + 0.5); -+ -+ if (FBDiv >= FB_DIV_LIMIT) -+ break; -+ -+ if (FBDiv > (500 + (13 * RefDiv))) /* rv6x0 limit */ -+ break; -+ -+ Diff = abs( PixelClock - (FBDiv * pll->reference_freq * 10) / (PostDiv * RefDiv) ); -+ -+ if (Diff < BestDiff) { -+ *FBDivider = FBDiv; -+ *RefDivider = RefDiv; -+ *PostDivider = PostDiv; -+ BestDiff = Diff; -+ } -+ -+ if (BestDiff == 0) -+ break; -+ } -+ if (BestDiff == 0) -+ break; -+ } -+ -+ if (BestDiff != 0xFFFFFFFF) { -+ ErrorF("PLL Calculation: %dkHz = " -+ "(((0x%X / 0x%X) * 0x%X) / 0x%X) (%dkHz off)\n", -+ (int) PixelClock, (unsigned int) pll->reference_freq * 10, *RefDivider, -+ *FBDivider, *PostDivider, (int) BestDiff); -+ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "PLL for %dkHz uses %dkHz internally.\n", -+ (int) PixelClock, -+ (int) (pll->reference_freq * 10 * *FBDivider) / *RefDivider); -+ return TRUE; -+ } else { /* Should never happen */ -+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR, -+ "%s: Failed to get a valid PLL setting for %dkHz\n", -+ __func__, (int) PixelClock); -+ return FALSE; -+ } -+} -+ +void +atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode) +{ @@ -8151,51 +8200,51 @@ index 0000000..5c2d261 + RADEONInfoPtr info = RADEONPTR(crtc->scrn); + unsigned char *RADEONMMIO = info->MMIO; + int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock); -+ int sclock = mode->Clock; -+ uint16_t ref_div = 0, fb_div = 0; -+ uint8_t post_div = 0; ++ CARD32 sclock = mode->Clock; ++ CARD32 ref_div = 0, fb_div = 0, post_div = 0; + int major, minor; + SET_PIXEL_CLOCK_PS_ALLOCATION spc_param; + void *ptr; + AtomBiosArgRec data; -+ unsigned char *space; -+ RADEONSavePtr save = &info->ModeReg; -+ ++ unsigned char *space; ++ RADEONSavePtr save = info->ModeReg; ++ + if (IS_AVIVO_VARIANT) { -+ CARD32 temp; -+ PLLCalculate(crtc->scrn, sclock, &ref_div, &fb_div, &post_div); ++ CARD32 temp; ++ RADEONComputePLL(&info->pll, mode->Clock, &temp, &fb_div, &ref_div, &post_div, 0); ++ sclock = temp; + + /* disable spread spectrum clocking for now -- thanks Hedy Lamarr */ + if (radeon_crtc->crtc_id == 0) { -+ temp = INREG(AVIVO_P1PLL_INT_SS_CNTL); -+ OUTREG(AVIVO_P1PLL_INT_SS_CNTL, temp & ~1); -+ } else { -+ temp = INREG(AVIVO_P2PLL_INT_SS_CNTL); -+ OUTREG(AVIVO_P2PLL_INT_SS_CNTL, temp & ~1); -+ } ++ temp = INREG(AVIVO_P1PLL_INT_SS_CNTL); ++ OUTREG(AVIVO_P1PLL_INT_SS_CNTL, temp & ~1); ++ } else { ++ temp = INREG(AVIVO_P2PLL_INT_SS_CNTL); ++ OUTREG(AVIVO_P2PLL_INT_SS_CNTL, temp & ~1); ++ } + } else { -+ sclock = save->dot_clock_freq * 10; ++ sclock = save->dot_clock_freq; + fb_div = save->feedback_div; + post_div = save->post_div; + ref_div = save->ppll_ref_div; + } + + xf86DrvMsg(crtc->scrn->scrnIndex, X_INFO, -+ "crtc(%d) Clock: mode %d, PLL %d\n", -+ radeon_crtc->crtc_id, mode->Clock, sclock); ++ "crtc(%d) Clock: mode %d, PLL %u\n", ++ radeon_crtc->crtc_id, mode->Clock, sclock * 10); + xf86DrvMsg(crtc->scrn->scrnIndex, X_INFO, -+ "crtc(%d) PLL : refdiv %d, fbdiv 0x%X(%d), pdiv %d\n", ++ "crtc(%d) PLL : refdiv %u, fbdiv 0x%X(%u), pdiv %u\n", + radeon_crtc->crtc_id, ref_div, fb_div, fb_div, post_div); + + atombios_get_command_table_version(info->atomBIOS, index, &major, &minor); -+ ++ + ErrorF("table is %d %d\n", major, minor); + switch(major) { + case 1: + switch(minor) { + case 1: + case 2: { -+ spc_param.sPCLKInput.usPixelClock = sclock / 10; ++ spc_param.sPCLKInput.usPixelClock = sclock; + spc_param.sPCLKInput.usRefDiv = ref_div; + spc_param.sPCLKInput.usFbDiv = fb_div; + spc_param.sPCLKInput.ucPostDiv = post_div; @@ -8224,7 +8273,7 @@ index 0000000..5c2d261 + ErrorF("Set CRTC PLL success\n"); + return; + } -+ ++ + ErrorF("Set CRTC PLL failed\n"); + return; +} @@ -8281,8 +8330,8 @@ index 0000000..5c2d261 + ErrorF("Mode %dx%d - %d %d %d\n", adjusted_mode->CrtcHDisplay, adjusted_mode->CrtcVDisplay, + adjusted_mode->CrtcHTotal, adjusted_mode->CrtcVTotal, adjusted_mode->Flags); + -+ RADEONInitMemMapRegisters(pScrn, &info->ModeReg, info); -+ RADEONRestoreMemMapRegisters(pScrn, &info->ModeReg); ++ RADEONInitMemMapRegisters(pScrn, info->ModeReg, info); ++ RADEONRestoreMemMapRegisters(pScrn, info->ModeReg); + + if (IS_AVIVO_VARIANT) { + radeon_crtc->fb_width = adjusted_mode->CrtcHDisplay; @@ -8303,7 +8352,8 @@ index 0000000..5c2d261 + default: + FatalError("Unsupported screen depth: %d\n", xf86GetDepth()); + } -+ if (info->tilingEnabled) { ++ ++ if (info->tilingEnabled && (crtc->rotatedData == NULL)) { + radeon_crtc->fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE; + } + @@ -8314,24 +8364,47 @@ index 0000000..5c2d261 + + /* setup fb format and location + */ -+ OUTREG(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset, (x << 16) | y); -+ OUTREG(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset, -+ (mode->HDisplay << 16) | mode->VDisplay); ++ if (crtc->rotatedData != NULL) { ++ /* x/y offset is already included */ ++ x = 0; ++ y = 0; ++ fb_location = fb_location + (char *)crtc->rotatedData - (char *)info->FB; ++ } ++ ++ /* lock the grph regs */ ++ OUTREG(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, AVIVO_D1GRPH_UPDATE_LOCK); + + OUTREG(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, fb_location); + OUTREG(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, fb_location); + OUTREG(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, + radeon_crtc->fb_format); + ++ OUTREG(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); ++ OUTREG(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); ++ OUTREG(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0); ++ OUTREG(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0); + OUTREG(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, + crtc->scrn->virtualX); + OUTREG(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, + crtc->scrn->virtualY); + OUTREG(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, + crtc->scrn->displayWidth); -+ + OUTREG(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1); + ++ /* unlock the grph regs */ ++ OUTREG(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, 0); ++ ++ /* lock the mode regs */ ++ OUTREG(AVIVO_D1SCL_UPDATE + radeon_crtc->crtc_offset, AVIVO_D1SCL_UPDATE_LOCK); ++ ++ OUTREG(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, ++ crtc->scrn->virtualY); ++ OUTREG(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset, (x << 16) | y); ++ OUTREG(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset, ++ (mode->HDisplay << 16) | mode->VDisplay); ++ /* unlock the mode regs */ ++ OUTREG(AVIVO_D1SCL_UPDATE + radeon_crtc->crtc_offset, 0); ++ + } + + atombios_crtc_set_pll(crtc, adjusted_mode); @@ -9113,126 +9186,207 @@ index f201cc4..a62e8a5 100644 +"0x958D","RV630_958D","RV630",,,,,,"ATI FireGL V3600" +"0x958E","RV630_958E","RV630",,,,,,"ATI ATI Radeon HD 2600 LE" diff --git a/src/radeon.h b/src/radeon.h -index fe491e8..2870ef5 100644 +index 03db360..7d57ca5 100644 --- a/src/radeon.h +++ b/src/radeon.h -@@ -200,7 +200,107 @@ typedef struct { +@@ -200,189 +200,26 @@ typedef struct { CARD16 rr4_offset; } RADEONBIOSInitTable; -+struct avivo_pll_state { -+ CARD32 ref_div_src; -+ CARD32 ref_div; -+ CARD32 fb_div; -+ CARD32 post_div_src; -+ CARD32 post_div; -+ CARD32 ext_ppll_cntl; -+ CARD32 pll_cntl; -+ CARD32 int_ss_cntl; -+}; -+ -+struct avivo_crtc_state { -+ CARD32 pll_source; -+ CARD32 h_total; -+ CARD32 h_blank_start_end; -+ CARD32 h_sync_a; -+ CARD32 h_sync_a_cntl; -+ CARD32 h_sync_b; -+ CARD32 h_sync_b_cntl; -+ CARD32 v_total; -+ CARD32 v_blank_start_end; -+ CARD32 v_sync_a; -+ CARD32 v_sync_a_cntl; -+ CARD32 v_sync_b; -+ CARD32 v_sync_b_cntl; -+ CARD32 control; -+ CARD32 blank_control; -+ CARD32 interlace_control; -+ CARD32 stereo_control; -+ CARD32 cursor_control; -+}; -+ -+struct avivo_grph_state { -+ CARD32 enable; -+ CARD32 control; -+ CARD32 prim_surf_addr; -+ CARD32 sec_surf_addr; -+ CARD32 pitch; -+ CARD32 x_offset; -+ CARD32 y_offset; -+ CARD32 x_start; -+ CARD32 y_start; -+ CARD32 x_end; -+ CARD32 y_end; -+ -+ CARD32 viewport_start; -+ CARD32 viewport_size; -+ CARD32 scl_enable; -+}; -+ -+struct avivo_dac_state { -+ CARD32 enable; -+ CARD32 source_select; -+ CARD32 force_output_cntl; -+ CARD32 powerdown; -+}; -+ -+struct avivo_dig_state { -+ CARD32 cntl; -+ CARD32 bit_depth_cntl; -+ CARD32 data_sync; -+ CARD32 transmitter_enable; -+ CARD32 transmitter_cntl; -+ CARD32 source_select; -+}; -+ -+struct avivo_state -+{ -+ CARD32 hdp_fb_location; -+ CARD32 mc_memory_map; -+ CARD32 vga_memory_base; -+ CARD32 vga_fb_start; -+ -+ CARD32 vga1_cntl; -+ CARD32 vga2_cntl; -+ -+ CARD32 crtc_master_en; -+ CARD32 crtc_tv_control; -+ -+ CARD32 lvtma_pwrseq_cntl; -+ CARD32 lvtma_pwrseq_state; -+ -+ struct avivo_pll_state pll1; -+ struct avivo_pll_state pll2; -+ -+ struct avivo_crtc_state crtc1; -+ struct avivo_crtc_state crtc2; -+ -+ struct avivo_grph_state grph1; -+ struct avivo_grph_state grph2; -+ -+ struct avivo_dac_state daca; -+ struct avivo_dac_state dacb; -+ -+ struct avivo_dig_state tmds1; -+ struct avivo_dig_state tmds2; -+ -+}; -+ +-typedef struct { +- /* Common registers */ +- CARD32 ovr_clr; +- CARD32 ovr_wid_left_right; +- CARD32 ovr_wid_top_bottom; +- CARD32 ov0_scale_cntl; +- CARD32 mpp_tb_config; +- CARD32 mpp_gp_config; +- CARD32 subpic_cntl; +- CARD32 viph_control; +- CARD32 i2c_cntl_1; +- CARD32 gen_int_cntl; +- CARD32 cap0_trig_cntl; +- CARD32 cap1_trig_cntl; +- CARD32 bus_cntl; +- CARD32 bios_4_scratch; +- CARD32 bios_5_scratch; +- CARD32 bios_6_scratch; +- CARD32 surface_cntl; +- CARD32 surfaces[8][3]; +- CARD32 mc_agp_location; +- CARD32 mc_fb_location; +- CARD32 display_base_addr; +- CARD32 display2_base_addr; +- CARD32 ov0_base_addr; +- +- /* Other registers to save for VT switches */ +- CARD32 dp_datatype; +- CARD32 rbbm_soft_reset; +- CARD32 clock_cntl_index; +- CARD32 amcgpio_en_reg; +- CARD32 amcgpio_mask; +- +- /* CRTC registers */ +- CARD32 crtc_gen_cntl; +- CARD32 crtc_ext_cntl; +- CARD32 dac_cntl; +- CARD32 crtc_h_total_disp; +- CARD32 crtc_h_sync_strt_wid; +- CARD32 crtc_v_total_disp; +- CARD32 crtc_v_sync_strt_wid; +- CARD32 crtc_offset; +- CARD32 crtc_offset_cntl; +- CARD32 crtc_pitch; +- CARD32 disp_merge_cntl; +- CARD32 grph_buffer_cntl; +- CARD32 crtc_more_cntl; +- CARD32 crtc_tile_x0_y0; +- +- /* CRTC2 registers */ +- CARD32 crtc2_gen_cntl; +- CARD32 dac_macro_cntl; +- CARD32 dac2_cntl; +- CARD32 disp_output_cntl; +- CARD32 disp_tv_out_cntl; +- CARD32 disp_hw_debug; +- CARD32 disp2_merge_cntl; +- CARD32 grph2_buffer_cntl; +- CARD32 crtc2_h_total_disp; +- CARD32 crtc2_h_sync_strt_wid; +- CARD32 crtc2_v_total_disp; +- CARD32 crtc2_v_sync_strt_wid; +- CARD32 crtc2_offset; +- CARD32 crtc2_offset_cntl; +- CARD32 crtc2_pitch; +- CARD32 crtc2_tile_x0_y0; +- +- /* Flat panel registers */ +- CARD32 fp_crtc_h_total_disp; +- CARD32 fp_crtc_v_total_disp; +- CARD32 fp_gen_cntl; +- CARD32 fp2_gen_cntl; +- CARD32 fp_h_sync_strt_wid; +- CARD32 fp_h2_sync_strt_wid; +- CARD32 fp_horz_stretch; +- CARD32 fp_panel_cntl; +- CARD32 fp_v_sync_strt_wid; +- CARD32 fp_v2_sync_strt_wid; +- CARD32 fp_vert_stretch; +- CARD32 lvds_gen_cntl; +- CARD32 lvds_pll_cntl; +- CARD32 tmds_pll_cntl; +- CARD32 tmds_transmitter_cntl; +- +- /* Computed values for PLL */ +- CARD32 dot_clock_freq; +- CARD32 pll_output_freq; +- int feedback_div; +- int reference_div; +- int post_div; +- +- /* PLL registers */ +- unsigned ppll_ref_div; +- unsigned ppll_div_3; +- CARD32 htotal_cntl; +- CARD32 vclk_ecp_cntl; +- +- /* Computed values for PLL2 */ +- CARD32 dot_clock_freq_2; +- CARD32 pll_output_freq_2; +- int feedback_div_2; +- int reference_div_2; +- int post_div_2; +- +- /* PLL2 registers */ +- CARD32 p2pll_ref_div; +- CARD32 p2pll_div_0; +- CARD32 htotal_cntl2; +- CARD32 pixclks_cntl; +- +- /* Pallet */ +- Bool palette_valid; +- CARD32 palette[256]; +- CARD32 palette2[256]; +- +- CARD32 rs480_unk_e30; +- CARD32 rs480_unk_e34; +- CARD32 rs480_unk_e38; +- CARD32 rs480_unk_e3c; +- +- /* TV out registers */ +- CARD32 tv_master_cntl; +- CARD32 tv_htotal; +- CARD32 tv_hsize; +- CARD32 tv_hdisp; +- CARD32 tv_hstart; +- CARD32 tv_vtotal; +- CARD32 tv_vdisp; +- CARD32 tv_timing_cntl; +- CARD32 tv_vscaler_cntl1; +- CARD32 tv_vscaler_cntl2; +- CARD32 tv_sync_size; +- CARD32 tv_vrestart; +- CARD32 tv_hrestart; +- CARD32 tv_frestart; +- CARD32 tv_ftotal; +- CARD32 tv_clock_sel_cntl; +- CARD32 tv_clkout_cntl; +- CARD32 tv_data_delay_a; +- CARD32 tv_data_delay_b; +- CARD32 tv_dac_cntl; +- CARD32 tv_pll_cntl; +- CARD32 tv_pll_cntl1; +- CARD32 tv_pll_fine_cntl; +- CARD32 tv_modulator_cntl1; +- CARD32 tv_modulator_cntl2; +- CARD32 tv_frame_lock_cntl; +- CARD32 tv_pre_dac_mux_cntl; +- CARD32 tv_rgb_cntl; +- CARD32 tv_y_saw_tooth_cntl; +- CARD32 tv_y_rise_cntl; +- CARD32 tv_y_fall_cntl; +- CARD32 tv_uv_adr; +- CARD32 tv_upsamp_and_gain_cntl; +- CARD32 tv_gain_limit_settings; +- CARD32 tv_linear_gain_settings; +- CARD32 tv_crc_cntl; +- CARD32 tv_sync_cntl; +- CARD32 gpiopad_a; +- CARD32 pll_test_cntl; +- +- CARD16 h_code_timing[MAX_H_CODE_TIMING_LEN]; +- CARD16 v_code_timing[MAX_V_CODE_TIMING_LEN]; +- +-} RADEONSaveRec, *RADEONSavePtr; +- + #define RADEON_PLL_USE_BIOS_DIVS (1 << 0) + #define RADEON_PLL_NO_ODD_POST_DIV (1 << 1) + #define RADEON_PLL_USE_REF_DIV (1 << 2) ++#define RADEON_PLL_LEGACY (1 << 3) + typedef struct { -+ struct avivo_state avivo; - /* Common registers */ - CARD32 ovr_clr; - CARD32 ovr_wid_left_right; -@@ -221,6 +321,7 @@ typedef struct { - CARD32 surface_cntl; - CARD32 surfaces[8][3]; - CARD32 mc_agp_location; -+ CARD32 mc_agp_location_hi; - CARD32 mc_fb_location; - CARD32 display_base_addr; - CARD32 display2_base_addr; -@@ -401,6 +502,18 @@ typedef enum { + CARD16 reference_freq; + CARD16 reference_div; +- CARD32 min_pll_freq; +- CARD32 max_pll_freq; ++ CARD32 pll_in_min; ++ CARD32 pll_in_max; ++ CARD32 pll_out_min; ++ CARD32 pll_out_max; + CARD16 xclk; + + CARD32 min_ref_div; + CARD32 max_ref_div; ++ CARD32 min_post_div; ++ CARD32 max_post_div; + CARD32 min_feedback_div; + CARD32 max_feedback_div; +- CARD32 pll_in_min; +- CARD32 pll_in_max; + CARD32 best_vco; + } RADEONPLLRec, *RADEONPLLPtr; + +@@ -415,6 +252,18 @@ typedef enum { CHIP_FAMILY_R420, /* R420/R423/M18 */ CHIP_FAMILY_RV410, /* RV410, M26 */ CHIP_FAMILY_RS400, /* xpress 200, 200m (RS400/410/480) */ @@ -9251,7 +9405,7 @@ index fe491e8..2870ef5 100644 CHIP_FAMILY_LAST } RADEONChipFamily; -@@ -421,6 +534,8 @@ typedef enum { +@@ -435,6 +284,8 @@ typedef enum { (info->ChipFamily == CHIP_FAMILY_RV410) || \ (info->ChipFamily == CHIP_FAMILY_RS400)) @@ -9260,7 +9414,7 @@ index fe491e8..2870ef5 100644 /* * Errata workarounds */ -@@ -455,6 +570,8 @@ typedef enum { +@@ -469,6 +320,8 @@ typedef enum { CARD_PCIE } RADEONCardType; @@ -9269,7 +9423,7 @@ index fe491e8..2870ef5 100644 typedef struct { CARD32 pci_device_id; RADEONChipFamily chip_family; -@@ -480,6 +597,7 @@ typedef struct { +@@ -494,6 +347,7 @@ typedef struct { CARD32 gartLocation; CARD32 mc_fb_location; CARD32 mc_agp_location; @@ -9277,7 +9431,18 @@ index fe491e8..2870ef5 100644 void *MMIO; /* Map of MMIO region */ void *FB; /* Map of frame buffer */ -@@ -840,6 +958,10 @@ typedef struct { +@@ -536,8 +390,8 @@ typedef struct { + Bool IsDDR; + int DispPriority; + +- RADEONSaveRec SavedReg; /* Original (text) mode */ +- RADEONSaveRec ModeReg; /* Current mode */ ++ RADEONSavePtr SavedReg; /* Original (text) mode */ ++ RADEONSavePtr ModeReg; /* Current mode */ + Bool (*CloseScreen)(int, ScreenPtr); + + void (*BlockHandler)(int, pointer, pointer, pointer); +@@ -850,6 +704,10 @@ typedef struct { #endif RADEONExtTMDSChip ext_tmds_chip; @@ -9285,10 +9450,24 @@ index fe491e8..2870ef5 100644 + unsigned long FbFreeStart, FbFreeSize; + unsigned char* BIOSCopy; + + /* output enable masks for outputs shared across connectors */ + int output_crt1; + int output_crt2; +@@ -861,6 +719,13 @@ typedef struct { Rotation rotation; void (*PointerMoved)(int, int, int); CreateScreenResourcesProcPtr CreateScreenResources; -@@ -870,6 +992,9 @@ extern void RADEONEngineRestore(ScrnInfoPtr pScrn); ++ ++ ++ Bool IsSecondary; ++ Bool IsPrimary; ++ ++ Bool r600_shadow_fb; ++ void *fb_shadow; + } RADEONInfoRec, *RADEONInfoPtr; + + #define RADEONWaitForFifo(pScrn, entries) \ +@@ -888,6 +753,9 @@ extern void RADEONEngineRestore(ScrnInfoPtr pScrn); extern unsigned RADEONINPLL(ScrnInfoPtr pScrn, int addr); extern void RADEONOUTPLL(ScrnInfoPtr pScrn, int addr, CARD32 data); @@ -9298,8 +9477,17 @@ index fe491e8..2870ef5 100644 extern void RADEONWaitForVerticalSync(ScrnInfoPtr pScrn); extern void RADEONWaitForVerticalSync2(ScrnInfoPtr pScrn); +@@ -981,7 +849,7 @@ extern void RADEONBlank(ScrnInfoPtr pScrn); + extern void RADEONDisplayPowerManagementSet(ScrnInfoPtr pScrn, + int PowerManagementMode, + int flags); +-extern Bool RADEONAllocateControllers(ScrnInfoPtr pScrn); ++extern Bool RADEONAllocateControllers(ScrnInfoPtr pScrn, int mask); + extern Bool RADEONAllocateConnectors(ScrnInfoPtr pScrn); + extern int RADEONValidateMergeModes(ScrnInfoPtr pScrn); + extern int RADEONValidateDDCModes(ScrnInfoPtr pScrn1, char **ppModeName, diff --git a/src/radeon_accel.c b/src/radeon_accel.c -index 6028aff..4ce76cb 100644 +index ed7d1e9..5bf03f5 100644 --- a/src/radeon_accel.c +++ b/src/radeon_accel.c @@ -250,7 +250,7 @@ void RADEONEngineReset(ScrnInfoPtr pScrn) @@ -9320,6 +9508,15 @@ index 6028aff..4ce76cb 100644 OUTREG(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset); OUTREG(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index); +@@ -322,7 +322,7 @@ void RADEONEngineRestore(ScrnInfoPtr pScrn) + #endif + + /* Restore SURFACE_CNTL */ +- OUTREG(RADEON_SURFACE_CNTL, info->ModeReg.surface_cntl); ++ OUTREG(RADEON_SURFACE_CNTL, info->ModeReg->surface_cntl); + + RADEONWaitForFifo(pScrn, 1); + OUTREG(RADEON_DEFAULT_SC_BOTTOM_RIGHT, (RADEON_DEFAULT_SC_RIGHT_MAX @@ -853,6 +853,9 @@ Bool RADEONAccelInit(ScreenPtr pScreen) ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; RADEONInfoPtr info = RADEONPTR(pScrn); @@ -9345,7 +9542,7 @@ index 212131f..6fbbc13 100644 } else if ((info->ChipFamily == CHIP_FAMILY_RV250) || diff --git a/src/radeon_atombios.c b/src/radeon_atombios.c new file mode 100644 -index 0000000..9d17e47 +index 0000000..a04598d --- /dev/null +++ b/src/radeon_atombios.c @@ -0,0 +1,2625 @@ @@ -10794,7 +10991,7 @@ index 0000000..9d17e47 + ErrorF("record type %d\n", Record->ucRecordType); + switch (Record->ucRecordType) { + case ATOM_I2C_RECORD_TYPE: -+ rhdAtomParseI2CRecord(&info->atomBIOS, ++ rhdAtomParseI2CRecord(info->atomBIOS, + (ATOM_I2C_RECORD *)Record, + &info->BiosConnector[i].ddc_line); + break; @@ -11955,7 +12152,7 @@ index 0000000..9d17e47 +void +atombios_get_command_table_version(atomBiosHandlePtr atomBIOS, int index, int *major, int *minor) +{ -+ ATOM_MASTER_COMMAND_TABLE *cmd_table = atomBIOS->BIOSBase + atomBIOS->cmd_offset; ++ ATOM_MASTER_COMMAND_TABLE *cmd_table = (void *)(atomBIOS->BIOSBase + atomBIOS->cmd_offset); + ATOM_MASTER_LIST_OF_COMMAND_TABLES *table_start; + ATOM_COMMON_ROM_COMMAND_TABLE_HEADER *table_hdr; + @@ -11966,7 +12163,7 @@ index 0000000..9d17e47 + + offset = *(((unsigned short *)table_start) + index); + -+ table_hdr = atomBIOS->BIOSBase + offset; ++ table_hdr = (ATOM_COMMON_ROM_COMMAND_TABLE_HEADER *)(atomBIOS->BIOSBase + offset); + + *major = table_hdr->CommonHeader.ucTableFormatRevision; + *minor = table_hdr->CommonHeader.ucTableContentRevision; @@ -12360,7 +12557,7 @@ index 0000000..1e7cc77 + +#endif /* RHD_ATOMWRAPPER_H_ */ diff --git a/src/radeon_bios.c b/src/radeon_bios.c -index 1b46746..3043de6 100644 +index d150c4b..46a58ca 100644 --- a/src/radeon_bios.c +++ b/src/radeon_bios.c @@ -39,8 +39,32 @@ @@ -12396,7 +12593,7 @@ index 1b46746..3043de6 100644 /* Read the Video BIOS block and the FP registers (if applicable). */ Bool RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10) { -@@ -131,66 +155,115 @@ Bool RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10) +@@ -130,66 +154,115 @@ Bool RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10) else info->IsAtomBios = FALSE; @@ -12515,11 +12712,11 @@ index 1b46746..3043de6 100644 + info->BiosConnector[i].ddc_line = 0; + else + info->BiosConnector[i].ddc_line = gpio; -+ -+ info->BiosConnector[i].output_id = id; -+ info->BiosConnector[i].devices = (1 << i); - if (i == 3) ++ info->BiosConnector[i].output_id = id; ++ info->BiosConnector[i].devices = (1 << i); ++ + if (i == ATOM_DEVICE_DFP1_INDEX) info->BiosConnector[i].TMDSType = TMDS_INT; - else if (i == 7) @@ -12544,7 +12741,7 @@ index 1b46746..3043de6 100644 } else { info->BiosConnector[i].valid = FALSE; } -@@ -200,23 +273,39 @@ static Bool RADEONGetATOMConnectorInfoFromBIOS (ScrnInfoPtr pScrn) +@@ -199,23 +272,39 @@ static Bool RADEONGetATOMConnectorInfoFromBIOS (ScrnInfoPtr pScrn) return FALSE; } @@ -12596,7 +12793,7 @@ index 1b46746..3043de6 100644 info->BiosConnector[i].TMDSType, info->BiosConnector[i].ConnectorType); } } -@@ -228,6 +317,8 @@ static Bool RADEONGetLegacyConnectorInfoFromBIOS (ScrnInfoPtr pScrn) +@@ -227,6 +316,8 @@ static Bool RADEONGetLegacyConnectorInfoFromBIOS (ScrnInfoPtr pScrn) { RADEONInfoPtr info = RADEONPTR (pScrn); int offset, i, entry, tmp, tmp0, tmp1; @@ -12605,7 +12802,7 @@ index 1b46746..3043de6 100644 if (!info->VBIOS) return FALSE; -@@ -242,7 +333,55 @@ static Bool RADEONGetLegacyConnectorInfoFromBIOS (ScrnInfoPtr pScrn) +@@ -241,7 +332,55 @@ static Bool RADEONGetLegacyConnectorInfoFromBIOS (ScrnInfoPtr pScrn) info->BiosConnector[i].valid = TRUE; tmp = RADEON_BIOS16(entry); info->BiosConnector[i].ConnectorType = (tmp >> 12) & 0xf; @@ -12662,7 +12859,7 @@ index 1b46746..3043de6 100644 info->BiosConnector[i].DACType = tmp & 0x1; info->BiosConnector[i].TMDSType = (tmp >> 4) & 0x1; -@@ -252,29 +391,22 @@ static Bool RADEONGetLegacyConnectorInfoFromBIOS (ScrnInfoPtr pScrn) +@@ -251,29 +390,22 @@ static Bool RADEONGetLegacyConnectorInfoFromBIOS (ScrnInfoPtr pScrn) * lets see what happens with that. */ if (info->ChipFamily == CHIP_FAMILY_RS400 && @@ -12696,7 +12893,7 @@ index 1b46746..3043de6 100644 } } else { xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "No Connector Info Table found!\n"); -@@ -286,7 +418,7 @@ static Bool RADEONGetLegacyConnectorInfoFromBIOS (ScrnInfoPtr pScrn) +@@ -285,7 +417,7 @@ static Bool RADEONGetLegacyConnectorInfoFromBIOS (ScrnInfoPtr pScrn) offset = RADEON_BIOS16(info->ROMHeaderStart + 0x40); if (offset) { info->BiosConnector[4].valid = TRUE; @@ -12705,7 +12902,7 @@ index 1b46746..3043de6 100644 info->BiosConnector[4].DACType = DAC_NONE; info->BiosConnector[4].TMDSType = TMDS_NONE; -@@ -295,19 +427,36 @@ static Bool RADEONGetLegacyConnectorInfoFromBIOS (ScrnInfoPtr pScrn) +@@ -294,19 +426,36 @@ static Bool RADEONGetLegacyConnectorInfoFromBIOS (ScrnInfoPtr pScrn) tmp0 = RADEON_BIOS16(tmp + 0x15); if (tmp0) { tmp1 = RADEON_BIOS8(tmp0+2) & 0x07; @@ -12750,7 +12947,7 @@ index 1b46746..3043de6 100644 } } } -@@ -322,7 +471,7 @@ static Bool RADEONGetLegacyConnectorInfoFromBIOS (ScrnInfoPtr pScrn) +@@ -321,7 +470,7 @@ static Bool RADEONGetLegacyConnectorInfoFromBIOS (ScrnInfoPtr pScrn) info->BiosConnector[5].ConnectorType = CONNECTOR_STV; info->BiosConnector[5].DACType = DAC_TVDAC; info->BiosConnector[5].TMDSType = TMDS_NONE; @@ -12759,7 +12956,7 @@ index 1b46746..3043de6 100644 } } } -@@ -330,8 +479,8 @@ static Bool RADEONGetLegacyConnectorInfoFromBIOS (ScrnInfoPtr pScrn) +@@ -329,8 +478,8 @@ static Bool RADEONGetLegacyConnectorInfoFromBIOS (ScrnInfoPtr pScrn) xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Bios Connector table: \n"); for (i = 0; i < RADEON_MAX_BIOS_CONNECTOR; i++) { if (info->BiosConnector[i].valid) { @@ -12770,6 +12967,55 @@ index 1b46746..3043de6 100644 info->BiosConnector[i].TMDSType, info->BiosConnector[i].ConnectorType); } } +@@ -462,8 +611,19 @@ Bool RADEONGetClockInfoFromBIOS (ScrnInfoPtr pScrn) + or use a new algorithm to calculate + from min_input and max_input + */ +- pll->min_pll_freq = RADEON_BIOS16 (pll_info_block + 78); +- pll->max_pll_freq = RADEON_BIOS32 (pll_info_block + 32); ++ pll->pll_out_min = RADEON_BIOS16 (pll_info_block + 78); ++ pll->pll_out_max = RADEON_BIOS32 (pll_info_block + 32); ++ ++ if (pll->pll_out_min == 0) { ++ if (IS_AVIVO_VARIANT) ++ pll->pll_out_min = 64800; ++ else ++ pll->pll_out_min = 20000; ++ } ++ ++ pll->pll_in_min = RADEON_BIOS16 (pll_info_block + 74); ++ pll->pll_in_max = RADEON_BIOS16 (pll_info_block + 76); ++ + pll->xclk = RADEON_BIOS16 (pll_info_block + 72); + + info->sclk = RADEON_BIOS32(pll_info_block + 8) / 100.0; +@@ -473,8 +633,13 @@ Bool RADEONGetClockInfoFromBIOS (ScrnInfoPtr pScrn) + + pll->reference_freq = RADEON_BIOS16 (pll_info_block + 0x0e); + pll->reference_div = RADEON_BIOS16 (pll_info_block + 0x10); +- pll->min_pll_freq = RADEON_BIOS32 (pll_info_block + 0x12); +- pll->max_pll_freq = RADEON_BIOS32 (pll_info_block + 0x16); ++ pll->pll_out_min = RADEON_BIOS32 (pll_info_block + 0x12); ++ pll->pll_out_max = RADEON_BIOS32 (pll_info_block + 0x16); ++ ++ /* not available in the bios */ ++ pll->pll_in_min = 40; ++ pll->pll_in_max = 500; ++ + pll->xclk = RADEON_BIOS16 (pll_info_block + 0x08); + + info->sclk = RADEON_BIOS16(pll_info_block + 8) / 100.0; +@@ -487,8 +652,8 @@ Bool RADEONGetClockInfoFromBIOS (ScrnInfoPtr pScrn) + + xf86DrvMsg(pScrn->scrnIndex, X_INFO, "ref_freq: %d, min_pll: %u, " + "max_pll: %u, xclk: %d, sclk: %f, mclk: %f\n", +- pll->reference_freq, (unsigned)pll->min_pll_freq, +- (unsigned)pll->max_pll_freq, pll->xclk, info->sclk, ++ pll->reference_freq, (unsigned)pll->pll_out_min, ++ (unsigned)pll->pll_out_max, pll->xclk, info->sclk, + info->mclk); + + return TRUE; diff --git a/src/radeon_chipinfo_gen.h b/src/radeon_chipinfo_gen.h index a12b225..cf70557 100644 --- a/src/radeon_chipinfo_gen.h @@ -13058,7 +13304,7 @@ index 0a7a9c1..9f15b3d 100644 { -1, NULL } }; diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c -index b1d216d..e288352 100644 +index 07857dd..8e66518 100644 --- a/src/radeon_crtc.c +++ b/src/radeon_crtc.c @@ -55,6 +55,12 @@ @@ -13098,7 +13344,7 @@ index b1d216d..e288352 100644 radeon_crtc_dpms(crtc, DPMSModeOff); } -@@ -168,7 +182,7 @@ RADEONInitSurfaceCntl(xf86CrtcPtr crtc, RADEONSavePtr save) +@@ -166,7 +180,7 @@ RADEONInitSurfaceCntl(xf86CrtcPtr crtc, RADEONSavePtr save) } @@ -13107,7 +13353,7 @@ index b1d216d..e288352 100644 RADEONInitCrtcBase(xf86CrtcPtr crtc, RADEONSavePtr save, int x, int y) { -@@ -286,7 +300,7 @@ RADEONInitCrtcBase(xf86CrtcPtr crtc, RADEONSavePtr save, +@@ -284,7 +298,7 @@ RADEONInitCrtcBase(xf86CrtcPtr crtc, RADEONSavePtr save, } /* Define CRTC registers for requested video mode */ @@ -13116,7 +13362,40 @@ index b1d216d..e288352 100644 RADEONInitCrtcRegisters(xf86CrtcPtr crtc, RADEONSavePtr save, DisplayModePtr mode) { -@@ -399,7 +413,7 @@ RADEONInitCrtcRegisters(xf86CrtcPtr crtc, RADEONSavePtr save, +@@ -309,7 +323,7 @@ RADEONInitCrtcRegisters(xf86CrtcPtr crtc, RADEONSavePtr save, + return FALSE; + } + +- /*save->bios_4_scratch = info->SavedReg.bios_4_scratch;*/ ++ /*save->bios_4_scratch = info->SavedReg->bios_4_scratch;*/ + save->crtc_gen_cntl = (RADEON_CRTC_EXT_DISP_EN + | RADEON_CRTC_EN + | (format << 8) +@@ -328,7 +342,7 @@ RADEONInitCrtcRegisters(xf86CrtcPtr crtc, RADEONSavePtr save, + RADEON_CRTC_HSYNC_DIS | + RADEON_CRTC_DISPLAY_DIS); + +- save->disp_merge_cntl = info->SavedReg.disp_merge_cntl; ++ save->disp_merge_cntl = info->SavedReg->disp_merge_cntl; + save->disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN; + + save->crtc_more_cntl = 0; +@@ -378,10 +392,10 @@ RADEONInitCrtcRegisters(xf86CrtcPtr crtc, RADEONSavePtr save, + save->fp_crtc_v_total_disp = save->crtc_v_total_disp; + + if (info->IsDellServer) { +- save->dac2_cntl = info->SavedReg.dac2_cntl; +- save->tv_dac_cntl = info->SavedReg.tv_dac_cntl; +- save->crtc2_gen_cntl = info->SavedReg.crtc2_gen_cntl; +- save->disp_hw_debug = info->SavedReg.disp_hw_debug; ++ save->dac2_cntl = info->SavedReg->dac2_cntl; ++ save->tv_dac_cntl = info->SavedReg->tv_dac_cntl; ++ save->crtc2_gen_cntl = info->SavedReg->crtc2_gen_cntl; ++ save->disp_hw_debug = info->SavedReg->disp_hw_debug; + + save->dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL; + save->dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL; +@@ -397,7 +411,7 @@ RADEONInitCrtcRegisters(xf86CrtcPtr crtc, RADEONSavePtr save, return TRUE; } @@ -13125,7 +13404,7 @@ index b1d216d..e288352 100644 RADEONInitCrtc2Base(xf86CrtcPtr crtc, RADEONSavePtr save, int x, int y) { -@@ -512,7 +526,7 @@ RADEONInitCrtc2Base(xf86CrtcPtr crtc, RADEONSavePtr save, +@@ -510,7 +524,7 @@ RADEONInitCrtc2Base(xf86CrtcPtr crtc, RADEONSavePtr save, } /* Define CRTC2 registers for requested video mode */ @@ -13134,64 +13413,321 @@ index b1d216d..e288352 100644 RADEONInitCrtc2Registers(xf86CrtcPtr crtc, RADEONSavePtr save, DisplayModePtr mode) { -@@ -783,7 +797,7 @@ radeon_update_tv_routing(ScrnInfoPtr pScrn, RADEONSavePtr restore) - } +@@ -587,7 +601,7 @@ RADEONInitCrtc2Registers(xf86CrtcPtr crtc, RADEONSavePtr save, + ? RADEON_CRTC2_INTERLACE_EN + : 0)); - static void --radeon_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode, -+legacy_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode, - DisplayModePtr adjusted_mode, int x, int y) - { - ScrnInfoPtr pScrn = crtc->scrn; -@@ -893,13 +907,19 @@ radeon_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode, - ErrorF("restore crtc1\n"); - RADEONRestoreCrtcRegisters(pScrn, &info->ModeReg); - ErrorF("restore pll1\n"); -- RADEONRestorePLLRegisters(pScrn, &info->ModeReg); -+ /*if (info->IsAtomBios) -+ atombios_crtc_set_pll(crtc, adjusted_mode); -+ else*/ -+ RADEONRestorePLLRegisters(pScrn, &info->ModeReg); - break; - case 1: - ErrorF("restore crtc2\n"); - RADEONRestoreCrtc2Registers(pScrn, &info->ModeReg); - ErrorF("restore pll2\n"); -- RADEONRestorePLL2Registers(pScrn, &info->ModeReg); -+ /*if (info->IsAtomBios) -+ atombios_crtc_set_pll(crtc, adjusted_mode); -+ else*/ -+ RADEONRestorePLL2Registers(pScrn, &info->ModeReg); - break; - } +- save->disp2_merge_cntl = info->SavedReg.disp2_merge_cntl; ++ save->disp2_merge_cntl = info->SavedReg->disp2_merge_cntl; + save->disp2_merge_cntl &= ~(RADEON_DISP2_RGB_OFFSET_EN); -@@ -927,8 +947,25 @@ radeon_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode, + save->fp_h2_sync_strt_wid = save->crtc2_h_sync_strt_wid; +@@ -604,12 +618,12 @@ RADEONInitCrtc2Registers(xf86CrtcPtr crtc, RADEONSavePtr save, } - static void -+radeon_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode, -+ DisplayModePtr adjusted_mode, int x, int y) -+{ -+ ScrnInfoPtr pScrn = crtc->scrn; -+ RADEONInfoPtr info = RADEONPTR(pScrn); -+ -+ if (IS_AVIVO_VARIANT) { -+ atombios_crtc_mode_set(crtc, mode, adjusted_mode, x, y); -+ } else { -+ legacy_crtc_mode_set(crtc, mode, adjusted_mode, x, y); -+ } -+} -+ -+static void - radeon_crtc_mode_commit(xf86CrtcPtr crtc) + +-static int RADEONDiv(int n, int d) ++static CARD32 RADEONDiv(CARD64 n, CARD32 d) { -+ ScrnInfoPtr pScrn = crtc->scrn; + return (n + (d / 2)) / d; + } + +-static void ++void + RADEONComputePLL(RADEONPLLPtr pll, + unsigned long freq, + CARD32 *chosen_dot_clock_freq, +@@ -618,10 +632,6 @@ RADEONComputePLL(RADEONPLLPtr pll, + CARD32 *chosen_post_div, + int flags) + { +- int post_divs[] = {1, 2, 4, 8, 3, 6, 12, 0}; +- +- int i; +- + CARD32 min_ref_div = pll->min_ref_div; + CARD32 max_ref_div = pll->max_ref_div; + CARD32 best_vco = pll->best_vco; +@@ -631,23 +641,33 @@ RADEONComputePLL(RADEONPLLPtr pll, + CARD32 best_freq = 1; + CARD32 best_error = 0xffffffff; + CARD32 best_vco_diff = 1; ++ CARD32 post_div; + +- freq = freq / 10; ++ freq = freq * 1000; + + ErrorF("freq: %lu\n", freq); + + if (flags & RADEON_PLL_USE_REF_DIV) + min_ref_div = max_ref_div = pll->reference_div; + +- for (i = 0; post_divs[i]; i++) { +- int post_div = post_divs[i]; ++ for (post_div = pll->min_post_div; post_div <= pll->max_post_div; ++post_div) { + CARD32 ref_div; +- CARD32 vco = freq * post_div; ++ CARD32 vco = (freq / 10000) * post_div; + + if ((flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1)) + continue; + +- if (vco < pll->min_pll_freq || vco > pll->max_pll_freq) ++ /* legacy radeons only have a few post_divs */ ++ if (flags & RADEON_PLL_LEGACY) { ++ if ((post_div == 5) || ++ (post_div == 7) || ++ (post_div == 9) || ++ (post_div == 10) || ++ (post_div == 11)) ++ continue; ++ } ++ ++ if (vco < pll->pll_out_min || vco > pll->pll_out_max) + continue; + + for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) { +@@ -657,21 +677,22 @@ RADEONComputePLL(RADEONPLLPtr pll, + if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max) + continue; + +- feedback_div = RADEONDiv(freq * ref_div * post_div, +- pll->reference_freq); ++ feedback_div = RADEONDiv((CARD64)freq * ref_div * post_div, ++ pll->reference_freq * 10000); + + if (feedback_div < pll->min_feedback_div || feedback_div > pll->max_feedback_div) + continue; + +- current_freq = RADEONDiv(pll->reference_freq * feedback_div, ++ current_freq = RADEONDiv((CARD64)pll->reference_freq * 10000 * feedback_div, + ref_div * post_div); + + error = abs(current_freq - freq); + vco_diff = abs(vco - best_vco); + + if ((best_vco == 0 && error < best_error) || ++ (ref_div == pll->reference_div) || + (best_vco != 0 && +- (error < best_error - 1000 || ++ (error < best_error - 100 || + (abs(error - best_error) < 100 && vco_diff < best_vco_diff )))) { + best_post_div = post_div; + best_ref_div = ref_div; +@@ -683,12 +704,12 @@ RADEONComputePLL(RADEONPLLPtr pll, + } + } + +- ErrorF("best_freq: %u\n", (unsigned)best_freq); +- ErrorF("best_feedback_div: %u\n", (unsigned)best_feedback_div); +- ErrorF("best_ref_div: %u\n", (unsigned)best_ref_div); +- ErrorF("best_post_div: %u\n", (unsigned)best_post_div); ++ ErrorF("best_freq: %u\n", best_freq); ++ ErrorF("best_feedback_div: %u\n", best_feedback_div); ++ ErrorF("best_ref_div: %u\n", best_ref_div); ++ ErrorF("best_post_div: %u\n", best_post_div); + +- *chosen_dot_clock_freq = best_freq; ++ *chosen_dot_clock_freq = best_freq / 10000; + *chosen_feedback_div = best_feedback_div; + *chosen_reference_div = best_ref_div; + *chosen_post_div = best_post_div; +@@ -772,9 +793,8 @@ RADEONInitPLLRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save, + + save->htotal_cntl = mode->HTotal & 0x7; + +- save->vclk_ecp_cntl = (info->SavedReg.vclk_ecp_cntl & +- ~RADEON_VCLK_SRC_SEL_MASK) | RADEON_VCLK_SRC_SEL_PPLLCLK; +- ++ save->vclk_ecp_cntl = (info->SavedReg->vclk_ecp_cntl & ++ ~RADEON_VCLK_SRC_SEL_MASK) | RADEON_VCLK_SRC_SEL_PPLLCLK; + } + + /* Define PLL2 registers for requested video mode */ +@@ -847,10 +867,9 @@ RADEONInitPLL2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save, + + save->htotal_cntl2 = mode->HTotal & 0x7; + +- save->pixclks_cntl = ((info->SavedReg.pixclks_cntl & ++ save->pixclks_cntl = ((info->SavedReg->pixclks_cntl & + ~(RADEON_PIX2CLK_SRC_SEL_MASK)) | + RADEON_PIX2CLK_SRC_SEL_P2PLLCLK); +- + } + + static void +@@ -860,8 +879,8 @@ RADEONInitBIOSRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save) + + /* tell the bios not to muck with the hardware on events */ + save->bios_4_scratch = 0x4; /* 0x4 needed for backlight */ +- save->bios_5_scratch = (info->SavedReg.bios_5_scratch & 0xff) | 0xff00; /* bits 0-3 keep backlight level */ +- save->bios_6_scratch = info->SavedReg.bios_6_scratch | 0x40000000; ++ save->bios_5_scratch = (info->SavedReg->bios_5_scratch & 0xff) | 0xff00; /* bits 0-3 keep backlight level */ ++ save->bios_6_scratch = info->SavedReg->bios_6_scratch | 0x40000000; + + } + +@@ -873,7 +892,7 @@ radeon_update_tv_routing(ScrnInfoPtr pScrn, RADEONSavePtr restore) + } + + static void +-radeon_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode, ++legacy_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode, + DisplayModePtr adjusted_mode, int x, int y) + { + ScrnInfoPtr pScrn = crtc->scrn; +@@ -883,7 +902,7 @@ radeon_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode, + Bool tilingOld = info->tilingEnabled; + int i = 0; + double dot_clock = 0; +- int pll_flags = 0; ++ int pll_flags = RADEON_PLL_LEGACY; + Bool update_tv_routing = FALSE; + + +@@ -915,38 +934,38 @@ radeon_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode, + } + + if (info->IsMobility) +- RADEONInitBIOSRegisters(pScrn, &info->ModeReg); ++ RADEONInitBIOSRegisters(pScrn, info->ModeReg); + + ErrorF("init memmap\n"); +- RADEONInitMemMapRegisters(pScrn, &info->ModeReg, info); ++ RADEONInitMemMapRegisters(pScrn, info->ModeReg, info); + ErrorF("init common\n"); +- RADEONInitCommonRegisters(&info->ModeReg, info); ++ RADEONInitCommonRegisters(info->ModeReg, info); + +- RADEONInitSurfaceCntl(crtc, &info->ModeReg); ++ RADEONInitSurfaceCntl(crtc, info->ModeReg); + + switch (radeon_crtc->crtc_id) { + case 0: + ErrorF("init crtc1\n"); +- RADEONInitCrtcRegisters(crtc, &info->ModeReg, adjusted_mode); +- RADEONInitCrtcBase(crtc, &info->ModeReg, x, y); ++ RADEONInitCrtcRegisters(crtc, info->ModeReg, adjusted_mode); ++ RADEONInitCrtcBase(crtc, info->ModeReg, x, y); + dot_clock = adjusted_mode->Clock / 1000.0; + if (dot_clock) { + ErrorF("init pll1\n"); +- RADEONInitPLLRegisters(pScrn, &info->ModeReg, &info->pll, adjusted_mode, pll_flags); ++ RADEONInitPLLRegisters(pScrn, info->ModeReg, &info->pll, adjusted_mode, pll_flags); + } else { +- info->ModeReg.ppll_ref_div = info->SavedReg.ppll_ref_div; +- info->ModeReg.ppll_div_3 = info->SavedReg.ppll_div_3; +- info->ModeReg.htotal_cntl = info->SavedReg.htotal_cntl; ++ info->ModeReg->ppll_ref_div = info->SavedReg->ppll_ref_div; ++ info->ModeReg->ppll_div_3 = info->SavedReg->ppll_div_3; ++ info->ModeReg->htotal_cntl = info->SavedReg->htotal_cntl; + } + break; + case 1: + ErrorF("init crtc2\n"); +- RADEONInitCrtc2Registers(crtc, &info->ModeReg, adjusted_mode); +- RADEONInitCrtc2Base(crtc, &info->ModeReg, x, y); ++ RADEONInitCrtc2Registers(crtc, info->ModeReg, adjusted_mode); ++ RADEONInitCrtc2Base(crtc, info->ModeReg, x, y); + dot_clock = adjusted_mode->Clock / 1000.0; + if (dot_clock) { + ErrorF("init pll2\n"); +- RADEONInitPLL2Registers(pScrn, &info->ModeReg, &info->pll, adjusted_mode, pll_flags); ++ RADEONInitPLL2Registers(pScrn, info->ModeReg, &info->pll, adjusted_mode, pll_flags); + } + break; + } +@@ -959,13 +978,13 @@ radeon_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode, + if (radeon_output->MonType == MT_STV || radeon_output->MonType == MT_CTV) { + switch (radeon_crtc->crtc_id) { + case 0: +- RADEONAdjustCrtcRegistersForTV(pScrn, &info->ModeReg, adjusted_mode, output); +- RADEONAdjustPLLRegistersForTV(pScrn, &info->ModeReg, adjusted_mode, output); ++ RADEONAdjustCrtcRegistersForTV(pScrn, info->ModeReg, adjusted_mode, output); ++ RADEONAdjustPLLRegistersForTV(pScrn, info->ModeReg, adjusted_mode, output); + update_tv_routing = TRUE; + break; + case 1: +- RADEONAdjustCrtc2RegistersForTV(pScrn, &info->ModeReg, adjusted_mode, output); +- RADEONAdjustPLL2RegistersForTV(pScrn, &info->ModeReg, adjusted_mode, output); ++ RADEONAdjustCrtc2RegistersForTV(pScrn, info->ModeReg, adjusted_mode, output); ++ RADEONAdjustPLL2RegistersForTV(pScrn, info->ModeReg, adjusted_mode, output); + break; + } + } +@@ -973,31 +992,37 @@ radeon_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode, + } + + if (info->IsMobility) +- RADEONRestoreBIOSRegisters(pScrn, &info->ModeReg); ++ RADEONRestoreBIOSRegisters(pScrn, info->ModeReg); + + ErrorF("restore memmap\n"); +- RADEONRestoreMemMapRegisters(pScrn, &info->ModeReg); ++ RADEONRestoreMemMapRegisters(pScrn, info->ModeReg); + ErrorF("restore common\n"); +- RADEONRestoreCommonRegisters(pScrn, &info->ModeReg); ++ RADEONRestoreCommonRegisters(pScrn, info->ModeReg); + + switch (radeon_crtc->crtc_id) { + case 0: + ErrorF("restore crtc1\n"); +- RADEONRestoreCrtcRegisters(pScrn, &info->ModeReg); ++ RADEONRestoreCrtcRegisters(pScrn, info->ModeReg); + ErrorF("restore pll1\n"); +- RADEONRestorePLLRegisters(pScrn, &info->ModeReg); ++ /*if (info->IsAtomBios) ++ atombios_crtc_set_pll(crtc, adjusted_mode); ++ else*/ ++ RADEONRestorePLLRegisters(pScrn, info->ModeReg); + break; + case 1: + ErrorF("restore crtc2\n"); +- RADEONRestoreCrtc2Registers(pScrn, &info->ModeReg); ++ RADEONRestoreCrtc2Registers(pScrn, info->ModeReg); + ErrorF("restore pll2\n"); +- RADEONRestorePLL2Registers(pScrn, &info->ModeReg); ++ /*if (info->IsAtomBios) ++ atombios_crtc_set_pll(crtc, adjusted_mode); ++ else*/ ++ RADEONRestorePLL2Registers(pScrn, info->ModeReg); + break; + } + + /* pixclks_cntl handles tv-out clock routing */ + if (update_tv_routing) +- radeon_update_tv_routing(pScrn, &info->ModeReg); ++ radeon_update_tv_routing(pScrn, info->ModeReg); + + if (info->DispPriority) + RADEONInitDispBandwidth(pScrn); +@@ -1019,8 +1044,25 @@ radeon_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode, + } + + static void ++radeon_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode, ++ DisplayModePtr adjusted_mode, int x, int y) ++{ ++ ScrnInfoPtr pScrn = crtc->scrn; ++ RADEONInfoPtr info = RADEONPTR(pScrn); ++ ++ if (IS_AVIVO_VARIANT) { ++ atombios_crtc_mode_set(crtc, mode, adjusted_mode, x, y); ++ } else { ++ legacy_crtc_mode_set(crtc, mode, adjusted_mode, x, y); ++ } ++} ++ ++static void + radeon_crtc_mode_commit(xf86CrtcPtr crtc) + { ++ ScrnInfoPtr pScrn = crtc->scrn; + RADEONInfoPtr info = RADEONPTR(pScrn); + radeon_crtc_dpms(crtc, DPMSModeOn); } -@@ -943,8 +980,25 @@ void radeon_crtc_load_lut(xf86CrtcPtr crtc) +@@ -1035,8 +1077,25 @@ void radeon_crtc_load_lut(xf86CrtcPtr crtc) if (!crtc->enabled) return; @@ -13217,27 +13753,109 @@ index b1d216d..e288352 100644 for (i = 0; i < 256; i++) { OUTPAL(i, radeon_crtc->lut_r[i], radeon_crtc->lut_g[i], radeon_crtc->lut_b[i]); } -@@ -1220,6 +1274,7 @@ Bool RADEONAllocateControllers(ScrnInfoPtr pScrn) +@@ -1229,7 +1288,7 @@ radeon_crtc_shadow_create(xf86CrtcPtr crtc, void *data, int width, int height) - pRADEONEnt->pCrtc[0]->driver_private = pRADEONEnt->Controller[0]; - pRADEONEnt->Controller[0]->crtc_id = 0; -+ pRADEONEnt->Controller[0]->crtc_offset = 0; + if (!data) + data = radeon_crtc_shadow_allocate(crtc, width, height); +- ++ + rotate_pitch = pScrn->displayWidth * cpp; - if (!pRADEONEnt->HasCRTC2) - return TRUE; -@@ -1237,6 +1292,8 @@ Bool RADEONAllocateControllers(ScrnInfoPtr pScrn) + rotate_pixmap = GetScratchPixmapHeader(pScrn->pScreen, +@@ -1295,40 +1354,47 @@ static const xf86CrtcFuncsRec radeon_crtc_funcs = { + .destroy = NULL, /* XXX */ + }; + +-Bool RADEONAllocateControllers(ScrnInfoPtr pScrn) ++Bool RADEONAllocateControllers(ScrnInfoPtr pScrn, int mask) + { + RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); - pRADEONEnt->pCrtc[1]->driver_private = pRADEONEnt->Controller[1]; - pRADEONEnt->Controller[1]->crtc_id = 1; -+ pRADEONEnt->Controller[1]->crtc_offset = AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL; +- if (pRADEONEnt->Controller[0]) +- return TRUE; +- +- pRADEONEnt->pCrtc[0] = xf86CrtcCreate(pScrn, &radeon_crtc_funcs); +- if (!pRADEONEnt->pCrtc[0]) +- return FALSE; +- +- pRADEONEnt->Controller[0] = xnfcalloc(sizeof(RADEONCrtcPrivateRec), 1); +- if (!pRADEONEnt->Controller[0]) +- return FALSE; +- +- pRADEONEnt->pCrtc[0]->driver_private = pRADEONEnt->Controller[0]; +- pRADEONEnt->Controller[0]->crtc_id = 0; +- +- if (!pRADEONEnt->HasCRTC2) +- return TRUE; ++ if (mask & 1) { ++ if (pRADEONEnt->Controller[0]) ++ return TRUE; ++ ++ pRADEONEnt->pCrtc[0] = xf86CrtcCreate(pScrn, &radeon_crtc_funcs); ++ if (!pRADEONEnt->pCrtc[0]) ++ return FALSE; ++ ++ pRADEONEnt->Controller[0] = xnfcalloc(sizeof(RADEONCrtcPrivateRec), 1); ++ if (!pRADEONEnt->Controller[0]) ++ return FALSE; + ++ pRADEONEnt->pCrtc[0]->driver_private = pRADEONEnt->Controller[0]; ++ pRADEONEnt->Controller[0]->crtc_id = 0; ++ pRADEONEnt->Controller[0]->crtc_offset = 0; ++ } + +- pRADEONEnt->pCrtc[1] = xf86CrtcCreate(pScrn, &radeon_crtc_funcs); +- if (!pRADEONEnt->pCrtc[1]) +- return FALSE; ++ if (mask & 2) { ++ if (!pRADEONEnt->HasCRTC2) ++ return TRUE; ++ ++ pRADEONEnt->pCrtc[1] = xf86CrtcCreate(pScrn, &radeon_crtc_funcs); ++ if (!pRADEONEnt->pCrtc[1]) ++ return FALSE; ++ ++ pRADEONEnt->Controller[1] = xnfcalloc(sizeof(RADEONCrtcPrivateRec), 1); ++ if (!pRADEONEnt->Controller[1]) ++ { ++ xfree(pRADEONEnt->Controller[0]); ++ return FALSE; ++ } + +- pRADEONEnt->Controller[1] = xnfcalloc(sizeof(RADEONCrtcPrivateRec), 1); +- if (!pRADEONEnt->Controller[1]) +- { +- xfree(pRADEONEnt->Controller[0]); +- return FALSE; ++ pRADEONEnt->pCrtc[1]->driver_private = pRADEONEnt->Controller[1]; ++ pRADEONEnt->Controller[1]->crtc_id = 1; ++ pRADEONEnt->Controller[1]->crtc_offset = AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL; + } + +- pRADEONEnt->pCrtc[1]->driver_private = pRADEONEnt->Controller[1]; +- pRADEONEnt->Controller[1]->crtc_id = 1; return TRUE; } diff --git a/src/radeon_cursor.c b/src/radeon_cursor.c -index b8cfffd..282ffd8 100644 +index ba1159c..0f7e668 100644 --- a/src/radeon_cursor.c +++ b/src/radeon_cursor.c +@@ -74,12 +74,12 @@ + #define CURSOR_SWAPPING_START() \ + do { \ + OUTREG(RADEON_SURFACE_CNTL, \ +- (info->ModeReg.surface_cntl | \ ++ (info->ModeReg->surface_cntl | \ + RADEON_NONSURF_AP0_SWP_32BPP | RADEON_NONSURF_AP1_SWP_32BPP) & \ + ~(RADEON_NONSURF_AP0_SWP_16BPP | RADEON_NONSURF_AP1_SWP_16BPP)); \ + } while (0) + #define CURSOR_SWAPPING_END() (OUTREG(RADEON_SURFACE_CNTL, \ +- info->ModeReg.surface_cntl)) ++ info->ModeReg->surface_cntl)) + + #else + @@ -89,6 +89,25 @@ #endif @@ -13253,7 +13871,7 @@ index b8cfffd..282ffd8 100644 + + if (enable) { + OUTREG(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, -+ info->fbLocation + info->cursor_offset); ++ info->fbLocation + radeon_crtc->cursor_offset); + OUTREG(AVIVO_D1CUR_SIZE + radeon_crtc->crtc_offset, + ((CURSOR_WIDTH - 1) << 16) | (CURSOR_HEIGHT - 1)); + OUTREG(AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset, @@ -13353,9 +13971,9 @@ index b8cfffd..282ffd8 100644 - | ((xorigin ? 0 : x) << 16) - | (yorigin ? 0 : y))); - RADEONCTRACE(("cursor_offset: 0x%x, yorigin: %d, stride: %d, temp %08X\n", -- info->cursor_offset + pScrn->fbOffset, yorigin, stride, temp)); +- radeon_crtc->cursor_offset + pScrn->fbOffset, yorigin, stride, temp)); - OUTREG(RADEON_CUR_OFFSET, -- info->cursor_offset + pScrn->fbOffset + yorigin * stride); +- radeon_crtc->cursor_offset + pScrn->fbOffset + yorigin * stride); - } else if (crtc_id == 1) { - OUTREG(RADEON_CUR2_HORZ_VERT_OFF, (RADEON_CUR2_LOCK - | (xorigin << 16) @@ -13364,9 +13982,9 @@ index b8cfffd..282ffd8 100644 - | ((xorigin ? 0 : x) << 16) - | (yorigin ? 0 : y))); - RADEONCTRACE(("cursor_offset2: 0x%x, yorigin: %d, stride: %d, temp %08X\n", -- info->cursor_offset + pScrn->fbOffset, yorigin, stride, temp)); +- radeon_crtc->cursor_offset + pScrn->fbOffset, yorigin, stride, temp)); - OUTREG(RADEON_CUR2_OFFSET, -- info->cursor_offset + pScrn->fbOffset + yorigin * stride); +- radeon_crtc->cursor_offset + pScrn->fbOffset + yorigin * stride); + if (IS_AVIVO_VARIANT) { + /* avivo cursor spans the full fb width */ + x += crtc->x; @@ -13383,9 +14001,9 @@ index b8cfffd..282ffd8 100644 + | ((xorigin ? 0 : x) << 16) + | (yorigin ? 0 : y))); + RADEONCTRACE(("cursor_offset: 0x%x, yorigin: %d, stride: %d, temp %08X\n", -+ info->cursor_offset + pScrn->fbOffset, yorigin, stride, temp)); ++ radeon_crtc->cursor_offset + pScrn->fbOffset, yorigin, stride, temp)); + OUTREG(RADEON_CUR_OFFSET, -+ info->cursor_offset + pScrn->fbOffset + yorigin * stride); ++ radeon_crtc->cursor_offset + pScrn->fbOffset + yorigin * stride); + } else if (crtc_id == 1) { + OUTREG(RADEON_CUR2_HORZ_VERT_OFF, (RADEON_CUR2_LOCK + | (xorigin << 16) @@ -13394,16 +14012,16 @@ index b8cfffd..282ffd8 100644 + | ((xorigin ? 0 : x) << 16) + | (yorigin ? 0 : y))); + RADEONCTRACE(("cursor_offset2: 0x%x, yorigin: %d, stride: %d, temp %08X\n", -+ info->cursor_offset + pScrn->fbOffset, yorigin, stride, temp)); ++ radeon_crtc->cursor_offset + pScrn->fbOffset, yorigin, stride, temp)); + OUTREG(RADEON_CUR2_OFFSET, -+ info->cursor_offset + pScrn->fbOffset + yorigin * stride); ++ radeon_crtc->cursor_offset + pScrn->fbOffset + yorigin * stride); + } } - } void -@@ -265,10 +306,11 @@ Bool RADEONCursorInit(ScreenPtr pScreen) +@@ -269,10 +310,11 @@ Bool RADEONCursorInit(ScreenPtr pScreen) #ifdef USE_XAA if (!info->useEXA) { @@ -13415,21 +14033,175 @@ index b8cfffd..282ffd8 100644 + align, NULL, NULL, NULL); if (!fbarea) { - info->cursor_offset = 0; -@@ -279,7 +321,7 @@ Bool RADEONCursorInit(ScreenPtr pScreen) - info->cursor_offset = RADEON_ALIGN((fbarea->box.x1 + - fbarea->box.y1 * width) * - info->CurrentLayout.pixel_bytes, -- 256); -+ align); - info->cursor_end = info->cursor_offset + size_bytes; + cursor_offset = 0; +@@ -284,7 +326,7 @@ Bool RADEONCursorInit(ScreenPtr pScreen) + cursor_offset = RADEON_ALIGN((fbarea->box.x1 + + fbarea->box.y1 * width) * + info->CurrentLayout.pixel_bytes, +- 256); ++ align); + + for (c = 0; c < xf86_config->num_crtc; c++) { + xf86CrtcPtr crtc = xf86_config->crtc[c]; +diff --git a/src/radeon_display.c b/src/radeon_display.c +index ea31a82..2043f24 100644 +--- a/src/radeon_display.c ++++ b/src/radeon_display.c +@@ -318,7 +318,7 @@ void RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable) + { + ScrnInfoPtr pScrn = output->scrn; + RADEONInfoPtr info = RADEONPTR(pScrn); +- RADEONSavePtr save = &info->ModeReg; ++ RADEONSavePtr save = info->ModeReg; + unsigned char * RADEONMMIO = info->MMIO; + unsigned long tmp; + RADEONOutputPrivatePtr radeon_output; +@@ -720,7 +720,7 @@ void RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_b + critical_point = 0x10; + } + +- temp = info->SavedReg.grph_buffer_cntl; ++ temp = info->SavedReg->grph_buffer_cntl; + temp &= ~(RADEON_GRPH_STOP_REQ_MASK); + temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT); + temp &= ~(RADEON_GRPH_START_REQ_MASK); +@@ -742,7 +742,7 @@ void RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_b + + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "GRPH_BUFFER_CNTL from %x to %x\n", +- (unsigned int)info->SavedReg.grph_buffer_cntl, ++ (unsigned int)info->SavedReg->grph_buffer_cntl, + (unsigned int)INREG(RADEON_GRPH_BUFFER_CNTL)); + + if (mode2) { +@@ -750,7 +750,7 @@ void RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_b + + if (stop_req > max_stop_req) stop_req = max_stop_req; + +- temp = info->SavedReg.grph2_buffer_cntl; ++ temp = info->SavedReg->grph2_buffer_cntl; + temp &= ~(RADEON_GRPH_STOP_REQ_MASK); + temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT); + temp &= ~(RADEON_GRPH_START_REQ_MASK); +@@ -792,7 +792,7 @@ void RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_b + + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "GRPH2_BUFFER_CNTL from %x to %x\n", +- (unsigned int)info->SavedReg.grph2_buffer_cntl, ++ (unsigned int)info->SavedReg->grph2_buffer_cntl, + (unsigned int)INREG(RADEON_GRPH2_BUFFER_CNTL)); + } + } +@@ -804,7 +804,10 @@ void RADEONInitDispBandwidth(ScrnInfoPtr pScrn) + DisplayModePtr mode1, mode2; + int pixel_bytes2 = 0; + +- mode1 = info->CurrentLayout.mode; ++ if (info->IsPrimary || info->IsSecondary) ++ mode1 = &xf86_config->crtc[0]->mode; ++ else ++ mode1 = info->CurrentLayout.mode; + mode2 = NULL; + pixel_bytes2 = info->CurrentLayout.pixel_bytes; + +diff --git a/src/radeon_dri.c b/src/radeon_dri.c +index 3190451..f1003d7 100644 +--- a/src/radeon_dri.c ++++ b/src/radeon_dri.c +@@ -1188,7 +1188,7 @@ static void RADEONDRIIrqInit(RADEONInfoPtr info, ScreenPtr pScreen) + info->irq = 0; + } else { + unsigned char *RADEONMMIO = info->MMIO; +- info->ModeReg.gen_int_cntl = INREG( RADEON_GEN_INT_CNTL ); ++ info->ModeReg->gen_int_cntl = INREG( RADEON_GEN_INT_CNTL ); } - RADEONCTRACE(("RADEONCursorInit (0x%08x-0x%08x)\n", + } + +@@ -1768,7 +1768,7 @@ void RADEONDRICloseScreen(ScreenPtr pScreen) + RADEONDRISetVBlankInterrupt (pScrn, FALSE); + drmCtlUninstHandler(info->drmFD); + info->irq = 0; +- info->ModeReg.gen_int_cntl = 0; ++ info->ModeReg->gen_int_cntl = 0; + } + + /* De-allocate vertex buffers */ diff --git a/src/radeon_driver.c b/src/radeon_driver.c -index 3422b66..7a469ed 100644 +index 25b2119..2002dd3 100644 --- a/src/radeon_driver.c +++ b/src/radeon_driver.c -@@ -441,18 +441,20 @@ RADEONPreInt10Save(ScrnInfoPtr pScrn, void **pPtr) +@@ -97,6 +97,7 @@ + #include "xf86cmap.h" + #include "vbe.h" + ++#include "shadow.h" + /* vgaHW definitions */ + #ifdef WITH_VGAHW + #include "vgaHW.h" +@@ -347,6 +348,15 @@ static const char *i2cSymbols[] = { + NULL + }; + ++static const char *shadowSymbols[] = { ++ "shadowAdd", ++ "shadowInit", ++ "shadowSetup", ++ "shadowUpdatePacked", ++ "shadowUpdatePackedWeak", ++ NULL ++}; ++ + void RADEONLoaderRefSymLists(void) + { + /* +@@ -405,23 +415,41 @@ struct RADEONInt10Save { + static Bool RADEONMapMMIO(ScrnInfoPtr pScrn); + static Bool RADEONUnmapMMIO(ScrnInfoPtr pScrn); + +-#if 0 ++static void * ++radeonShadowWindow(ScreenPtr screen, CARD32 row, CARD32 offset, int mode, ++ CARD32 *size, void *closure) ++{ ++ ScrnInfoPtr pScrn = xf86Screens[screen->myNum]; ++ RADEONInfoPtr info = RADEONPTR(pScrn); ++ int stride; ++ ++ stride = (pScrn->displayWidth * pScrn->bitsPerPixel) / 8; ++ *size = stride; ++ ++ return ((CARD8 *)info->FB + pScrn->fbOffset + ++ row * stride + offset); ++} + static Bool + RADEONCreateScreenResources (ScreenPtr pScreen) + { + ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; + RADEONInfoPtr info = RADEONPTR(pScrn); ++ PixmapPtr pixmap; + + pScreen->CreateScreenResources = info->CreateScreenResources; + if (!(*pScreen->CreateScreenResources)(pScreen)) + return FALSE; ++ pScreen->CreateScreenResources = RADEONCreateScreenResources; + +- if (!xf86RandR12CreateScreenResources(pScreen)) +- return FALSE; ++ if (info->r600_shadow_fb) { ++ pixmap = pScreen->GetScreenPixmap(pScreen); + +- return TRUE; ++ if (!shadowAdd(pScreen, pixmap, shadowUpdatePackedWeak(), ++ radeonShadowWindow, 0, NULL)) ++ return FALSE; ++ } ++ return TRUE; + } +-#endif + + RADEONEntPtr RADEONEntPriv(ScrnInfoPtr pScrn) + { +@@ -440,18 +468,20 @@ RADEONPreInt10Save(ScrnInfoPtr pScrn, void **pPtr) CARD32 CardTmp; static struct RADEONInt10Save SaveStruct = { 0, 0, 0 }; @@ -13461,7 +14233,7 @@ index 3422b66..7a469ed 100644 *pPtr = (void *)&SaveStruct; } -@@ -469,6 +471,9 @@ RADEONPostInt10Check(ScrnInfoPtr pScrn, void *ptr) +@@ -468,6 +498,9 @@ RADEONPostInt10Check(ScrnInfoPtr pScrn, void *ptr) if (!pSave || !pSave->MEM_CNTL) return; @@ -13471,7 +14243,7 @@ index 3422b66..7a469ed 100644 /* * If either MEM_CNTL is currently zero or inconistent (configured for * two channels with the two channels configured differently), restore -@@ -719,6 +724,141 @@ void RADEONOUTPLL(ScrnInfoPtr pScrn, int addr, CARD32 data) +@@ -718,6 +751,141 @@ void RADEONOUTPLL(ScrnInfoPtr pScrn, int addr, CARD32 data) RADEONPllErrataAfterData(info); } @@ -13613,7 +14385,94 @@ index 3422b66..7a469ed 100644 #if 0 /* Read PAL information (only used for debugging) */ -@@ -1188,9 +1328,14 @@ void RADEONInitMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save, +@@ -1022,22 +1190,25 @@ static void RADEONGetClockInfo(ScrnInfoPtr pScrn) + + if (pll->reference_div < 2) pll->reference_div = 12; + } +- + } else { + xf86DrvMsg (pScrn->scrnIndex, X_WARNING, + "Video BIOS not detected, using default clock settings!\n"); + + /* Default min/max PLL values */ + if (info->ChipFamily == CHIP_FAMILY_R420 || info->ChipFamily == CHIP_FAMILY_RV410) { +- pll->min_pll_freq = 20000; +- pll->max_pll_freq = 50000; ++ pll->pll_in_min = 100; ++ pll->pll_in_max = 1350; ++ pll->pll_out_min = 20000; ++ pll->pll_out_max = 50000; + } else { +- pll->min_pll_freq = 12500; +- pll->max_pll_freq = 35000; ++ pll->pll_in_min = 40; ++ pll->pll_in_max = 500; ++ pll->pll_out_min = 12500; ++ pll->pll_out_max = 35000; + } + + if (RADEONProbePLLParameters(pScrn)) +- return; ++ return; + + if (info->IsIGP) + pll->reference_freq = 1432; +@@ -1058,25 +1229,30 @@ static void RADEONGetClockInfo(ScrnInfoPtr pScrn) + * Empirical value changed to 24 to raise pixel clock limit and + * allow higher resolution modes on capable monitors + */ +- pll->max_pll_freq = min(pll->max_pll_freq, ++ pll->pll_out_max = min(pll->pll_out_max, + 24 * info->mclk * 100 / pScrn->bitsPerPixel * + info->RamWidth / 16); + } + + /* card limits for computing PLLs */ ++ if (IS_AVIVO_VARIANT) { ++ pll->min_post_div = 2; ++ pll->max_post_div = 0x7f; ++ } else { ++ pll->min_post_div = 1; ++ pll->max_post_div = 12; //16 on crtc0 ++ } + pll->min_ref_div = 2; + pll->max_ref_div = 0x3ff; + pll->min_feedback_div = 4; + pll->max_feedback_div = 0x7ff; +- pll->pll_in_min = 40; +- pll->pll_in_max = 500; + pll->best_vco = 0; + + xf86DrvMsg (pScrn->scrnIndex, X_INFO, + "PLL parameters: rf=%u rd=%u min=%u max=%u; xclk=%u\n", + pll->reference_freq, + pll->reference_div, +- (unsigned)pll->min_pll_freq, (unsigned)pll->max_pll_freq, ++ (unsigned)pll->pll_out_min, (unsigned)pll->pll_out_max, + pll->xclk); + + /* (Some?) Radeon BIOSes seem too lie about their minimum dot +@@ -1085,7 +1261,7 @@ static void RADEONGetClockInfo(ScrnInfoPtr pScrn) + */ + if (xf86GetOptValFreq(info->Options, OPTION_MIN_DOTCLOCK, + OPTUNITS_MHZ, &min_dotclock)) { +- if (min_dotclock < 12 || min_dotclock*100 >= pll->max_pll_freq) { ++ if (min_dotclock < 12 || min_dotclock*100 >= pll->pll_out_max) { + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + "Illegal minimum dotclock specified %.2f MHz " + "(option ignored)\n", +@@ -1094,8 +1270,8 @@ static void RADEONGetClockInfo(ScrnInfoPtr pScrn) + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + "Forced minimum dotclock to %.2f MHz " + "(instead of detected %.2f MHz)\n", +- min_dotclock, ((double)pll->min_pll_freq/1000)); +- pll->min_pll_freq = min_dotclock * 1000; ++ min_dotclock, ((double)pll->pll_out_min/1000)); ++ pll->pll_out_min = min_dotclock * 1000; + } + } + } +@@ -1196,9 +1372,14 @@ void RADEONInitMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save, { save->mc_fb_location = info->mc_fb_location; save->mc_agp_location = info->mc_agp_location; @@ -13631,7 +14490,7 @@ index 3422b66..7a469ed 100644 } static void RADEONInitMemoryMap(ScrnInfoPtr pScrn) -@@ -1200,15 +1345,20 @@ static void RADEONInitMemoryMap(ScrnInfoPtr pScrn) +@@ -1208,15 +1389,20 @@ static void RADEONInitMemoryMap(ScrnInfoPtr pScrn) CARD32 mem_size; CARD32 aper_size; @@ -13657,7 +14516,7 @@ index 3422b66..7a469ed 100644 if (mem_size == 0) mem_size = 0x800000; -@@ -1237,7 +1387,13 @@ static void RADEONInitMemoryMap(ScrnInfoPtr pScrn) +@@ -1245,7 +1431,13 @@ static void RADEONInitMemoryMap(ScrnInfoPtr pScrn) else #endif { @@ -13672,7 +14531,7 @@ index 3422b66..7a469ed 100644 /* Recent chips have an "issue" with the memory controller, the * location must be aligned to the size. We just align it down, -@@ -1254,17 +1410,30 @@ static void RADEONInitMemoryMap(ScrnInfoPtr pScrn) +@@ -1262,17 +1454,30 @@ static void RADEONInitMemoryMap(ScrnInfoPtr pScrn) info->ChipFamily == CHIP_FAMILY_RV410) aper0_base &= ~(mem_size - 1); @@ -13707,7 +14566,7 @@ index 3422b66..7a469ed 100644 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "RADEONInitMemoryMap() : \n"); xf86DrvMsg(pScrn->scrnIndex, X_INFO, -@@ -1326,9 +1495,14 @@ static CARD32 RADEONGetAccessibleVRAM(ScrnInfoPtr pScrn) +@@ -1334,9 +1539,14 @@ static CARD32 RADEONGetAccessibleVRAM(ScrnInfoPtr pScrn) { RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; @@ -13723,7 +14582,7 @@ index 3422b66..7a469ed 100644 #ifdef XF86DRI /* If we use the DRI, we need to check if it's a version that has the * bug of always cropping MC_FB_LOCATION to one aperture, in which case -@@ -1356,7 +1530,8 @@ static CARD32 RADEONGetAccessibleVRAM(ScrnInfoPtr pScrn) +@@ -1364,7 +1574,8 @@ static CARD32 RADEONGetAccessibleVRAM(ScrnInfoPtr pScrn) info->ChipFamily == CHIP_FAMILY_RV350 || info->ChipFamily == CHIP_FAMILY_RV380 || info->ChipFamily == CHIP_FAMILY_R420 || @@ -13733,7 +14592,7 @@ index 3422b66..7a469ed 100644 OUTREGP (RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL, ~RADEON_HDP_APER_CNTL); xf86DrvMsg(pScrn->scrnIndex, X_INFO, -@@ -1403,13 +1578,18 @@ static Bool RADEONPreInitVRAM(ScrnInfoPtr pScrn) +@@ -1411,13 +1622,18 @@ static Bool RADEONPreInitVRAM(ScrnInfoPtr pScrn) OUTREG(RADEON_CONFIG_MEMSIZE, pScrn->videoRam * 1024); } else { @@ -13759,7 +14618,7 @@ index 3422b66..7a469ed 100644 } } -@@ -1429,7 +1609,8 @@ static Bool RADEONPreInitVRAM(ScrnInfoPtr pScrn) +@@ -1437,7 +1653,8 @@ static Bool RADEONPreInitVRAM(ScrnInfoPtr pScrn) if (pScrn->videoRam > accessible) pScrn->videoRam = accessible; @@ -13769,7 +14628,29 @@ index 3422b66..7a469ed 100644 info->BusCntl = INREG(RADEON_BUS_CNTL); RADEONGetVRamType(pScrn); -@@ -1554,6 +1735,15 @@ static Bool RADEONPreInitChipType(ScrnInfoPtr pScrn) +@@ -1454,6 +1671,21 @@ static Bool RADEONPreInitVRAM(ScrnInfoPtr pScrn) + xf86DrvMsg(pScrn->scrnIndex, from, + "Mapped VideoRAM: %d kByte (%d bit %s SDRAM)\n", pScrn->videoRam, info->RamWidth, info->IsDDR?"DDR":"SDR"); + ++ if (info->IsPrimary) { ++ pScrn->videoRam /= 2; ++ xf86DrvMsg(pScrn->scrnIndex, X_INFO, ++ "Using %dk of videoram for primary head\n", ++ pScrn->videoRam); ++ } ++ ++ if (info->IsSecondary) { ++ pScrn->videoRam /= 2; ++ info->LinearAddr += pScrn->videoRam * 1024; ++ xf86DrvMsg(pScrn->scrnIndex, X_INFO, ++ "Using %dk of videoram for secondary head\n", ++ pScrn->videoRam); ++ } ++ + pScrn->videoRam &= ~1023; + info->FbMapSize = pScrn->videoRam * 1024; + +@@ -1562,6 +1794,15 @@ static Bool RADEONPreInitChipType(ScrnInfoPtr pScrn) break; } @@ -13785,7 +14666,22 @@ index 3422b66..7a469ed 100644 from = X_PROBED; info->LinearAddr = PCI_REGION_BASE(info->PciInfo, 0, REGION_MEM) & ~0x1ffffffUL; -@@ -1769,6 +1959,12 @@ static Bool RADEONPreInitAccel(ScrnInfoPtr pScrn) +@@ -1717,6 +1958,14 @@ static Bool RADEONPreInitChipType(ScrnInfoPtr pScrn) + info->Chipset != PCI_CHIP_RN50_5969); + #endif + ++ if (info->ChipFamily >= CHIP_FAMILY_R600) { ++ info->r600_shadow_fb = TRUE; ++ xf86DrvMsg(pScrn->scrnIndex, X_INFO, ++ "using shadow framebuffer\n"); ++ if (!xf86LoadSubModule(pScrn, "shadow")) ++ return FALSE; ++ xf86LoaderReqSymLists(shadowSymbols, NULL); ++ } + return TRUE; + } + +@@ -1777,6 +2026,12 @@ static Bool RADEONPreInitAccel(ScrnInfoPtr pScrn) info->useEXA = FALSE; @@ -13798,7 +14694,23 @@ index 3422b66..7a469ed 100644 if (!xf86ReturnOptValBool(info->Options, OPTION_NOACCEL, FALSE)) { int errmaj = 0, errmin = 0; -@@ -1885,15 +2081,16 @@ static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn) +@@ -1889,19 +2144,32 @@ static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn) + info->pLibDRMVersion = NULL; + info->pKernelDRMVersion = NULL; + ++ if (xf86IsEntityShared(info->pEnt->index)) { ++ xf86DrvMsg(pScrn->scrnIndex, X_WARNING, ++ "Direct Rendering Disabled -- " ++ "Dual-head configuration is not working with " ++ "DRI at present.\n" ++ "Please use the radeon MergedFB option if you " ++ "want Dual-head with DRI.\n"); ++ return FALSE; ++ } ++ if (info->IsSecondary) ++ return FALSE; ++ + if (info->Chipset == PCI_CHIP_RN50_515E || info->Chipset == PCI_CHIP_RN50_5969 || info->Chipset == PCI_CHIP_RC410_5A61 || info->Chipset == PCI_CHIP_RC410_5A62 || @@ -13818,7 +14730,7 @@ index 3422b66..7a469ed 100644 return FALSE; } } -@@ -2079,7 +2276,7 @@ static void RADEONPreInitColorTiling(ScrnInfoPtr pScrn) +@@ -2087,7 +2355,7 @@ static void RADEONPreInitColorTiling(ScrnInfoPtr pScrn) info->allowColorTiling = xf86ReturnOptValBool(info->Options, OPTION_COLOR_TILING, TRUE); @@ -13827,17 +14739,136 @@ index 3422b66..7a469ed 100644 /* this may be 4096 on r4xx -- need to double check */ info->MaxSurfaceWidth = 3968; /* one would have thought 4096...*/ info->MaxLines = 4096; -@@ -2091,6 +2288,9 @@ static void RADEONPreInitColorTiling(ScrnInfoPtr pScrn) +@@ -2099,6 +2367,13 @@ static void RADEONPreInitColorTiling(ScrnInfoPtr pScrn) if (!info->allowColorTiling) return; + if (info->ChipFamily >= CHIP_FAMILY_R600) + info->allowColorTiling = FALSE; + ++ /* for zaphod disable tiling for now */ ++ if (info->IsPrimary || info->IsSecondary) ++ info->allowColorTiling = FALSE; ++ #ifdef XF86DRI if (info->directRenderingEnabled && info->pKernelDRMVersion->version_minor < 14) { -@@ -2549,7 +2749,7 @@ _X_EXPORT Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) +@@ -2319,12 +2594,41 @@ static void RADEONPreInitBIOS(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10) + #endif + } + ++static void RADEONFixZaphodOutputs(ScrnInfoPtr pScrn) ++{ ++ RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); ++ RADEONInfoPtr info = RADEONPTR(pScrn); ++ xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(pScrn); ++ int i; ++ ++ if (info->IsPrimary) { ++ xf86OutputDestroy(config->output[0]); ++ while(config->num_output > 1) { ++ xf86OutputDestroy(config->output[1]); ++ } ++ } else { ++ while(config->num_output > 1) { ++ xf86OutputDestroy(config->output[1]); ++ } ++ } ++} ++ + static Bool RADEONPreInitControllers(ScrnInfoPtr pScrn) + { + xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(pScrn); ++ RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); ++ RADEONInfoPtr info = RADEONPTR(pScrn); + int i; ++ int mask; + +- if (!RADEONAllocateControllers(pScrn)) ++ if (!info->IsPrimary && !info->IsSecondary) ++ mask = 3; ++ else if (info->IsPrimary) ++ mask = 1; ++ else ++ mask = 2; ++ ++ if (!RADEONAllocateControllers(pScrn, mask)) + return FALSE; + + RADEONGetClockInfo(pScrn); +@@ -2332,6 +2636,11 @@ static Bool RADEONPreInitControllers(ScrnInfoPtr pScrn) + if (!RADEONSetupConnectors(pScrn)) { + return FALSE; + } ++ ++ if (info->IsPrimary || info->IsSecondary) { ++ /* fixup outputs for zaphod */ ++ RADEONFixZaphodOutputs(pScrn); ++ } + + RADEONPrintPortMap(pScrn); + +@@ -2341,6 +2650,10 @@ static Bool RADEONPreInitControllers(ScrnInfoPtr pScrn) + + output->status = (*output->funcs->detect) (output); + ErrorF("finished output detect: %d\n", i); ++ if (info->IsPrimary || info->IsSecondary) { ++ if (output->status != XF86OutputStatusConnected) ++ return FALSE; ++ } + } + ErrorF("finished all detect\n"); + return TRUE; +@@ -2378,6 +2691,8 @@ _X_EXPORT Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) + void *int10_save = NULL; + const char *s; + int crtc_max_X, crtc_max_Y; ++ RADEONEntPtr pRADEONEnt; ++ DevUnion* pPriv; + + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "RADEONPreInit\n"); +@@ -2388,9 +2703,39 @@ _X_EXPORT Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) + info = RADEONPTR(pScrn); + info->MMIO = NULL; + ++ info->IsSecondary = FALSE; ++ info->IsPrimary = FALSE; ++ + info->pEnt = xf86GetEntityInfo(pScrn->entityList[pScrn->numEntities - 1]); + if (info->pEnt->location.type != BUS_PCI) goto fail; + ++ pPriv = xf86GetEntityPrivate(pScrn->entityList[0], ++ getRADEONEntityIndex()); ++ pRADEONEnt = pPriv->ptr; ++ ++ if(xf86IsEntityShared(pScrn->entityList[0])) ++ { ++ if(xf86IsPrimInitDone(pScrn->entityList[0])) ++ { ++ info->IsSecondary = TRUE; ++ pRADEONEnt->pSecondaryScrn = pScrn; ++ info->SavedReg = &pRADEONEnt->SavedReg; ++ info->ModeReg = &pRADEONEnt->ModeReg; ++ } ++ else ++ { ++ info->IsPrimary = TRUE; ++ xf86SetPrimInitDone(pScrn->entityList[0]); ++ pRADEONEnt->pPrimaryScrn = pScrn; ++ pRADEONEnt->HasSecondary = FALSE; ++ info->SavedReg = &pRADEONEnt->SavedReg; ++ info->ModeReg = &pRADEONEnt->ModeReg; ++ } ++ } else { ++ info->SavedReg = &pRADEONEnt->SavedReg; ++ info->ModeReg = &pRADEONEnt->ModeReg; ++ } ++ + info->PciInfo = xf86GetPciInfoForEntity(info->pEnt->index); + info->PciTag = pciTag(PCI_DEV_BUS(info->PciInfo), + PCI_DEV_DEV(info->PciInfo), +@@ -2557,7 +2902,7 @@ _X_EXPORT Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) crtc_max_X = 1600; crtc_max_Y = 1200; } else { @@ -13846,7 +14877,55 @@ index 3422b66..7a469ed 100644 crtc_max_X = 2560; crtc_max_Y = 1200; } else { -@@ -3176,9 +3376,10 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -2738,10 +3083,11 @@ static void RADEONLoadPalette(ScrnInfoPtr pScrn, int numColors, + + /* Make the change through RandR */ + #ifdef RANDR_12_INTERFACE +- RRCrtcGammaSet(crtc->randr_crtc, lut_r, lut_g, lut_b); +-#else +- crtc->funcs->gamma_set(crtc, lut_r, lut_g, lut_b, 256); ++ if (crtc->randr_crtc) ++ RRCrtcGammaSet(crtc->randr_crtc, lut_r, lut_g, lut_b); ++ else + #endif ++ crtc->funcs->gamma_set(crtc, lut_r, lut_g, lut_b, 256); + } + } + +@@ -3152,15 +3498,6 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, + char* s; + #endif + +-#ifdef XF86DRI +- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, +- "RADEONScreenInit %lx %ld %d\n", +- pScrn->memPhysBase, pScrn->fbOffset, info->frontOffset); +-#else +- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, +- "RADEONScreenInit %lx %ld\n", +- pScrn->memPhysBase, pScrn->fbOffset); +-#endif + + info->accelOn = FALSE; + #ifdef USE_XAA +@@ -3170,6 +3507,16 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, + pScrn->fbOffset = info->frontOffset; + #endif + ++ if (info->IsSecondary) pScrn->fbOffset = pScrn->videoRam * 1024; ++#ifdef XF86DRI ++ xf86DrvMsg(pScrn->scrnIndex, X_INFO, ++ "RADEONScreenInit %lx %ld %d\n", ++ pScrn->memPhysBase, pScrn->fbOffset, info->frontOffset); ++#else ++ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, ++ "RADEONScreenInit %lx %ld\n", ++ pScrn->memPhysBase, pScrn->fbOffset); ++#endif + if (!RADEONMapMem(pScrn)) return FALSE; + + #ifdef XF86DRI +@@ -3184,9 +3531,10 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, RADEONSave(pScrn); @@ -13859,7 +14938,63 @@ index 3422b66..7a469ed 100644 if (xf86ReturnOptValBool(info->Options, OPTION_DYNAMIC_CLOCKS, FALSE)) { RADEONSetDynamicClock(pScrn, 1); } else { -@@ -3562,9 +3763,11 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3385,13 +3733,32 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, + #endif + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "Initializing fb layer\n"); ++ ++ if (info->r600_shadow_fb) { ++ info->fb_shadow = xcalloc(1, ++ pScrn->displayWidth * pScrn->virtualY * ++ ((pScrn->bitsPerPixel + 7) >> 3)); ++ if (info->fb_shadow == NULL) { ++ xf86DrvMsg(pScrn->scrnIndex, X_ERROR, ++ "Failed to allocate shadow framebuffer\n"); ++ info->r600_shadow_fb = FALSE; ++ } else { ++ if (!fbScreenInit(pScreen, info->fb_shadow, ++ pScrn->virtualX, pScrn->virtualY, ++ pScrn->xDpi, pScrn->yDpi, pScrn->displayWidth, ++ pScrn->bitsPerPixel)) ++ return FALSE; ++ } ++ } + +- /* Init fb layer */ +- if (!fbScreenInit(pScreen, info->FB + pScrn->fbOffset, +- pScrn->virtualX, pScrn->virtualY, +- pScrn->xDpi, pScrn->yDpi, pScrn->displayWidth, +- pScrn->bitsPerPixel)) +- return FALSE; ++ if (info->r600_shadow_fb == FALSE) { ++ /* Init fb layer */ ++ if (!fbScreenInit(pScreen, info->FB, ++ pScrn->virtualX, pScrn->virtualY, ++ pScrn->xDpi, pScrn->yDpi, pScrn->displayWidth, ++ pScrn->bitsPerPixel)) ++ return FALSE; ++ } + + xf86SetBlackWhitePixels(pScreen); + +@@ -3477,7 +3844,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, + * our local image to make sure we restore them properly on mode + * changes or VT switches + */ +- RADEONAdjustMemMapRegisters(pScrn, &info->ModeReg); ++ RADEONAdjustMemMapRegisters(pScrn, info->ModeReg); + + if ((info->DispPriority == 1) && (info->cardType==CARD_AGP)) { + /* we need to re-calculate bandwidth because of AGPMode difference. */ +@@ -3503,6 +3870,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, + + RADEONChangeSurfaces(pScrn); + ++ + /* Enable aceleration */ + if (!xf86ReturnOptValBool(info->Options, OPTION_NOACCEL, FALSE)) { + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, +@@ -3565,9 +3933,17 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, RADEONDGAInit(pScreen); /* Init Xv */ @@ -13871,18 +15006,35 @@ index 3422b66..7a469ed 100644 + "Initializing Xv\n"); + RADEONInitVideo(pScreen); + } ++ ++ if (info->r600_shadow_fb == TRUE) { ++ if (!shadowSetup(pScreen)) { ++ return FALSE; ++ } ++ } /* Provide SaveScreen & wrap BlockHandler and CloseScreen */ /* Wrap CloseScreen */ -@@ -3611,184 +3814,247 @@ void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn, +@@ -3576,6 +3952,8 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, + pScreen->SaveScreen = RADEONSaveScreen; + info->BlockHandler = pScreen->BlockHandler; + pScreen->BlockHandler = RADEONBlockHandler; ++ info->CreateScreenResources = pScreen->CreateScreenResources; ++ pScreen->CreateScreenResources = RADEONCreateScreenResources; + + if (!xf86CrtcScreenInit (pScreen)) + return FALSE; +@@ -3614,184 +3992,252 @@ void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn, RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); unsigned char *RADEONMMIO = info->MMIO; int timeout; + CARD32 mc_fb_loc, mc_agp_loc, mc_agp_loc_hi; -+ + + radeon_read_mc_fb_agp_location(pScrn, LOC_FB | LOC_AGP, &mc_fb_loc, + &mc_agp_loc, &mc_agp_loc_hi); - ++ ++ if (info->IsSecondary) ++ return; xf86DrvMsg(pScrn->scrnIndex, X_INFO, "RADEONRestoreMemMapRegisters() : \n"); xf86DrvMsg(pScrn->scrnIndex, X_INFO, @@ -14092,8 +15244,7 @@ index 3422b66..7a469ed 100644 + else + status_idle = RADEON_MC_IDLE; + - timeout = 0; -- while(INREG(RADEON_CRTC2_OFFSET) & RADEON_CRTC2_OFFSET__GUI_TRIG_OFFSET) { ++ timeout = 0; + while (!(INREG(RADEON_MC_STATUS) & status_idle)) { + if (++timeout > 1000000) { + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, @@ -14139,7 +15290,8 @@ index 3422b66..7a469ed 100644 + OUTREG(RADEON_CRTC_OFFSET_CNTL, RADEON_CRTC_OFFSET_FLIP_CNTL); + OUTREG(RADEON_CRTC_OFFSET, 0); + OUTREG(RADEON_CUR_OFFSET, 0); -+ timeout = 0; + timeout = 0; +- while(INREG(RADEON_CRTC2_OFFSET) & RADEON_CRTC2_OFFSET__GUI_TRIG_OFFSET) { + while(INREG(RADEON_CRTC_OFFSET) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET) { if (timeout++ > 1000000) { xf86DrvMsg(pScrn->scrnIndex, X_ERROR, @@ -14204,7 +15356,9 @@ index 3422b66..7a469ed 100644 - - fb = INREG(RADEON_MC_FB_LOCATION); - agp = INREG(RADEON_MC_AGP_LOCATION); -- ++ CARD32 fb, agp, agp_hi; ++ int changed; + - if (fb != info->mc_fb_location || agp != info->mc_agp_location) { - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, - "DRI init changed memory map, adjusting ...\n"); @@ -14220,8 +15374,8 @@ index 3422b66..7a469ed 100644 - info->dst_pitch_offset = - (((pScrn->displayWidth * info->CurrentLayout.pixel_bytes / 64) - << 22) | ((info->fbLocation + pScrn->fbOffset) >> 10)); -+ CARD32 fb, agp, agp_hi; -+ int changed; ++ if (info->IsSecondary) ++ return; + radeon_read_mc_fb_agp_location(pScrn, LOC_FB | LOC_AGP, &fb, &agp, &agp_hi); + @@ -14256,7 +15410,17 @@ index 3422b66..7a469ed 100644 } #ifdef USE_EXA -@@ -4685,7 +4951,7 @@ void RADEONChangeSurfaces(ScrnInfoPtr pScrn) +@@ -3826,6 +4272,9 @@ void RADEONRestoreCommonRegisters(ScrnInfoPtr pScrn, + RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); + unsigned char *RADEONMMIO = info->MMIO; + ++ if (info->IsSecondary) ++ return; ++ + OUTREG(RADEON_OVR_CLR, restore->ovr_clr); + OUTREG(RADEON_OVR_WID_LEFT_RIGHT, restore->ovr_wid_left_right); + OUTREG(RADEON_OVR_WID_TOP_BOTTOM, restore->ovr_wid_top_bottom); +@@ -4692,7 +5141,7 @@ void RADEONChangeSurfaces(ScrnInfoPtr pScrn) #endif if (info->ChipFamily < CHIP_FAMILY_R200) { color_pattern = RADEON_SURF_TILE_COLOR_MACRO; @@ -14265,7 +15429,7 @@ index 3422b66..7a469ed 100644 color_pattern = R300_SURF_TILE_COLOR_MACRO; } else { color_pattern = R200_SURF_TILE_COLOR_MACRO; -@@ -4724,7 +4990,7 @@ void RADEONChangeSurfaces(ScrnInfoPtr pScrn) +@@ -4731,7 +5180,7 @@ void RADEONChangeSurfaces(ScrnInfoPtr pScrn) drmsurfalloc.flags = swap_pattern; if (info->tilingEnabled) { @@ -14274,7 +15438,7 @@ index 3422b66..7a469ed 100644 drmsurfalloc.flags |= (width_bytes / 8) | color_pattern; else drmsurfalloc.flags |= (width_bytes / 16) | color_pattern; -@@ -4749,7 +5015,7 @@ void RADEONChangeSurfaces(ScrnInfoPtr pScrn) +@@ -4756,7 +5205,7 @@ void RADEONChangeSurfaces(ScrnInfoPtr pScrn) depth_pattern = RADEON_SURF_TILE_DEPTH_16BPP; else depth_pattern = RADEON_SURF_TILE_DEPTH_32BPP; @@ -14283,7 +15447,7 @@ index 3422b66..7a469ed 100644 if (depthCpp == 2) depth_pattern = R300_SURF_TILE_COLOR_MACRO; else -@@ -4769,7 +5035,7 @@ void RADEONChangeSurfaces(ScrnInfoPtr pScrn) +@@ -4776,7 +5225,7 @@ void RADEONChangeSurfaces(ScrnInfoPtr pScrn) drmRadeonSurfaceAlloc drmsurfalloc; drmsurfalloc.size = depthBufferSize; drmsurfalloc.address = info->depthOffset; @@ -14292,7 +15456,7 @@ index 3422b66..7a469ed 100644 drmsurfalloc.flags = swap_pattern | (depth_width_bytes / 8) | depth_pattern; else drmsurfalloc.flags = swap_pattern | (depth_width_bytes / 16) | depth_pattern; -@@ -4787,7 +5053,7 @@ void RADEONChangeSurfaces(ScrnInfoPtr pScrn) +@@ -4794,7 +5243,7 @@ void RADEONChangeSurfaces(ScrnInfoPtr pScrn) unsigned char *RADEONMMIO = info->MMIO; /* we don't need anything like WaitForFifo, no? */ if (info->tilingEnabled) { @@ -14301,7 +15465,16 @@ index 3422b66..7a469ed 100644 surf_info |= (width_bytes / 8) | color_pattern; else surf_info |= (width_bytes / 16) | color_pattern; -@@ -4810,11 +5076,14 @@ static void RADEONSaveMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save) +@@ -4808,7 +5257,7 @@ void RADEONChangeSurfaces(ScrnInfoPtr pScrn) + } + + /* Update surface images */ +- RADEONSaveSurfaces(pScrn, &info->ModeReg); ++ RADEONSaveSurfaces(pScrn, info->ModeReg); + } + + /* Read memory map */ +@@ -4817,11 +5266,14 @@ static void RADEONSaveMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save) RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; @@ -14321,7 +15494,7 @@ index 3422b66..7a469ed 100644 } /* Read common registers */ -@@ -5123,6 +5392,305 @@ static void RADEONSavePalette(ScrnInfoPtr pScrn, RADEONSavePtr save) +@@ -5130,13 +5582,326 @@ static void RADEONSavePalette(ScrnInfoPtr pScrn, RADEONSavePtr save) } #endif @@ -14458,11 +15631,18 @@ index 3422b66..7a469ed 100644 + state->tmds2.source_select = INREG(AVIVO_LVTMA_SOURCE_SELECT); + state->tmds2.bit_depth_cntl = INREG(AVIVO_LVTMA_BIT_DEPTH_CONTROL); + state->tmds2.data_sync = INREG(AVIVO_LVTMA_DATA_SYNCHRONIZATION); -+ state->tmds2.transmitter_enable = INREG(AVIVO_LVTMA_TRANSMITTER_ENABLE); -+ state->tmds2.transmitter_cntl = INREG(AVIVO_LVTMA_TRANSMITTER_CONTROL); + -+ state->lvtma_pwrseq_cntl = INREG(AVIVO_LVTMA_PWRSEQ_CNTL); -+ state->lvtma_pwrseq_state = INREG(AVIVO_LVTMA_PWRSEQ_STATE); ++ if (info->ChipFamily >= CHIP_FAMILY_R600) { ++ state->tmds2.transmitter_enable = INREG(R600_LVTMA_TRANSMITTER_ENABLE); ++ state->tmds2.transmitter_cntl = INREG(R600_LVTMA_TRANSMITTER_CONTROL); ++ state->lvtma_pwrseq_cntl = INREG(R600_LVTMA_PWRSEQ_CNTL); ++ state->lvtma_pwrseq_state = INREG(R600_LVTMA_PWRSEQ_STATE); ++ } else { ++ state->tmds2.transmitter_enable = INREG(R500_LVTMA_TRANSMITTER_ENABLE); ++ state->tmds2.transmitter_cntl = INREG(R500_LVTMA_TRANSMITTER_CONTROL); ++ state->lvtma_pwrseq_cntl = INREG(R500_LVTMA_PWRSEQ_CNTL); ++ state->lvtma_pwrseq_state = INREG(R500_LVTMA_PWRSEQ_STATE); ++ } + + if (state->crtc1.control & AVIVO_CRTC_EN) + info->crtc_on = TRUE; @@ -14603,12 +15783,19 @@ index 3422b66..7a469ed 100644 + OUTREG(AVIVO_LVTMA_CNTL, state->tmds2.cntl); + OUTREG(AVIVO_LVTMA_BIT_DEPTH_CONTROL, state->tmds2.bit_depth_cntl); + OUTREG(AVIVO_LVTMA_DATA_SYNCHRONIZATION, state->tmds2.data_sync); -+ OUTREG(AVIVO_LVTMA_TRANSMITTER_ENABLE, state->tmds2.transmitter_enable); -+ OUTREG(AVIVO_LVTMA_TRANSMITTER_CONTROL, state->tmds2.transmitter_cntl); + OUTREG(AVIVO_LVTMA_SOURCE_SELECT, state->tmds2.source_select); -+ -+ OUTREG(AVIVO_LVTMA_PWRSEQ_CNTL, state->lvtma_pwrseq_cntl); -+ OUTREG(AVIVO_LVTMA_PWRSEQ_STATE, state->lvtma_pwrseq_state); ++ ++ if (info->ChipFamily >= CHIP_FAMILY_R600) { ++ OUTREG(R600_LVTMA_TRANSMITTER_ENABLE, state->tmds2.transmitter_enable); ++ OUTREG(R600_LVTMA_TRANSMITTER_CONTROL, state->tmds2.transmitter_cntl); ++ OUTREG(R600_LVTMA_PWRSEQ_CNTL, state->lvtma_pwrseq_cntl); ++ OUTREG(R600_LVTMA_PWRSEQ_STATE, state->lvtma_pwrseq_state); ++ } else { ++ OUTREG(R500_LVTMA_TRANSMITTER_ENABLE, state->tmds2.transmitter_enable); ++ OUTREG(R500_LVTMA_TRANSMITTER_CONTROL, state->tmds2.transmitter_cntl); ++ OUTREG(R500_LVTMA_PWRSEQ_CNTL, state->lvtma_pwrseq_cntl); ++ OUTREG(R500_LVTMA_PWRSEQ_STATE, state->lvtma_pwrseq_state); ++ } + + OUTREG(AVIVO_D1VGA_CONTROL, state->vga1_cntl); + OUTREG(AVIVO_D2VGA_CONTROL, state->vga2_cntl); @@ -14627,7 +15814,15 @@ index 3422b66..7a469ed 100644 /* Save everything needed to restore the original VC state */ static void RADEONSave(ScrnInfoPtr pScrn) { -@@ -5153,26 +5721,33 @@ static void RADEONSave(ScrnInfoPtr pScrn) + RADEONInfoPtr info = RADEONPTR(pScrn); + RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); + unsigned char *RADEONMMIO = info->MMIO; +- RADEONSavePtr save = &info->SavedReg; ++ RADEONSavePtr save = info->SavedReg; + + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "RADEONSave\n"); +@@ -5160,26 +5925,33 @@ static void RADEONSave(ScrnInfoPtr pScrn) vgaHWLock(hwp); } #endif @@ -14646,6 +15841,11 @@ index 3422b66..7a469ed 100644 - if (pRADEONEnt->HasCRTC2) { - RADEONSaveCrtc2Registers(pScrn, save); - RADEONSavePLL2Registers(pScrn, save); +- } +- if (info->InternalTVOut) +- RADEONSaveTVRegisters(pScrn, save); +- +- RADEONSaveSurfaces(pScrn, save); + if (IS_AVIVO_VARIANT) { + RADEONSaveMemMapRegisters(pScrn, save); + avivo_save(pScrn, save); @@ -14668,17 +15868,23 @@ index 3422b66..7a469ed 100644 + } + if (info->InternalTVOut) + RADEONSaveTVRegisters(pScrn, save); - } -- if (info->InternalTVOut) -- RADEONSaveTVRegisters(pScrn, save); - -- RADEONSaveSurfaces(pScrn, save); ++ } ++ + RADEONSaveSurfaces(pScrn, save); + } /* Restore the original (text) mode */ -@@ -5195,31 +5770,37 @@ void RADEONRestore(ScrnInfoPtr pScrn) +@@ -5188,7 +5960,7 @@ void RADEONRestore(ScrnInfoPtr pScrn) + RADEONInfoPtr info = RADEONPTR(pScrn); + RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); + unsigned char *RADEONMMIO = info->MMIO; +- RADEONSavePtr restore = &info->SavedReg; ++ RADEONSavePtr restore = info->SavedReg; + xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); + xf86CrtcPtr crtc; + +@@ -5202,33 +5974,40 @@ void RADEONRestore(ScrnInfoPtr pScrn) RADEONBlank(pScrn); @@ -14701,6 +15907,7 @@ index 3422b66..7a469ed 100644 - RADEONRestoreMemMapRegisters(pScrn, restore); - RADEONRestoreCommonRegisters(pScrn, restore); ++ if (!info->IsSecondary) { + RADEONRestoreMemMapRegisters(pScrn, restore); + RADEONRestoreCommonRegisters(pScrn, restore); @@ -14732,12 +15939,26 @@ index 3422b66..7a469ed 100644 - RADEONRestoreTVRegisters(pScrn, restore); + if (info->InternalTVOut) + RADEONRestoreTVRegisters(pScrn, restore); -+ + } - RADEONRestoreSurfaces(pScrn, restore); +- RADEONRestoreSurfaces(pScrn, restore); ++ RADEONRestoreSurfaces(pScrn, restore); ++ } + + #if 1 + /* Temp fix to "solve" VT switch problems. When switching VTs on +@@ -5256,8 +6035,8 @@ void RADEONRestore(ScrnInfoPtr pScrn) + #endif -@@ -5262,6 +5843,8 @@ void RADEONRestore(ScrnInfoPtr pScrn) + /* need to make sure we don't enable a crtc by accident or we may get a hang */ +- if (pRADEONEnt->HasCRTC2) { +- if (info->crtc2_on) { ++ if (pRADEONEnt->HasCRTC2 && !info->IsSecondary) { ++ if (info->crtc2_on && xf86_config->num_crtc > 1) { + crtc = xf86_config->crtc[1]; + crtc->funcs->dpms(crtc, DPMSModeOn); + } +@@ -5269,6 +6048,8 @@ void RADEONRestore(ScrnInfoPtr pScrn) /* to restore console mode, DAC registers should be set after every other registers are set, * otherwise,we may get blank screen */ @@ -14746,7 +15967,7 @@ index 3422b66..7a469ed 100644 RADEONRestoreDACRegisters(pScrn, restore); #if 0 -@@ -5441,7 +6024,7 @@ void RADEONDoAdjustFrame(ScrnInfoPtr pScrn, int x, int y, Bool crtc2) +@@ -5448,7 +6229,7 @@ void RADEONDoAdjustFrame(ScrnInfoPtr pScrn, int x, int y, Bool crtc2) crtcoffsetcntl &= ~RADEON_CRTC_OFFSET_FLIP_CNTL; #endif if (info->tilingEnabled) { @@ -14755,7 +15976,7 @@ index 3422b66..7a469ed 100644 /* On r300/r400 when tiling is enabled crtc_offset is set to the address of * the surface. the x/y offsets are handled by the X_Y tile reg for each crtc * Makes tiling MUCH easier. -@@ -5498,7 +6081,7 @@ void RADEONDoAdjustFrame(ScrnInfoPtr pScrn, int x, int y, Bool crtc2) +@@ -5505,7 +6286,7 @@ void RADEONDoAdjustFrame(ScrnInfoPtr pScrn, int x, int y, Bool crtc2) } #endif @@ -14764,6 +15985,64 @@ index 3422b66..7a469ed 100644 OUTREG(xytilereg, crtcxytile); } else { OUTREG(regcntl, crtcoffsetcntl); +@@ -5592,7 +6373,7 @@ Bool RADEONEnterVT(int scrnIndex, int flags) + + } + +- RADEONRestoreSurfaces(pScrn, &info->ModeReg); ++ RADEONRestoreSurfaces(pScrn, info->ModeReg); + #ifdef XF86DRI + if (info->directRenderingEnabled) { + if (info->cardType == CARD_PCIE && info->pKernelDRMVersion->version_minor >= 19 && info->FbSecureSize) +@@ -5604,7 +6385,7 @@ Bool RADEONEnterVT(int scrnIndex, int flags) + /* get the DRI back into shape after resume */ + RADEONDRISetVBlankInterrupt (pScrn, TRUE); + RADEONDRIResume(pScrn->pScreen); +- RADEONAdjustMemMapRegisters(pScrn, &info->ModeReg); ++ RADEONAdjustMemMapRegisters(pScrn, info->ModeReg); + + } + #endif +diff --git a/src/radeon_exa_funcs.c b/src/radeon_exa_funcs.c +index 2b7f0e8..278d5a7 100644 +--- a/src/radeon_exa_funcs.c ++++ b/src/radeon_exa_funcs.c +@@ -251,7 +251,7 @@ FUNC_NAME(RADEONUploadToScreen)(PixmapPtr pDst, int x, int y, int w, int h, + #endif + #if X_BYTE_ORDER == X_BIG_ENDIAN + unsigned char *RADEONMMIO = info->MMIO; +- unsigned int swapper = info->ModeReg.surface_cntl & ++ unsigned int swapper = info->ModeReg->surface_cntl & + ~(RADEON_NONSURF_AP0_SWP_32BPP | RADEON_NONSURF_AP1_SWP_32BPP | + RADEON_NONSURF_AP0_SWP_16BPP | RADEON_NONSURF_AP1_SWP_16BPP); + #endif +@@ -311,7 +311,7 @@ FUNC_NAME(RADEONUploadToScreen)(PixmapPtr pDst, int x, int y, int w, int h, + + #if X_BYTE_ORDER == X_BIG_ENDIAN + /* restore byte swapping */ +- OUTREG(RADEON_SURFACE_CNTL, info->ModeReg.surface_cntl); ++ OUTREG(RADEON_SURFACE_CNTL, info->ModeReg->surface_cntl); + #endif + + return TRUE; +@@ -354,7 +354,7 @@ FUNC_NAME(RADEONDownloadFromScreen)(PixmapPtr pSrc, int x, int y, int w, int h, + RINFO_FROM_SCREEN(pSrc->drawable.pScreen); + #if X_BYTE_ORDER == X_BIG_ENDIAN + unsigned char *RADEONMMIO = info->MMIO; +- unsigned int swapper = info->ModeReg.surface_cntl & ++ unsigned int swapper = info->ModeReg->surface_cntl & + ~(RADEON_NONSURF_AP0_SWP_32BPP | RADEON_NONSURF_AP1_SWP_32BPP | + RADEON_NONSURF_AP0_SWP_16BPP | RADEON_NONSURF_AP1_SWP_16BPP); + #endif +@@ -492,7 +492,7 @@ FUNC_NAME(RADEONDownloadFromScreen)(PixmapPtr pSrc, int x, int y, int w, int h, + + #if X_BYTE_ORDER == X_BIG_ENDIAN + /* restore byte swapping */ +- OUTREG(RADEON_SURFACE_CNTL, info->ModeReg.surface_cntl); ++ OUTREG(RADEON_SURFACE_CNTL, info->ModeReg->surface_cntl); + #endif + + return TRUE; diff --git a/src/radeon_macros.h b/src/radeon_macros.h index efc9e82..7f532a8 100644 --- a/src/radeon_macros.h @@ -14845,10 +16124,39 @@ index efc9e82..7f532a8 100644 + #endif diff --git a/src/radeon_modes.c b/src/radeon_modes.c -index 3c4badd..21fb659 100644 +index 3c4badd..c9e99b8 100644 --- a/src/radeon_modes.c +++ b/src/radeon_modes.c -@@ -214,7 +214,7 @@ RADEONProbeOutputModes(xf86OutputPtr output) +@@ -59,20 +59,22 @@ void RADEONSetPitch (ScrnInfoPtr pScrn) + { + int dummy = pScrn->virtualX; + RADEONInfoPtr info = RADEONPTR(pScrn); ++ int pitch_mask = 0; ++ int align_large; ++ ++ align_large = info->allowColorTiling || IS_AVIVO_VARIANT; + + /* FIXME: May need to validate line pitch here */ + switch (pScrn->depth / 8) { +- case 1: if (info->allowColorTiling) dummy = (pScrn->virtualX + 255) & ~255; +- else dummy = (pScrn->virtualX + 127) & ~127; ++ case 1: pitch_mask = align_large ? 255 : 127; + break; +- case 2: if (info->allowColorTiling) dummy = (pScrn->virtualX + 127) & ~127; +- else dummy = (pScrn->virtualX + 31) & ~31; ++ case 2: pitch_mask = align_large ? 127 : 31; + break; + case 3: +- case 4: if (info->allowColorTiling) dummy = (pScrn->virtualX + 63) & ~63; +- else dummy = (pScrn->virtualX + 15) & ~15; ++ case 4: pitch_mask = align_large ? 63 : 15; + break; + } ++ dummy = (pScrn->virtualX + pitch_mask) & ~pitch_mask; + pScrn->displayWidth = dummy; + info->CurrentLayout.displayWidth = pScrn->displayWidth; + +@@ -214,7 +216,7 @@ RADEONProbeOutputModes(xf86OutputPtr output) ErrorF("in RADEONProbeOutputModes\n"); if (output->status == XF86OutputStatusConnected) { @@ -14858,7 +16166,7 @@ index 3c4badd..21fb659 100644 } else { if (output->MonInfo) diff --git a/src/radeon_output.c b/src/radeon_output.c -index 11a2a8a..15b4ddf 100644 +index 6454460..5a99094 100644 --- a/src/radeon_output.c +++ b/src/radeon_output.c @@ -46,7 +46,7 @@ @@ -14960,7 +16268,7 @@ index 11a2a8a..15b4ddf 100644 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); RADEONOutputPrivatePtr radeon_output; xf86OutputPtr output; -@@ -261,32 +259,61 @@ void RADEONPrintPortMap(ScrnInfoPtr pScrn) +@@ -261,32 +259,63 @@ void RADEONPrintPortMap(ScrnInfoPtr pScrn) radeon_output = output->driver_private; xf86DrvMsg(pScrn->scrnIndex, X_INFO, @@ -14999,6 +16307,8 @@ index 11a2a8a..15b4ddf 100644 + MonType = MT_LCD; + else if (radeon_output->type == OUTPUT_DVI_D) + MonType = MT_DFP; ++ else if (radeon_output->type == OUTPUT_HDMI) ++ MonType = MT_DFP; + else if (radeon_output->type == OUTPUT_DVI_I && (MonInfo->rawData[0x14] & 0x80)) /* if it's digital and DVI */ + MonType = MT_DFP; + else @@ -15029,7 +16339,7 @@ index 11a2a8a..15b4ddf 100644 /* Read and output monitor info using DDC2 over I2C bus */ if (radeon_output->pI2CBus && info->ddc2 && (DDCReg != RADEON_LCD_GPIO_MASK) && (DDCReg != RADEON_MDGPIO_EN_REG)) { -@@ -357,22 +384,18 @@ RADEONDisplayDDCConnected(ScrnInfoPtr pScrn, xf86OutputPtr output) +@@ -357,22 +386,20 @@ RADEONDisplayDDCConnected(ScrnInfoPtr pScrn, xf86OutputPtr output) if (MonInfo) { if (!xf86ReturnOptValBool(info->Options, OPTION_IGNORE_EDID, FALSE)) xf86OutputSetEDID(output, MonInfo); @@ -15043,9 +16353,11 @@ index 11a2a8a..15b4ddf 100644 MonType = MT_DFP; - } else if (radeon_output->type == OUTPUT_DVI && - (MonInfo->rawData[0x14] & 0x80)) { /* if it's digital and DVI */ -+ else if (radeon_output->type == OUTPUT_DVI_I && (MonInfo->rawData[0x14] & 0x80)) /* if it's digital and DVI */ ++ else if (radeon_output->type == OUTPUT_HDMI) MonType = MT_DFP; - } else { ++ else if (radeon_output->type == OUTPUT_DVI_I && (MonInfo->rawData[0x14] & 0x80)) /* if it's digital and DVI */ ++ MonType = MT_DFP; + else MonType = MT_CRT; - } @@ -15057,7 +16369,7 @@ index 11a2a8a..15b4ddf 100644 return MonType; } -@@ -624,6 +647,38 @@ RADEONCrtIsPhysicallyConnected(ScrnInfoPtr pScrn, int IsCrtDac) +@@ -624,6 +651,45 @@ RADEONCrtIsPhysicallyConnected(ScrnInfoPtr pScrn, int IsCrtDac) } #endif @@ -15069,11 +16381,18 @@ index 11a2a8a..15b4ddf 100644 + RADEONMonitorType found = MT_NONE; + + if (OUTPUT_IS_TV) { -+ if (info->InternalTVOut) { -+ if (radeon_output->load_detection) -+ found = radeon_detect_tv(pScrn); ++ if (xf86ReturnOptValBool(info->Options, OPTION_FORCE_TVOUT, FALSE)) { ++ if (radeon_output->type == OUTPUT_STV) ++ radeon_output->MonType = MT_STV; + else -+ found = MT_NONE; ++ radeon_output->MonType = MT_CTV; ++ } else { ++ if (info->InternalTVOut) { ++ if (radeon_output->load_detection) ++ radeon_output->MonType = radeon_detect_tv(pScrn); ++ else ++ radeon_output->MonType = MT_NONE; ++ } + } + } else { + if (radeon_output->DACType == DAC_PRIMARY) { @@ -15096,28 +16415,38 @@ index 11a2a8a..15b4ddf 100644 /* Primary Head (DVI or Laptop Int. panel)*/ /* A ddc capable display connected on DVI port */ /* Secondary Head (mostly VGA, can be DVI on some OEM boards)*/ -@@ -633,8 +688,18 @@ void RADEONConnectorFindMonitor(ScrnInfoPtr pScrn, xf86OutputPtr output) +@@ -633,38 +699,32 @@ void RADEONConnectorFindMonitor(ScrnInfoPtr pScrn, xf86OutputPtr output) RADEONOutputPrivatePtr radeon_output = output->driver_private; if (radeon_output->MonType == MT_UNKNOWN) { - if (radeon_output->type == OUTPUT_STV || radeon_output->type == OUTPUT_CTV) { - if (xf86ReturnOptValBool(info->Options, OPTION_FORCE_TVOUT, FALSE)) { +- if (radeon_output->type == OUTPUT_STV) +- radeon_output->MonType = MT_STV; +- else +- radeon_output->MonType = MT_CTV; +- } else { +- if (info->InternalTVOut) { +- if (radeon_output->load_detection) +- radeon_output->MonType = radeon_detect_tv(pScrn); +- else + if (IS_AVIVO_VARIANT) { + radeon_output->MonType = avivo_display_ddc_connected(pScrn, output); + if (!radeon_output->MonType) { + if (radeon_output->type == OUTPUT_LVDS) + radeon_output->MonType = MT_LCD; -+ else if (OUTPUT_IS_TV) -+ radeon_output->MonType = MT_NONE; -+ else ++ else if (OUTPUT_IS_TV) { ++ if (xf86ReturnOptValBool(info->Options, OPTION_FORCE_TVOUT, FALSE)) { ++ if (radeon_output->type == OUTPUT_STV) ++ radeon_output->MonType = MT_STV; ++ else ++ radeon_output->MonType = MT_CTV; ++ } else + radeon_output->MonType = MT_NONE; +- } ++ } else + radeon_output->MonType = atombios_dac_detect(pScrn, output); -+ } -+ } else if (radeon_output->type == OUTPUT_STV || radeon_output->type == OUTPUT_CTV) { -+ if (xf86ReturnOptValBool(info->Options, OPTION_FORCE_TVOUT, FALSE)) { - if (radeon_output->type == OUTPUT_STV) - radeon_output->MonType = MT_STV; - else -@@ -650,21 +715,13 @@ void RADEONConnectorFindMonitor(ScrnInfoPtr pScrn, xf86OutputPtr output) + } } else { radeon_output->MonType = RADEONDisplayDDCConnected(pScrn, output); if (!radeon_output->MonType) { @@ -15144,7 +16473,7 @@ index 11a2a8a..15b4ddf 100644 } } } -@@ -676,10 +733,7 @@ void RADEONConnectorFindMonitor(ScrnInfoPtr pScrn, xf86OutputPtr output) +@@ -676,10 +736,7 @@ void RADEONConnectorFindMonitor(ScrnInfoPtr pScrn, xf86OutputPtr output) if (output->MonInfo) { xf86DrvMsg(pScrn->scrnIndex, X_INFO, "EDID data from the display on connector: %s ----------------------\n", @@ -15156,7 +16485,7 @@ index 11a2a8a..15b4ddf 100644 xf86PrintEDID( output->MonInfo ); } } -@@ -717,7 +771,7 @@ static RADEONMonitorType RADEONPortCheckNonDDC(ScrnInfoPtr pScrn, xf86OutputPtr +@@ -752,7 +809,7 @@ static RADEONMonitorType RADEONPortCheckNonDDC(ScrnInfoPtr pScrn, xf86OutputPtr }*/ xf86DrvMsg(pScrn->scrnIndex, X_INFO, @@ -15165,7 +16494,7 @@ index 11a2a8a..15b4ddf 100644 return MonType; -@@ -726,6 +780,14 @@ static RADEONMonitorType RADEONPortCheckNonDDC(ScrnInfoPtr pScrn, xf86OutputPtr +@@ -761,6 +818,14 @@ static RADEONMonitorType RADEONPortCheckNonDDC(ScrnInfoPtr pScrn, xf86OutputPtr static void radeon_dpms(xf86OutputPtr output, int mode) { @@ -15180,7 +16509,7 @@ index 11a2a8a..15b4ddf 100644 switch(mode) { case DPMSModeOn: RADEONEnableDisplay(output, TRUE); -@@ -755,8 +817,7 @@ radeon_mode_valid(xf86OutputPtr output, DisplayModePtr pMode) +@@ -790,8 +855,7 @@ radeon_mode_valid(xf86OutputPtr output, DisplayModePtr pMode) { RADEONOutputPrivatePtr radeon_output = output->driver_private; @@ -15190,7 +16519,172 @@ index 11a2a8a..15b4ddf 100644 /* FIXME: Update when more modes are added */ if (pMode->HDisplay == 800 && pMode->VDisplay == 600) return MODE_OK; -@@ -1166,7 +1227,7 @@ RADEONInitOutputRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save, +@@ -872,7 +936,7 @@ static void RADEONInitFPRegisters(xf86OutputPtr output, RADEONSavePtr save, + RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); + RADEONOutputPrivatePtr radeon_output = output->driver_private; + int i; +- CARD32 tmp = info->SavedReg.tmds_pll_cntl & 0xfffff; ++ CARD32 tmp = info->SavedReg->tmds_pll_cntl & 0xfffff; + + for (i=0; i<4; i++) { + if (radeon_output->tmds_pll[i].freq == 0) break; +@@ -886,12 +950,12 @@ static void RADEONInitFPRegisters(xf86OutputPtr output, RADEONSavePtr save, + if (tmp & 0xfff00000) + save->tmds_pll_cntl = tmp; + else { +- save->tmds_pll_cntl = info->SavedReg.tmds_pll_cntl & 0xfff00000; ++ save->tmds_pll_cntl = info->SavedReg->tmds_pll_cntl & 0xfff00000; + save->tmds_pll_cntl |= tmp; + } + } else save->tmds_pll_cntl = tmp; + +- save->tmds_transmitter_cntl = info->SavedReg.tmds_transmitter_cntl & ++ save->tmds_transmitter_cntl = info->SavedReg->tmds_transmitter_cntl & + ~(RADEON_TMDS_TRANSMITTER_PLLRST); + + if (IS_R300_VARIANT || (info->ChipFamily == CHIP_FAMILY_R200) || !pRADEONEnt->HasCRTC2) +@@ -899,7 +963,7 @@ static void RADEONInitFPRegisters(xf86OutputPtr output, RADEONSavePtr save, + else /* weird, RV chips got this bit reversed? */ + save->tmds_transmitter_cntl |= (RADEON_TMDS_TRANSMITTER_PLLEN); + +- save->fp_gen_cntl = info->SavedReg.fp_gen_cntl | ++ save->fp_gen_cntl = info->SavedReg->fp_gen_cntl | + (RADEON_FP_CRTC_DONT_SHADOW_VPAR | + RADEON_FP_CRTC_DONT_SHADOW_HEND ); + +@@ -938,10 +1002,10 @@ static void RADEONInitFP2Registers(xf86OutputPtr output, RADEONSavePtr save, + + + if (pScrn->rgbBits == 8) +- save->fp2_gen_cntl = info->SavedReg.fp2_gen_cntl | ++ save->fp2_gen_cntl = info->SavedReg->fp2_gen_cntl | + RADEON_FP2_PANEL_FORMAT; /* 24 bit format, */ + else +- save->fp2_gen_cntl = info->SavedReg.fp2_gen_cntl & ++ save->fp2_gen_cntl = info->SavedReg->fp2_gen_cntl & + ~RADEON_FP2_PANEL_FORMAT;/* 18 bit format, */ + + save->fp2_gen_cntl &= ~(RADEON_FP2_ON | +@@ -983,12 +1047,12 @@ static void RADEONInitLVDSRegisters(xf86OutputPtr output, RADEONSavePtr save, + ScrnInfoPtr pScrn = output->scrn; + RADEONInfoPtr info = RADEONPTR(pScrn); + +- save->lvds_pll_cntl = (info->SavedReg.lvds_pll_cntl | ++ save->lvds_pll_cntl = (info->SavedReg->lvds_pll_cntl | + RADEON_LVDS_PLL_EN); + + save->lvds_pll_cntl &= ~RADEON_LVDS_PLL_RESET; + +- save->lvds_gen_cntl = info->SavedReg.lvds_gen_cntl; ++ save->lvds_gen_cntl = info->SavedReg->lvds_gen_cntl; + save->lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS; + save->lvds_gen_cntl &= ~(RADEON_LVDS_ON | + RADEON_LVDS_BLON | +@@ -1023,9 +1087,9 @@ static void RADEONInitRMXRegisters(xf86OutputPtr output, RADEONSavePtr save, + int yres = mode->VDisplay; + float Hratio, Vratio; + +- save->fp_vert_stretch = info->SavedReg.fp_vert_stretch & ++ save->fp_vert_stretch = info->SavedReg->fp_vert_stretch & + RADEON_VERT_STRETCH_RESERVED; +- save->fp_horz_stretch = info->SavedReg.fp_horz_stretch & ++ save->fp_horz_stretch = info->SavedReg->fp_horz_stretch & + (RADEON_HORZ_FP_LOOP_STRETCH | + RADEON_HORZ_AUTO_RATIO_INC); + +@@ -1074,25 +1138,25 @@ static void RADEONInitDACRegisters(xf86OutputPtr output, RADEONSavePtr save, + + if (IsPrimary) { + if ((info->ChipFamily == CHIP_FAMILY_R200) || IS_R300_VARIANT) { +- save->disp_output_cntl = info->SavedReg.disp_output_cntl & ++ save->disp_output_cntl = info->SavedReg->disp_output_cntl & + ~RADEON_DISP_DAC_SOURCE_MASK; + } else { +- save->dac2_cntl = info->SavedReg.dac2_cntl & ~(RADEON_DAC2_DAC_CLK_SEL); ++ save->dac2_cntl = info->SavedReg->dac2_cntl & ~(RADEON_DAC2_DAC_CLK_SEL); + } + } else { + if ((info->ChipFamily == CHIP_FAMILY_R200) || IS_R300_VARIANT) { +- save->disp_output_cntl = info->SavedReg.disp_output_cntl & ++ save->disp_output_cntl = info->SavedReg->disp_output_cntl & + ~RADEON_DISP_DAC_SOURCE_MASK; + save->disp_output_cntl |= RADEON_DISP_DAC_SOURCE_CRTC2; + } else { +- save->dac2_cntl = info->SavedReg.dac2_cntl | RADEON_DAC2_DAC_CLK_SEL; ++ save->dac2_cntl = info->SavedReg->dac2_cntl | RADEON_DAC2_DAC_CLK_SEL; + } + } + save->dac_cntl = (RADEON_DAC_MASK_ALL + | RADEON_DAC_VGA_ADR_EN + | (info->dac6bits ? 0 : RADEON_DAC_8BIT_EN)); + +- save->dac_macro_cntl = info->SavedReg.dac_macro_cntl; ++ save->dac_macro_cntl = info->SavedReg->dac_macro_cntl; + } + + static void +@@ -1104,7 +1168,7 @@ RADEONInitTvDacCntl(xf86OutputPtr output, RADEONSavePtr save) + + if (info->ChipFamily == CHIP_FAMILY_R420 || + info->ChipFamily == CHIP_FAMILY_RV410) { +- save->tv_dac_cntl = info->SavedReg.tv_dac_cntl & ++ save->tv_dac_cntl = info->SavedReg->tv_dac_cntl & + ~(RADEON_TV_DAC_STD_MASK | + RADEON_TV_DAC_BGADJ_MASK | + R420_TV_DAC_DACADJ_MASK | +@@ -1113,7 +1177,7 @@ RADEONInitTvDacCntl(xf86OutputPtr output, RADEONSavePtr save) + R420_TV_DAC_GDACPD | + R420_TV_DAC_TVENABLE); + } else { +- save->tv_dac_cntl = info->SavedReg.tv_dac_cntl & ++ save->tv_dac_cntl = info->SavedReg->tv_dac_cntl & + ~(RADEON_TV_DAC_STD_MASK | + RADEON_TV_DAC_BGADJ_MASK | + RADEON_TV_DAC_DACADJ_MASK | +@@ -1139,34 +1203,34 @@ static void RADEONInitDAC2Registers(xf86OutputPtr output, RADEONSavePtr save, + RADEONInitTvDacCntl(output, save); + + if (IS_R300_VARIANT) +- save->gpiopad_a = info->SavedReg.gpiopad_a | 1; ++ save->gpiopad_a = info->SavedReg->gpiopad_a | 1; + +- save->dac2_cntl = info->SavedReg.dac2_cntl | RADEON_DAC2_DAC2_CLK_SEL; ++ save->dac2_cntl = info->SavedReg->dac2_cntl | RADEON_DAC2_DAC2_CLK_SEL; + + if (IsPrimary) { + if (IS_R300_VARIANT) { +- save->disp_output_cntl = info->SavedReg.disp_output_cntl & ++ save->disp_output_cntl = info->SavedReg->disp_output_cntl & + ~RADEON_DISP_TVDAC_SOURCE_MASK; + save->disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC; + } else if (info->ChipFamily == CHIP_FAMILY_R200) { +- save->fp2_gen_cntl = info->SavedReg.fp2_gen_cntl & ++ save->fp2_gen_cntl = info->SavedReg->fp2_gen_cntl & + ~(R200_FP2_SOURCE_SEL_MASK | + RADEON_FP2_DVO_RATE_SEL_SDR); + } else { +- save->disp_hw_debug = info->SavedReg.disp_hw_debug | RADEON_CRT2_DISP1_SEL; ++ save->disp_hw_debug = info->SavedReg->disp_hw_debug | RADEON_CRT2_DISP1_SEL; + } + } else { + if (IS_R300_VARIANT) { +- save->disp_output_cntl = info->SavedReg.disp_output_cntl & ++ save->disp_output_cntl = info->SavedReg->disp_output_cntl & + ~RADEON_DISP_TVDAC_SOURCE_MASK; + save->disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC2; + } else if (info->ChipFamily == CHIP_FAMILY_R200) { +- save->fp2_gen_cntl = info->SavedReg.fp2_gen_cntl & ++ save->fp2_gen_cntl = info->SavedReg->fp2_gen_cntl & + ~(R200_FP2_SOURCE_SEL_MASK | + RADEON_FP2_DVO_RATE_SEL_SDR); + save->fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2; + } else { +- save->disp_hw_debug = info->SavedReg.disp_hw_debug & ++ save->disp_hw_debug = info->SavedReg->disp_hw_debug & + ~RADEON_CRT2_DISP1_SEL; + } + } +@@ -1204,7 +1268,7 @@ RADEONInitOutputRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save, } static void @@ -15199,19 +16693,53 @@ index 11a2a8a..15b4ddf 100644 DisplayModePtr adjusted_mode) { ScrnInfoPtr pScrn = output->scrn; -@@ -1191,7 +1252,10 @@ radeon_mode_set(xf86OutputPtr output, DisplayModePtr mode, - RADEONRestoreFPRegisters(pScrn, &info->ModeReg); +@@ -1213,43 +1277,60 @@ radeon_mode_set(xf86OutputPtr output, DisplayModePtr mode, + xf86CrtcPtr crtc = output->crtc; + RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; + +- RADEONInitOutputRegisters(pScrn, &info->ModeReg, adjusted_mode, output, radeon_crtc->crtc_id); ++ RADEONInitOutputRegisters(pScrn, info->ModeReg, adjusted_mode, output, radeon_crtc->crtc_id); + + if (radeon_crtc->crtc_id == 0) +- RADEONRestoreRMXRegisters(pScrn, &info->ModeReg); ++ RADEONRestoreRMXRegisters(pScrn, info->ModeReg); + + switch(radeon_output->MonType) { + case MT_LCD: + ErrorF("restore LVDS\n"); +- RADEONRestoreLVDSRegisters(pScrn, &info->ModeReg); ++ RADEONRestoreLVDSRegisters(pScrn, info->ModeReg); + break; + case MT_DFP: + if (radeon_output->TMDSType == TMDS_INT) { + ErrorF("restore FP\n"); +- RADEONRestoreFPRegisters(pScrn, &info->ModeReg); ++ RADEONRestoreFPRegisters(pScrn, info->ModeReg); } else { ErrorF("restore FP2\n"); - RADEONRestoreDVOChip(pScrn, output); +- RADEONRestoreFP2Registers(pScrn, &info->ModeReg); + if (info->IsAtomBios) + atombios_external_tmds_setup(output, mode); + else + RADEONRestoreDVOChip(pScrn, output); - RADEONRestoreFP2Registers(pScrn, &info->ModeReg); ++ RADEONRestoreFP2Registers(pScrn, info->ModeReg); } break; -@@ -1209,9 +1273,23 @@ radeon_mode_set(xf86OutputPtr output, DisplayModePtr mode, + case MT_STV: + case MT_CTV: + ErrorF("restore tv\n"); +- RADEONRestoreDACRegisters(pScrn, &info->ModeReg); +- RADEONRestoreTVRegisters(pScrn, &info->ModeReg); ++ RADEONRestoreDACRegisters(pScrn, info->ModeReg); ++ RADEONRestoreTVRegisters(pScrn, info->ModeReg); + break; + default: + ErrorF("restore dac\n"); +- RADEONRestoreDACRegisters(pScrn, &info->ModeReg); ++ RADEONRestoreDACRegisters(pScrn, info->ModeReg); + } + } static void @@ -15236,7 +16764,7 @@ index 11a2a8a..15b4ddf 100644 } /* the following functions are based on the load detection code -@@ -1642,19 +1720,6 @@ radeon_detect(xf86OutputPtr output) +@@ -1680,19 +1761,6 @@ radeon_detect(xf86OutputPtr output) radeon_output->MonType = MT_UNKNOWN; RADEONConnectorFindMonitor(pScrn, output); @@ -15256,7 +16784,7 @@ index 11a2a8a..15b4ddf 100644 /* set montype so users can force outputs on even if detection fails */ if (radeon_output->MonType == MT_NONE) { connected = FALSE; -@@ -1666,9 +1731,20 @@ radeon_detect(xf86OutputPtr output) +@@ -1704,9 +1772,20 @@ radeon_detect(xf86OutputPtr output) radeon_output->MonType = MT_STV; else if (radeon_output->type == OUTPUT_CTV) radeon_output->MonType = MT_CTV; @@ -15266,11 +16794,11 @@ index 11a2a8a..15b4ddf 100644 + radeon_output->MonType = MT_CV; + else if (radeon_output->type == OUTPUT_DVI_D) radeon_output->MonType = MT_DFP; ++ else if (radeon_output->type == OUTPUT_HDMI) ++ radeon_output->MonType = MT_DFP; + else if (radeon_output->type == OUTPUT_DVI_A) + radeon_output->MonType = MT_CRT; + else if (radeon_output->type == OUTPUT_DVI_I) { -+ if (radeon_output->MonType == MT_NONE) -+ connected = FALSE; + if (radeon_output->DVIType == DVI_ANALOG) + radeon_output->MonType = MT_CRT; + else if (radeon_output->DVIType == DVI_DIGITAL) @@ -15279,7 +16807,7 @@ index 11a2a8a..15b4ddf 100644 } if (radeon_output->MonType == MT_UNKNOWN) { -@@ -1690,13 +1766,13 @@ radeon_detect(xf86OutputPtr output) +@@ -1728,13 +1807,13 @@ radeon_detect(xf86OutputPtr output) /* default to unknown for flaky chips/connectors * so we can get something on the screen */ @@ -15295,7 +16823,16 @@ index 11a2a8a..15b4ddf 100644 radeon_output->MonType = MT_DFP; /* MT_LCD ??? */ return XF86OutputStatusUnknown; } -@@ -1824,8 +1900,7 @@ radeon_create_resources(xf86OutputPtr output) +@@ -1819,7 +1898,7 @@ radeon_create_resources(xf86OutputPtr output) + "RRConfigureOutputProperty error, %d\n", err); + } + /* Set the current value of the backlight property */ +- //data = (info->SavedReg.lvds_gen_cntl & RADEON_LVDS_BL_MOD_LEVEL_MASK) >> RADEON_LVDS_BL_MOD_LEVEL_SHIFT; ++ //data = (info->SavedReg->lvds_gen_cntl & RADEON_LVDS_BL_MOD_LEVEL_MASK) >> RADEON_LVDS_BL_MOD_LEVEL_SHIFT; + data = RADEON_MAX_BACKLIGHT_LEVEL; + err = RRChangeOutputProperty(output->randr_output, backlight_atom, + XA_INTEGER, 32, PropModeReplace, 1, &data, +@@ -1862,8 +1941,7 @@ radeon_create_resources(xf86OutputPtr output) } } @@ -15305,7 +16842,7 @@ index 11a2a8a..15b4ddf 100644 tmds_pll_atom = MAKE_ATOM("tmds_pll"); err = RRConfigureOutputProperty(output->randr_output, tmds_pll_atom, -@@ -1856,8 +1931,7 @@ radeon_create_resources(xf86OutputPtr output) +@@ -1894,8 +1972,7 @@ radeon_create_resources(xf86OutputPtr output) /* RMX control - fullscreen, centered, keep ratio, off */ /* actually more of a crtc property as only crtc1 has rmx */ @@ -15315,7 +16852,7 @@ index 11a2a8a..15b4ddf 100644 rmx_atom = MAKE_ATOM("scaler"); err = RRConfigureOutputProperty(output->randr_output, rmx_atom, -@@ -1881,31 +1955,27 @@ radeon_create_resources(xf86OutputPtr output) +@@ -1919,31 +1996,27 @@ radeon_create_resources(xf86OutputPtr output) } /* force auto/analog/digital for DVI-I ports */ @@ -15365,7 +16902,7 @@ index 11a2a8a..15b4ddf 100644 tv_hsize_atom = MAKE_ATOM("tv_horizontal_size"); range[0] = -MAX_H_SIZE; -@@ -1924,10 +1994,7 @@ radeon_create_resources(xf86OutputPtr output) +@@ -1962,10 +2035,7 @@ radeon_create_resources(xf86OutputPtr output) xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "RRChangeOutputProperty error, %d\n", err); } @@ -15376,7 +16913,7 @@ index 11a2a8a..15b4ddf 100644 tv_hpos_atom = MAKE_ATOM("tv_horizontal_position"); range[0] = -MAX_H_POSITION; -@@ -1946,10 +2013,7 @@ radeon_create_resources(xf86OutputPtr output) +@@ -1984,10 +2054,7 @@ radeon_create_resources(xf86OutputPtr output) xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "RRChangeOutputProperty error, %d\n", err); } @@ -15387,7 +16924,7 @@ index 11a2a8a..15b4ddf 100644 tv_vpos_atom = MAKE_ATOM("tv_vertical_position"); range[0] = -MAX_V_POSITION; -@@ -1968,10 +2032,7 @@ radeon_create_resources(xf86OutputPtr output) +@@ -2006,10 +2073,7 @@ radeon_create_resources(xf86OutputPtr output) xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "RRChangeOutputProperty error, %d\n", err); } @@ -15398,7 +16935,7 @@ index 11a2a8a..15b4ddf 100644 tv_std_atom = MAKE_ATOM("tv_standard"); err = RRConfigureOutputProperty(output->randr_output, tv_std_atom, -@@ -2187,6 +2248,12 @@ radeon_set_property(xf86OutputPtr output, Atom property, +@@ -2225,6 +2289,12 @@ radeon_set_property(xf86OutputPtr output, Atom property, } else if (value->size == strlen("scart-pal") && !strncmp("scart-pal", s, strlen("scart-pal"))) { radeon_output->tvStd = TV_STD_SCART_PAL; return TRUE; @@ -15411,7 +16948,7 @@ index 11a2a8a..15b4ddf 100644 } return FALSE; } -@@ -2212,52 +2279,133 @@ static const xf86OutputFuncsRec radeon_output_funcs = { +@@ -2250,52 +2320,136 @@ static const xf86OutputFuncsRec radeon_output_funcs = { void RADEONSetOutputType(ScrnInfoPtr pScrn, RADEONOutputPrivatePtr radeon_output) { @@ -15472,6 +17009,9 @@ index 11a2a8a..15b4ddf 100644 + output = OUTPUT_CTV; break; + case CONNECTOR_LVDS: + output = OUTPUT_LVDS; break; ++ case CONNECTOR_HDMI_TYPE_A: ++ case CONNECTOR_HDMI_TYPE_B: ++ output = OUTPUT_HDMI; break; + case CONNECTOR_DIGITAL: + case CONNECTOR_NONE: + case CONNECTOR_UNSUPPORTED: @@ -15585,7 +17125,7 @@ index 11a2a8a..15b4ddf 100644 static void RADEONI2CGetBits(I2CBusPtr b, int *Clock, int *data) { ScrnInfoPtr pScrn = xf86Screens[b->scrnIndex]; -@@ -2611,18 +2759,20 @@ RADEONGetTVInfo(xf86OutputPtr output) +@@ -2649,18 +2803,20 @@ RADEONGetTVInfo(xf86OutputPtr output) void RADEONInitConnector(xf86OutputPtr output) { ScrnInfoPtr pScrn = output->scrn; @@ -15617,7 +17157,7 @@ index 11a2a8a..15b4ddf 100644 } if (radeon_output->DACType == DAC_PRIMARY) -@@ -2633,17 +2783,12 @@ void RADEONInitConnector(xf86OutputPtr output) +@@ -2671,17 +2827,12 @@ void RADEONInitConnector(xf86OutputPtr output) else radeon_output->load_detection = 0; /* shared tvdac between vga/dvi/tv */ @@ -15636,7 +17176,7 @@ index 11a2a8a..15b4ddf 100644 I2CBusPtr pDVOBus; radeon_output->rmx_type = RMX_OFF; if (radeon_output->TMDSType == TMDS_EXT) { -@@ -2667,8 +2812,7 @@ void RADEONInitConnector(xf86OutputPtr output) +@@ -2705,8 +2856,7 @@ void RADEONInitConnector(xf86OutputPtr output) RADEONGetTMDSInfo(output); } @@ -15646,7 +17186,7 @@ index 11a2a8a..15b4ddf 100644 RADEONGetTVInfo(output); RADEONGetTVDacAdjInfo(output); } -@@ -2688,32 +2832,32 @@ static Bool RADEONSetupAppleConnectors(ScrnInfoPtr pScrn) +@@ -2726,32 +2876,32 @@ static Bool RADEONSetupAppleConnectors(ScrnInfoPtr pScrn) switch (info->MacModel) { case RADEON_MAC_IBOOK: @@ -15687,7 +17227,7 @@ index 11a2a8a..15b4ddf 100644 info->BiosConnector[1].DACType = DAC_PRIMARY; info->BiosConnector[1].TMDSType = TMDS_EXT; info->BiosConnector[1].ConnectorType = CONNECTOR_DVI_I; -@@ -2722,17 +2866,18 @@ static Bool RADEONSetupAppleConnectors(ScrnInfoPtr pScrn) +@@ -2760,17 +2910,18 @@ static Bool RADEONSetupAppleConnectors(ScrnInfoPtr pScrn) info->BiosConnector[2].ConnectorType = CONNECTOR_STV; info->BiosConnector[2].DACType = DAC_TVDAC; info->BiosConnector[2].TMDSType = TMDS_NONE; @@ -15710,7 +17250,7 @@ index 11a2a8a..15b4ddf 100644 info->BiosConnector[1].DACType = DAC_PRIMARY; info->BiosConnector[1].TMDSType = TMDS_INT; info->BiosConnector[1].ConnectorType = CONNECTOR_DVI_I; -@@ -2741,17 +2886,17 @@ static Bool RADEONSetupAppleConnectors(ScrnInfoPtr pScrn) +@@ -2779,17 +2930,17 @@ static Bool RADEONSetupAppleConnectors(ScrnInfoPtr pScrn) info->BiosConnector[2].ConnectorType = CONNECTOR_STV; info->BiosConnector[2].DACType = DAC_TVDAC; info->BiosConnector[2].TMDSType = TMDS_NONE; @@ -15732,7 +17272,7 @@ index 11a2a8a..15b4ddf 100644 info->BiosConnector[1].DACType = DAC_PRIMARY; info->BiosConnector[1].TMDSType = TMDS_INT; info->BiosConnector[1].ConnectorType = CONNECTOR_DVI_I; -@@ -2760,11 +2905,11 @@ static Bool RADEONSetupAppleConnectors(ScrnInfoPtr pScrn) +@@ -2798,11 +2949,11 @@ static Bool RADEONSetupAppleConnectors(ScrnInfoPtr pScrn) info->BiosConnector[2].ConnectorType = CONNECTOR_STV; info->BiosConnector[2].DACType = DAC_TVDAC; info->BiosConnector[2].TMDSType = TMDS_NONE; @@ -15746,7 +17286,7 @@ index 11a2a8a..15b4ddf 100644 info->BiosConnector[0].DACType = DAC_TVDAC; info->BiosConnector[0].TMDSType = TMDS_EXT; info->BiosConnector[0].ConnectorType = CONNECTOR_DVI_I; -@@ -2773,11 +2918,11 @@ static Bool RADEONSetupAppleConnectors(ScrnInfoPtr pScrn) +@@ -2811,11 +2962,11 @@ static Bool RADEONSetupAppleConnectors(ScrnInfoPtr pScrn) info->BiosConnector[1].ConnectorType = CONNECTOR_STV; info->BiosConnector[1].DACType = DAC_TVDAC; info->BiosConnector[1].TMDSType = TMDS_NONE; @@ -15760,7 +17300,7 @@ index 11a2a8a..15b4ddf 100644 info->BiosConnector[0].DACType = DAC_TVDAC; info->BiosConnector[0].TMDSType = TMDS_INT; info->BiosConnector[0].ConnectorType = CONNECTOR_DVI_I; -@@ -2786,26 +2931,26 @@ static Bool RADEONSetupAppleConnectors(ScrnInfoPtr pScrn) +@@ -2824,26 +2975,26 @@ static Bool RADEONSetupAppleConnectors(ScrnInfoPtr pScrn) info->BiosConnector[1].ConnectorType = CONNECTOR_STV; info->BiosConnector[1].DACType = DAC_TVDAC; info->BiosConnector[1].TMDSType = TMDS_NONE; @@ -15792,7 +17332,7 @@ index 11a2a8a..15b4ddf 100644 info->BiosConnector[2].valid = TRUE; return TRUE; default: -@@ -2822,108 +2967,146 @@ static void RADEONSetupGenericConnectors(ScrnInfoPtr pScrn) +@@ -2860,108 +3011,146 @@ static void RADEONSetupGenericConnectors(ScrnInfoPtr pScrn) RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); if (!pRADEONEnt->HasCRTC2) { @@ -15994,7 +17534,7 @@ index 11a2a8a..15b4ddf 100644 +#endif + } + } -+ + + if (info->InternalTVOut) { + info->BiosConnector[2].ConnectorType = CONNECTOR_STV; + info->BiosConnector[2].DACType = DAC_TVDAC; @@ -16002,7 +17542,7 @@ index 11a2a8a..15b4ddf 100644 + info->BiosConnector[2].ddc_line = 0; + info->BiosConnector[2].valid = TRUE; + } - ++ + /* Some cards have the DDC lines swapped and we have no way to + * detect it yet (Mac cards) + */ @@ -16014,7 +17554,15 @@ index 11a2a8a..15b4ddf 100644 } #if defined(__powerpc__) -@@ -3060,7 +3243,7 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn) +@@ -3091,6 +3280,7 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn) + int i = 0; + int num_vga = 0; + int num_dvi = 0; ++ int num_hdmi = 0; + + /* We first get the information about all connectors from BIOS. + * This is how the card is phyiscally wired up. +@@ -3098,7 +3288,7 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn) */ for (i = 0; i < RADEON_MAX_BIOS_CONNECTOR; i++) { info->BiosConnector[i].valid = FALSE; @@ -16023,7 +17571,7 @@ index 11a2a8a..15b4ddf 100644 info->BiosConnector[i].DACType = DAC_UNKNOWN; info->BiosConnector[i].TMDSType = TMDS_UNKNOWN; info->BiosConnector[i].ConnectorType = CONNECTOR_NONE; -@@ -3114,12 +3297,12 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn) +@@ -3152,12 +3342,12 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn) if (info->HasSingleDAC) { /* For RS300/RS350/RS400 chips, there is no primary DAC. Force VGA port to use TVDAC*/ for (i = 0; i < RADEON_MAX_BIOS_CONNECTOR; i++) { @@ -16038,7 +17586,7 @@ index 11a2a8a..15b4ddf 100644 info->BiosConnector[i].DACType = DAC_PRIMARY; } } -@@ -3134,11 +3317,11 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn) +@@ -3172,11 +3362,11 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn) info->BiosConnector[0].valid = TRUE; info->BiosConnector[1].valid = TRUE; if (sscanf(optstr, "%u,%d,%d,%u,%u,%d,%d,%u", @@ -16052,7 +17600,7 @@ index 11a2a8a..15b4ddf 100644 &info->BiosConnector[1].DACType, &info->BiosConnector[1].TMDSType, &info->BiosConnector[1].ConnectorType) != 8) { -@@ -3153,21 +3336,12 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn) +@@ -3191,21 +3381,15 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn) if (info->BiosConnector[i].DACType == DAC_TVDAC) info->tvdac_use_count++; @@ -16077,10 +17625,13 @@ index 11a2a8a..15b4ddf 100644 + num_dvi++; + } else if (info->BiosConnector[i].ConnectorType == CONNECTOR_VGA) { + num_vga++; ++ } else if ((info->BiosConnector[i].ConnectorType == CONNECTOR_HDMI_TYPE_A) || ++ (info->BiosConnector[i].ConnectorType == CONNECTOR_HDMI_TYPE_B)) { ++ num_hdmi++; } } } -@@ -3180,67 +3354,39 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn) +@@ -3226,67 +3410,47 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn) } radeon_output->MonType = MT_UNKNOWN; radeon_output->ConnectorType = info->BiosConnector[i].ConnectorType; @@ -16173,6 +17724,14 @@ index 11a2a8a..15b4ddf 100644 + } else { + output = xf86OutputCreate(pScrn, &radeon_output_funcs, "VGA-0"); + } ++ } else if ((info->BiosConnector[i].ConnectorType == CONNECTOR_HDMI_TYPE_A) || ++ (info->BiosConnector[i].ConnectorType == CONNECTOR_HDMI_TYPE_B)) { ++ if (num_hdmi > 1) { ++ output = xf86OutputCreate(pScrn, &radeon_output_funcs, "HDMI-1"); ++ num_hdmi--; ++ } else { ++ output = xf86OutputCreate(pScrn, &radeon_output_funcs, "HDMI-0"); ++ } + } else + output = xf86OutputCreate(pScrn, &radeon_output_funcs, OutputType[radeon_output->type]); @@ -16322,8 +17881,21 @@ index 7a36242..5847d5a 100644 + { PCI_CHIP_RV630_958E, PCI_CHIP_RV630_958E, RES_SHARED_VGA }, { -1, -1, RES_UNDEFINED } }; +diff --git a/src/radeon_probe.c b/src/radeon_probe.c +index baea47c..e0a77e6 100644 +--- a/src/radeon_probe.c ++++ b/src/radeon_probe.c +@@ -175,7 +175,7 @@ RADEONProbe(DriverPtr drv, int flags) + DevUnion *pPriv; + RADEONEntPtr pRADEONEnt; + +- /*xf86SetEntitySharable(usedChips[i]);*/ ++ xf86SetEntitySharable(usedChips[i]); + + if (gRADEONEntityIndex == -1) + gRADEONEntityIndex = xf86AllocateEntityPrivateIndex(); diff --git a/src/radeon_probe.h b/src/radeon_probe.h -index 66ece94..d01fd8b 100644 +index 7f8ce45..a25d635 100644 --- a/src/radeon_probe.h +++ b/src/radeon_probe.h @@ -36,6 +36,7 @@ @@ -16358,7 +17930,7 @@ index 66ece94..d01fd8b 100644 - MT_STV = 5 + MT_STV = 5, + MT_CV = 6, -+ MT_HDMI = 7, ++ MT_HDMI = 7, // this should really just be MT_DFP + MT_DP = 8 } RADEONMonitorType; @@ -16437,8 +18009,8 @@ index 66ece94..d01fd8b 100644 } TVStd; typedef struct _RADEONCrtcPrivateRec { -@@ -168,21 +167,33 @@ typedef struct _RADEONCrtcPrivateRec { - int binding; +@@ -169,21 +168,32 @@ typedef struct _RADEONCrtcPrivateRec { + CARD32 cursor_offset; /* Lookup table values to be set when the CRTC is enabled */ CARD8 lut_r[256], lut_g[256], lut_b[256]; + @@ -16449,7 +18021,6 @@ index 66ece94..d01fd8b 100644 + int fb_pitch, fb_width, fb_height; + INT16 cursor_x; + INT16 cursor_y; -+ unsigned long cursor_offset; } RADEONCrtcPrivateRec, *RADEONCrtcPrivatePtr; typedef struct { @@ -16473,7 +18044,7 @@ index 66ece94..d01fd8b 100644 RADEONDacType DACType; RADEONDviType DVIType; RADEONTmdsType TMDSType; -@@ -221,10 +232,14 @@ typedef struct _RADEONOutputPrivateRec { +@@ -222,10 +232,289 @@ typedef struct _RADEONOutputPrivateRec { int SupportedTVStds; Bool tv_on; int load_detection; @@ -16483,17 +18054,305 @@ index 66ece94..d01fd8b 100644 + int devices; } RADEONOutputPrivateRec, *RADEONOutputPrivatePtr; ++struct avivo_pll_state { ++ CARD32 ref_div_src; ++ CARD32 ref_div; ++ CARD32 fb_div; ++ CARD32 post_div_src; ++ CARD32 post_div; ++ CARD32 ext_ppll_cntl; ++ CARD32 pll_cntl; ++ CARD32 int_ss_cntl; ++}; ++ ++ ++struct avivo_crtc_state { ++ CARD32 pll_source; ++ CARD32 h_total; ++ CARD32 h_blank_start_end; ++ CARD32 h_sync_a; ++ CARD32 h_sync_a_cntl; ++ CARD32 h_sync_b; ++ CARD32 h_sync_b_cntl; ++ CARD32 v_total; ++ CARD32 v_blank_start_end; ++ CARD32 v_sync_a; ++ CARD32 v_sync_a_cntl; ++ CARD32 v_sync_b; ++ CARD32 v_sync_b_cntl; ++ CARD32 control; ++ CARD32 blank_control; ++ CARD32 interlace_control; ++ CARD32 stereo_control; ++ CARD32 cursor_control; ++}; ++ ++struct avivo_grph_state { ++ CARD32 enable; ++ CARD32 control; ++ CARD32 prim_surf_addr; ++ CARD32 sec_surf_addr; ++ CARD32 pitch; ++ CARD32 x_offset; ++ CARD32 y_offset; ++ CARD32 x_start; ++ CARD32 y_start; ++ CARD32 x_end; ++ CARD32 y_end; ++ ++ CARD32 viewport_start; ++ CARD32 viewport_size; ++ CARD32 scl_enable; ++}; ++ ++struct avivo_dac_state { ++ CARD32 enable; ++ CARD32 source_select; ++ CARD32 force_output_cntl; ++ CARD32 powerdown; ++}; ++ ++struct avivo_dig_state { ++ CARD32 cntl; ++ CARD32 bit_depth_cntl; ++ CARD32 data_sync; ++ CARD32 transmitter_enable; ++ CARD32 transmitter_cntl; ++ CARD32 source_select; ++}; ++ ++struct avivo_state ++{ ++ CARD32 hdp_fb_location; ++ CARD32 mc_memory_map; ++ CARD32 vga_memory_base; ++ CARD32 vga_fb_start; ++ ++ CARD32 vga1_cntl; ++ CARD32 vga2_cntl; ++ ++ CARD32 crtc_master_en; ++ CARD32 crtc_tv_control; ++ ++ CARD32 lvtma_pwrseq_cntl; ++ CARD32 lvtma_pwrseq_state; ++ ++ struct avivo_pll_state pll1; ++ struct avivo_pll_state pll2; ++ ++ struct avivo_crtc_state crtc1; ++ struct avivo_crtc_state crtc2; ++ ++ struct avivo_grph_state grph1; ++ struct avivo_grph_state grph2; ++ ++ struct avivo_dac_state daca; ++ struct avivo_dac_state dacb; ++ ++ struct avivo_dig_state tmds1; ++ struct avivo_dig_state tmds2; ++ ++}; ++ ++/* ++ * Maximum length of horizontal/vertical code timing tables for state storage ++ */ ++#define MAX_H_CODE_TIMING_LEN 32 ++#define MAX_V_CODE_TIMING_LEN 32 ++ ++typedef struct { ++ struct avivo_state avivo; ++ ++ /* Common registers */ ++ CARD32 ovr_clr; ++ CARD32 ovr_wid_left_right; ++ CARD32 ovr_wid_top_bottom; ++ CARD32 ov0_scale_cntl; ++ CARD32 mpp_tb_config; ++ CARD32 mpp_gp_config; ++ CARD32 subpic_cntl; ++ CARD32 viph_control; ++ CARD32 i2c_cntl_1; ++ CARD32 gen_int_cntl; ++ CARD32 cap0_trig_cntl; ++ CARD32 cap1_trig_cntl; ++ CARD32 bus_cntl; ++ CARD32 bios_4_scratch; ++ CARD32 bios_5_scratch; ++ CARD32 bios_6_scratch; ++ CARD32 surface_cntl; ++ CARD32 surfaces[8][3]; ++ CARD32 mc_agp_location; ++ CARD32 mc_agp_location_hi; ++ CARD32 mc_fb_location; ++ CARD32 display_base_addr; ++ CARD32 display2_base_addr; ++ CARD32 ov0_base_addr; ++ ++ /* Other registers to save for VT switches */ ++ CARD32 dp_datatype; ++ CARD32 rbbm_soft_reset; ++ CARD32 clock_cntl_index; ++ CARD32 amcgpio_en_reg; ++ CARD32 amcgpio_mask; ++ ++ /* CRTC registers */ ++ CARD32 crtc_gen_cntl; ++ CARD32 crtc_ext_cntl; ++ CARD32 dac_cntl; ++ CARD32 crtc_h_total_disp; ++ CARD32 crtc_h_sync_strt_wid; ++ CARD32 crtc_v_total_disp; ++ CARD32 crtc_v_sync_strt_wid; ++ CARD32 crtc_offset; ++ CARD32 crtc_offset_cntl; ++ CARD32 crtc_pitch; ++ CARD32 disp_merge_cntl; ++ CARD32 grph_buffer_cntl; ++ CARD32 crtc_more_cntl; ++ CARD32 crtc_tile_x0_y0; ++ ++ /* CRTC2 registers */ ++ CARD32 crtc2_gen_cntl; ++ CARD32 dac_macro_cntl; ++ CARD32 dac2_cntl; ++ CARD32 disp_output_cntl; ++ CARD32 disp_tv_out_cntl; ++ CARD32 disp_hw_debug; ++ CARD32 disp2_merge_cntl; ++ CARD32 grph2_buffer_cntl; ++ CARD32 crtc2_h_total_disp; ++ CARD32 crtc2_h_sync_strt_wid; ++ CARD32 crtc2_v_total_disp; ++ CARD32 crtc2_v_sync_strt_wid; ++ CARD32 crtc2_offset; ++ CARD32 crtc2_offset_cntl; ++ CARD32 crtc2_pitch; ++ CARD32 crtc2_tile_x0_y0; ++ ++ /* Flat panel registers */ ++ CARD32 fp_crtc_h_total_disp; ++ CARD32 fp_crtc_v_total_disp; ++ CARD32 fp_gen_cntl; ++ CARD32 fp2_gen_cntl; ++ CARD32 fp_h_sync_strt_wid; ++ CARD32 fp_h2_sync_strt_wid; ++ CARD32 fp_horz_stretch; ++ CARD32 fp_panel_cntl; ++ CARD32 fp_v_sync_strt_wid; ++ CARD32 fp_v2_sync_strt_wid; ++ CARD32 fp_vert_stretch; ++ CARD32 lvds_gen_cntl; ++ CARD32 lvds_pll_cntl; ++ CARD32 tmds_pll_cntl; ++ CARD32 tmds_transmitter_cntl; ++ ++ /* Computed values for PLL */ ++ CARD32 dot_clock_freq; ++ CARD32 pll_output_freq; ++ int feedback_div; ++ int reference_div; ++ int post_div; ++ ++ /* PLL registers */ ++ unsigned ppll_ref_div; ++ unsigned ppll_div_3; ++ CARD32 htotal_cntl; ++ CARD32 vclk_ecp_cntl; ++ ++ /* Computed values for PLL2 */ ++ CARD32 dot_clock_freq_2; ++ CARD32 pll_output_freq_2; ++ int feedback_div_2; ++ int reference_div_2; ++ int post_div_2; ++ ++ /* PLL2 registers */ ++ CARD32 p2pll_ref_div; ++ CARD32 p2pll_div_0; ++ CARD32 htotal_cntl2; ++ CARD32 pixclks_cntl; ++ ++ /* Pallet */ ++ Bool palette_valid; ++ CARD32 palette[256]; ++ CARD32 palette2[256]; ++ ++ CARD32 rs480_unk_e30; ++ CARD32 rs480_unk_e34; ++ CARD32 rs480_unk_e38; ++ CARD32 rs480_unk_e3c; ++ ++ /* TV out registers */ ++ CARD32 tv_master_cntl; ++ CARD32 tv_htotal; ++ CARD32 tv_hsize; ++ CARD32 tv_hdisp; ++ CARD32 tv_hstart; ++ CARD32 tv_vtotal; ++ CARD32 tv_vdisp; ++ CARD32 tv_timing_cntl; ++ CARD32 tv_vscaler_cntl1; ++ CARD32 tv_vscaler_cntl2; ++ CARD32 tv_sync_size; ++ CARD32 tv_vrestart; ++ CARD32 tv_hrestart; ++ CARD32 tv_frestart; ++ CARD32 tv_ftotal; ++ CARD32 tv_clock_sel_cntl; ++ CARD32 tv_clkout_cntl; ++ CARD32 tv_data_delay_a; ++ CARD32 tv_data_delay_b; ++ CARD32 tv_dac_cntl; ++ CARD32 tv_pll_cntl; ++ CARD32 tv_pll_cntl1; ++ CARD32 tv_pll_fine_cntl; ++ CARD32 tv_modulator_cntl1; ++ CARD32 tv_modulator_cntl2; ++ CARD32 tv_frame_lock_cntl; ++ CARD32 tv_pre_dac_mux_cntl; ++ CARD32 tv_rgb_cntl; ++ CARD32 tv_y_saw_tooth_cntl; ++ CARD32 tv_y_rise_cntl; ++ CARD32 tv_y_fall_cntl; ++ CARD32 tv_uv_adr; ++ CARD32 tv_upsamp_and_gain_cntl; ++ CARD32 tv_gain_limit_settings; ++ CARD32 tv_linear_gain_settings; ++ CARD32 tv_crc_cntl; ++ CARD32 tv_sync_cntl; ++ CARD32 gpiopad_a; ++ CARD32 pll_test_cntl; ++ ++ CARD16 h_code_timing[MAX_H_CODE_TIMING_LEN]; ++ CARD16 v_code_timing[MAX_V_CODE_TIMING_LEN]; ++ ++} RADEONSaveRec, *RADEONSavePtr; ++ #define RADEON_MAX_CRTC 2 -#define RADEON_MAX_BIOS_CONNECTOR 8 +#define RADEON_MAX_BIOS_CONNECTOR 16 typedef struct { +@@ -243,6 +532,12 @@ typedef struct + xf86CrtcPtr pCrtc[RADEON_MAX_CRTC]; + RADEONCrtcPrivatePtr Controller[RADEON_MAX_CRTC]; + ++ ScrnInfoPtr pSecondaryScrn; ++ ScrnInfoPtr pPrimaryScrn; ++ ++ RADEONSaveRec ModeReg; /* Current mode */ ++ RADEONSaveRec SavedReg; /* Original (text) mode */ ++ + } RADEONEntRec, *RADEONEntPtr; + + /* radeon_probe.c */ diff --git a/src/radeon_reg.h b/src/radeon_reg.h -index 2653339..8737d2e 100644 +index 6e4e383..dce29e2 100644 --- a/src/radeon_reg.h +++ b/src/radeon_reg.h -@@ -996,6 +996,7 @@ +@@ -997,6 +997,7 @@ #define RADEON_MPP_GP_CONFIG 0x01c8 /* ? */ #define R300_MC_IND_INDEX 0x01f8 # define R300_MC_IND_ADDR_MASK 0x3f @@ -16501,7 +18360,7 @@ index 2653339..8737d2e 100644 #define R300_MC_IND_DATA 0x01fc #define R300_MC_READ_CNTL_AB 0x017c # define R300_MEM_RBS_POSITION_A_MASK 0x03 -@@ -3270,4 +3271,455 @@ +@@ -3271,4 +3272,464 @@ #define RADEON_RS480_UNK_e38 0xe38 #define RADEON_RS480_UNK_e3c 0xe3c @@ -16624,6 +18483,7 @@ index 2653339..8737d2e 100644 +#define AVIVO_D1GRPH_X_END 0x6134 +#define AVIVO_D1GRPH_Y_END 0x6138 +#define AVIVO_D1GRPH_UPDATE 0x6144 ++# define AVIVO_D1GRPH_UPDATE_LOCK (1<<16) +#define AVIVO_D1GRPH_FLIP_CONTROL 0x6148 + +#define AVIVO_D1CUR_CONTROL 0x6400 @@ -16655,12 +18515,15 @@ index 2653339..8737d2e 100644 +#define AVIVO_DC_LUTA_WHITE_OFFSET_RED 0x64d8 + + ++#define AVIVO_D1MODE_DESKTOP_HEIGHT 0x652C +#define AVIVO_D1MODE_VIEWPORT_START 0x6580 +#define AVIVO_D1MODE_VIEWPORT_SIZE 0x6584 +#define AVIVO_D1MODE_EXT_OVERSCAN_LEFT_RIGHT 0x6588 +#define AVIVO_D1MODE_EXT_OVERSCAN_TOP_BOTTOM 0x658c + +#define AVIVO_D1SCL_SCALER_ENABLE 0x6590 ++#define AVIVO_D1SCL_UPDATE 0x65cc ++# define AVIVO_D1SCL_UPDATE_LOCK (1<<16) + +/* second crtc */ +#define AVIVO_D2CRTC_H_TOTAL 0x6800 @@ -16836,9 +18699,11 @@ index 2653339..8737d2e 100644 +#define AVIVO_LVTMA_DATA_SYNCHRONIZATION 0x78d8 +# define AVIVO_LVTMA_DATA_SYNCHRONIZATION_DSYNSEL (1 << 0) +# define AVIVO_LVTMA_DATA_SYNCHRONIZATION_PFREQCHG (1 << 8) -+#define AVIVO_LVTMA_CLOCK_ENABLE 0x7b00 ++#define R500_LVTMA_CLOCK_ENABLE 0x7b00 ++#define R600_LVTMA_CLOCK_ENABLE 0x7b04 + -+#define AVIVO_LVTMA_TRANSMITTER_ENABLE 0x7b04 ++#define R500_LVTMA_TRANSMITTER_ENABLE 0x7b04 ++#define R600_LVTMA_TRANSMITTER_ENABLE 0x7b08 +# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKC0EN (1 << 1) +# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD00EN (1 << 2) +# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD01EN (1 << 3) @@ -16851,7 +18716,8 @@ index 2653339..8737d2e 100644 +# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK (1 << 17) +# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK (1 << 18) + -+#define AVIVO_LVTMA_TRANSMITTER_CONTROL 0x7b10 ++#define R500_LVTMA_TRANSMITTER_CONTROL 0x7b10 ++#define R600_LVTMA_TRANSMITTER_CONTROL 0x7b14 +# define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_ENABLE (1 << 0) +# define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_RESET (1 << 1) +# define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_HPD_MASK_SHIFT (2) @@ -16867,7 +18733,8 @@ index 2653339..8737d2e 100644 +# define AVIVO_LVTMA_TRANSMITTER_CONTROL_USE_CLK_DATA (1 << 29) +# define AVIVO_LVTMA_TRANSMITTER_CONTROL_INPUT_TEST_CLK_SEL (1 << 31) + -+#define AVIVO_LVTMA_PWRSEQ_CNTL 0x7af0 ++#define R500_LVTMA_PWRSEQ_CNTL 0x7af0 ++#define R600_LVTMA_PWRSEQ_CNTL 0x7af4 +# define AVIVO_LVTMA_PWRSEQ_EN (1 << 0) +# define AVIVO_LVTMA_PWRSEQ_PLL_ENABLE_MASK (1 << 2) +# define AVIVO_LVTMA_PWRSEQ_PLL_RESET_MASK (1 << 3) @@ -16882,7 +18749,8 @@ index 2653339..8737d2e 100644 +# define AVIVO_LVTMA_BLON_OVRD (1 << 25) +# define AVIVO_LVTMA_BLON_POL (1 << 26) + -+#define AVIVO_LVTMA_PWRSEQ_STATE 0x7af4 ++#define R500_LVTMA_PWRSEQ_STATE 0x7af4 ++#define R600_LVTMA_PWRSEQ_STATE 0x7af8 +# define AVIVO_LVTMA_PWRSEQ_STATE_TARGET_STATE_R (1 << 0) +# define AVIVO_LVTMA_PWRSEQ_STATE_DIGON (1 << 1) +# define AVIVO_LVTMA_PWRSEQ_STATE_SYNCEN (1 << 2) @@ -16957,3 +18825,142 @@ index 2653339..8737d2e 100644 +#define R600_CONFIG_F0_BASE 0x542C +#define R600_CONFIG_APER_SIZE 0x5430 #endif +diff --git a/src/radeon_render.c b/src/radeon_render.c +index 490dec1..a80d136 100644 +--- a/src/radeon_render.c ++++ b/src/radeon_render.c +@@ -317,7 +317,7 @@ static Bool RADEONSetupRenderByteswap(ScrnInfoPtr pScrn, int tex_bytepp) + { + RADEONInfoPtr info = RADEONPTR(pScrn); + unsigned char *RADEONMMIO = info->MMIO; +- CARD32 swapper = info->ModeReg.surface_cntl; ++ CARD32 swapper = info->ModeReg->surface_cntl; + + swapper &= ~(RADEON_NONSURF_AP0_SWP_16BPP | RADEON_NONSURF_AP1_SWP_16BPP | + RADEON_NONSURF_AP0_SWP_32BPP | RADEON_NONSURF_AP1_SWP_32BPP); +@@ -345,7 +345,7 @@ static void RADEONRestoreByteswap(RADEONInfoPtr info) + { + unsigned char *RADEONMMIO = info->MMIO; + +- OUTREG(RADEON_SURFACE_CNTL, info->ModeReg.surface_cntl); ++ OUTREG(RADEON_SURFACE_CNTL, info->ModeReg->surface_cntl); + } + #endif /* X_BYTE_ORDER == X_BIG_ENDIAN */ + +diff --git a/src/radeon_tv.c b/src/radeon_tv.c +index 2a8873c..5e9a9c8 100644 +--- a/src/radeon_tv.c ++++ b/src/radeon_tv.c +@@ -540,7 +540,7 @@ void RADEONInitTVRegisters(xf86OutputPtr output, RADEONSavePtr save, + save->dac_cntl &= ~RADEON_DAC_TVO_EN; + + if (IS_R300_VARIANT) +- save->gpiopad_a = info->SavedReg.gpiopad_a & ~1; ++ save->gpiopad_a = info->SavedReg->gpiopad_a & ~1; + + if (IsPrimary) { + save->disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK; +@@ -571,7 +571,7 @@ void RADEONUpdateHVPosition(xf86OutputPtr output, DisplayModePtr mode) + RADEONInfoPtr info = RADEONPTR(pScrn); + unsigned char *RADEONMMIO = info->MMIO; + Bool reloadTable; +- RADEONSavePtr restore = &info->ModeReg; ++ RADEONSavePtr restore = info->ModeReg; + + reloadTable = RADEONInitTVRestarts(output, restore, mode); + +diff --git a/src/radeon_tv.h b/src/radeon_tv.h +index 5c8c8c9..c4b7838 100644 +--- a/src/radeon_tv.h ++++ b/src/radeon_tv.h +@@ -3,11 +3,6 @@ + * Federico Ulivi + */ + +-/* +- * Maximum length of horizontal/vertical code timing tables for state storage +- */ +-#define MAX_H_CODE_TIMING_LEN 32 +-#define MAX_V_CODE_TIMING_LEN 32 + + /* + * Limits of h/v positions (hPos & vPos) +diff --git a/src/radeon_video.c b/src/radeon_video.c +index 3f0209e..a84662e 100644 +--- a/src/radeon_video.c ++++ b/src/radeon_video.c +@@ -1430,7 +1430,7 @@ RADEONAllocAdaptor(ScrnInfoPtr pScrn) + * 0 for PIXCLK < 175Mhz, and 1 (divide by 2) + * for higher clocks, sure makes life nicer + */ +- dot_clock = info->ModeReg.dot_clock_freq; ++ dot_clock = info->ModeReg->dot_clock_freq; + + if (dot_clock < 17500) + info->ecp_div = 0; +@@ -2156,7 +2156,7 @@ RADEONCopyData( + { + #if X_BYTE_ORDER == X_BIG_ENDIAN + unsigned char *RADEONMMIO = info->MMIO; +- unsigned int swapper = info->ModeReg.surface_cntl & ++ unsigned int swapper = info->ModeReg->surface_cntl & + ~(RADEON_NONSURF_AP0_SWP_32BPP | RADEON_NONSURF_AP1_SWP_32BPP | + RADEON_NONSURF_AP0_SWP_16BPP | RADEON_NONSURF_AP1_SWP_16BPP); + +@@ -2182,7 +2182,7 @@ RADEONCopyData( + + #if X_BYTE_ORDER == X_BIG_ENDIAN + /* restore byte swapping */ +- OUTREG(RADEON_SURFACE_CNTL, info->ModeReg.surface_cntl); ++ OUTREG(RADEON_SURFACE_CNTL, info->ModeReg->surface_cntl); + #endif + } + } +@@ -2238,7 +2238,7 @@ RADEONCopyRGB24Data( + { + #if X_BYTE_ORDER == X_BIG_ENDIAN + unsigned char *RADEONMMIO = info->MMIO; +- OUTREG(RADEON_SURFACE_CNTL, (info->ModeReg.surface_cntl ++ OUTREG(RADEON_SURFACE_CNTL, (info->ModeReg->surface_cntl + | RADEON_NONSURF_AP0_SWP_32BPP) + & ~RADEON_NONSURF_AP0_SWP_16BPP); + #endif +@@ -2254,7 +2254,7 @@ RADEONCopyRGB24Data( + + #if X_BYTE_ORDER == X_BIG_ENDIAN + /* restore byte swapping */ +- OUTREG(RADEON_SURFACE_CNTL, info->ModeReg.surface_cntl); ++ OUTREG(RADEON_SURFACE_CNTL, info->ModeReg->surface_cntl); + #endif + } + } +@@ -2333,7 +2333,7 @@ RADEONCopyMungedData( + + #if X_BYTE_ORDER == X_BIG_ENDIAN + unsigned char *RADEONMMIO = info->MMIO; +- OUTREG(RADEON_SURFACE_CNTL, (info->ModeReg.surface_cntl ++ OUTREG(RADEON_SURFACE_CNTL, (info->ModeReg->surface_cntl + | RADEON_NONSURF_AP0_SWP_32BPP) + & ~RADEON_NONSURF_AP0_SWP_16BPP); + #endif +@@ -2371,7 +2371,7 @@ RADEONCopyMungedData( + } + #if X_BYTE_ORDER == X_BIG_ENDIAN + /* restore byte swapping */ +- OUTREG(RADEON_SURFACE_CNTL, info->ModeReg.surface_cntl); ++ OUTREG(RADEON_SURFACE_CNTL, info->ModeReg->surface_cntl); + #endif + } + } +@@ -2552,9 +2552,9 @@ RADEONDisplayVideo( + + /* Figure out which head we are on for dot clock */ + if (radeon_crtc->crtc_id == 1) +- dot_clock = info->ModeReg.dot_clock_freq_2; ++ dot_clock = info->ModeReg->dot_clock_freq_2; + else +- dot_clock = info->ModeReg.dot_clock_freq; ++ dot_clock = info->ModeReg->dot_clock_freq; + + if (dot_clock < 17500) + ecp_div = 0; diff --git a/radeon-fix-randr-gamma.patch b/radeon-fix-randr-gamma.patch deleted file mode 100644 index aa4dae8..0000000 --- a/radeon-fix-randr-gamma.patch +++ /dev/null @@ -1,20 +0,0 @@ -diff -up xf86-video-ati-6.7.196/src/radeon_driver.c.randr-gamma xf86-video-ati-6.7.196/src/radeon_driver.c ---- xf86-video-ati-6.7.196/src/radeon_driver.c.randr-gamma 2007-11-12 11:29:55.000000000 +1000 -+++ xf86-video-ati-6.7.196/src/radeon_driver.c 2007-11-29 17:30:03.000000000 +1000 -@@ -2932,10 +2932,13 @@ static void RADEONLoadPalette(ScrnInfoPt - - /* Make the change through RandR */ - #ifdef RANDR_12_INTERFACE -- RRCrtcGammaSet(crtc->randr_crtc, lut_r, lut_g, lut_b); --#else -- crtc->funcs->gamma_set(crtc, lut_r, lut_g, lut_b, 256); -+ if (crtc->randr_crtc) -+ RRCrtcGammaSet(crtc->randr_crtc, lut_r, lut_g, lut_b); -+ else - #endif -+ { -+ crtc->funcs->gamma_set(crtc, lut_r, lut_g, lut_b, 256); -+ } - } - } - diff --git a/radeon-git-upstream-fixes.patch b/radeon-git-upstream-fixes.patch index 03250fc..3b1ada5 100644 --- a/radeon-git-upstream-fixes.patch +++ b/radeon-git-upstream-fixes.patch @@ -1,7 +1,384 @@ +commit ce4fa1cedec0cf56b9979dfaa12a8d3a7c643df4 +Author: Arkadiusz Miskiewicz +Date: Tue Dec 18 15:34:14 2007 -0500 + + RADEON: fix fd leak in lid detect code + +commit 20568f66f9a9a60a33bd9a69ccc14a891c656836 +Author: Arkadiusz Miskiewicz +Date: Tue Dec 18 15:32:10 2007 -0500 + + RADEON: more cleanups and warning fixes + +commit 1496194200adbcb044ec3977367a0908262e389c +Author: Arkadiusz Miskiewicz +Date: Tue Dec 18 15:29:53 2007 -0500 + + RADEON: driver cleanups, warning fixes + +commit 44d07c4ccce9acb5bd21a17acb082e91f7225764 +Author: Alex Deucher +Date: Mon Dec 17 18:56:12 2007 -0500 + + RADEON: typo from last commit + +commit 4da3782239921eb377216d4de4a9cc5bb55e0e8a +Author: Alex Deucher +Date: Mon Dec 17 18:51:31 2007 -0500 + + RADEON: add output enable masks + + add output enable masks for outputs that drive + more than one connector. Make sure we don't turn off + an output that's driving another connector. + +commit 5c5d2d19b2b032a06dd333b4ecc029aac342fb93 +Author: Alex Deucher +Date: Mon Dec 17 18:15:55 2007 -0500 + + RADEON: whitespace clean-ups + +commit 9f1d8220315c8894a17f2cc328025dc682b0c6e0 +Author: Alex Deucher +Date: Mon Dec 17 18:04:05 2007 -0500 + + RADEON: more PLL fixes + + - reduce the calculation accuracy + - certain LVDS panels seem to only like certain ref_divs + - add pll flags to handle special cases + - adjust the pll limits on legacy cards + +commit 4747c1f3cd4167b6a51d4864a297719ea48b9346 +Author: Alex Deucher +Date: Sun Dec 16 14:07:29 2007 -0500 + + RADEON: Make sure LVDS_EN bit is set when enabling LVDS + +commit b653e5a628bfa4dfb168e96f93f41eb910f409fb +Author: Michel Dänzer +Date: Sat Dec 15 00:50:10 2007 +0100 + + radeon: Default to 1x again with non-v3 AGP cards. + + Seems more reliable in general than what was set up by firmware - fingers + crossed... + +commit 6229825fa5d6715569098afbb21a40f7a2e7e6be +Author: Michel Dänzer +Date: Sat Dec 15 00:48:26 2007 +0100 + + radeon: Warning fixes. + + The lid detection code probably wouldn't work on other non-x86 platforms + though... + +commit 818ccf0fd4b5879171c5f20526d5a58638f8fde5 +Author: Fredrik Höglund +Date: Fri Dec 14 23:56:12 2007 +0100 + + RADEON: Fix the vertex coordinates for transformed pictures + + This partially fixes transformed pictures on R100/R200 based + cards. The texture still doesn't appear to be clamped correctly, + but since that doesn't matter for rotations at perpendicular + angles, I'm committing this now so randr rotation and reflection + will work properly. + +commit 3cfbcf4cafbdfdb33411d16e51fb1f77cd0f93dd +Author: Alex Deucher +Date: Fri Dec 14 17:11:00 2007 -0500 + + RADEON: Fix PLL set up on certain notebooks + + Some LVDS panels require specific PLL dividers as + specified in the bios tables. Make sure to use them + if the output is LVDS. + +commit a84d446fd301d456bcea8f7abdc52e5a30776412 +Author: Alex Deucher +Date: Fri Dec 14 02:17:14 2007 -0500 + + RADEON: select fb_div0 for LVDS on RV410 (x700) mobility + + Fixes bug 8038 + I wonder if desktop RV410 need a similar fix. + If your x700 laptop panel has problems after this let me know. + +commit 6ccf5b33d27218ae1c45ab93c122438ed536d8ba +Author: Alex Deucher +Date: Wed Dec 12 20:12:06 2007 -0500 + + RADEON: only enable vblanks if we want them + + should fix bug 13610 + +commit 1668f2056f56370f1b5681c13f1e14904e301216 +Author: Alex Deucher +Date: Wed Dec 12 19:39:08 2007 -0500 + + RADEON: use /proc/acpi to determine lid status + + Linux only + +commit 33a39947f7f79533cd90007a17d57b20126642c6 +Author: Alex Deucher +Date: Wed Dec 12 18:50:18 2007 -0500 + + RADEON: fix cursors when using rotation + + allocate separate cursor buffers for each crtc + +commit 9e5efdecd12092031a4aebce58747cb4a6f48f28 +Author: Arkadiusz Miskiewicz +Date: Tue Dec 11 23:53:03 2007 -0500 + + sparse fixes and cleanups from arekm + +commit f3d2ec3a5ae61215c792018320158750e7aa937c +Author: Alex Deucher +Date: Tue Dec 11 11:57:27 2007 -0500 + + RADEON: rewrite PLL computation + + Algorithm adapted from BeOS radeon driver with some tweaks by me. + Actually calulate and use the reference divider rather than using the bios default. + Also, always calculate the PLL, rather than falling back to bios dividers. + This should fix bugs 12913, 13590, 13533, possibly others. + +commit 9b125312ab6edc585e4f5931a6a6de81e13b6acc +Author: Alex Deucher +Date: Mon Dec 10 13:53:15 2007 -0500 + + RADEON: only update crtc values when RMX is active + +commit 3a161e1b5d80361e318ced8da5c19e797749d693 +Author: Alex Deucher +Date: Mon Dec 10 00:57:26 2007 -0500 + + RADEON: bios PLL cleanup + +commit 5896ca4097d439f59f90f397939132c061c3c364 +Author: LisaWu +Date: Fri Dec 7 09:45:05 2007 +0100 + + radeon: Use %u instead of %d for unsigned value. + +commit df44f8380268c27d3978c4e91d736f093322b8b8 +Author: Michel Dänzer +Date: Fri Dec 7 09:41:47 2007 +0100 + + radeon: Use gettimeofday instead of xf86getsecs. + +commit 64ab1cdf343a9a69e7e9e64f0bba77c54a94e9d0 +Author: James Cloos +Date: Thu Dec 6 15:51:12 2007 -0500 + + Add missing PHONY line for automatic ChangeLog generation + +commit 21ed435398e4a398dd8a0a5d7c1d4cc45e916332 +Author: Alex Deucher +Date: Tue Dec 4 17:08:58 2007 -0500 + + RADEON: add MacModel imac-g5-isight for iMac G5 iSight + + Thanks to Étienne Bersac for helping to figure this out. + +commit 54bfd522405d9fdfb69d3a59e111ac3d63483dbb +Author: Étienne Bersac +Date: Tue Dec 4 14:22:42 2007 -0500 + + RADEON: fix typo + +commit 5022d006cfc06ca0395981526b2c2c94c6878567 +Author: Michel Dänzer +Date: Sun Dec 2 17:27:33 2007 +0100 + + radeon: Further XVideo fixes. + + * Make sure pitch constraints are always met for DMA upload blits. + * RGB24 is not affected by endianness. + +commit 6ed55b70b23dfdc7b41103ea59c1df2bda5e41e6 +Author: Kusanagi Kouichi +Date: Sun Dec 2 17:18:46 2007 +0100 + + radeon: Fix crash with XVideo 24bit RGB images. + + See https://bugs.freedesktop.org/show_bug.cgi?id=13274 . + +commit a697b590899bb7704ec4d7ae9a9c3cbbfcaef382 +Author: Michel Dänzer +Date: Sun Dec 2 17:11:20 2007 +0100 + + Fix build against xserver master. + + (DE)ALLOCATE_LOCAL are gone. + +commit 00b4480aa2c5d7f751e34fc964f431b90b14c8d2 +Author: Alex Deucher +Date: Sat Dec 1 14:18:40 2007 -0500 + + RADEON: add options for force TV out as detected and to set TV standard + + Also fix a typo in internal tv-out parsing + +commit 0175b79987ef4d7b0ce8238c3bdde989e504516a +Author: Alex Deucher +Date: Fri Nov 30 15:37:42 2007 -0500 + + RADEON: rework MacModel option + + this brings in some previous research from Michel Dänzer, + Sjoerd Simons, and myself. Hopefully, the driver will pick + the correct MacModel in more cases. This also changes the + default connector table for desktop Macs to dual DVI rather + than DVI+VGA as that seems to be the case more often than not. + External TMDS chips are handled separately now as well. + Eventually we should add an option to allow the user to specify + what external TMDS chip they need, but we don't have enough info + yet, so we'll rely on OF to init the external chip in most cases + for now. + +commit 9840a0fd4fc8c980533fcd4a02c55cd0d5634b6d +Author: Alex Deucher +Date: Thu Nov 29 13:27:37 2007 -0500 + + RADEON: add MacModel "mini-internal" for minis with internal TMDS + + Some macs (minis and powerbooks) use internal tmds, others use external tmds + and not just for dual-link TMDS, it shows up with single-link as well. + Unforunately, there doesn't seem to be any good way to figure it out. + +commit 6f080d00e6f4f84d5e0d6b4eff302bf42c230e81 +Author: Arkadiusz Miskiewicz +Date: Mon Nov 26 12:43:30 2007 -0500 + + RADEON: fix backlight control on some laptops + + It seems the bios scratch regs are involved in backlight control + on some laptops. This patch fixes the problematic laptops and doesn't + seem to break the previous bios lid and output control fixes. + +commit dcf22aed87366f4625fb5042cb84fecccd9ceece +Author: Alex Deucher +Date: Mon Nov 26 11:10:03 2007 -0500 + + RADEON: only return status unknown for XPRESS chips + + this seems to cause more issues than it attempted to fix + so limit it to XPRESS chips for now. + +commit 206e280f02324641b4fe5a1986e26adf0e021fd4 +Author: Alex Deucher +Date: Mon Nov 26 09:39:27 2007 -0500 + + RADEON: fix typo in man page + +commit 197a62704742a4a19736c2637ac92d1dc5ab34ed +Author: Adam Jackson +Date: Thu Nov 22 20:26:23 2007 +1000 + + radeon: fix openoffice/render bug on r100 chips + +commit 64010fc4eae8359c01e430f64252931242c91435 +Author: Dave Airlie +Date: Thu Nov 22 20:25:31 2007 +1000 + + Revert "Disable RENDER acceleration by default on some RV200 chips." + + This reverts commit 145da701bf4fb9c0ad9f95620b20914ae0126852. + + pull in fix from ajax next commit + +commit 145da701bf4fb9c0ad9f95620b20914ae0126852 +Author: Stefan Dirsch +Date: Thu Nov 22 08:38:09 2007 +0100 + + Disable RENDER acceleration by default on some RV200 chips. + + Novell Bug #341699: Render acceleration is known to be broken + on at least "Radeon 7500 QW" and "Radeon Mobility M7 LW". + +commit e810c3ae9908cd57e95b1b091cded87cbfc12fdc +Author: Roland Scheidegger +Date: Thu Nov 22 02:37:55 2007 +0100 + + really do not set up surface regs for depth buf on r100-class igps (bug #13080) + + fix the if condition testing for these chips... + +commit c8872603454e6a4ffed9fc7d9adc2c364a429608 +Author: Dave Airlie +Date: Tue Nov 20 22:33:39 2007 +1000 + + radeon: restructure pci ids to avoid effort later + + This uses a single file with all the pciids and parameters for radeon + family and setup in it. I don't run the perl script at build time to avoid + a perl dependency on build but adding pci ids should be done via the csv file + with openoffice or gnumeric if possible. + +commit 49055d8aff91ff12186feaf5343c8fd2f96bcba0 +Author: Alex Deucher +Date: Thu Nov 15 22:56:09 2007 -0500 + + RADEON: set proper defaults for tv dac BGADJ/DACADJ + + we should get these values from the bios tables, but for now use + some reasonable defaults. This should fix the washed out color + problems on bugs 1082 and 12844. + +commit 821acf38b716ab87c3d07263d6e4a139fe54803f +Author: Alex Deucher +Date: Thu Nov 15 22:28:42 2007 -0500 + + RADEON: Make sure we set the MT properly for connected status unknown + +commit a94123f33ec6584fbdfc4b9ecd543d1357de8814 +Author: Alex Deucher +Date: Thu Nov 15 22:19:54 2007 -0500 + + Revert "Portability fix from netbsd" + + This reverts commit c9264aa53bf1470ad9104d1e7c4a8ce13c49c270. + This breaks damage support. See bug 13244 + +commit e9d721c31372db045550f9562534b28f16121bb9 +Author: Roland Scheidegger +Date: Tue Nov 13 23:42:42 2007 +0100 + + ignore sometime bogus agp_mode bit from chip (bug #13190) + + bit is wrong on at least X700 cards with rialto pcie-agp bridge chip, + should be safe to use just the bit from the bridge hopefully to make + agp setup work on these cards and not adversely affect others. +diff --git a/Makefile.am b/Makefile.am +index 2ae4852..ea2e4a3 100644 +--- a/Makefile.am ++++ b/Makefile.am +@@ -33,6 +33,8 @@ endif + EXTRA_DIST = README.ati README.r128 README.ati.sgml README.r128.sgml ChangeLog + CLEANFILES = ChangeLog + ++.PHONY: ChangeLog ++ + ChangeLog: + (GIT_DIR=$(top_srcdir)/.git git-log > .changelog.tmp && mv .changelog.tmp ChangeLog; rm -f .changelog.tmp) || (touch ChangeLog; echo 'git directory not found: installing possibly empty changelog.' >&2) + diff --git a/configure.ac b/configure.ac -index 450d951..b3d46a5 100644 +index 450d951..1570e54 100644 --- a/configure.ac +++ b/configure.ac +@@ -58,7 +58,7 @@ AC_ARG_ENABLE(dri, AC_HELP_STRING([--disable-dri], + + AC_ARG_ENABLE(exa, + AC_HELP_STRING([--disable-exa], +- [Disable EXA support [[default enabled]]]), ++ [Disable EXA support [[default=enabled]]]), + [EXA="$enableval"], + [EXA=yes]) + @@ -79,7 +79,7 @@ sdkdir=$(pkg-config --variable=sdkdir xorg-server) # Checks for header files. AC_HEADER_STDC @@ -659,6 +1036,67 @@ index 2aa8a3e..f24f8fb 100644 /* Misc */ #define PCI_CHIP_AMD761 0x700E +diff --git a/src/atividmem.c b/src/atividmem.c +index 8910c73..986ac0f 100644 +--- a/src/atividmem.c ++++ b/src/atividmem.c +@@ -103,14 +103,12 @@ ATIUnmapLinear + ATIPtr pATI + ) + { +- pciVideoPtr pVideo = pATI->PCIInfo; +- + if (pATI->pMemory) + { + #ifndef XSERVER_LIBPCIACCESS + xf86UnMapVidMem(iScreen, pATI->pMemory, pATI->LinearSize); + #else +- pci_device_unmap_range(pVideo, pATI->pMemory, pATI->LinearSize); ++ pci_device_unmap_range(pATI->PCIInfo, pATI->pMemory, pATI->LinearSize); + #endif + + #if X_BYTE_ORDER != X_LITTLE_ENDIAN +@@ -120,7 +118,7 @@ ATIUnmapLinear + #ifndef XSERVER_LIBPCIACCESS + xf86UnMapVidMem(iScreen, pATI->pMemoryLE, pATI->LinearSize); + #else +- pci_device_unmap_range(pVideo, pATI->pMemoryLE, pATI->LinearSize); ++ pci_device_unmap_range(pATI->PCIInfo, pATI->pMemoryLE, pATI->LinearSize); + #endif + } + +@@ -143,14 +141,12 @@ ATIUnmapMMIO + ATIPtr pATI + ) + { +- pciVideoPtr pVideo = pATI->PCIInfo; +- + if (pATI->pMMIO) + { + #ifndef XSERVER_LIBPCIACCESS + xf86UnMapVidMem(iScreen, pATI->pMMIO, getpagesize()); + #else +- pci_device_unmap_range(pVideo, pATI->pMMIO, getpagesize()); ++ pci_device_unmap_range(pATI->PCIInfo, pATI->pMMIO, getpagesize()); + #endif + } + +@@ -169,14 +165,12 @@ ATIUnmapCursor + ATIPtr pATI + ) + { +- pciVideoPtr pVideo = pATI->PCIInfo; +- + if (pATI->pCursorPage) + { + #ifndef XSERVER_LIBPCIACCESS + xf86UnMapVidMem(iScreen, pATI->pCursorPage, getpagesize()); + #else +- pci_device_unmap_range(pVideo, pATI->pCursorPage, getpagesize()); ++ pci_device_unmap_range(pATI->PCIInfo, pATI->pCursorPage, getpagesize()); + #endif + } + diff --git a/src/pcidb/ati_pciids.csv b/src/pcidb/ati_pciids.csv new file mode 100644 index 0000000..f201cc4 @@ -985,8 +1423,38 @@ index 0000000..e6eac76 +close PCICHIPSET; +close RADEONCHIPSET; +close RADEONCHIPINFO; +diff --git a/src/r128_dri.c b/src/r128_dri.c +index fc91421..edb77ba 100644 +--- a/src/r128_dri.c ++++ b/src/r128_dri.c +@@ -80,9 +80,9 @@ static Bool R128InitVisualConfigs(ScreenPtr pScreen) + ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; + R128InfoPtr info = R128PTR(pScrn); + int numConfigs = 0; +- __GLXvisualConfig *pConfigs = 0; +- R128ConfigPrivPtr pR128Configs = 0; +- R128ConfigPrivPtr *pR128ConfigPtrs = 0; ++ __GLXvisualConfig *pConfigs = NULL; ++ R128ConfigPrivPtr pR128Configs = NULL; ++ R128ConfigPrivPtr *pR128ConfigPtrs = NULL; + int i, accum, stencil, db; + + switch (info->CurrentLayout.pixel_code) { +diff --git a/src/r128_probe.c b/src/r128_probe.c +index b2298df..0be21e8 100644 +--- a/src/r128_probe.c ++++ b/src/r128_probe.c +@@ -193,7 +193,7 @@ R128Probe(DriverPtr drv, int flags) + + pScrn = NULL; + if((pScrn = xf86ConfigPciEntity(pScrn, 0, usedChips[i], +- R128PciChipsets, 0, 0, 0, 0, 0))) ++ R128PciChipsets, NULL, NULL, NULL, NULL, NULL))) + { + pScrn->driverVersion = R128_VERSION_CURRENT; + pScrn->driverName = R128_DRIVER_NAME; diff --git a/src/radeon.h b/src/radeon.h -index 532f04c..fe491e8 100644 +index 532f04c..03db360 100644 --- a/src/radeon.h +++ b/src/radeon.h @@ -158,7 +158,9 @@ typedef enum { @@ -1000,7 +1468,48 @@ index 532f04c..fe491e8 100644 } RADEONOpts; -@@ -428,12 +430,22 @@ typedef enum { +@@ -286,6 +288,7 @@ typedef struct { + CARD32 dot_clock_freq; + CARD32 pll_output_freq; + int feedback_div; ++ int reference_div; + int post_div; + + /* PLL registers */ +@@ -298,6 +301,7 @@ typedef struct { + CARD32 dot_clock_freq_2; + CARD32 pll_output_freq_2; + int feedback_div_2; ++ int reference_div_2; + int post_div_2; + + /* PLL2 registers */ +@@ -362,12 +366,24 @@ typedef struct { + + } RADEONSaveRec, *RADEONSavePtr; + ++#define RADEON_PLL_USE_BIOS_DIVS (1 << 0) ++#define RADEON_PLL_NO_ODD_POST_DIV (1 << 1) ++#define RADEON_PLL_USE_REF_DIV (1 << 2) ++ + typedef struct { + CARD16 reference_freq; + CARD16 reference_div; + CARD32 min_pll_freq; + CARD32 max_pll_freq; + CARD16 xclk; ++ ++ CARD32 min_ref_div; ++ CARD32 max_ref_div; ++ CARD32 min_feedback_div; ++ CARD32 max_feedback_div; ++ CARD32 pll_in_min; ++ CARD32 pll_in_max; ++ CARD32 best_vco; + } RADEONPLLRec, *RADEONPLLPtr; + + typedef struct { +@@ -428,12 +444,22 @@ typedef enum { CHIP_ERRATA_PLL_DELAY = 0x00000004 } RADEONErrata; @@ -1027,7 +1536,7 @@ index 532f04c..fe491e8 100644 } RADEONMacModel; #endif -@@ -444,6 +456,16 @@ typedef enum { +@@ -444,6 +470,16 @@ typedef enum { } RADEONCardType; typedef struct { @@ -1044,14 +1553,112 @@ index 532f04c..fe491e8 100644 EntityInfoPtr pEnt; pciVideoPtr PciInfo; PCITAG PciTag; -@@ -816,6 +838,7 @@ typedef struct { +@@ -525,10 +561,6 @@ typedef struct { + #endif + Bool accelOn; + xf86CursorInfoPtr cursor; +- CARD32 cursor_offset; +-#ifdef USE_XAA +- unsigned long cursor_end; +-#endif + Bool allowColorTiling; + Bool tilingEnabled; /* mirror of sarea->tiling_enabled */ + #ifdef ARGB_CURSOR +@@ -816,6 +848,15 @@ typedef struct { #if defined(__powerpc__) RADEONMacModel MacModel; #endif + RADEONExtTMDSChip ext_tmds_chip; ++ ++ /* output enable masks for outputs shared across connectors */ ++ int output_crt1; ++ int output_crt2; ++ int output_dfp1; ++ int output_dfp2; ++ int output_lcd1; ++ int output_tv1; Rotation rotation; void (*PointerMoved)(int, int, int); +diff --git a/src/radeon_accel.c b/src/radeon_accel.c +index 6028aff..ed7d1e9 100644 +--- a/src/radeon_accel.c ++++ b/src/radeon_accel.c +@@ -136,8 +136,8 @@ void RADEONWaitForFifoFunction(ScrnInfoPtr pScrn, int entries) + } + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "FIFO timed out: %u entries, stat=0x%08x\n", +- INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK, +- INREG(RADEON_RBBM_STATUS)); ++ (unsigned int)INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK, ++ (unsigned int)INREG(RADEON_RBBM_STATUS)); + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, + "FIFO timed out, resetting engine...\n"); + RADEONEngineReset(pScrn); +@@ -168,7 +168,7 @@ void RADEONEngineFlush(ScrnInfoPtr pScrn) + if (i == RADEON_TIMEOUT) { + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "DC flush timeout: %x\n", +- INREG(RADEON_RB3D_DSTCACHE_CTLSTAT)); ++ (unsigned int)INREG(RADEON_RB3D_DSTCACHE_CTLSTAT)); + } + } + +diff --git a/src/radeon_bios.c b/src/radeon_bios.c +index 1b46746..d150c4b 100644 +--- a/src/radeon_bios.c ++++ b/src/radeon_bios.c +@@ -48,13 +48,12 @@ Bool RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10) + int tmp; + unsigned short dptr; + +- if (!(info->VBIOS = xalloc( + #ifdef XSERVER_LIBPCIACCESS +- info->PciInfo->rom_size ++ info->VBIOS = xalloc(info->PciInfo->rom_size); + #else +- RADEON_VBIOS_SIZE ++ info->VBIOS = xalloc(RADEON_VBIOS_SIZE); + #endif +- ))) { ++ if (!info->VBIOS) { + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, + "Cannot allocate space for hold Video BIOS!\n"); + return FALSE; +@@ -469,15 +468,6 @@ Bool RADEONGetClockInfoFromBIOS (ScrnInfoPtr pScrn) + + info->sclk = RADEON_BIOS32(pll_info_block + 8) / 100.0; + info->mclk = RADEON_BIOS32(pll_info_block + 12) / 100.0; +- if (info->sclk == 0) info->sclk = 200; +- if (info->mclk == 0) info->mclk = 200; +- +- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "ref_freq: %d, min_pll: %u, " +- "max_pll: %u, xclk: %d, sclk: %f, mclk: %f\n", +- pll->reference_freq, (unsigned)pll->min_pll_freq, +- (unsigned)pll->max_pll_freq, pll->xclk, info->sclk, +- info->mclk); +- + } else { + pll_info_block = RADEON_BIOS16 (info->ROMHeaderStart + 0x30); + +@@ -490,8 +480,17 @@ Bool RADEONGetClockInfoFromBIOS (ScrnInfoPtr pScrn) + info->sclk = RADEON_BIOS16(pll_info_block + 8) / 100.0; + info->mclk = RADEON_BIOS16(pll_info_block + 10) / 100.0; + } ++ ++ if (info->sclk == 0) info->sclk = 200; ++ if (info->mclk == 0) info->mclk = 200; + } + ++ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "ref_freq: %d, min_pll: %u, " ++ "max_pll: %u, xclk: %d, sclk: %f, mclk: %f\n", ++ pll->reference_freq, (unsigned)pll->min_pll_freq, ++ (unsigned)pll->max_pll_freq, pll->xclk, info->sclk, ++ info->mclk); ++ + return TRUE; + } + diff --git a/src/radeon_chipinfo_gen.h b/src/radeon_chipinfo_gen.h new file mode 100644 index 0000000..a12b225 @@ -1493,11 +2100,310 @@ index 0000000..0a7a9c1 + { PCI_CHIP_RS350_7835, "ATI Radeon Mobility 9200 IGP 7835" }, + { -1, NULL } +}; +diff --git a/src/radeon_commonfuncs.c b/src/radeon_commonfuncs.c +index 6a999af..a1802f8 100644 +--- a/src/radeon_commonfuncs.c ++++ b/src/radeon_commonfuncs.c +@@ -174,8 +174,8 @@ void FUNC_NAME(RADEONWaitForIdle)(ScrnInfoPtr pScrn) + } + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "Idle timed out: %u entries, stat=0x%08x\n", +- INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK, +- INREG(RADEON_RBBM_STATUS)); ++ (unsigned int)INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK, ++ (unsigned int)INREG(RADEON_RBBM_STATUS)); + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, + "Idle timed out, resetting engine...\n"); + RADEONEngineReset(pScrn); diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c -index de24273..b1d216d 100644 +index de24273..07857dd 100644 --- a/src/radeon_crtc.c +++ b/src/radeon_crtc.c -@@ -769,8 +769,8 @@ RADEONInitBIOSRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save) +@@ -145,15 +145,13 @@ RADEONInitCommonRegisters(RADEONSavePtr save, RADEONInfoPtr info) + static void + RADEONInitSurfaceCntl(xf86CrtcPtr crtc, RADEONSavePtr save) + { +- ScrnInfoPtr pScrn = crtc->scrn; +- + save->surface_cntl = 0; + + #if X_BYTE_ORDER == X_BIG_ENDIAN + /* We must set both apertures as they can be both used to map the entire + * video memory. -BenH. + */ +- switch (pScrn->bitsPerPixel) { ++ switch (crtc->scrn->bitsPerPixel) { + case 16: + save->surface_cntl |= RADEON_NONSURF_AP0_SWP_16BPP; + save->surface_cntl |= RADEON_NONSURF_AP1_SWP_16BPP; +@@ -606,19 +604,108 @@ RADEONInitCrtc2Registers(xf86CrtcPtr crtc, RADEONSavePtr save, + } + + +-/* Compute n/d with rounding */ + static int RADEONDiv(int n, int d) + { + return (n + (d / 2)) / d; + } + ++static void ++RADEONComputePLL(RADEONPLLPtr pll, ++ unsigned long freq, ++ CARD32 *chosen_dot_clock_freq, ++ CARD32 *chosen_feedback_div, ++ CARD32 *chosen_reference_div, ++ CARD32 *chosen_post_div, ++ int flags) ++{ ++ int post_divs[] = {1, 2, 4, 8, 3, 6, 12, 0}; ++ ++ int i; ++ ++ CARD32 min_ref_div = pll->min_ref_div; ++ CARD32 max_ref_div = pll->max_ref_div; ++ CARD32 best_vco = pll->best_vco; ++ CARD32 best_post_div = 1; ++ CARD32 best_ref_div = 1; ++ CARD32 best_feedback_div = 1; ++ CARD32 best_freq = 1; ++ CARD32 best_error = 0xffffffff; ++ CARD32 best_vco_diff = 1; ++ ++ freq = freq / 10; ++ ++ ErrorF("freq: %lu\n", freq); ++ ++ if (flags & RADEON_PLL_USE_REF_DIV) ++ min_ref_div = max_ref_div = pll->reference_div; ++ ++ for (i = 0; post_divs[i]; i++) { ++ int post_div = post_divs[i]; ++ CARD32 ref_div; ++ CARD32 vco = freq * post_div; ++ ++ if ((flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1)) ++ continue; ++ ++ if (vco < pll->min_pll_freq || vco > pll->max_pll_freq) ++ continue; ++ ++ for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) { ++ CARD32 feedback_div, current_freq, error, vco_diff; ++ CARD32 pll_in = pll->reference_freq / ref_div; ++ ++ if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max) ++ continue; ++ ++ feedback_div = RADEONDiv(freq * ref_div * post_div, ++ pll->reference_freq); ++ ++ if (feedback_div < pll->min_feedback_div || feedback_div > pll->max_feedback_div) ++ continue; ++ ++ current_freq = RADEONDiv(pll->reference_freq * feedback_div, ++ ref_div * post_div); ++ ++ error = abs(current_freq - freq); ++ vco_diff = abs(vco - best_vco); ++ ++ if ((best_vco == 0 && error < best_error) || ++ (best_vco != 0 && ++ (error < best_error - 1000 || ++ (abs(error - best_error) < 100 && vco_diff < best_vco_diff )))) { ++ best_post_div = post_div; ++ best_ref_div = ref_div; ++ best_feedback_div = feedback_div; ++ best_freq = current_freq; ++ best_error = error; ++ best_vco_diff = vco_diff; ++ } ++ } ++ } ++ ++ ErrorF("best_freq: %u\n", (unsigned)best_freq); ++ ErrorF("best_feedback_div: %u\n", (unsigned)best_feedback_div); ++ ErrorF("best_ref_div: %u\n", (unsigned)best_ref_div); ++ ErrorF("best_post_div: %u\n", (unsigned)best_post_div); ++ ++ *chosen_dot_clock_freq = best_freq; ++ *chosen_feedback_div = best_feedback_div; ++ *chosen_reference_div = best_ref_div; ++ *chosen_post_div = best_post_div; ++ ++} ++ + /* Define PLL registers for requested video mode */ + static void +-RADEONInitPLLRegisters(ScrnInfoPtr pScrn, RADEONInfoPtr info, +- RADEONSavePtr save, RADEONPLLPtr pll, +- double dot_clock) ++RADEONInitPLLRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save, ++ RADEONPLLPtr pll, DisplayModePtr mode, ++ int flags) + { +- unsigned long freq = dot_clock * 100; ++ RADEONInfoPtr info = RADEONPTR(pScrn); ++ CARD32 feedback_div = 0; ++ CARD32 reference_div = 0; ++ CARD32 post_divider = 0; ++ CARD32 freq = 0; + + struct { + int divider; +@@ -640,21 +727,19 @@ RADEONInitPLLRegisters(ScrnInfoPtr pScrn, RADEONInfoPtr info, + { 0, 0 } + }; + +- if (info->UseBiosDividers) { ++ ++ if ((flags & RADEON_PLL_USE_BIOS_DIVS) && info->UseBiosDividers) { + save->ppll_ref_div = info->RefDivider; + save->ppll_div_3 = info->FeedbackDivider | (info->PostDivider << 16); + save->htotal_cntl = 0; + return; + } + +- if (freq > pll->max_pll_freq) freq = pll->max_pll_freq; +- if (freq * 12 < pll->min_pll_freq) freq = pll->min_pll_freq / 12; ++ RADEONComputePLL(pll, mode->Clock, &freq, &feedback_div, &reference_div, &post_divider, flags); + + for (post_div = &post_divs[0]; post_div->divider; ++post_div) { +- save->pll_output_freq = post_div->divider * freq; +- +- if (save->pll_output_freq >= pll->min_pll_freq +- && save->pll_output_freq <= pll->max_pll_freq) break; ++ if (post_div->divider == post_divider) ++ break; + } + + if (!post_div->divider) { +@@ -663,19 +748,19 @@ RADEONInitPLLRegisters(ScrnInfoPtr pScrn, RADEONInfoPtr info, + } + + save->dot_clock_freq = freq; +- save->feedback_div = RADEONDiv(pll->reference_div +- * save->pll_output_freq, +- pll->reference_freq); +- save->post_div = post_div->divider; ++ save->feedback_div = feedback_div; ++ save->reference_div = reference_div; ++ save->post_div = post_divider; + + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, +- "dc=%u, of=%u, fd=%d, pd=%d\n", ++ "dc=%u, of=%u, fd=%d, rd=%d, pd=%d\n", + (unsigned)save->dot_clock_freq, + (unsigned)save->pll_output_freq, + save->feedback_div, ++ save->reference_div, + save->post_div); + +- save->ppll_ref_div = pll->reference_div; ++ save->ppll_ref_div = save->reference_div; + + #if defined(__powerpc__) + /* apparently programming this otherwise causes a hang??? */ +@@ -685,21 +770,24 @@ RADEONInitPLLRegisters(ScrnInfoPtr pScrn, RADEONInfoPtr info, + #endif + save->ppll_div_3 = (save->feedback_div | (post_div->bitvalue << 16)); + +- save->htotal_cntl = 0; ++ save->htotal_cntl = mode->HTotal & 0x7; + +- save->vclk_ecp_cntl = (info->SavedReg.vclk_ecp_cntl & +- ~RADEON_VCLK_SRC_SEL_MASK) | RADEON_VCLK_SRC_SEL_PPLLCLK; ++ save->vclk_ecp_cntl = (info->SavedReg.vclk_ecp_cntl & ++ ~RADEON_VCLK_SRC_SEL_MASK) | RADEON_VCLK_SRC_SEL_PPLLCLK; + + } + + /* Define PLL2 registers for requested video mode */ + static void + RADEONInitPLL2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save, +- RADEONPLLPtr pll, double dot_clock, +- int no_odd_postdiv) ++ RADEONPLLPtr pll, DisplayModePtr mode, ++ int flags) + { +- RADEONInfoPtr info = RADEONPTR(pScrn); +- unsigned long freq = dot_clock * 100; ++ RADEONInfoPtr info = RADEONPTR(pScrn); ++ CARD32 feedback_div = 0; ++ CARD32 reference_div = 0; ++ CARD32 post_divider = 0; ++ CARD32 freq = 0; + + struct { + int divider; +@@ -720,18 +808,18 @@ RADEONInitPLL2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save, + { 0, 0 } + }; + +- if (freq > pll->max_pll_freq) freq = pll->max_pll_freq; +- if (freq * 12 < pll->min_pll_freq) freq = pll->min_pll_freq / 12; ++ if ((flags & RADEON_PLL_USE_BIOS_DIVS) && info->UseBiosDividers) { ++ save->p2pll_ref_div = info->RefDivider; ++ save->p2pll_div_0 = info->FeedbackDivider | (info->PostDivider << 16); ++ save->htotal_cntl2 = 0; ++ return; ++ } ++ ++ RADEONComputePLL(pll, mode->Clock, &freq, &feedback_div, &reference_div, &post_divider, flags); + + for (post_div = &post_divs[0]; post_div->divider; ++post_div) { +- /* Odd post divider value don't work properly on the second digital +- * output +- */ +- if (no_odd_postdiv && (post_div->divider & 1)) +- continue; +- save->pll_output_freq_2 = post_div->divider * freq; +- if (save->pll_output_freq_2 >= pll->min_pll_freq +- && save->pll_output_freq_2 <= pll->max_pll_freq) break; ++ if (post_div->divider == post_divider) ++ break; + } + + if (!post_div->divider) { +@@ -740,26 +828,28 @@ RADEONInitPLL2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save, + } + + save->dot_clock_freq_2 = freq; +- save->feedback_div_2 = RADEONDiv(pll->reference_div +- * save->pll_output_freq_2, +- pll->reference_freq); +- save->post_div_2 = post_div->divider; ++ save->feedback_div_2 = feedback_div; ++ save->reference_div_2 = reference_div; ++ save->post_div_2 = post_divider; + + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, +- "dc=%u, of=%u, fd=%d, pd=%d\n", ++ "dc=%u, of=%u, fd=%d, rd=%d, pd=%d\n", + (unsigned)save->dot_clock_freq_2, + (unsigned)save->pll_output_freq_2, + save->feedback_div_2, ++ save->reference_div_2, + save->post_div_2); + +- save->p2pll_ref_div = pll->reference_div; ++ save->p2pll_ref_div = save->reference_div_2; ++ + save->p2pll_div_0 = (save->feedback_div_2 | + (post_div->bitvalue << 16)); +- save->htotal_cntl2 = 0; + +- save->pixclks_cntl = ((info->SavedReg.pixclks_cntl & +- ~(RADEON_PIX2CLK_SRC_SEL_MASK)) | +- RADEON_PIX2CLK_SRC_SEL_P2PLLCLK); ++ save->htotal_cntl2 = mode->HTotal & 0x7; ++ ++ save->pixclks_cntl = ((info->SavedReg.pixclks_cntl & ++ ~(RADEON_PIX2CLK_SRC_SEL_MASK)) | ++ RADEON_PIX2CLK_SRC_SEL_P2PLLCLK); + + } + +@@ -769,8 +859,8 @@ RADEONInitBIOSRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save) RADEONInfoPtr info = RADEONPTR(pScrn); /* tell the bios not to muck with the hardware on events */ @@ -1508,8 +2414,630 @@ index de24273..b1d216d 100644 save->bios_6_scratch = info->SavedReg.bios_6_scratch | 0x40000000; } +@@ -792,8 +882,8 @@ radeon_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode, + RADEONInfoPtr info = RADEONPTR(pScrn); + Bool tilingOld = info->tilingEnabled; + int i = 0; +- double dot_clock = 0; +- Bool no_odd_post_div = FALSE; ++ double dot_clock = 0; ++ int pll_flags = 0; + Bool update_tv_routing = FALSE; + + +@@ -818,7 +908,9 @@ radeon_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode, + + if (output->crtc == crtc) { + if (radeon_output->MonType != MT_CRT) +- no_odd_post_div = TRUE; ++ pll_flags |= RADEON_PLL_NO_ODD_POST_DIV; ++ if (radeon_output->MonType == MT_LCD) ++ pll_flags |= (RADEON_PLL_USE_BIOS_DIVS | RADEON_PLL_USE_REF_DIV); + } + } + +@@ -837,25 +929,25 @@ radeon_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode, + ErrorF("init crtc1\n"); + RADEONInitCrtcRegisters(crtc, &info->ModeReg, adjusted_mode); + RADEONInitCrtcBase(crtc, &info->ModeReg, x, y); +- dot_clock = adjusted_mode->Clock / 1000.0; +- if (dot_clock) { ++ dot_clock = adjusted_mode->Clock / 1000.0; ++ if (dot_clock) { + ErrorF("init pll1\n"); +- RADEONInitPLLRegisters(pScrn, info, &info->ModeReg, &info->pll, dot_clock); +- } else { +- info->ModeReg.ppll_ref_div = info->SavedReg.ppll_ref_div; +- info->ModeReg.ppll_div_3 = info->SavedReg.ppll_div_3; +- info->ModeReg.htotal_cntl = info->SavedReg.htotal_cntl; +- } ++ RADEONInitPLLRegisters(pScrn, &info->ModeReg, &info->pll, adjusted_mode, pll_flags); ++ } else { ++ info->ModeReg.ppll_ref_div = info->SavedReg.ppll_ref_div; ++ info->ModeReg.ppll_div_3 = info->SavedReg.ppll_div_3; ++ info->ModeReg.htotal_cntl = info->SavedReg.htotal_cntl; ++ } + break; + case 1: + ErrorF("init crtc2\n"); +- RADEONInitCrtc2Registers(crtc, &info->ModeReg, adjusted_mode); ++ RADEONInitCrtc2Registers(crtc, &info->ModeReg, adjusted_mode); + RADEONInitCrtc2Base(crtc, &info->ModeReg, x, y); +- dot_clock = adjusted_mode->Clock / 1000.0; +- if (dot_clock) { ++ dot_clock = adjusted_mode->Clock / 1000.0; ++ if (dot_clock) { + ErrorF("init pll2\n"); +- RADEONInitPLL2Registers(pScrn, &info->ModeReg, &info->pll, dot_clock, no_odd_post_div); +- } ++ RADEONInitPLL2Registers(pScrn, &info->ModeReg, &info->pll, adjusted_mode, pll_flags); ++ } + break; + } + +diff --git a/src/radeon_cursor.c b/src/radeon_cursor.c +index b8cfffd..ba1159c 100644 +--- a/src/radeon_cursor.c ++++ b/src/radeon_cursor.c +@@ -166,9 +166,9 @@ radeon_crtc_set_cursor_position (xf86CrtcPtr crtc, int x, int y) + | ((xorigin ? 0 : x) << 16) + | (yorigin ? 0 : y))); + RADEONCTRACE(("cursor_offset: 0x%x, yorigin: %d, stride: %d, temp %08X\n", +- info->cursor_offset + pScrn->fbOffset, yorigin, stride, temp)); ++ radeon_crtc->cursor_offset + pScrn->fbOffset, yorigin, stride, temp)); + OUTREG(RADEON_CUR_OFFSET, +- info->cursor_offset + pScrn->fbOffset + yorigin * stride); ++ radeon_crtc->cursor_offset + pScrn->fbOffset + yorigin * stride); + } else if (crtc_id == 1) { + OUTREG(RADEON_CUR2_HORZ_VERT_OFF, (RADEON_CUR2_LOCK + | (xorigin << 16) +@@ -177,9 +177,9 @@ radeon_crtc_set_cursor_position (xf86CrtcPtr crtc, int x, int y) + | ((xorigin ? 0 : x) << 16) + | (yorigin ? 0 : y))); + RADEONCTRACE(("cursor_offset2: 0x%x, yorigin: %d, stride: %d, temp %08X\n", +- info->cursor_offset + pScrn->fbOffset, yorigin, stride, temp)); ++ radeon_crtc->cursor_offset + pScrn->fbOffset, yorigin, stride, temp)); + OUTREG(RADEON_CUR2_OFFSET, +- info->cursor_offset + pScrn->fbOffset + yorigin * stride); ++ radeon_crtc->cursor_offset + pScrn->fbOffset + yorigin * stride); + } + + } +@@ -188,8 +188,9 @@ void + radeon_crtc_set_cursor_colors (xf86CrtcPtr crtc, int bg, int fg) + { + ScrnInfoPtr pScrn = crtc->scrn; ++ RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; + RADEONInfoPtr info = RADEONPTR(pScrn); +- CARD32 *pixels = (CARD32 *)(pointer)(info->FB + info->cursor_offset + pScrn->fbOffset); ++ CARD32 *pixels = (CARD32 *)(pointer)(info->FB + radeon_crtc->cursor_offset + pScrn->fbOffset); + int pixel, i; + CURSOR_SWAPPING_DECL_MMIO + +@@ -229,9 +230,10 @@ void + radeon_crtc_load_cursor_argb (xf86CrtcPtr crtc, CARD32 *image) + { + ScrnInfoPtr pScrn = crtc->scrn; ++ RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; + RADEONInfoPtr info = RADEONPTR(pScrn); +- unsigned char *RADEONMMIO = info->MMIO; +- CARD32 *d = (CARD32 *)(pointer)(info->FB + info->cursor_offset + pScrn->fbOffset); ++ CURSOR_SWAPPING_DECL_MMIO ++ CARD32 *d = (CARD32 *)(pointer)(info->FB + radeon_crtc->cursor_offset + pScrn->fbOffset); + + RADEONCTRACE(("RADEONLoadCursorARGB\n")); + +@@ -252,16 +254,18 @@ Bool RADEONCursorInit(ScreenPtr pScreen) + { + ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; + RADEONInfoPtr info = RADEONPTR(pScrn); ++ xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); + int width; + int width_bytes; + int height; + int size_bytes; +- ++ CARD32 cursor_offset = 0; ++ int c; + + size_bytes = CURSOR_WIDTH * 4 * CURSOR_HEIGHT; + width = pScrn->displayWidth; + width_bytes = width * (pScrn->bitsPerPixel / 8); +- height = (size_bytes + width_bytes - 1) / width_bytes; ++ height = ((size_bytes * xf86_config->num_crtc) + width_bytes - 1) / width_bytes; + + #ifdef USE_XAA + if (!info->useEXA) { +@@ -271,19 +275,30 @@ Bool RADEONCursorInit(ScreenPtr pScreen) + 256, NULL, NULL, NULL); + + if (!fbarea) { +- info->cursor_offset = 0; ++ cursor_offset = 0; + xf86DrvMsg(pScrn->scrnIndex, X_WARNING, + "Hardware cursor disabled" + " due to insufficient offscreen memory\n"); ++ return FALSE; + } else { +- info->cursor_offset = RADEON_ALIGN((fbarea->box.x1 + +- fbarea->box.y1 * width) * +- info->CurrentLayout.pixel_bytes, +- 256); +- info->cursor_end = info->cursor_offset + size_bytes; ++ cursor_offset = RADEON_ALIGN((fbarea->box.x1 + ++ fbarea->box.y1 * width) * ++ info->CurrentLayout.pixel_bytes, ++ 256); ++ ++ for (c = 0; c < xf86_config->num_crtc; c++) { ++ xf86CrtcPtr crtc = xf86_config->crtc[c]; ++ RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; ++ ++ radeon_crtc->cursor_offset = cursor_offset + (c * size_bytes); ++ ++ xf86DrvMsg(pScrn->scrnIndex, X_INFO, ++ "Using hardware cursor %d (scanline %u)\n", c, ++ (unsigned)(radeon_crtc->cursor_offset / pScrn->displayWidth ++ / info->CurrentLayout.pixel_bytes)); ++ } ++ + } +- RADEONCTRACE(("RADEONCursorInit (0x%08x-0x%08x)\n", +- info->cursor_offset, info->cursor_end)); + } + #endif + +diff --git a/src/radeon_display.c b/src/radeon_display.c +index 5c4fbfa..ea31a82 100644 +--- a/src/radeon_display.c ++++ b/src/radeon_display.c +@@ -163,7 +163,7 @@ void RADEONGetTVDacAdjInfo(xf86OutputPtr output) + ScrnInfoPtr pScrn = output->scrn; + RADEONInfoPtr info = RADEONPTR(pScrn); + RADEONOutputPrivatePtr radeon_output = output->driver_private; +- ++ + /* Todo: get this setting from BIOS */ + radeon_output->tv_dac_adj = default_tvdac_adj[info->ChipFamily]; + if (info->IsMobility) { /* some mobility chips may different */ +@@ -202,7 +202,7 @@ static void RADEONDacPowerSet(ScrnInfoPtr pScrn, Bool IsOn, Bool IsPrimaryDAC) + } else { + CARD32 tv_dac_cntl; + CARD32 fp2_gen_cntl; +- ++ + switch(info->ChipFamily) + { + case CHIP_FAMILY_R420: +@@ -259,19 +259,19 @@ void RADEONDisableDisplays(ScrnInfoPtr pScrn) { + + /* primary DAC */ + tmp = INREG(RADEON_CRTC_EXT_CNTL); +- tmp &= ~RADEON_CRTC_CRT_ON; ++ tmp &= ~RADEON_CRTC_CRT_ON; + OUTREG(RADEON_CRTC_EXT_CNTL, tmp); + RADEONDacPowerSet(pScrn, FALSE, TRUE); + + /* Secondary DAC */ + if (info->ChipFamily == CHIP_FAMILY_R200) { +- tmp = INREG(RADEON_FP2_GEN_CNTL); +- tmp &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN); +- OUTREG(RADEON_FP2_GEN_CNTL, tmp); ++ tmp = INREG(RADEON_FP2_GEN_CNTL); ++ tmp &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN); ++ OUTREG(RADEON_FP2_GEN_CNTL, tmp); + } else { +- tmp = INREG(RADEON_CRTC2_GEN_CNTL); +- tmp &= ~RADEON_CRTC2_CRT2_ON; +- OUTREG(RADEON_CRTC2_GEN_CNTL, tmp); ++ tmp = INREG(RADEON_CRTC2_GEN_CNTL); ++ tmp &= ~RADEON_CRTC2_CRT2_ON; ++ OUTREG(RADEON_CRTC2_GEN_CNTL, tmp); + } + RADEONDacPowerSet(pScrn, FALSE, FALSE); + +@@ -304,7 +304,7 @@ void RADEONDisableDisplays(ScrnInfoPtr pScrn) { + } + tmp = INREG(RADEON_LVDS_GEN_CNTL); + tmp |= RADEON_LVDS_DISPLAY_DIS; +- tmp &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON); ++ tmp &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN); + OUTREG(RADEON_LVDS_GEN_CNTL, tmp); + if (info->IsMobility || info->IsIGP) { + OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, tmpPixclksCntl); +@@ -322,130 +322,161 @@ void RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable) + unsigned char * RADEONMMIO = info->MMIO; + unsigned long tmp; + RADEONOutputPrivatePtr radeon_output; +- int tv_dac_change = 0; ++ int tv_dac_change = 0, o; + radeon_output = output->driver_private; ++ xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); ++ ++ for (o = 0; o < xf86_config->num_output; o++) { ++ if (output == xf86_config->output[o]) { ++ break; ++ } ++ } + + if (bEnable) { + ErrorF("enable montype: %d\n", radeon_output->MonType); +- if (radeon_output->MonType == MT_CRT) { +- if (radeon_output->DACType == DAC_PRIMARY) { +- tmp = INREG(RADEON_CRTC_EXT_CNTL); +- tmp |= RADEON_CRTC_CRT_ON; +- OUTREG(RADEON_CRTC_EXT_CNTL, tmp); +- save->crtc_ext_cntl |= RADEON_CRTC_CRT_ON; +- RADEONDacPowerSet(pScrn, bEnable, (radeon_output->DACType == DAC_PRIMARY)); +- } else if (radeon_output->DACType == DAC_TVDAC) { +- if (info->ChipFamily == CHIP_FAMILY_R200) { +- tmp = INREG(RADEON_FP2_GEN_CNTL); +- tmp |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN); +- OUTREG(RADEON_FP2_GEN_CNTL, tmp); +- save->fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN); +- } else { +- tmp = INREG(RADEON_CRTC2_GEN_CNTL); +- tmp |= RADEON_CRTC2_CRT2_ON; +- OUTREG(RADEON_CRTC2_GEN_CNTL, tmp); +- save->crtc2_gen_cntl |= RADEON_CRTC2_CRT2_ON; +- } +- tv_dac_change = 1; +- } +- } else if (radeon_output->MonType == MT_DFP) { +- if (radeon_output->TMDSType == TMDS_INT) { +- tmp = INREG(RADEON_FP_GEN_CNTL); +- tmp |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN); +- OUTREG(RADEON_FP_GEN_CNTL, tmp); +- save->fp_gen_cntl |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN); +- } else if (radeon_output->TMDSType == TMDS_EXT) { +- tmp = INREG(RADEON_FP2_GEN_CNTL); ++ if (radeon_output->MonType == MT_CRT) { ++ if (radeon_output->DACType == DAC_PRIMARY) { ++ info->output_crt1 |= (1 << o); ++ tmp = INREG(RADEON_CRTC_EXT_CNTL); ++ tmp |= RADEON_CRTC_CRT_ON; ++ OUTREG(RADEON_CRTC_EXT_CNTL, tmp); ++ save->crtc_ext_cntl |= RADEON_CRTC_CRT_ON; ++ RADEONDacPowerSet(pScrn, bEnable, (radeon_output->DACType == DAC_PRIMARY)); ++ } else if (radeon_output->DACType == DAC_TVDAC) { ++ info->output_crt2 |= (1 << o); ++ if (info->ChipFamily == CHIP_FAMILY_R200) { ++ tmp = INREG(RADEON_FP2_GEN_CNTL); ++ tmp |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN); ++ OUTREG(RADEON_FP2_GEN_CNTL, tmp); ++ save->fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN); ++ } else { ++ tmp = INREG(RADEON_CRTC2_GEN_CNTL); ++ tmp |= RADEON_CRTC2_CRT2_ON; ++ OUTREG(RADEON_CRTC2_GEN_CNTL, tmp); ++ save->crtc2_gen_cntl |= RADEON_CRTC2_CRT2_ON; ++ } ++ tv_dac_change = 1; ++ } ++ } else if (radeon_output->MonType == MT_DFP) { ++ if (radeon_output->TMDSType == TMDS_INT) { ++ info->output_dfp1 |= (1 << o); ++ tmp = INREG(RADEON_FP_GEN_CNTL); ++ tmp |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN); ++ OUTREG(RADEON_FP_GEN_CNTL, tmp); ++ save->fp_gen_cntl |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN); ++ } else if (radeon_output->TMDSType == TMDS_EXT) { ++ info->output_dfp2 |= (1 << o); ++ tmp = INREG(RADEON_FP2_GEN_CNTL); + tmp &= ~RADEON_FP2_BLANK_EN; +- tmp |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN); +- OUTREG(RADEON_FP2_GEN_CNTL, tmp); +- save->fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN); ++ tmp |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN); ++ OUTREG(RADEON_FP2_GEN_CNTL, tmp); ++ save->fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN); + save->fp2_gen_cntl &= ~RADEON_FP2_BLANK_EN; +- } +- } else if (radeon_output->MonType == MT_LCD) { +- tmp = INREG(RADEON_LVDS_GEN_CNTL); +- tmp |= (RADEON_LVDS_ON | RADEON_LVDS_BLON); +- tmp &= ~(RADEON_LVDS_DISPLAY_DIS); ++ } ++ } else if (radeon_output->MonType == MT_LCD) { ++ info->output_lcd1 |= (1 << o); ++ tmp = INREG(RADEON_LVDS_GEN_CNTL); ++ tmp |= (RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN); ++ tmp &= ~(RADEON_LVDS_DISPLAY_DIS); + usleep (radeon_output->PanelPwrDly * 1000); +- OUTREG(RADEON_LVDS_GEN_CNTL, tmp); +- save->lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_BLON); +- save->lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS); +- } else if (radeon_output->MonType == MT_STV || ++ OUTREG(RADEON_LVDS_GEN_CNTL, tmp); ++ save->lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN); ++ save->lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS); ++ } else if (radeon_output->MonType == MT_STV || + radeon_output->MonType == MT_CTV) { ++ info->output_tv1 |= (1 << o); + tmp = INREG(RADEON_TV_MASTER_CNTL); + tmp |= RADEON_TV_ON; + OUTREG(RADEON_TV_MASTER_CNTL, tmp); +- tv_dac_change = 2; ++ tv_dac_change = 2; + radeon_output->tv_on = TRUE; + } + } else { + ErrorF("disable montype: %d\n", radeon_output->MonType); +- if (radeon_output->MonType == MT_CRT) { +- if (radeon_output->DACType == DAC_PRIMARY) { +- tmp = INREG(RADEON_CRTC_EXT_CNTL); +- tmp &= ~RADEON_CRTC_CRT_ON; +- OUTREG(RADEON_CRTC_EXT_CNTL, tmp); +- save->crtc_ext_cntl &= ~RADEON_CRTC_CRT_ON; +- RADEONDacPowerSet(pScrn, bEnable, (radeon_output->DACType == DAC_PRIMARY)); +- } else if (radeon_output->DACType == DAC_TVDAC) { +- if (info->ChipFamily == CHIP_FAMILY_R200) { +- tmp = INREG(RADEON_FP2_GEN_CNTL); +- tmp &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN); +- OUTREG(RADEON_FP2_GEN_CNTL, tmp); +- save->fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN); +- } else { +- tmp = INREG(RADEON_CRTC2_GEN_CNTL); +- tmp &= ~RADEON_CRTC2_CRT2_ON; +- OUTREG(RADEON_CRTC2_GEN_CNTL, tmp); +- save->crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON; +- } +- tv_dac_change = 1; +- } +- } else if (radeon_output->MonType == MT_DFP) { +- if (radeon_output->TMDSType == TMDS_INT) { +- tmp = INREG(RADEON_FP_GEN_CNTL); +- tmp &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN); +- OUTREG(RADEON_FP_GEN_CNTL, tmp); +- save->fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN); +- } else if (radeon_output->TMDSType == TMDS_EXT) { +- tmp = INREG(RADEON_FP2_GEN_CNTL); +- tmp |= RADEON_FP2_BLANK_EN; +- tmp &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN); +- OUTREG(RADEON_FP2_GEN_CNTL, tmp); +- save->fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN); +- save->fp2_gen_cntl |= RADEON_FP2_BLANK_EN; +- } +- } else if (radeon_output->MonType == MT_LCD) { +- unsigned long tmpPixclksCntl = INPLL(pScrn, RADEON_PIXCLKS_CNTL); +- if (info->IsMobility || info->IsIGP) { +- /* Asic bug, when turning off LVDS_ON, we have to make sure +- RADEON_PIXCLK_LVDS_ALWAYS_ON bit is off +- */ +- OUTPLLP(pScrn, RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb); ++ if (radeon_output->MonType == MT_CRT) { ++ if (radeon_output->DACType == DAC_PRIMARY) { ++ info->output_crt1 &= ~(1 << o); ++ if (!info->output_crt1) { ++ tmp = INREG(RADEON_CRTC_EXT_CNTL); ++ tmp &= ~RADEON_CRTC_CRT_ON; ++ OUTREG(RADEON_CRTC_EXT_CNTL, tmp); ++ save->crtc_ext_cntl &= ~RADEON_CRTC_CRT_ON; ++ RADEONDacPowerSet(pScrn, bEnable, (radeon_output->DACType == DAC_PRIMARY)); ++ } ++ } else if (radeon_output->DACType == DAC_TVDAC) { ++ info->output_crt2 &= ~(1 << o); ++ tv_dac_change = 1; ++ if (!info->output_crt2) { ++ if (info->ChipFamily == CHIP_FAMILY_R200) { ++ tmp = INREG(RADEON_FP2_GEN_CNTL); ++ tmp &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN); ++ OUTREG(RADEON_FP2_GEN_CNTL, tmp); ++ save->fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN); ++ } else { ++ tmp = INREG(RADEON_CRTC2_GEN_CNTL); ++ tmp &= ~RADEON_CRTC2_CRT2_ON; ++ OUTREG(RADEON_CRTC2_GEN_CNTL, tmp); ++ save->crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON; ++ } ++ } + } +- tmp = INREG(RADEON_LVDS_GEN_CNTL); +- tmp |= RADEON_LVDS_DISPLAY_DIS; +- tmp &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON); +- OUTREG(RADEON_LVDS_GEN_CNTL, tmp); +- save->lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS; +- save->lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON); +- if (info->IsMobility || info->IsIGP) { +- OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, tmpPixclksCntl); ++ } else if (radeon_output->MonType == MT_DFP) { ++ if (radeon_output->TMDSType == TMDS_INT) { ++ info->output_dfp1 &= ~(1 << o); ++ if (!info->output_dfp1) { ++ tmp = INREG(RADEON_FP_GEN_CNTL); ++ tmp &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN); ++ OUTREG(RADEON_FP_GEN_CNTL, tmp); ++ save->fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN); ++ } ++ } else if (radeon_output->TMDSType == TMDS_EXT) { ++ info->output_dfp2 &= ~(1 << o); ++ if (!info->output_dfp2) { ++ tmp = INREG(RADEON_FP2_GEN_CNTL); ++ tmp |= RADEON_FP2_BLANK_EN; ++ tmp &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN); ++ OUTREG(RADEON_FP2_GEN_CNTL, tmp); ++ save->fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN); ++ save->fp2_gen_cntl |= RADEON_FP2_BLANK_EN; ++ } ++ } ++ } else if (radeon_output->MonType == MT_LCD) { ++ info->output_lcd1 &= ~(1 << o); ++ if (!info->output_lcd1) { ++ unsigned long tmpPixclksCntl = INPLL(pScrn, RADEON_PIXCLKS_CNTL); ++ if (info->IsMobility || info->IsIGP) { ++ /* Asic bug, when turning off LVDS_ON, we have to make sure ++ RADEON_PIXCLK_LVDS_ALWAYS_ON bit is off ++ */ ++ OUTPLLP(pScrn, RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb); ++ } ++ tmp = INREG(RADEON_LVDS_GEN_CNTL); ++ tmp |= RADEON_LVDS_DISPLAY_DIS; ++ tmp &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN); ++ OUTREG(RADEON_LVDS_GEN_CNTL, tmp); ++ save->lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS; ++ save->lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN); ++ if (info->IsMobility || info->IsIGP) { ++ OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, tmpPixclksCntl); ++ } ++ } ++ } else if (radeon_output->MonType == MT_STV || radeon_output->MonType == MT_CTV) { ++ info->output_tv1 &= ~(1 << o); ++ tv_dac_change = 2; ++ if (!info->output_tv1) { ++ tmp = INREG(RADEON_TV_MASTER_CNTL); ++ tmp &= ~RADEON_TV_ON; ++ OUTREG(RADEON_TV_MASTER_CNTL, tmp); ++ radeon_output->tv_on = FALSE; + } +- } else if (radeon_output->MonType == MT_STV || radeon_output->MonType == MT_CTV) { +- tmp = INREG(RADEON_TV_MASTER_CNTL); +- tmp &= ~RADEON_TV_ON; +- OUTREG(RADEON_TV_MASTER_CNTL, tmp); +- tv_dac_change = 2; +- radeon_output->tv_on = FALSE; + } + } + + if (tv_dac_change) { + if (bEnable) +- info->tv_dac_enable_mask |= tv_dac_change; ++ info->tv_dac_enable_mask |= tv_dac_change; + else +- info->tv_dac_enable_mask &= ~tv_dac_change; ++ info->tv_dac_enable_mask &= ~tv_dac_change; + + if (bEnable && info->tv_dac_enable_mask) + RADEONDacPowerSet(pScrn, bEnable, (radeon_output->DACType == DAC_PRIMARY)); +@@ -487,13 +518,13 @@ void RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_b + int stop_req, max_stop_req; + float read_return_rate, time_disp1_drop_priority; + +- /* +- * Set display0/1 priority up on r3/4xx in the memory controller for +- * high res modes if the user specifies HIGH for displaypriority ++ /* ++ * Set display0/1 priority up on r3/4xx in the memory controller for ++ * high res modes if the user specifies HIGH for displaypriority + * option. + */ + if ((info->DispPriority == 2) && IS_R300_VARIANT) { +- CARD32 mc_init_misc_lat_timer = INREG(R300_MC_INIT_MISC_LAT_TIMER); ++ CARD32 mc_init_misc_lat_timer = INREG(R300_MC_INIT_MISC_LAT_TIMER); + if (pRADEONEnt->pCrtc[1]->enabled) { + mc_init_misc_lat_timer |= 0x1100; /* display 0 and 1 */ + } else { +@@ -522,14 +553,14 @@ void RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_b + peak_disp_bw += (pix_clk2 * pixel_bytes2); + + if (peak_disp_bw >= mem_bw * min_mem_eff) { +- xf86DrvMsg(pScrn->scrnIndex, X_WARNING, ++ xf86DrvMsg(pScrn->scrnIndex, X_WARNING, + "You may not have enough display bandwidth for current mode\n" + "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n"); +- } ++ } + + /* CRTC1 + Set GRPH_BUFFER_CNTL register using h/w defined optimal values. +- GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ] ++ GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ] + */ + stop_req = mode1->HDisplay * info->CurrentLayout.pixel_bytes / 16; + +@@ -540,7 +571,7 @@ void RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_b + max_stop_req = 0x7c; + if (stop_req > max_stop_req) + stop_req = max_stop_req; +- ++ + /* Get values from the EXT_MEM_CNTL register...converting its contents. */ + temp = INREG(RADEON_MEM_TIMING_CNTL); + if ((info->ChipFamily == CHIP_FAMILY_RV100) || info->IsIGP) { /* RV100, M6, IGPs */ +@@ -552,8 +583,8 @@ void RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_b + mem_trp = MemTrpMemTimingCntl[ (temp & 0x700) >> 8]; + mem_tras = MemTrasMemTimingCntl[(temp & 0xf000) >> 12]; + } +- +- /* Get values from the MEM_SDRAM_MODE_REG register...converting its */ ++ ++ /* Get values from the MEM_SDRAM_MODE_REG register...converting its */ + temp = INREG(RADEON_MEM_SDRAM_MODE_REG); + data = (temp & (7<<20)) >> 20; + if ((info->ChipFamily == CHIP_FAMILY_RV100) || info->IsIGP) { /* RV100, M6, IGPs */ +@@ -625,7 +656,7 @@ void RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_b + } + + mc_latency_sclk = sclk_delay / sclk_eff; +- ++ + if (info->IsDDR) { + if (info->RamWidth == 32) { + k1 = 40; +@@ -667,7 +698,7 @@ void RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_b + /* + Find the critical point of the display buffer. + */ +- critical_point= (CARD32)(disp_drain_rate * disp_latency + 0.5); ++ critical_point= (CARD32)(disp_drain_rate * disp_latency + 0.5); + + /* ???? */ + /* +@@ -682,7 +713,7 @@ void RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_b + The critical point should never be above max_stop_req-4. Setting + GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time. + */ +- if (max_stop_req - critical_point < 4) critical_point = 0; ++ if (max_stop_req - critical_point < 4) critical_point = 0; + + if (critical_point == 0 && mode2 && info->ChipFamily == CHIP_FAMILY_R300) { + /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/ +@@ -712,7 +743,7 @@ void RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_b + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "GRPH_BUFFER_CNTL from %x to %x\n", + (unsigned int)info->SavedReg.grph_buffer_cntl, +- INREG(RADEON_GRPH_BUFFER_CNTL)); ++ (unsigned int)INREG(RADEON_GRPH_BUFFER_CNTL)); + + if (mode2) { + stop_req = mode2->HDisplay * pixel_bytes2 / 16; +@@ -733,7 +764,7 @@ void RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_b + RADEON_GRPH_CRITICAL_AT_SOF | + RADEON_GRPH_STOP_CNTL); + +- if ((info->ChipFamily == CHIP_FAMILY_RS100) || ++ if ((info->ChipFamily == CHIP_FAMILY_RS100) || + (info->ChipFamily == CHIP_FAMILY_RS200)) + critical_point2 = 0; + else { +@@ -762,7 +793,7 @@ void RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_b + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "GRPH2_BUFFER_CNTL from %x to %x\n", + (unsigned int)info->SavedReg.grph2_buffer_cntl, +- INREG(RADEON_GRPH2_BUFFER_CNTL)); ++ (unsigned int)INREG(RADEON_GRPH2_BUFFER_CNTL)); + } + } + +@@ -810,7 +841,7 @@ void RADEONBlank(ScrnInfoPtr pScrn) + + for (c = 0; c < xf86_config->num_crtc; c++) { + crtc = xf86_config->crtc[c]; +- for (o = 0; o < xf86_config->num_output; o++) { ++ for (o = 0; o < xf86_config->num_output; o++) { + output = xf86_config->output[o]; + if (output->crtc != crtc) + continue; +@@ -833,7 +864,7 @@ void RADEONUnblank(ScrnInfoPtr pScrn) + if(!crtc->enabled) + continue; + crtc->funcs->dpms(crtc, DPMSModeOn); +- for (o = 0; o < xf86_config->num_output; o++) { ++ for (o = 0; o < xf86_config->num_output; o++) { + output = xf86_config->output[o]; + if (output->crtc != crtc) + continue; diff --git a/src/radeon_dri.c b/src/radeon_dri.c -index 2c533b1..7136e4e 100644 +index 2c533b1..3190451 100644 --- a/src/radeon_dri.c +++ b/src/radeon_dri.c @@ -559,12 +559,12 @@ static void RADEONDRIMoveBuffers(WindowPtr pParent, DDXPointRec ptOldOrg, @@ -1564,7 +3092,7 @@ index 2c533b1..7136e4e 100644 info->accel->NeedToSync = TRUE; #endif /* USE_XAA */ -@@ -722,7 +722,9 @@ static Bool RADEONSetAgpMode(RADEONInfoPtr info, ScreenPtr pScreen) +@@ -722,20 +722,13 @@ static Bool RADEONSetAgpMode(RADEONInfoPtr info, ScreenPtr pScreen) unsigned long mode = drmAgpGetMode(info->drmFD); /* Default mode */ unsigned int vendor = drmAgpVendorId(info->drmFD); unsigned int device = drmAgpDeviceId(info->drmFD); @@ -1573,13 +3101,47 @@ index 2c533b1..7136e4e 100644 + pcie-agp rialto bridge chip - use the one from bridge which must match */ + CARD32 agp_status = (INREG(RADEON_AGP_STATUS) | RADEON_AGPv3_MODE) & mode; Bool is_v3 = (agp_status & RADEON_AGPv3_MODE); - unsigned int defaultMode; - MessageType from; +- unsigned int defaultMode; +- MessageType from; +- +- if (is_v3) { +- defaultMode = (agp_status & RADEON_AGPv3_8X_MODE) ? 8 : 4; +- } else { +- if (agp_status & RADEON_AGP_4X_MODE) defaultMode = 4; +- else if (agp_status & RADEON_AGP_2X_MODE) defaultMode = 2; +- else defaultMode = 1; +- } +- +- from = X_DEFAULT; ++ unsigned int defaultMode = is_v3 ? ++ ((agp_status & RADEON_AGPv3_8X_MODE) ? 8 : 4) : 1; ++ MessageType from = X_DEFAULT; + + if (xf86GetOptValInteger(info->Options, OPTION_AGP_MODE, &info->agpMode)) { + if ((info->agpMode < (is_v3 ? 4 : 1)) || +@@ -1359,6 +1352,9 @@ Bool RADEONDRISetVBlankInterrupt(ScrnInfoPtr pScrn, Bool on) + xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); + int value = 0; + ++ if (!info->want_vblank_interrupts) ++ on = FALSE; ++ + if (info->directRenderingEnabled && info->pKernelDRMVersion->version_minor >= 28) { + if (on) { + if (xf86_config->num_crtc > 1 && xf86_config->crtc[1]->enabled) diff --git a/src/radeon_driver.c b/src/radeon_driver.c -index e027379..3422b66 100644 +index e027379..25b2119 100644 --- a/src/radeon_driver.c +++ b/src/radeon_driver.c -@@ -107,9 +107,10 @@ +@@ -90,7 +90,6 @@ + + /* X and server generic header files */ + #include "xf86.h" +-#include "xf86_ansic.h" /* For xf86getsecs() */ + #include "xf86_OSproc.h" + #include "xf86RAC.h" + #include "xf86RandR12.h" +@@ -107,9 +106,10 @@ #include #include "atipciids.h" @@ -1591,7 +3153,7 @@ index e027379..3422b66 100644 /* Forward definitions for driver functions */ static Bool RADEONCloseScreen(int scrnIndex, ScreenPtr pScreen); -@@ -191,6 +192,8 @@ static const OptionInfoRec RADEONOptions[] = { +@@ -191,6 +191,8 @@ static const OptionInfoRec RADEONOptions[] = { { OPTION_MAC_MODEL, "MacModel", OPTV_STRING, {0}, FALSE }, #endif { OPTION_TVDAC_LOAD_DETECT, "TVDACLoadDetect", OPTV_BOOLEAN, {0}, FALSE }, @@ -1600,7 +3162,79 @@ index e027379..3422b66 100644 { -1, NULL, OPTV_NONE, {0}, FALSE } }; -@@ -1472,6 +1475,7 @@ static Bool RADEONPreInitChipType(ScrnInfoPtr pScrn) +@@ -802,8 +804,8 @@ static Bool RADEONProbePLLParameters(ScrnInfoPtr pScrn) + unsigned xclk, tmp, ref_div; + int hTotal, vTotal, num, denom, m, n; + float hz, prev_xtal, vclk, xtal, mpll, spll; +- long start_secs, start_usecs, stop_secs, stop_usecs, total_usecs; +- long to1_secs, to1_usecs, to2_secs, to2_usecs; ++ long total_usecs; ++ struct timeval start, stop, to1, to2; + unsigned int f1, f2, f3; + int tries = 0; + +@@ -813,32 +815,32 @@ static Bool RADEONProbePLLParameters(ScrnInfoPtr pScrn) + if (++tries > 10) + goto failed; + +- xf86getsecs(&to1_secs, &to1_usecs); ++ gettimeofday(&to1, NULL); + f1 = INREG(RADEON_CRTC_CRNT_FRAME); + for (;;) { + f2 = INREG(RADEON_CRTC_CRNT_FRAME); + if (f1 != f2) + break; +- xf86getsecs(&to2_secs, &to2_usecs); +- if ((to2_secs - to1_secs) > 1) { ++ gettimeofday(&to2, NULL); ++ if ((to2.tv_sec - to1.tv_sec) > 1) { + xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Clock not counting...\n"); + goto failed; + } + } +- xf86getsecs(&start_secs, &start_usecs); ++ gettimeofday(&start, NULL); + for(;;) { + f3 = INREG(RADEON_CRTC_CRNT_FRAME); + if (f3 != f2) + break; +- xf86getsecs(&to2_secs, &to2_usecs); +- if ((to2_secs - start_secs) > 1) ++ gettimeofday(&to2, NULL); ++ if ((to2.tv_sec - start.tv_sec) > 1) + goto failed; + } +- xf86getsecs(&stop_secs, &stop_usecs); ++ gettimeofday(&stop, NULL); + +- if ((stop_secs - start_secs) != 0) ++ if ((stop.tv_sec - start.tv_sec) != 0) + goto again; +- total_usecs = abs(stop_usecs - start_usecs); ++ total_usecs = abs(stop.tv_usec - start.tv_usec); + if (total_usecs == 0) + goto again; + hz = 1000000.0/(float)total_usecs; +@@ -1061,8 +1063,17 @@ static void RADEONGetClockInfo(ScrnInfoPtr pScrn) + info->RamWidth / 16); + } + ++ /* card limits for computing PLLs */ ++ pll->min_ref_div = 2; ++ pll->max_ref_div = 0x3ff; ++ pll->min_feedback_div = 4; ++ pll->max_feedback_div = 0x7ff; ++ pll->pll_in_min = 40; ++ pll->pll_in_max = 500; ++ pll->best_vco = 0; ++ + xf86DrvMsg (pScrn->scrnIndex, X_INFO, +- "PLL parameters: rf=%d rd=%d min=%d max=%d; xclk=%d\n", ++ "PLL parameters: rf=%u rd=%u min=%u max=%u; xclk=%u\n", + pll->reference_freq, + pll->reference_div, + (unsigned)pll->min_pll_freq, (unsigned)pll->max_pll_freq, +@@ -1472,6 +1483,7 @@ static Bool RADEONPreInitChipType(ScrnInfoPtr pScrn) GDevPtr dev = pEnt->device; unsigned char *RADEONMMIO = info->MMIO; MessageType from = X_PROBED; @@ -1608,7 +3242,7 @@ index e027379..3422b66 100644 #ifdef XF86DRI const char *s; uint32_t cmd_stat; -@@ -1511,20 +1515,25 @@ static Bool RADEONPreInitChipType(ScrnInfoPtr pScrn) +@@ -1511,20 +1523,25 @@ static Bool RADEONPreInitChipType(ScrnInfoPtr pScrn) info->IsDellServer = FALSE; info->HasSingleDAC = FALSE; info->InternalTVOut = TRUE; @@ -1643,7 +3277,7 @@ index e027379..3422b66 100644 /* DELL triple-head configuration. */ if ((PCI_SUB_VENDOR_ID(info->PciInfo) == PCI_VENDOR_DELL) && ((PCI_SUB_DEVICE_ID(info->PciInfo) == 0x016c) || -@@ -1540,220 +1549,9 @@ static Bool RADEONPreInitChipType(ScrnInfoPtr pScrn) +@@ -1540,220 +1557,9 @@ static Bool RADEONPreInitChipType(ScrnInfoPtr pScrn) info->IsDellServer = TRUE; xf86DrvMsg(pScrn->scrnIndex, X_INFO, "DELL server detected, force to special setup\n"); } @@ -1865,7 +3499,37 @@ index e027379..3422b66 100644 } -@@ -4245,10 +4043,13 @@ void RADEONRestoreBIOSRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore) +@@ -3736,10 +3542,6 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, + if (!info->useEXA) { + int width, height; + +- xf86DrvMsg(pScrn->scrnIndex, X_INFO, +- "Using hardware cursor (scanline %u)\n", +- (unsigned)(info->cursor_offset / pScrn->displayWidth +- / info->CurrentLayout.pixel_bytes)); + if (xf86QueryLargestOffscreenArea(pScreen, &width, &height, + 0, 0, 0)) { + xf86DrvMsg(scrnIndex, X_INFO, +@@ -3754,7 +3556,6 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, + xf86DrvMsg(scrnIndex, X_INFO, "Using software cursor\n"); + } + } else { +- info->cursor_offset = 0; + xf86DrvMsg(scrnIndex, X_INFO, "Using software cursor\n"); + } + +@@ -4237,6 +4038,10 @@ void RADEONRestoreLVDSRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore) + if (info->IsMobility) { + OUTREG(RADEON_LVDS_GEN_CNTL, restore->lvds_gen_cntl); + OUTREG(RADEON_LVDS_PLL_CNTL, restore->lvds_pll_cntl); ++ ++ if (info->ChipFamily == CHIP_FAMILY_RV410) { ++ OUTREG(RADEON_CLOCK_CNTL_INDEX, 0); ++ } + } + + } +@@ -4245,10 +4050,13 @@ void RADEONRestoreBIOSRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore) { RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; @@ -1880,7 +3544,7 @@ index e027379..3422b66 100644 if (restore->bios_6_scratch & 0x40000000) bios_6_scratch |= 0x40000000; else -@@ -4904,9 +4705,9 @@ void RADEONChangeSurfaces(ScrnInfoPtr pScrn) +@@ -4904,9 +4712,9 @@ void RADEONChangeSurfaces(ScrnInfoPtr pScrn) retvalue = drmCommandWrite(info->drmFD, DRM_RADEON_SURF_FREE, &drmsurffree, sizeof(drmsurffree)); @@ -1893,7 +3557,7 @@ index e027379..3422b66 100644 drmsurffree.address = info->depthOffset; retvalue = drmCommandWrite(info->drmFD, DRM_RADEON_SURF_FREE, &drmsurffree, sizeof(drmsurffree)); -@@ -4961,9 +4762,10 @@ void RADEONChangeSurfaces(ScrnInfoPtr pScrn) +@@ -4961,9 +4769,10 @@ void RADEONChangeSurfaces(ScrnInfoPtr pScrn) } /* rv100 and probably the derivative igps don't have depth tiling on all the time? */ @@ -1907,8 +3571,177 @@ index e027379..3422b66 100644 drmRadeonSurfaceAlloc drmsurfalloc; drmsurfalloc.size = depthBufferSize; drmsurfalloc.address = info->depthOffset; +diff --git a/src/radeon_exa.c b/src/radeon_exa.c +index 8a12e1b..4da4841 100644 +--- a/src/radeon_exa.c ++++ b/src/radeon_exa.c +@@ -374,6 +374,7 @@ Bool RADEONSetupMemEXA (ScreenPtr pScreen) + { + ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; + RADEONInfoPtr info = RADEONPTR(pScrn); ++ xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); + int cpp = info->CurrentLayout.pixel_bytes; + int screen_size; + int byteStride = pScrn->displayWidth * cpp; +@@ -405,14 +406,23 @@ Bool RADEONSetupMemEXA (ScreenPtr pScreen) + /* Reserve static area for hardware cursor */ + if (!xf86ReturnOptValBool(info->Options, OPTION_SW_CURSOR, FALSE)) { + int cursor_size = 64 * 4 * 64; ++ int c; + +- info->cursor_offset = info->exa->offScreenBase; ++ for (c = 0; c < xf86_config->num_crtc; c++) { ++ xf86CrtcPtr crtc = xf86_config->crtc[c]; ++ RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; ++ ++ radeon_crtc->cursor_offset = info->exa->offScreenBase; ++ info->exa->offScreenBase += cursor_size; ++ ++ xf86DrvMsg(pScrn->scrnIndex, X_INFO, ++ "Will use %d kb for hardware cursor %d at offset 0x%08x\n", ++ (cursor_size * xf86_config->num_crtc) / 1024, ++ c, ++ (unsigned int)radeon_crtc->cursor_offset); ++ } + +- xf86DrvMsg(pScrn->scrnIndex, X_INFO, +- "Will use %d kb for hardware cursor at offset 0x%08x\n", +- cursor_size / 1024, (unsigned int)info->cursor_offset); + +- info->exa->offScreenBase += cursor_size; + } + + #if defined(XF86DRI) +diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c +index 9251569..eae69c4 100644 +--- a/src/radeon_exa_render.c ++++ b/src/radeon_exa_render.c +@@ -736,6 +736,21 @@ do { \ + + #endif /* !ACCEL_CP */ + ++#ifdef ONLY_ONCE ++static inline void transformPoint(PictTransform *transform, xPointFixed *point) ++{ ++ PictVector v; ++ v.vector[0] = point->x; ++ v.vector[1] = point->y; ++ v.vector[2] = xFixed1; ++ PictureTransformPoint(transform, &v); ++ point->x = v.vector[0]; ++ point->y = v.vector[1]; ++} ++#endif ++ ++#define xFixedToFloat(f) (((float) (f)) / 65536) ++ + static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst, + int srcX, int srcY, + int maskX, int maskY, +@@ -744,7 +759,8 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst, + { + RINFO_FROM_SCREEN(pDst->drawable.pScreen); + int srcXend, srcYend, maskXend, maskYend; +- PictVector v; ++ xPointFixed srcTopLeft, srcTopRight, srcBottomLeft, srcBottomRight; ++ xPointFixed maskTopLeft, maskTopRight, maskBottomLeft, maskBottomRight; + ACCEL_PREAMBLE(); + + ENTER_DRAW(0); +@@ -756,33 +772,36 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst, + srcYend = srcY + h; + maskXend = maskX + w; + maskYend = maskY + h; ++ ++ srcTopLeft.x = IntToxFixed(srcX); ++ srcTopLeft.y = IntToxFixed(srcY); ++ srcTopRight.x = IntToxFixed(srcX + w); ++ srcTopRight.y = IntToxFixed(srcY); ++ srcBottomLeft.x = IntToxFixed(srcX); ++ srcBottomLeft.y = IntToxFixed(srcY + h); ++ srcBottomRight.x = IntToxFixed(srcX + w); ++ srcBottomRight.y = IntToxFixed(srcY + h); ++ ++ maskTopLeft.x = IntToxFixed(maskX); ++ maskTopLeft.y = IntToxFixed(maskY); ++ maskTopRight.x = IntToxFixed(maskX + w); ++ maskTopRight.y = IntToxFixed(maskY); ++ maskBottomLeft.x = IntToxFixed(maskX); ++ maskBottomLeft.y = IntToxFixed(maskY + h); ++ maskBottomRight.x = IntToxFixed(maskX + w); ++ maskBottomRight.y = IntToxFixed(maskY + h); ++ + if (is_transform[0]) { +- v.vector[0] = IntToxFixed(srcX); +- v.vector[1] = IntToxFixed(srcY); +- v.vector[2] = xFixed1; +- PictureTransformPoint(transform[0], &v); +- srcX = xFixedToInt(v.vector[0]); +- srcY = xFixedToInt(v.vector[1]); +- v.vector[0] = IntToxFixed(srcXend); +- v.vector[1] = IntToxFixed(srcYend); +- v.vector[2] = xFixed1; +- PictureTransformPoint(transform[0], &v); +- srcXend = xFixedToInt(v.vector[0]); +- srcYend = xFixedToInt(v.vector[1]); ++ transformPoint(transform[0], &srcTopLeft); ++ transformPoint(transform[0], &srcTopRight); ++ transformPoint(transform[0], &srcBottomLeft); ++ transformPoint(transform[0], &srcBottomRight); + } + if (is_transform[1]) { +- v.vector[0] = IntToxFixed(maskX); +- v.vector[1] = IntToxFixed(maskY); +- v.vector[2] = xFixed1; +- PictureTransformPoint(transform[1], &v); +- maskX = xFixedToInt(v.vector[0]); +- maskY = xFixedToInt(v.vector[1]); +- v.vector[0] = IntToxFixed(maskXend); +- v.vector[1] = IntToxFixed(maskYend); +- v.vector[2] = xFixed1; +- PictureTransformPoint(transform[1], &v); +- maskXend = xFixedToInt(v.vector[0]); +- maskYend = xFixedToInt(v.vector[1]); ++ transformPoint(transform[1], &maskTopLeft); ++ transformPoint(transform[1], &maskTopRight); ++ transformPoint(transform[1], &maskBottomLeft); ++ transformPoint(transform[1], &maskBottomRight); + } + + #ifdef ACCEL_CP +@@ -828,18 +847,18 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst, + VTX_OUT(dstX + w, dstY + h, srcXend, srcYend, maskXend, maskYend); + VTX_OUT(dstX + w, dstY, srcXend, srcY, maskXend, maskY); + } else { +- VTX_OUT((float)dstX, (float)dstY, +- (float)srcX / info->texW[0], (float)srcY / info->texH[0], +- (float)maskX / info->texW[1], (float)maskY / info->texH[1]); +- VTX_OUT((float)dstX, (float)(dstY + h), +- (float)srcX / info->texW[0], (float)srcYend / info->texH[0], +- (float)maskX / info->texW[1], (float)maskYend / info->texH[1]); +- VTX_OUT((float)(dstX + w), (float)(dstY + h), +- (float)srcXend / info->texW[0], (float)srcYend / info->texH[0], +- (float)maskXend / info->texW[1], (float)maskYend / info->texH[1]); +- VTX_OUT((float)(dstX + w), (float)dstY, +- (float)srcXend / info->texW[0], (float)srcY / info->texH[0], +- (float)maskXend / info->texW[1], (float)maskY / info->texH[1]); ++ VTX_OUT((float)dstX, (float)dstY, ++ xFixedToFloat(srcTopLeft.x) / info->texW[0], xFixedToFloat(srcTopLeft.y) / info->texH[0], ++ xFixedToFloat(maskTopLeft.x) / info->texW[1], xFixedToFloat(maskTopLeft.y) / info->texH[1]); ++ VTX_OUT((float)dstX, (float)(dstY + h), ++ xFixedToFloat(srcBottomLeft.x) / info->texW[0], xFixedToFloat(srcBottomLeft.y) / info->texH[0], ++ xFixedToFloat(maskBottomLeft.x) / info->texW[1], xFixedToFloat(maskBottomLeft.y) / info->texH[1]); ++ VTX_OUT((float)(dstX + w), (float)(dstY + h), ++ xFixedToFloat(srcBottomRight.x) / info->texW[0], xFixedToFloat(srcBottomRight.y) / info->texH[0], ++ xFixedToFloat(maskBottomRight.x) / info->texW[1], xFixedToFloat(maskBottomRight.y) / info->texH[1]); ++ VTX_OUT((float)(dstX + w), (float)dstY, ++ xFixedToFloat(srcTopRight.x) / info->texW[0], xFixedToFloat(srcTopRight.y) / info->texH[0], ++ xFixedToFloat(maskTopRight.x) / info->texW[1], xFixedToFloat(maskTopRight.y) / info->texH[1]); + } + + #ifdef ACCEL_CP diff --git a/src/radeon_output.c b/src/radeon_output.c -index 599a89c..11a2a8a 100644 +index 599a89c..6454460 100644 --- a/src/radeon_output.c +++ b/src/radeon_output.c @@ -218,22 +218,33 @@ RADEONRestoreDVOChip(ScrnInfoPtr pScrn, xf86OutputPtr output) @@ -1973,7 +3806,105 @@ index 599a89c..11a2a8a 100644 } } else { radeon_output->MonType = RADEONDisplayDDCConnected(pScrn, output); -@@ -1039,11 +1057,12 @@ static void RADEONInitDACRegisters(xf86OutputPtr output, RADEONSavePtr save, +@@ -666,6 +684,52 @@ void RADEONConnectorFindMonitor(ScrnInfoPtr pScrn, xf86OutputPtr output) + } + } + ++#ifndef __powerpc__ ++ ++static RADEONMonitorType ++RADEONDetectLidStatus(ScrnInfoPtr pScrn) ++{ ++ RADEONInfoPtr info = RADEONPTR(pScrn); ++ RADEONMonitorType MonType = MT_NONE; ++#ifdef __linux__ ++ char lidline[50]; /* 50 should be sufficient for our purposes */ ++ FILE *f = fopen ("/proc/acpi/button/lid/LID/state", "r"); ++ ++ if (f != NULL) { ++ while (fgets(lidline, sizeof lidline, f)) { ++ if (!strncmp(lidline, "state:", strlen ("state:"))) { ++ if (strstr(lidline, "open")) { ++ fclose(f); ++ ErrorF("proc lid open\n"); ++ return MT_LCD; ++ } ++ else if (strstr(lidline, "closed")) { ++ fclose(f); ++ ErrorF("proc lid closed\n"); ++ return MT_NONE; ++ } ++ } ++ } ++ fclose(f); ++ } ++#endif ++ ++ if (!info->IsAtomBios) { ++ unsigned char *RADEONMMIO = info->MMIO; ++ ++ /* see if the lid is closed -- only works at boot */ ++ if (INREG(RADEON_BIOS_6_SCRATCH) & 0x10) ++ MonType = MT_NONE; ++ else ++ MonType = MT_LCD; ++ } else ++ MonType = MT_LCD; ++ ++ return MonType; ++} ++ ++#endif /* __powerpc__ */ ++ + static RADEONMonitorType RADEONPortCheckNonDDC(ScrnInfoPtr pScrn, xf86OutputPtr output) + { + RADEONOutputPrivatePtr radeon_output = output->driver_private; +@@ -673,21 +737,10 @@ static RADEONMonitorType RADEONPortCheckNonDDC(ScrnInfoPtr pScrn, xf86OutputPtr + + if (radeon_output->type == OUTPUT_LVDS) { + #if defined(__powerpc__) +- /* not sure on ppc, OF? */ ++ MonType = MT_LCD; + #else +- RADEONInfoPtr info = RADEONPTR(pScrn); +- +- if (!info->IsAtomBios) { +- unsigned char *RADEONMMIO = info->MMIO; +- +- /* see if the lid is closed -- only works at boot */ +- if (INREG(RADEON_BIOS_6_SCRATCH) & 0x10) +- MonType = MT_NONE; +- else +- MonType = MT_LCD; +- } else ++ MonType = RADEONDetectLidStatus(pScrn); + #endif +- MonType = MT_LCD; + } /*else if (radeon_output->type == OUTPUT_DVI) { + if (radeon_output->TMDSType == TMDS_INT) { + if (INREG(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE) +@@ -782,7 +835,7 @@ radeon_mode_fixup(xf86OutputPtr output, DisplayModePtr mode, + } + + /* update timing for LVDS and DFP if RMX is active */ +- if ((radeon_output->MonType == MT_LCD) || (radeon_output->Flags & RADEON_USE_RMX)) { ++ if (radeon_output->Flags & RADEON_USE_RMX) { + /* set to the panel's native mode */ + adjusted_mode->HTotal = radeon_output->PanelXRes + radeon_output->HBlank; + adjusted_mode->HSyncStart = radeon_output->PanelXRes + radeon_output->HOverPlus; +@@ -937,7 +990,10 @@ static void RADEONInitLVDSRegisters(xf86OutputPtr output, RADEONSavePtr save, + + save->lvds_gen_cntl = info->SavedReg.lvds_gen_cntl; + save->lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS; +- save->lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON); ++ save->lvds_gen_cntl &= ~(RADEON_LVDS_ON | ++ RADEON_LVDS_BLON | ++ RADEON_LVDS_EN | ++ RADEON_LVDS_RST_FM); + + if (IS_R300_VARIANT) + save->lvds_pll_cntl &= ~(R300_LVDS_SRC_SEL_MASK); +@@ -1039,11 +1095,12 @@ static void RADEONInitDACRegisters(xf86OutputPtr output, RADEONSavePtr save, save->dac_macro_cntl = info->SavedReg.dac_macro_cntl; } @@ -1988,7 +3919,7 @@ index 599a89c..11a2a8a 100644 if (info->ChipFamily == CHIP_FAMILY_R420 || info->ChipFamily == CHIP_FAMILY_RV410) { -@@ -1064,10 +1083,11 @@ RADEONInitTvDacCntl(ScrnInfoPtr pScrn, RADEONSavePtr save) +@@ -1064,10 +1121,11 @@ RADEONInitTvDacCntl(ScrnInfoPtr pScrn, RADEONSavePtr save) RADEON_TV_DAC_GDACPD | RADEON_TV_DAC_GDACPD); } @@ -2003,7 +3934,7 @@ index 599a89c..11a2a8a 100644 } -@@ -1078,7 +1098,7 @@ static void RADEONInitDAC2Registers(xf86OutputPtr output, RADEONSavePtr save, +@@ -1078,7 +1136,7 @@ static void RADEONInitDAC2Registers(xf86OutputPtr output, RADEONSavePtr save, RADEONInfoPtr info = RADEONPTR(pScrn); /*0x0028023;*/ @@ -2012,7 +3943,7 @@ index 599a89c..11a2a8a 100644 if (IS_R300_VARIANT) save->gpiopad_a = info->SavedReg.gpiopad_a | 1; -@@ -1670,10 +1690,16 @@ radeon_detect(xf86OutputPtr output) +@@ -1670,10 +1728,16 @@ radeon_detect(xf86OutputPtr output) /* default to unknown for flaky chips/connectors * so we can get something on the screen */ @@ -2032,7 +3963,7 @@ index 599a89c..11a2a8a 100644 } if (connected) -@@ -1740,6 +1766,7 @@ radeon_create_resources(xf86OutputPtr output) +@@ -1740,6 +1804,7 @@ radeon_create_resources(xf86OutputPtr output) INT32 range[2]; int data, err; const char *s; @@ -2040,7 +3971,7 @@ index 599a89c..11a2a8a 100644 /* backlight control */ if (radeon_output->type == OUTPUT_LVDS) { -@@ -1975,6 +2002,26 @@ radeon_create_resources(xf86OutputPtr output) +@@ -1975,6 +2040,26 @@ radeon_create_resources(xf86OutputPtr output) s = "ntsc"; break; } @@ -2067,7 +3998,7 @@ index 599a89c..11a2a8a 100644 err = RRChangeOutputProperty(output->randr_output, tv_std_atom, XA_STRING, 8, PropModeReplace, strlen(s), (pointer)s, FALSE, FALSE); -@@ -2623,6 +2670,7 @@ void RADEONInitConnector(xf86OutputPtr output) +@@ -2623,6 +2708,7 @@ void RADEONInitConnector(xf86OutputPtr output) if (radeon_output->type == OUTPUT_STV || radeon_output->type == OUTPUT_CTV) { RADEONGetTVInfo(output); @@ -2075,7 +4006,7 @@ index 599a89c..11a2a8a 100644 } if (radeon_output->DACType == DAC_TVDAC) { -@@ -2658,7 +2706,7 @@ static Bool RADEONSetupAppleConnectors(ScrnInfoPtr pScrn) +@@ -2658,7 +2744,7 @@ static Bool RADEONSetupAppleConnectors(ScrnInfoPtr pScrn) info->BiosConnector[2].DDCType = DDC_NONE_DETECTED; info->BiosConnector[2].valid = TRUE; return TRUE; @@ -2084,7 +4015,7 @@ index 599a89c..11a2a8a 100644 info->BiosConnector[0].DDCType = DDC_DVI; info->BiosConnector[0].DACType = DAC_NONE; info->BiosConnector[0].TMDSType = TMDS_NONE; -@@ -2677,7 +2725,7 @@ static Bool RADEONSetupAppleConnectors(ScrnInfoPtr pScrn) +@@ -2677,7 +2763,7 @@ static Bool RADEONSetupAppleConnectors(ScrnInfoPtr pScrn) info->BiosConnector[2].DDCType = DDC_NONE_DETECTED; info->BiosConnector[2].valid = TRUE; return TRUE; @@ -2093,7 +4024,7 @@ index 599a89c..11a2a8a 100644 info->BiosConnector[0].DDCType = DDC_DVI; info->BiosConnector[0].DACType = DAC_NONE; info->BiosConnector[0].TMDSType = TMDS_NONE; -@@ -2696,7 +2744,26 @@ static Bool RADEONSetupAppleConnectors(ScrnInfoPtr pScrn) +@@ -2696,7 +2782,26 @@ static Bool RADEONSetupAppleConnectors(ScrnInfoPtr pScrn) info->BiosConnector[2].DDCType = DDC_NONE_DETECTED; info->BiosConnector[2].valid = TRUE; return TRUE; @@ -2121,7 +4052,7 @@ index 599a89c..11a2a8a 100644 info->BiosConnector[0].DDCType = DDC_CRT2; info->BiosConnector[0].DACType = DAC_TVDAC; info->BiosConnector[0].TMDSType = TMDS_EXT; -@@ -2709,6 +2776,38 @@ static Bool RADEONSetupAppleConnectors(ScrnInfoPtr pScrn) +@@ -2709,6 +2814,38 @@ static Bool RADEONSetupAppleConnectors(ScrnInfoPtr pScrn) info->BiosConnector[1].DDCType = DDC_NONE_DETECTED; info->BiosConnector[1].valid = TRUE; return TRUE; @@ -2160,7 +4091,7 @@ index 599a89c..11a2a8a 100644 default: return FALSE; } -@@ -2793,11 +2892,19 @@ static void RADEONSetupGenericConnectors(ScrnInfoPtr pScrn) +@@ -2793,11 +2930,19 @@ static void RADEONSetupGenericConnectors(ScrnInfoPtr pScrn) info->BiosConnector[0].ConnectorType = CONNECTOR_DVI_I; info->BiosConnector[0].valid = TRUE; @@ -2180,7 +4111,7 @@ index 599a89c..11a2a8a 100644 } } -@@ -2826,40 +2933,81 @@ static void RADEONSetupGenericConnectors(ScrnInfoPtr pScrn) +@@ -2826,40 +2971,81 @@ static void RADEONSetupGenericConnectors(ScrnInfoPtr pScrn) * in /proc/cpuinfo (on Linux) */ static RADEONMacModel RADEONDetectMacModel(ScrnInfoPtr pScrn) { @@ -2276,7 +4207,7 @@ index 599a89c..11a2a8a 100644 fclose (f); } else -@@ -2871,10 +3019,13 @@ static RADEONMacModel RADEONDetectMacModel(ScrnInfoPtr pScrn) +@@ -2871,10 +3057,13 @@ static RADEONMacModel RADEONDetectMacModel(ScrnInfoPtr pScrn) if (ret) { xf86DrvMsg(pScrn->scrnIndex, X_DEFAULT, "Detected %s.\n", @@ -2293,7 +4224,7 @@ index 599a89c..11a2a8a 100644 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "If this is not correct, try Option \"MacModel\" and " "consider reporting to the\n"); -@@ -2921,12 +3072,24 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn) +@@ -2921,12 +3110,24 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn) if (optstr) { if (!strncmp("ibook", optstr, strlen("ibook"))) info->MacModel = RADEON_MAC_IBOOK; @@ -2324,6 +4255,21 @@ index 599a89c..11a2a8a 100644 else { xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Invalid Mac Model: %s\n", optstr); } +@@ -3009,6 +3210,14 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn) + } + } + ++ /* clear the enable masks */ ++ info->output_crt1 = 0; ++ info->output_crt2 = 0; ++ info->output_dfp1 = 0; ++ info->output_dfp2 = 0; ++ info->output_lcd1 = 0; ++ info->output_tv1 = 0; ++ + for (i = 0 ; i < RADEON_MAX_BIOS_CONNECTOR; i++) { + if (info->BiosConnector[i].valid) { + RADEONOutputPrivatePtr radeon_output = xnfcalloc(sizeof(RADEONOutputPrivateRec), 1); diff --git a/src/radeon_pci_chipset_gen.h b/src/radeon_pci_chipset_gen.h new file mode 100644 index 0000000..7a36242 @@ -2628,6 +4574,30 @@ index d68a956..baea47c 100644 int gRADEONEntityIndex = -1; +diff --git a/src/radeon_probe.h b/src/radeon_probe.h +index 66ece94..7f8ce45 100644 +--- a/src/radeon_probe.h ++++ b/src/radeon_probe.h +@@ -166,6 +166,7 @@ typedef struct _RADEONCrtcPrivateRec { + #endif + int crtc_id; + int binding; ++ CARD32 cursor_offset; + /* Lookup table values to be set when the CRTC is enabled */ + CARD8 lut_r[256], lut_g[256], lut_b[256]; + } RADEONCrtcPrivateRec, *RADEONCrtcPrivatePtr; +diff --git a/src/radeon_reg.h b/src/radeon_reg.h +index 2653339..6e4e383 100644 +--- a/src/radeon_reg.h ++++ b/src/radeon_reg.h +@@ -916,6 +916,7 @@ + # define RADEON_LVDS_DISPLAY_DIS (1 << 1) + # define RADEON_LVDS_PANEL_TYPE (1 << 2) + # define RADEON_LVDS_PANEL_FORMAT (1 << 3) ++# define RADEON_LVDS_RST_FM (1 << 6) + # define RADEON_LVDS_EN (1 << 7) + # define RADEON_LVDS_BL_MOD_LEVEL_SHIFT 8 + # define RADEON_LVDS_BL_MOD_LEVEL_MASK (0xff << 8) diff --git a/src/radeon_render.c b/src/radeon_render.c index 5074fe1..490dec1 100644 --- a/src/radeon_render.c diff --git a/xorg-x11-drv-ati.spec b/xorg-x11-drv-ati.spec index 5c21fa0..7c214ba 100644 --- a/xorg-x11-drv-ati.spec +++ b/xorg-x11-drv-ati.spec @@ -5,7 +5,7 @@ Summary: Xorg X11 ati video driver Name: xorg-x11-drv-ati Version: 6.7.196 -Release: 4%{?dist} +Release: 5%{?dist} URL: http://www.x.org License: MIT Group: User Interface/X Hardware Support @@ -17,9 +17,7 @@ Source2: r128.xinf Source3: radeon.xinf # Radeon patches (0-99) -Patch2: radeon-6.6.3-renderaccel-buglet.patch Patch3: radeon-git-upstream-fixes.patch -Patch4: radeon-fix-randr-gamma.patch Patch5: radeon-6.7.196-atombios-support.patch # Rage 128 patches (100-199) @@ -44,9 +42,7 @@ X.Org X11 ati video driver. %prep %setup -q -n %{tarball}-%{version} -%patch2 -p1 -b .renderaccel %patch3 -p1 -b .fixes -%patch4 -p1 -b .randr-gamma %patch5 -p1 -b .atombios %build @@ -89,6 +85,9 @@ rm -rf $RPM_BUILD_ROOT %{_mandir}/man4/radeon.4* %changelog +* Wed Dec 19 2007 Dave Airlie 6.7.196-5 +- update to git upstream and update atombios support for r600 shadow framebuffer + * Thu Dec 06 2007 Dave Airlie 6.7.196-4 - radeon-6.7.196-atombios-support.patch - update for ppc build