diff --git a/ati-6.7.196-alloca.patch b/ati-6.7.196-alloca.patch deleted file mode 100644 index b30e143..0000000 --- a/ati-6.7.196-alloca.patch +++ /dev/null @@ -1,53 +0,0 @@ -diff -up xf86-video-ati-6.7.196/src/atidri.c.jx xf86-video-ati-6.7.196/src/atidri.c ---- xf86-video-ati-6.7.196/src/atidri.c.jx 2007-10-05 18:52:55.000000000 -0400 -+++ xf86-video-ati-6.7.196/src/atidri.c 2007-12-17 19:17:36.000000000 -0500 -@@ -553,11 +553,11 @@ static void ATIDRIMoveBuffers( WindowPtr - - if (nbox > 1) { - /* Keep ordering in each band, reverse order of bands */ -- pboxNew1 = (BoxPtr)ALLOCATE_LOCAL(sizeof(BoxRec)*nbox); -+ pboxNew1 = (BoxPtr)xalloc(sizeof(BoxRec)*nbox); - if (!pboxNew1) return; -- pptNew1 = (DDXPointPtr)ALLOCATE_LOCAL(sizeof(DDXPointRec)*nbox); -+ pptNew1 = (DDXPointPtr)xalloc(sizeof(DDXPointRec)*nbox); - if (!pptNew1) { -- DEALLOCATE_LOCAL(pboxNew1); -+ xfree(pboxNew1); - return; - } - pboxBase = pboxNext = pbox+nbox-1; -@@ -588,13 +588,13 @@ static void ATIDRIMoveBuffers( WindowPtr - - if (nbox > 1) { - /* reverse order of rects in each band */ -- pboxNew2 = (BoxPtr)ALLOCATE_LOCAL(sizeof(BoxRec)*nbox); -- pptNew2 = (DDXPointPtr)ALLOCATE_LOCAL(sizeof(DDXPointRec)*nbox); -+ pboxNew2 = (BoxPtr)xalloc(sizeof(BoxRec)*nbox); -+ pptNew2 = (DDXPointPtr)xalloc(sizeof(DDXPointRec)*nbox); - if (!pboxNew2 || !pptNew2) { -- DEALLOCATE_LOCAL(pptNew2); -- DEALLOCATE_LOCAL(pboxNew2); -- DEALLOCATE_LOCAL(pptNew1); -- DEALLOCATE_LOCAL(pboxNew1); -+ xfree(pptNew2); -+ xfree(pboxNew2); -+ xfree(pptNew1); -+ xfree(pboxNew1); - return; - } - pboxBase = pboxNext = pbox; -@@ -665,10 +665,10 @@ static void ATIDRIMoveBuffers( WindowPtr - outf(SRC_OFF_PITCH, pATI->NewHW.dst_off_pitch); - outf(DST_OFF_PITCH, pATI->NewHW.src_off_pitch); - -- DEALLOCATE_LOCAL(pptNew2); -- DEALLOCATE_LOCAL(pboxNew2); -- DEALLOCATE_LOCAL(pptNew1); -- DEALLOCATE_LOCAL(pboxNew1); -+ xfree(pptNew2); -+ xfree(pboxNew2); -+ xfree(pptNew1); -+ xfree(pboxNew1); - - ATIDRIMarkSyncInt(pScreenInfo); - #endif diff --git a/radeon-6.6.3-renderaccel-buglet.patch b/radeon-6.6.3-renderaccel-buglet.patch deleted file mode 100644 index e959704..0000000 --- a/radeon-6.6.3-renderaccel-buglet.patch +++ /dev/null @@ -1,20 +0,0 @@ ---- xf86-video-ati-6.6.3/src/radeon_render.c.jx 2006-10-03 11:00:42.000000000 -0400 -+++ xf86-video-ati-6.6.3/src/radeon_render.c 2007-06-18 11:27:55.000000000 -0400 -@@ -396,7 +396,7 @@ - if (flags & XAA_RENDER_REPEAT) - return FALSE; - -- if ((width > 2048) || (height > 2048)) -+ if ((width > 2047) || (height > 2047)) - return FALSE; - - txformat = RadeonGetTextureFormat(format); -@@ -424,7 +424,7 @@ - txformat |= ATILog2(width) << RADEON_TXFORMAT_WIDTH_SHIFT; - txformat |= ATILog2(height) << RADEON_TXFORMAT_HEIGHT_SHIFT; - } else { -- tex_size = ((height - 1) << 16) | (width - 1); -+ tex_size = (height << 16) | width; - txformat |= RADEON_TXFORMAT_NON_POWER2; - } - diff --git a/radeon-6.7.196-alloca.patch b/radeon-6.7.196-alloca.patch deleted file mode 100644 index f218723..0000000 --- a/radeon-6.7.196-alloca.patch +++ /dev/null @@ -1,55 +0,0 @@ -diff -up xf86-video-ati-6.7.196/src/radeon_dri.c.jx xf86-video-ati-6.7.196/src/radeon_dri.c ---- xf86-video-ati-6.7.196/src/radeon_dri.c.jx 2007-10-05 18:52:55.000000000 -0400 -+++ xf86-video-ati-6.7.196/src/radeon_dri.c 2007-12-17 19:19:43.000000000 -0500 -@@ -559,12 +559,12 @@ static void RADEONDRIMoveBuffers(WindowP - - if (nbox > 1) { - /* Keep ordering in each band, reverse order of bands */ -- pboxNew1 = (BoxPtr)ALLOCATE_LOCAL(sizeof(BoxRec)*nbox); -+ pboxNew1 = (BoxPtr)xalloc(sizeof(BoxRec)*nbox); - if (!pboxNew1) return; - -- pptNew1 = (DDXPointPtr)ALLOCATE_LOCAL(sizeof(DDXPointRec)*nbox); -+ pptNew1 = (DDXPointPtr)xalloc(sizeof(DDXPointRec)*nbox); - if (!pptNew1) { -- DEALLOCATE_LOCAL(pboxNew1); -+ xfree(pboxNew1); - return; - } - -@@ -601,14 +601,14 @@ static void RADEONDRIMoveBuffers(WindowP - - if (nbox > 1) { - /* reverse order of rects in each band */ -- pboxNew2 = (BoxPtr)ALLOCATE_LOCAL(sizeof(BoxRec)*nbox); -- pptNew2 = (DDXPointPtr)ALLOCATE_LOCAL(sizeof(DDXPointRec)*nbox); -+ pboxNew2 = (BoxPtr)xalloc(sizeof(BoxRec)*nbox); -+ pptNew2 = (DDXPointPtr)xalloc(sizeof(DDXPointRec)*nbox); - - if (!pboxNew2 || !pptNew2) { -- DEALLOCATE_LOCAL(pptNew2); -- DEALLOCATE_LOCAL(pboxNew2); -- DEALLOCATE_LOCAL(pptNew1); -- DEALLOCATE_LOCAL(pboxNew1); -+ xfree(pptNew2); -+ xfree(pboxNew2); -+ xfree(pptNew1); -+ xfree(pboxNew1); - return; - } - -@@ -679,10 +679,10 @@ static void RADEONDRIMoveBuffers(WindowP - - info->dst_pitch_offset = info->frontPitchOffset;; - -- DEALLOCATE_LOCAL(pptNew2); -- DEALLOCATE_LOCAL(pboxNew2); -- DEALLOCATE_LOCAL(pptNew1); -- DEALLOCATE_LOCAL(pboxNew1); -+ xfree(pptNew2); -+ xfree(pboxNew2); -+ xfree(pptNew1); -+ xfree(pboxNew1); - - info->accel->NeedToSync = TRUE; - #endif /* USE_XAA */ diff --git a/radeon-6.7.196-atombios-support.patch b/radeon-6.7.196-atombios-support.patch new file mode 100644 index 0000000..35b19d7 --- /dev/null +++ b/radeon-6.7.196-atombios-support.patch @@ -0,0 +1,18966 @@ +commit 78fb6c77f88d2ce5d2e1ec925958b97c51955ec6 +Merge: f5e8c18... ce4fa1c... +Author: Dave Airlie +Date: Wed Dec 19 14:45:11 2007 +1000 + + Merge branch 'master' into atombios-support + + Conflicts: + + src/radeon_display.c + +diff --git a/configure.ac b/configure.ac +index 1570e54..d395899 100644 +--- a/configure.ac ++++ b/configure.ac +@@ -62,6 +62,11 @@ AC_ARG_ENABLE(exa, + [EXA="$enableval"], + [EXA=yes]) + ++AC_ARG_WITH(xserver-source,AC_HELP_STRING([--with-xserver-source=XSERVER_SOURCE], ++ [Path to X server source tree]), ++ [ XSERVER_SOURCE="$withval" ], ++ [ XSERVER_SOURCE="" ]) ++ + # Checks for extensions + XORG_DRIVER_CHECK_EXT(XINERAMA, xineramaproto) + XORG_DRIVER_CHECK_EXT(RANDR, randrproto) +@@ -71,7 +76,7 @@ XORG_DRIVER_CHECK_EXT(XF86MISC, xf86miscproto) + XORG_DRIVER_CHECK_EXT(DPMSExtension, xextproto) + + # Checks for pkg-config packages +-PKG_CHECK_MODULES(XORG, [xorg-server >= 1.3 xproto fontsproto $REQUIRED_MODULES]) ++PKG_CHECK_MODULES(XORG, [xorg-server xproto fontsproto $REQUIRED_MODULES]) + sdkdir=$(pkg-config --variable=sdkdir xorg-server) + + # Checks for libraries. +@@ -112,6 +117,10 @@ if test "$DRI" = yes; then + fi + fi + ++CFLAGS="$XORG_CFLAGS" ++AC_CHECK_HEADER(xf86Modes.h,[XMODES=yes],[XMODES=no],[#include "xorg-server.h"]) ++CFLAGS="$save_CFLAGS" ++ + # Note that this is sort of inverted from drivers/ati/Imakefile in + # the monolith. We test for foo, not for !foo (i.e. ATMISC_CPIO, not + # ATIMISC_AVOID_CPIO), but the defines are negative. So beware. Oh yeah, +@@ -208,6 +217,48 @@ AC_CHECK_DECL(XSERVER_LIBPCIACCESS, + [XSERVER_LIBPCIACCESS=yes],[XSERVER_LIBPCIACCESS=no], + [#include "xorg-server.h"]) + ++AM_CONDITIONAL(XMODES, test "x$XMODES" = xno) ++ ++if test "x$XSERVER_SOURCE" = x; then ++ if test -d ../../xserver; then ++ XSERVER_SOURCE="`cd ../../xserver && pwd`" ++ fi ++fi ++ ++if test -d "$XSERVER_SOURCE"; then ++ case "$XSERVER_SOURCE" in ++ /*) ++ ;; ++ *) ++ XSERVER_SOURCE="`cd $XSERVER_SOURCE && pwd`" ++ esac ++ if test -f src/modes/xf86Modes.h; then ++ : ++ else ++ ln -sf $XSERVER_SOURCE/hw/xfree86/modes src/modes ++ fi ++ ++ if test -f src/parser/xf86Parser.h; then ++ : ++ else ++ ln -sf $XSERVER_SOURCE/hw/xfree86/parser src/parser ++ fi ++fi ++if test "x$XMODES" = xyes; then ++ AC_MSG_NOTICE([X server has new mode code]) ++ AC_DEFINE(XMODES, 1,[X server has built-in mode code]) ++ XMODES_CFLAGS= ++else ++ if test -f src/modes/xf86Modes.h -a -f src/parser/xf86Parser.h; then ++ AC_MSG_NOTICE([X server is missing new mode code, using local copy]) ++ else ++ AC_MSG_ERROR([Must have X server >= 1.3 source tree for mode setting code. Please specify --with-xserver-source]) ++ fi ++ XMODES_CFLAGS='-DXF86_MODES_RENAME -I$(top_srcdir)/src -I$(top_srcdir)/src/modes -I$(top_srcdir)/src/parser' ++fi ++ ++AC_SUBST([XMODES_CFLAGS]) ++ + CPPFLAGS="$SAVE_CPPFLAGS" + + AM_CONDITIONAL(USE_EXA, test "x$USE_EXA" = xyes) +diff --git a/src/AtomBios/CD_Operations.c b/src/AtomBios/CD_Operations.c +new file mode 100644 +index 0000000..1e48f81 +--- /dev/null ++++ b/src/AtomBios/CD_Operations.c +@@ -0,0 +1,954 @@ ++/* ++ * Copyright 2006-2007 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in ++ * all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++/** ++ ++Module Name: ++ ++ CD_Operations.c ++ ++Abstract: ++ ++ Functions Implementing Command Operations and other common functions ++ ++Revision History: ++ ++ NEG:27.09.2002 Initiated. ++--*/ ++#define __SW_4 ++ ++#include "Decoder.h" ++#include "atombios.h" ++ ++ ++ ++VOID PutDataRegister(PARSER_TEMP_DATA STACK_BASED * pParserTempData); ++VOID PutDataPS(PARSER_TEMP_DATA STACK_BASED * pParserTempData); ++VOID PutDataWS(PARSER_TEMP_DATA STACK_BASED * pParserTempData); ++VOID PutDataFB(PARSER_TEMP_DATA STACK_BASED * pParserTempData); ++VOID PutDataPLL(PARSER_TEMP_DATA STACK_BASED * pParserTempData); ++VOID PutDataMC(PARSER_TEMP_DATA STACK_BASED * pParserTempData); ++ ++UINT32 GetParametersDirect32(PARSER_TEMP_DATA STACK_BASED * pParserTempData); ++UINT32 GetParametersDirect16(PARSER_TEMP_DATA STACK_BASED * pParserTempData); ++UINT32 GetParametersDirect8(PARSER_TEMP_DATA STACK_BASED * pParserTempData); ++ ++UINT32 GetParametersRegister(PARSER_TEMP_DATA STACK_BASED * pParserTempData); ++UINT32 GetParametersPS(PARSER_TEMP_DATA STACK_BASED * pParserTempData); ++UINT32 GetParametersWS(PARSER_TEMP_DATA STACK_BASED * pParserTempData); ++UINT32 GetParametersFB(PARSER_TEMP_DATA STACK_BASED * pParserTempData); ++UINT32 GetParametersPLL(PARSER_TEMP_DATA STACK_BASED * pParserTempData); ++UINT32 GetParametersMC(PARSER_TEMP_DATA STACK_BASED * pParserTempData); ++ ++VOID SkipParameters16(PARSER_TEMP_DATA STACK_BASED * pParserTempData); ++VOID SkipParameters8(PARSER_TEMP_DATA STACK_BASED * pParserTempData); ++ ++UINT32 GetParametersIndirect(PARSER_TEMP_DATA STACK_BASED * pParserTempData); ++UINT32 GetParametersDirect(PARSER_TEMP_DATA STACK_BASED * pParserTempData); ++ ++UINT16* GetDataMasterTablePointer(DEVICE_DATA STACK_BASED* pDeviceData); ++UINT8 GetTrueIndexInMasterTable(PARSER_TEMP_DATA STACK_BASED * pParserTempData, UINT8 IndexInMasterTable); ++ ++ ++WRITE_IO_FUNCTION WritePCIFunctions[8] = { ++ WritePCIReg32, ++ WritePCIReg16, WritePCIReg16, WritePCIReg16, ++ WritePCIReg8,WritePCIReg8,WritePCIReg8,WritePCIReg8 ++}; ++WRITE_IO_FUNCTION WriteIOFunctions[8] = { ++ WriteSysIOReg32, ++ WriteSysIOReg16,WriteSysIOReg16,WriteSysIOReg16, ++ WriteSysIOReg8,WriteSysIOReg8,WriteSysIOReg8,WriteSysIOReg8 ++}; ++READ_IO_FUNCTION ReadPCIFunctions[8] = { ++ (READ_IO_FUNCTION)ReadPCIReg32, ++ (READ_IO_FUNCTION)ReadPCIReg16, ++ (READ_IO_FUNCTION)ReadPCIReg16, ++ (READ_IO_FUNCTION)ReadPCIReg16, ++ (READ_IO_FUNCTION)ReadPCIReg8, ++ (READ_IO_FUNCTION)ReadPCIReg8, ++ (READ_IO_FUNCTION)ReadPCIReg8, ++ (READ_IO_FUNCTION)ReadPCIReg8 ++}; ++READ_IO_FUNCTION ReadIOFunctions[8] = { ++ (READ_IO_FUNCTION)ReadSysIOReg32, ++ (READ_IO_FUNCTION)ReadSysIOReg16, ++ (READ_IO_FUNCTION)ReadSysIOReg16, ++ (READ_IO_FUNCTION)ReadSysIOReg16, ++ (READ_IO_FUNCTION)ReadSysIOReg8, ++ (READ_IO_FUNCTION)ReadSysIOReg8, ++ (READ_IO_FUNCTION)ReadSysIOReg8, ++ (READ_IO_FUNCTION)ReadSysIOReg8 ++}; ++READ_IO_FUNCTION GetParametersDirectArray[8]={ ++ GetParametersDirect32, ++ GetParametersDirect16,GetParametersDirect16,GetParametersDirect16, ++ GetParametersDirect8,GetParametersDirect8,GetParametersDirect8, ++ GetParametersDirect8 ++}; ++ ++COMMANDS_DECODER PutDataFunctions[6] = { ++ PutDataRegister, ++ PutDataPS, ++ PutDataWS, ++ PutDataFB, ++ PutDataPLL, ++ PutDataMC ++}; ++CD_GET_PARAMETERS GetDestination[6] = { ++ GetParametersRegister, ++ GetParametersPS, ++ GetParametersWS, ++ GetParametersFB, ++ GetParametersPLL, ++ GetParametersMC ++}; ++ ++COMMANDS_DECODER SkipDestination[6] = { ++ SkipParameters16, ++ SkipParameters8, ++ SkipParameters8, ++ SkipParameters8, ++ SkipParameters8, ++ SkipParameters8 ++}; ++ ++CD_GET_PARAMETERS GetSource[8] = { ++ GetParametersRegister, ++ GetParametersPS, ++ GetParametersWS, ++ GetParametersFB, ++ GetParametersIndirect, ++ GetParametersDirect, ++ GetParametersPLL, ++ GetParametersMC ++}; ++ ++UINT32 AlignmentMask[8] = {0xFFFFFFFF,0xFFFF,0xFFFF,0xFFFF,0xFF,0xFF,0xFF,0xFF}; ++UINT8 SourceAlignmentShift[8] = {0,0,8,16,0,8,16,24}; ++UINT8 DestinationAlignmentShift[4] = {0,8,16,24}; ++ ++#define INDIRECTIO_ID 1 ++#define INDIRECTIO_END_OF_ID 9 ++ ++VOID IndirectIOCommand(PARSER_TEMP_DATA STACK_BASED * pParserTempData); ++VOID IndirectIOCommand_MOVE(PARSER_TEMP_DATA STACK_BASED * pParserTempData, UINT32 temp); ++VOID IndirectIOCommand_MOVE_INDEX(PARSER_TEMP_DATA STACK_BASED * pParserTempData); ++VOID IndirectIOCommand_MOVE_ATTR(PARSER_TEMP_DATA STACK_BASED * pParserTempData); ++VOID IndirectIOCommand_MOVE_DATA(PARSER_TEMP_DATA STACK_BASED * pParserTempData); ++VOID IndirectIOCommand_SET(PARSER_TEMP_DATA STACK_BASED * pParserTempData); ++VOID IndirectIOCommand_CLEAR(PARSER_TEMP_DATA STACK_BASED * pParserTempData); ++ ++ ++INDIRECT_IO_PARSER_COMMANDS IndirectIOParserCommands[10]={ ++ {IndirectIOCommand,1}, ++ {IndirectIOCommand,2}, ++ {ReadIndReg32,3}, ++ {WriteIndReg32,3}, ++ {IndirectIOCommand_CLEAR,3}, ++ {IndirectIOCommand_SET,3}, ++ {IndirectIOCommand_MOVE_INDEX,4}, ++ {IndirectIOCommand_MOVE_ATTR,4}, ++ {IndirectIOCommand_MOVE_DATA,4}, ++ {IndirectIOCommand,3} ++}; ++ ++ ++VOID IndirectIOCommand(PARSER_TEMP_DATA STACK_BASED * pParserTempData) ++{ ++} ++ ++ ++VOID IndirectIOCommand_MOVE_INDEX(PARSER_TEMP_DATA STACK_BASED * pParserTempData) ++{ ++ pParserTempData->IndirectData &= ~((0xFFFFFFFF >> (32-pParserTempData->IndirectIOTablePointer[1])) << pParserTempData->IndirectIOTablePointer[3]); ++ pParserTempData->IndirectData |=(((pParserTempData->Index >> pParserTempData->IndirectIOTablePointer[2]) & ++ (0xFFFFFFFF >> (32-pParserTempData->IndirectIOTablePointer[1]))) << pParserTempData->IndirectIOTablePointer[3]); ++} ++ ++VOID IndirectIOCommand_MOVE_ATTR(PARSER_TEMP_DATA STACK_BASED * pParserTempData) ++{ ++ pParserTempData->IndirectData &= ~((0xFFFFFFFF >> (32-pParserTempData->IndirectIOTablePointer[1])) << pParserTempData->IndirectIOTablePointer[3]); ++ pParserTempData->IndirectData |=(((pParserTempData->AttributesData >> pParserTempData->IndirectIOTablePointer[2]) ++ & (0xFFFFFFFF >> (32-pParserTempData->IndirectIOTablePointer[1]))) << pParserTempData->IndirectIOTablePointer[3]); ++} ++ ++VOID IndirectIOCommand_MOVE_DATA(PARSER_TEMP_DATA STACK_BASED * pParserTempData) ++{ ++ pParserTempData->IndirectData &= ~((0xFFFFFFFF >> (32-pParserTempData->IndirectIOTablePointer[1])) << pParserTempData->IndirectIOTablePointer[3]); ++ pParserTempData->IndirectData |=(((pParserTempData->DestData32 >> pParserTempData->IndirectIOTablePointer[2]) ++ & (0xFFFFFFFF >> (32-pParserTempData->IndirectIOTablePointer[1]))) << pParserTempData->IndirectIOTablePointer[3]); ++} ++ ++ ++VOID IndirectIOCommand_SET(PARSER_TEMP_DATA STACK_BASED * pParserTempData) ++{ ++ pParserTempData->IndirectData |= ((0xFFFFFFFF >> (32-pParserTempData->IndirectIOTablePointer[1])) << pParserTempData->IndirectIOTablePointer[2]); ++} ++ ++VOID IndirectIOCommand_CLEAR(PARSER_TEMP_DATA STACK_BASED * pParserTempData) ++{ ++ pParserTempData->IndirectData &= ~((0xFFFFFFFF >> (32-pParserTempData->IndirectIOTablePointer[1])) << pParserTempData->IndirectIOTablePointer[2]); ++} ++ ++ ++UINT32 IndirectInputOutput(PARSER_TEMP_DATA STACK_BASED * pParserTempData) ++{ ++ // if ((pParserTempData->IndirectData & 0x7f)==INDIRECT_IO_MM) pParserTempData->IndirectData|=pParserTempData->CurrentPortID; ++// pParserTempData->IndirectIOTablePointer=pParserTempData->IndirectIOTable; ++ while (*pParserTempData->IndirectIOTablePointer) ++ { ++ if ((pParserTempData->IndirectIOTablePointer[0] == INDIRECTIO_ID) && ++ (pParserTempData->IndirectIOTablePointer[1] == pParserTempData->IndirectData)) ++ { ++ pParserTempData->IndirectIOTablePointer+=IndirectIOParserCommands[*pParserTempData->IndirectIOTablePointer].csize; ++ while (*pParserTempData->IndirectIOTablePointer != INDIRECTIO_END_OF_ID) ++ { ++ IndirectIOParserCommands[*pParserTempData->IndirectIOTablePointer].func(pParserTempData); ++ pParserTempData->IndirectIOTablePointer+=IndirectIOParserCommands[*pParserTempData->IndirectIOTablePointer].csize; ++ } ++ pParserTempData->IndirectIOTablePointer-=*(UINT16*)(pParserTempData->IndirectIOTablePointer+1); ++ pParserTempData->IndirectIOTablePointer++; ++ return pParserTempData->IndirectData; ++ } else pParserTempData->IndirectIOTablePointer+=IndirectIOParserCommands[*pParserTempData->IndirectIOTablePointer].csize; ++ } ++ return 0; ++} ++ ++ ++ ++VOID PutDataRegister(PARSER_TEMP_DATA STACK_BASED * pParserTempData) ++{ ++ pParserTempData->Index=(UINT32)pParserTempData->pCmd->Parameters.WordXX.PA_Destination; ++ pParserTempData->Index+=pParserTempData->CurrentRegBlock; ++ switch(pParserTempData->Multipurpose.CurrentPort){ ++ case ATI_RegsPort: ++ if (pParserTempData->CurrentPortID == INDIRECT_IO_MM) ++ { ++ if (pParserTempData->Index==0) pParserTempData->DestData32 <<= 2; ++ WriteReg32( pParserTempData); ++ } else ++ { ++ pParserTempData->IndirectData=pParserTempData->CurrentPortID+INDIRECT_IO_WRITE; ++ IndirectInputOutput(pParserTempData); ++ } ++ break; ++ case PCI_Port: ++ WritePCIFunctions[pParserTempData->pCmd->Header.Attribute.SourceAlignment](pParserTempData); ++ break; ++ case SystemIO_Port: ++ WriteIOFunctions[pParserTempData->pCmd->Header.Attribute.SourceAlignment](pParserTempData); ++ break; ++ } ++} ++ ++VOID PutDataPS(PARSER_TEMP_DATA STACK_BASED * pParserTempData) ++{ ++ *(pParserTempData->pDeviceData->pParameterSpace+pParserTempData->pCmd->Parameters.ByteXX.PA_Destination)= ++ pParserTempData->DestData32; ++} ++ ++VOID PutDataWS(PARSER_TEMP_DATA STACK_BASED * pParserTempData) ++{ ++ if (pParserTempData->pCmd->Parameters.ByteXX.PA_Destination < WS_QUOTIENT_C) ++ *(pParserTempData->pWorkingTableData->pWorkSpace+pParserTempData->pCmd->Parameters.ByteXX.PA_Destination) = pParserTempData->DestData32; ++ else ++ switch (pParserTempData->pCmd->Parameters.ByteXX.PA_Destination) ++ { ++ case WS_REMINDER_C: ++ pParserTempData->MultiplicationOrDivision.Division.Reminder32=pParserTempData->DestData32; ++ break; ++ case WS_QUOTIENT_C: ++ pParserTempData->MultiplicationOrDivision.Division.Quotient32=pParserTempData->DestData32; ++ break; ++ case WS_DATAPTR_C: ++#ifndef UEFI_BUILD ++ pParserTempData->CurrentDataBlock=(UINT16)pParserTempData->DestData32; ++#else ++ pParserTempData->CurrentDataBlock=(UINTN)pParserTempData->DestData32; ++#endif ++ break; ++ case WS_SHIFT_C: ++ pParserTempData->Shift2MaskConverter=(UINT8)pParserTempData->DestData32; ++ break; ++ case WS_FB_WINDOW_C: ++ pParserTempData->CurrentFB_Window=pParserTempData->DestData32; ++ break; ++ case WS_ATTRIBUTES_C: ++ pParserTempData->AttributesData=(UINT16)pParserTempData->DestData32; ++ break; ++ } ++ ++} ++ ++VOID PutDataFB(PARSER_TEMP_DATA STACK_BASED * pParserTempData) ++{ ++ pParserTempData->Index=(UINT32)pParserTempData->pCmd->Parameters.ByteXX.PA_Destination; ++ //Make an Index from address first, then add to the Index ++ pParserTempData->Index+=(pParserTempData->CurrentFB_Window>>2); ++ WriteFrameBuffer32(pParserTempData); ++} ++ ++VOID PutDataPLL(PARSER_TEMP_DATA STACK_BASED * pParserTempData) ++{ ++ pParserTempData->Index=(UINT32)pParserTempData->pCmd->Parameters.ByteXX.PA_Destination; ++ WritePLL32( pParserTempData ); ++} ++ ++VOID PutDataMC(PARSER_TEMP_DATA STACK_BASED * pParserTempData) ++{ ++ pParserTempData->Index=(UINT32)pParserTempData->pCmd->Parameters.ByteXX.PA_Destination; ++ WriteMC32( pParserTempData ); ++} ++ ++ ++VOID SkipParameters8(PARSER_TEMP_DATA STACK_BASED * pParserTempData) ++{ ++ pParserTempData->pWorkingTableData->IP+=sizeof(UINT8); ++} ++ ++VOID SkipParameters16(PARSER_TEMP_DATA STACK_BASED * pParserTempData) ++{ ++ pParserTempData->pWorkingTableData->IP+=sizeof(UINT16); ++} ++ ++ ++UINT32 GetParametersRegister(PARSER_TEMP_DATA STACK_BASED * pParserTempData) ++{ ++ pParserTempData->Index=*(UINT16*)pParserTempData->pWorkingTableData->IP; ++ pParserTempData->pWorkingTableData->IP+=sizeof(UINT16); ++ pParserTempData->Index+=pParserTempData->CurrentRegBlock; ++ switch(pParserTempData->Multipurpose.CurrentPort) ++ { ++ case PCI_Port: ++ return ReadPCIFunctions[pParserTempData->pCmd->Header.Attribute.SourceAlignment](pParserTempData); ++ case SystemIO_Port: ++ return ReadIOFunctions[pParserTempData->pCmd->Header.Attribute.SourceAlignment](pParserTempData); ++ case ATI_RegsPort: ++ default: ++ if (pParserTempData->CurrentPortID == INDIRECT_IO_MM) return ReadReg32( pParserTempData ); ++ else ++ { ++ pParserTempData->IndirectData=pParserTempData->CurrentPortID+INDIRECT_IO_READ; ++ return IndirectInputOutput(pParserTempData); ++ } ++ } ++} ++ ++UINT32 GetParametersPS(PARSER_TEMP_DATA STACK_BASED * pParserTempData) ++{ ++ pParserTempData->Index=*pParserTempData->pWorkingTableData->IP; ++ pParserTempData->pWorkingTableData->IP+=sizeof(UINT8); ++ return *(pParserTempData->pDeviceData->pParameterSpace+pParserTempData->Index); ++} ++ ++UINT32 GetParametersWS(PARSER_TEMP_DATA STACK_BASED * pParserTempData) ++{ ++ pParserTempData->Index=*pParserTempData->pWorkingTableData->IP; ++ pParserTempData->pWorkingTableData->IP+=sizeof(UINT8); ++ if (pParserTempData->Index < WS_QUOTIENT_C) ++ return *(pParserTempData->pWorkingTableData->pWorkSpace+pParserTempData->Index); ++ else ++ switch (pParserTempData->Index) ++ { ++ case WS_REMINDER_C: ++ return pParserTempData->MultiplicationOrDivision.Division.Reminder32; ++ case WS_QUOTIENT_C: ++ return pParserTempData->MultiplicationOrDivision.Division.Quotient32; ++ case WS_DATAPTR_C: ++ return (UINT32)pParserTempData->CurrentDataBlock; ++ case WS_OR_MASK_C: ++ return ((UINT32)1) << pParserTempData->Shift2MaskConverter; ++ case WS_AND_MASK_C: ++ return ~(((UINT32)1) << pParserTempData->Shift2MaskConverter); ++ case WS_FB_WINDOW_C: ++ return pParserTempData->CurrentFB_Window; ++ case WS_ATTRIBUTES_C: ++ return pParserTempData->AttributesData; ++ } ++ return 0; ++ ++} ++ ++UINT32 GetParametersFB(PARSER_TEMP_DATA STACK_BASED * pParserTempData) ++{ ++ pParserTempData->Index=*pParserTempData->pWorkingTableData->IP; ++ pParserTempData->pWorkingTableData->IP+=sizeof(UINT8); ++ pParserTempData->Index+=(pParserTempData->CurrentFB_Window>>2); ++ return ReadFrameBuffer32(pParserTempData); ++} ++ ++UINT32 GetParametersPLL(PARSER_TEMP_DATA STACK_BASED * pParserTempData) ++{ ++ pParserTempData->Index=*pParserTempData->pWorkingTableData->IP; ++ pParserTempData->pWorkingTableData->IP+=sizeof(UINT8); ++ return ReadPLL32( pParserTempData ); ++} ++ ++UINT32 GetParametersMC(PARSER_TEMP_DATA STACK_BASED * pParserTempData) ++{ ++ pParserTempData->Index=*pParserTempData->pWorkingTableData->IP; ++ pParserTempData->pWorkingTableData->IP+=sizeof(UINT8); ++ return ReadMC32( pParserTempData ); ++} ++ ++ ++UINT32 GetParametersIndirect(PARSER_TEMP_DATA STACK_BASED * pParserTempData) ++{ ++ pParserTempData->Index=*(UINT16*)pParserTempData->pWorkingTableData->IP; ++ pParserTempData->pWorkingTableData->IP+=sizeof(UINT16); ++ return *(UINT32*)(RELATIVE_TO_BIOS_IMAGE(pParserTempData->Index)+pParserTempData->CurrentDataBlock); ++} ++ ++UINT32 GetParametersDirect8(PARSER_TEMP_DATA STACK_BASED * pParserTempData) ++{ ++ pParserTempData->CD_Mask.SrcAlignment=alignmentByte0; ++ pParserTempData->Index=*(UINT8*)pParserTempData->pWorkingTableData->IP; ++ pParserTempData->pWorkingTableData->IP+=sizeof(UINT8); ++ return pParserTempData->Index; ++} ++ ++UINT32 GetParametersDirect16(PARSER_TEMP_DATA STACK_BASED * pParserTempData) ++{ ++ pParserTempData->CD_Mask.SrcAlignment=alignmentLowerWord; ++ pParserTempData->Index=*(UINT16*)pParserTempData->pWorkingTableData->IP; ++ pParserTempData->pWorkingTableData->IP+=sizeof(UINT16); ++ return pParserTempData->Index; ++} ++ ++UINT32 GetParametersDirect32(PARSER_TEMP_DATA STACK_BASED * pParserTempData) ++{ ++ pParserTempData->CD_Mask.SrcAlignment=alignmentDword; ++ pParserTempData->Index=*(UINT32*)pParserTempData->pWorkingTableData->IP; ++ pParserTempData->pWorkingTableData->IP+=sizeof(UINT32); ++ return pParserTempData->Index; ++} ++ ++ ++UINT32 GetParametersDirect(PARSER_TEMP_DATA STACK_BASED * pParserTempData) ++{ ++ return GetParametersDirectArray[pParserTempData->pCmd->Header.Attribute.SourceAlignment](pParserTempData); ++} ++ ++ ++VOID CommonSourceDataTransformation(PARSER_TEMP_DATA STACK_BASED * pParserTempData) ++{ ++ pParserTempData->SourceData32 >>= SourceAlignmentShift[pParserTempData->CD_Mask.SrcAlignment]; ++ pParserTempData->SourceData32 &= AlignmentMask[pParserTempData->CD_Mask.SrcAlignment]; ++ pParserTempData->SourceData32 <<= DestinationAlignmentShift[pParserTempData->CD_Mask.DestAlignment]; ++} ++ ++VOID CommonOperationDataTransformation(PARSER_TEMP_DATA STACK_BASED * pParserTempData) ++{ ++ pParserTempData->SourceData32 >>= SourceAlignmentShift[pParserTempData->CD_Mask.SrcAlignment]; ++ pParserTempData->SourceData32 &= AlignmentMask[pParserTempData->CD_Mask.SrcAlignment]; ++ pParserTempData->DestData32 >>= DestinationAlignmentShift[pParserTempData->CD_Mask.DestAlignment]; ++ pParserTempData->DestData32 &= AlignmentMask[pParserTempData->CD_Mask.SrcAlignment]; ++} ++ ++VOID ProcessMove(PARSER_TEMP_DATA STACK_BASED * pParserTempData) ++{ ++ if (pParserTempData->CD_Mask.SrcAlignment!=alignmentDword) ++ { ++ pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData); ++ } else ++ { ++ SkipDestination[pParserTempData->ParametersType.Destination](pParserTempData); ++ } ++ pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData); ++ ++ if (pParserTempData->CD_Mask.SrcAlignment!=alignmentDword) ++ { ++ pParserTempData->DestData32 &= ~(AlignmentMask[pParserTempData->CD_Mask.SrcAlignment] << DestinationAlignmentShift[pParserTempData->CD_Mask.DestAlignment]); ++ CommonSourceDataTransformation(pParserTempData); ++ pParserTempData->DestData32 |= pParserTempData->SourceData32; ++ } else ++ { ++ pParserTempData->DestData32=pParserTempData->SourceData32; ++ } ++ PutDataFunctions[pParserTempData->ParametersType.Destination](pParserTempData); ++} ++ ++VOID ProcessMask(PARSER_TEMP_DATA STACK_BASED * pParserTempData) ++{ ++ ++ pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData); ++ pParserTempData->SourceData32=GetParametersDirect(pParserTempData); ++ pParserTempData->Index=GetParametersDirect(pParserTempData); ++ pParserTempData->SourceData32 <<= DestinationAlignmentShift[pParserTempData->CD_Mask.DestAlignment]; ++ pParserTempData->SourceData32 |= ~(AlignmentMask[pParserTempData->CD_Mask.SrcAlignment] << DestinationAlignmentShift[pParserTempData->CD_Mask.DestAlignment]); ++ pParserTempData->DestData32 &= pParserTempData->SourceData32; ++ pParserTempData->Index &= AlignmentMask[pParserTempData->CD_Mask.SrcAlignment]; ++ pParserTempData->Index <<= DestinationAlignmentShift[pParserTempData->CD_Mask.DestAlignment]; ++ pParserTempData->DestData32 |= pParserTempData->Index; ++ PutDataFunctions[pParserTempData->ParametersType.Destination](pParserTempData); ++} ++ ++VOID ProcessAnd(PARSER_TEMP_DATA STACK_BASED * pParserTempData) ++{ ++ pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData); ++ pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData); ++ pParserTempData->SourceData32 >>= SourceAlignmentShift[pParserTempData->CD_Mask.SrcAlignment]; ++ pParserTempData->SourceData32 <<= DestinationAlignmentShift[pParserTempData->CD_Mask.DestAlignment]; ++ pParserTempData->SourceData32 |= ~(AlignmentMask[pParserTempData->CD_Mask.SrcAlignment] << DestinationAlignmentShift[pParserTempData->CD_Mask.DestAlignment]); ++ pParserTempData->DestData32 &= pParserTempData->SourceData32; ++ PutDataFunctions[pParserTempData->ParametersType.Destination](pParserTempData); ++} ++ ++VOID ProcessOr(PARSER_TEMP_DATA STACK_BASED * pParserTempData) ++{ ++ pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData); ++ pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData); ++ CommonSourceDataTransformation(pParserTempData); ++ pParserTempData->DestData32 |= pParserTempData->SourceData32; ++ PutDataFunctions[pParserTempData->ParametersType.Destination](pParserTempData); ++} ++ ++VOID ProcessXor(PARSER_TEMP_DATA STACK_BASED * pParserTempData) ++{ ++ pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData); ++ pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData); ++ CommonSourceDataTransformation(pParserTempData); ++ pParserTempData->DestData32 ^= pParserTempData->SourceData32; ++ PutDataFunctions[pParserTempData->ParametersType.Destination](pParserTempData); ++} ++ ++VOID ProcessShl(PARSER_TEMP_DATA STACK_BASED * pParserTempData) ++{ ++ pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData); ++ pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData); ++ CommonSourceDataTransformation(pParserTempData); ++ pParserTempData->DestData32 <<= pParserTempData->SourceData32; ++ PutDataFunctions[pParserTempData->ParametersType.Destination](pParserTempData); ++} ++ ++VOID ProcessShr(PARSER_TEMP_DATA STACK_BASED * pParserTempData) ++{ ++ pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData); ++ pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData); ++ CommonSourceDataTransformation(pParserTempData); ++ pParserTempData->DestData32 >>= pParserTempData->SourceData32; ++ PutDataFunctions[pParserTempData->ParametersType.Destination](pParserTempData); ++} ++ ++ ++VOID ProcessADD(PARSER_TEMP_DATA STACK_BASED * pParserTempData) ++{ ++ pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData); ++ pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData); ++ CommonSourceDataTransformation(pParserTempData); ++ pParserTempData->DestData32 += pParserTempData->SourceData32; ++ PutDataFunctions[pParserTempData->ParametersType.Destination](pParserTempData); ++} ++ ++VOID ProcessSUB(PARSER_TEMP_DATA STACK_BASED * pParserTempData) ++{ ++ pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData); ++ pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData); ++ CommonSourceDataTransformation(pParserTempData); ++ pParserTempData->DestData32 -= pParserTempData->SourceData32; ++ PutDataFunctions[pParserTempData->ParametersType.Destination](pParserTempData); ++} ++ ++VOID ProcessMUL(PARSER_TEMP_DATA STACK_BASED * pParserTempData) ++{ ++ pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData); ++ pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData); ++ CommonOperationDataTransformation(pParserTempData); ++ pParserTempData->MultiplicationOrDivision.Multiplication.Low32Bit=pParserTempData->DestData32 * pParserTempData->SourceData32; ++} ++ ++VOID ProcessDIV(PARSER_TEMP_DATA STACK_BASED * pParserTempData) ++{ ++ pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData); ++ pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData); ++ ++ CommonOperationDataTransformation(pParserTempData); ++ pParserTempData->MultiplicationOrDivision.Division.Quotient32= ++ pParserTempData->DestData32 / pParserTempData->SourceData32; ++ pParserTempData->MultiplicationOrDivision.Division.Reminder32= ++ pParserTempData->DestData32 % pParserTempData->SourceData32; ++} ++ ++ ++VOID ProcessCompare(PARSER_TEMP_DATA STACK_BASED * pParserTempData) ++{ ++ pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData); ++ pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData); ++ ++ CommonOperationDataTransformation(pParserTempData); ++ ++ // Here we just set flags based on evaluation ++ if (pParserTempData->DestData32==pParserTempData->SourceData32) ++ pParserTempData->CompareFlags = Equal; ++ else ++ pParserTempData->CompareFlags = ++ (UINT8)((pParserTempData->DestData32SourceData32) ? Below : Above); ++ ++} ++ ++VOID ProcessClear(PARSER_TEMP_DATA STACK_BASED * pParserTempData) ++{ ++ pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData); ++ pParserTempData->DestData32 &= ~(AlignmentMask[pParserTempData->CD_Mask.SrcAlignment] << SourceAlignmentShift[pParserTempData->CD_Mask.SrcAlignment]); ++ PutDataFunctions[pParserTempData->ParametersType.Destination](pParserTempData); ++ ++} ++ ++VOID ProcessShift(PARSER_TEMP_DATA STACK_BASED * pParserTempData) ++{ ++ UINT32 mask = AlignmentMask[pParserTempData->CD_Mask.SrcAlignment] << SourceAlignmentShift[pParserTempData->CD_Mask.SrcAlignment]; ++ pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData); ++ pParserTempData->SourceData32=GetParametersDirect8(pParserTempData); ++ ++ // save original value of the destination ++ pParserTempData->Index = pParserTempData->DestData32 & ~mask; ++ pParserTempData->DestData32 &= mask; ++ ++ if (pParserTempData->pCmd->Header.Opcode < SHIFT_RIGHT_REG_OPCODE) ++ pParserTempData->DestData32 <<= pParserTempData->SourceData32; else ++ pParserTempData->DestData32 >>= pParserTempData->SourceData32; ++ ++ // Clear any bits shifted out of masked area... ++ pParserTempData->DestData32 &= mask; ++ // ... and restore the area outside of masked with original values ++ pParserTempData->DestData32 |= pParserTempData->Index; ++ ++ // write data back ++ PutDataFunctions[pParserTempData->ParametersType.Destination](pParserTempData); ++} ++ ++VOID ProcessTest(PARSER_TEMP_DATA STACK_BASED * pParserTempData) ++{ ++ pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData); ++ pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData); ++ CommonOperationDataTransformation(pParserTempData); ++ pParserTempData->CompareFlags = ++ (UINT8)((pParserTempData->DestData32 & pParserTempData->SourceData32) ? NotEqual : Equal); ++ ++} ++ ++VOID ProcessSetFB_Base(PARSER_TEMP_DATA STACK_BASED * pParserTempData) ++{ ++ pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData); ++ pParserTempData->SourceData32 >>= SourceAlignmentShift[pParserTempData->CD_Mask.SrcAlignment]; ++ pParserTempData->SourceData32 &= AlignmentMask[pParserTempData->CD_Mask.SrcAlignment]; ++ pParserTempData->CurrentFB_Window=pParserTempData->SourceData32; ++} ++ ++VOID ProcessSwitch(PARSER_TEMP_DATA STACK_BASED * pParserTempData){ ++ pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData); ++ pParserTempData->SourceData32 >>= SourceAlignmentShift[pParserTempData->CD_Mask.SrcAlignment]; ++ pParserTempData->SourceData32 &= AlignmentMask[pParserTempData->CD_Mask.SrcAlignment]; ++ while ( *(UINT16*)pParserTempData->pWorkingTableData->IP != (((UINT16)NOP_OPCODE << 8)+NOP_OPCODE)) ++ { ++ if (*pParserTempData->pWorkingTableData->IP == 'c') ++ { ++ pParserTempData->pWorkingTableData->IP++; ++ pParserTempData->DestData32=GetParametersDirect(pParserTempData); ++ pParserTempData->Index=GetParametersDirect16(pParserTempData); ++ if (pParserTempData->SourceData32 == pParserTempData->DestData32) ++ { ++ pParserTempData->pWorkingTableData->IP= RELATIVE_TO_TABLE(pParserTempData->Index); ++ return; ++ } ++ } ++ } ++ pParserTempData->pWorkingTableData->IP+=sizeof(UINT16); ++} ++ ++ ++VOID cmdSetDataBlock(PARSER_TEMP_DATA STACK_BASED * pParserTempData) ++{ ++ UINT8 value; ++ UINT16* pMasterDataTable; ++ value=((COMMAND_TYPE_1*)pParserTempData->pWorkingTableData->IP)->Parameters.ByteXX.PA_Destination; ++ if (value == 0) pParserTempData->CurrentDataBlock=0; else ++ { ++ if (value == DB_CURRENT_COMMAND_TABLE) ++ { ++ pParserTempData->CurrentDataBlock= (UINT16)(pParserTempData->pWorkingTableData->pTableHead-pParserTempData->pDeviceData->pBIOS_Image); ++ } else ++ { ++ pMasterDataTable = GetDataMasterTablePointer(pParserTempData->pDeviceData); ++ pParserTempData->CurrentDataBlock= (TABLE_UNIT_TYPE)((PTABLE_UNIT_TYPE)pMasterDataTable)[value]; ++ } ++ } ++ pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_VALUE_BYTE); ++} ++ ++VOID cmdSet_ATI_Port(PARSER_TEMP_DATA STACK_BASED * pParserTempData) ++{ ++ pParserTempData->Multipurpose.CurrentPort=ATI_RegsPort; ++ pParserTempData->CurrentPortID = (UINT8)((COMMAND_TYPE_1*)pParserTempData->pWorkingTableData->IP)->Parameters.WordXX.PA_Destination; ++ pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_OFFSET16); ++} ++ ++VOID cmdSet_Reg_Block(PARSER_TEMP_DATA STACK_BASED * pParserTempData) ++{ ++ pParserTempData->CurrentRegBlock = ((COMMAND_TYPE_1*)pParserTempData->pWorkingTableData->IP)->Parameters.WordXX.PA_Destination; ++ pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_OFFSET16); ++} ++ ++ ++//Atavism!!! Review!!! ++VOID cmdSet_X_Port(PARSER_TEMP_DATA STACK_BASED * pParserTempData){ ++ pParserTempData->Multipurpose.CurrentPort=pParserTempData->ParametersType.Destination; ++ pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_ONLY); ++ ++} ++ ++VOID cmdDelay_Millisec(PARSER_TEMP_DATA STACK_BASED * pParserTempData){ ++ pParserTempData->SourceData32 = ++ ((COMMAND_TYPE_1*)pParserTempData->pWorkingTableData->IP)->Parameters.ByteXX.PA_Destination; ++ DelayMilliseconds(pParserTempData); ++ pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_VALUE_BYTE); ++} ++VOID cmdDelay_Microsec(PARSER_TEMP_DATA STACK_BASED * pParserTempData){ ++ pParserTempData->SourceData32 = ++ ((COMMAND_TYPE_1*)pParserTempData->pWorkingTableData->IP)->Parameters.ByteXX.PA_Destination; ++ DelayMicroseconds(pParserTempData); ++ pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_VALUE_BYTE); ++} ++ ++VOID ProcessPostChar(PARSER_TEMP_DATA STACK_BASED * pParserTempData) ++{ ++ pParserTempData->SourceData32 = ++ ((COMMAND_TYPE_1*)pParserTempData->pWorkingTableData->IP)->Parameters.ByteXX.PA_Destination; ++ PostCharOutput(pParserTempData); ++ pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_VALUE_BYTE); ++} ++ ++VOID ProcessDebug(PARSER_TEMP_DATA STACK_BASED * pParserTempData) ++{ ++ pParserTempData->SourceData32 = ++ ((COMMAND_TYPE_1*)pParserTempData->pWorkingTableData->IP)->Parameters.ByteXX.PA_Destination; ++ CallerDebugFunc(pParserTempData); ++ pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_VALUE_BYTE); ++} ++ ++ ++VOID ProcessDS(PARSER_TEMP_DATA STACK_BASED * pParserTempData) ++{ ++ pParserTempData->pWorkingTableData->IP+=((COMMAND_TYPE_1*)pParserTempData->pWorkingTableData->IP)->Parameters.WordXX.PA_Destination+sizeof(COMMAND_TYPE_OPCODE_OFFSET16); ++} ++ ++ ++VOID cmdCall_Table(PARSER_TEMP_DATA STACK_BASED * pParserTempData){ ++ UINT16* MasterTableOffset; ++ pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_VALUE_BYTE); ++ MasterTableOffset = GetCommandMasterTablePointer(pParserTempData->pDeviceData); ++ if(((PTABLE_UNIT_TYPE)MasterTableOffset)[((COMMAND_TYPE_OPCODE_VALUE_BYTE*)pParserTempData->pCmd)->Value]!=0 ) // if the offset is not ZERO ++ { ++ pParserTempData->CommandSpecific.IndexInMasterTable=GetTrueIndexInMasterTable(pParserTempData,((COMMAND_TYPE_OPCODE_VALUE_BYTE*)pParserTempData->pCmd)->Value); ++ pParserTempData->Multipurpose.PS_SizeInDwordsUsedByCallingTable = ++ (((ATOM_COMMON_ROM_COMMAND_TABLE_HEADER *)pParserTempData->pWorkingTableData->pTableHead)->TableAttribute.PS_SizeInBytes>>2); ++ pParserTempData->pDeviceData->pParameterSpace+= ++ pParserTempData->Multipurpose.PS_SizeInDwordsUsedByCallingTable; ++ pParserTempData->Status=CD_CALL_TABLE; ++ pParserTempData->pCmd=(GENERIC_ATTRIBUTE_COMMAND*)MasterTableOffset; ++ } ++} ++ ++ ++VOID cmdNOP_(PARSER_TEMP_DATA STACK_BASED * pParserTempData) ++{ ++} ++ ++ ++static VOID NotImplemented(PARSER_TEMP_DATA STACK_BASED * pParserTempData) ++{ ++ pParserTempData->Status = CD_NOT_IMPLEMENTED; ++} ++ ++ ++VOID ProcessJump(PARSER_TEMP_DATA STACK_BASED * pParserTempData) ++{ ++ if ((pParserTempData->ParametersType.Destination == NoCondition) || ++ (pParserTempData->ParametersType.Destination == pParserTempData->CompareFlags )) ++ { ++ ++ pParserTempData->pWorkingTableData->IP= RELATIVE_TO_TABLE(((COMMAND_TYPE_OPCODE_OFFSET16*)pParserTempData->pWorkingTableData->IP)->CD_Offset16); ++ } else ++ { ++ pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_OFFSET16); ++ } ++} ++ ++VOID ProcessJumpE(PARSER_TEMP_DATA STACK_BASED * pParserTempData) ++{ ++ if ((pParserTempData->CompareFlags == Equal) || ++ (pParserTempData->CompareFlags == pParserTempData->ParametersType.Destination)) ++ { ++ ++ pParserTempData->pWorkingTableData->IP= RELATIVE_TO_TABLE(((COMMAND_TYPE_OPCODE_OFFSET16*)pParserTempData->pWorkingTableData->IP)->CD_Offset16); ++ } else ++ { ++ pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_OFFSET16); ++ } ++} ++ ++VOID ProcessJumpNE(PARSER_TEMP_DATA STACK_BASED * pParserTempData) ++{ ++ if (pParserTempData->CompareFlags != Equal) ++ { ++ ++ pParserTempData->pWorkingTableData->IP= RELATIVE_TO_TABLE(((COMMAND_TYPE_OPCODE_OFFSET16*)pParserTempData->pWorkingTableData->IP)->CD_Offset16); ++ } else ++ { ++ pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_OFFSET16); ++ } ++} ++ ++ ++ ++COMMANDS_PROPERTIES CallTable[] = ++{ ++ { NULL, 0,0}, ++ { ProcessMove, destRegister, sizeof(COMMAND_HEADER)}, ++ { ProcessMove, destParamSpace, sizeof(COMMAND_HEADER)}, ++ { ProcessMove, destWorkSpace, sizeof(COMMAND_HEADER)}, ++ { ProcessMove, destFrameBuffer, sizeof(COMMAND_HEADER)}, ++ { ProcessMove, destPLL, sizeof(COMMAND_HEADER)}, ++ { ProcessMove, destMC, sizeof(COMMAND_HEADER)}, ++ { ProcessAnd, destRegister, sizeof(COMMAND_HEADER)}, ++ { ProcessAnd, destParamSpace, sizeof(COMMAND_HEADER)}, ++ { ProcessAnd, destWorkSpace, sizeof(COMMAND_HEADER)}, ++ { ProcessAnd, destFrameBuffer, sizeof(COMMAND_HEADER)}, ++ { ProcessAnd, destPLL, sizeof(COMMAND_HEADER)}, ++ { ProcessAnd, destMC, sizeof(COMMAND_HEADER)}, ++ { ProcessOr, destRegister, sizeof(COMMAND_HEADER)}, ++ { ProcessOr, destParamSpace, sizeof(COMMAND_HEADER)}, ++ { ProcessOr, destWorkSpace, sizeof(COMMAND_HEADER)}, ++ { ProcessOr, destFrameBuffer, sizeof(COMMAND_HEADER)}, ++ { ProcessOr, destPLL, sizeof(COMMAND_HEADER)}, ++ { ProcessOr, destMC, sizeof(COMMAND_HEADER)}, ++ { ProcessShift, destRegister, sizeof(COMMAND_HEADER)}, ++ { ProcessShift, destParamSpace, sizeof(COMMAND_HEADER)}, ++ { ProcessShift, destWorkSpace, sizeof(COMMAND_HEADER)}, ++ { ProcessShift, destFrameBuffer, sizeof(COMMAND_HEADER)}, ++ { ProcessShift, destPLL, sizeof(COMMAND_HEADER)}, ++ { ProcessShift, destMC, sizeof(COMMAND_HEADER)}, ++ { ProcessShift, destRegister, sizeof(COMMAND_HEADER)}, ++ { ProcessShift, destParamSpace, sizeof(COMMAND_HEADER)}, ++ { ProcessShift, destWorkSpace, sizeof(COMMAND_HEADER)}, ++ { ProcessShift, destFrameBuffer, sizeof(COMMAND_HEADER)}, ++ { ProcessShift, destPLL, sizeof(COMMAND_HEADER)}, ++ { ProcessShift, destMC, sizeof(COMMAND_HEADER)}, ++ { ProcessMUL, destRegister, sizeof(COMMAND_HEADER)}, ++ { ProcessMUL, destParamSpace, sizeof(COMMAND_HEADER)}, ++ { ProcessMUL, destWorkSpace, sizeof(COMMAND_HEADER)}, ++ { ProcessMUL, destFrameBuffer, sizeof(COMMAND_HEADER)}, ++ { ProcessMUL, destPLL, sizeof(COMMAND_HEADER)}, ++ { ProcessMUL, destMC, sizeof(COMMAND_HEADER)}, ++ { ProcessDIV, destRegister, sizeof(COMMAND_HEADER)}, ++ { ProcessDIV, destParamSpace, sizeof(COMMAND_HEADER)}, ++ { ProcessDIV, destWorkSpace, sizeof(COMMAND_HEADER)}, ++ { ProcessDIV, destFrameBuffer, sizeof(COMMAND_HEADER)}, ++ { ProcessDIV, destPLL, sizeof(COMMAND_HEADER)}, ++ { ProcessDIV, destMC, sizeof(COMMAND_HEADER)}, ++ { ProcessADD, destRegister, sizeof(COMMAND_HEADER)}, ++ { ProcessADD, destParamSpace, sizeof(COMMAND_HEADER)}, ++ { ProcessADD, destWorkSpace, sizeof(COMMAND_HEADER)}, ++ { ProcessADD, destFrameBuffer, sizeof(COMMAND_HEADER)}, ++ { ProcessADD, destPLL, sizeof(COMMAND_HEADER)}, ++ { ProcessADD, destMC, sizeof(COMMAND_HEADER)}, ++ { ProcessSUB, destRegister, sizeof(COMMAND_HEADER)}, ++ { ProcessSUB, destParamSpace, sizeof(COMMAND_HEADER)}, ++ { ProcessSUB, destWorkSpace, sizeof(COMMAND_HEADER)}, ++ { ProcessSUB, destFrameBuffer, sizeof(COMMAND_HEADER)}, ++ { ProcessSUB, destPLL, sizeof(COMMAND_HEADER)}, ++ { ProcessSUB, destMC, sizeof(COMMAND_HEADER)}, ++ { cmdSet_ATI_Port, ATI_RegsPort, 0}, ++ { cmdSet_X_Port, PCI_Port, 0}, ++ { cmdSet_X_Port, SystemIO_Port, 0}, ++ { cmdSet_Reg_Block, 0, 0}, ++ { ProcessSetFB_Base,0, sizeof(COMMAND_HEADER)}, ++ { ProcessCompare, destRegister, sizeof(COMMAND_HEADER)}, ++ { ProcessCompare, destParamSpace, sizeof(COMMAND_HEADER)}, ++ { ProcessCompare, destWorkSpace, sizeof(COMMAND_HEADER)}, ++ { ProcessCompare, destFrameBuffer, sizeof(COMMAND_HEADER)}, ++ { ProcessCompare, destPLL, sizeof(COMMAND_HEADER)}, ++ { ProcessCompare, destMC, sizeof(COMMAND_HEADER)}, ++ { ProcessSwitch, 0, sizeof(COMMAND_HEADER)}, ++ { ProcessJump, NoCondition, 0}, ++ { ProcessJump, Equal, 0}, ++ { ProcessJump, Below, 0}, ++ { ProcessJump, Above, 0}, ++ { ProcessJumpE, Below, 0}, ++ { ProcessJumpE, Above, 0}, ++ { ProcessJumpNE, 0, 0}, ++ { ProcessTest, destRegister, sizeof(COMMAND_HEADER)}, ++ { ProcessTest, destParamSpace, sizeof(COMMAND_HEADER)}, ++ { ProcessTest, destWorkSpace, sizeof(COMMAND_HEADER)}, ++ { ProcessTest, destFrameBuffer, sizeof(COMMAND_HEADER)}, ++ { ProcessTest, destPLL, sizeof(COMMAND_HEADER)}, ++ { ProcessTest, destMC, sizeof(COMMAND_HEADER)}, ++ { cmdDelay_Millisec,0, 0}, ++ { cmdDelay_Microsec,0, 0}, ++ { cmdCall_Table, 0, 0}, ++ /*cmdRepeat*/ { NotImplemented, 0, 0}, ++ { ProcessClear, destRegister, sizeof(COMMAND_HEADER)}, ++ { ProcessClear, destParamSpace, sizeof(COMMAND_HEADER)}, ++ { ProcessClear, destWorkSpace, sizeof(COMMAND_HEADER)}, ++ { ProcessClear, destFrameBuffer, sizeof(COMMAND_HEADER)}, ++ { ProcessClear, destPLL, sizeof(COMMAND_HEADER)}, ++ { ProcessClear, destMC, sizeof(COMMAND_HEADER)}, ++ { cmdNOP_, 0, sizeof(COMMAND_TYPE_OPCODE_ONLY)}, ++ /*cmdEOT*/ { cmdNOP_, 0, sizeof(COMMAND_TYPE_OPCODE_ONLY)}, ++ { ProcessMask, destRegister, sizeof(COMMAND_HEADER)}, ++ { ProcessMask, destParamSpace, sizeof(COMMAND_HEADER)}, ++ { ProcessMask, destWorkSpace, sizeof(COMMAND_HEADER)}, ++ { ProcessMask, destFrameBuffer, sizeof(COMMAND_HEADER)}, ++ { ProcessMask, destPLL, sizeof(COMMAND_HEADER)}, ++ { ProcessMask, destMC, sizeof(COMMAND_HEADER)}, ++ /*cmdPost_Card*/ { ProcessPostChar, 0, 0}, ++ /*cmdBeep*/ { NotImplemented, 0, 0}, ++ /*cmdSave_Reg*/ { NotImplemented, 0, 0}, ++ /*cmdRestore_Reg*/{ NotImplemented, 0, 0}, ++ { cmdSetDataBlock, 0, 0}, ++ { ProcessXor, destRegister, sizeof(COMMAND_HEADER)}, ++ { ProcessXor, destParamSpace, sizeof(COMMAND_HEADER)}, ++ { ProcessXor, destWorkSpace, sizeof(COMMAND_HEADER)}, ++ { ProcessXor, destFrameBuffer, sizeof(COMMAND_HEADER)}, ++ { ProcessXor, destPLL, sizeof(COMMAND_HEADER)}, ++ { ProcessXor, destMC, sizeof(COMMAND_HEADER)}, ++ ++ { ProcessShl, destRegister, sizeof(COMMAND_HEADER)}, ++ { ProcessShl, destParamSpace, sizeof(COMMAND_HEADER)}, ++ { ProcessShl, destWorkSpace, sizeof(COMMAND_HEADER)}, ++ { ProcessShl, destFrameBuffer, sizeof(COMMAND_HEADER)}, ++ { ProcessShl, destPLL, sizeof(COMMAND_HEADER)}, ++ { ProcessShl, destMC, sizeof(COMMAND_HEADER)}, ++ ++ { ProcessShr, destRegister, sizeof(COMMAND_HEADER)}, ++ { ProcessShr, destParamSpace, sizeof(COMMAND_HEADER)}, ++ { ProcessShr, destWorkSpace, sizeof(COMMAND_HEADER)}, ++ { ProcessShr, destFrameBuffer, sizeof(COMMAND_HEADER)}, ++ { ProcessShr, destPLL, sizeof(COMMAND_HEADER)}, ++ { ProcessShr, destMC, sizeof(COMMAND_HEADER)}, ++ /*cmdDebug*/ { ProcessDebug, 0, 0}, ++ { ProcessDS, 0, 0}, ++ ++}; ++ ++// EOF +diff --git a/src/AtomBios/Decoder.c b/src/AtomBios/Decoder.c +new file mode 100644 +index 0000000..95908d5 +--- /dev/null ++++ b/src/AtomBios/Decoder.c +@@ -0,0 +1,235 @@ ++/* ++ * Copyright 2006-2007 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in ++ * all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++/** ++ ++Module Name: ++ ++ Decoder.c ++ ++Abstract: ++ ++ Commands Decoder ++ ++Revision History: ++ ++ NEG:24.09.2002 Initiated. ++--*/ ++//#include "AtomBios.h" ++#include "Decoder.h" ++#include "atombios.h" ++#include "CD_binding.h" ++#include "CD_Common_Types.h" ++ ++#ifndef DISABLE_EASF ++ #include "easf.h" ++#endif ++ ++ ++ ++#define INDIRECT_IO_TABLE (((UINT16)&((ATOM_MASTER_LIST_OF_DATA_TABLES*)0)->IndirectIOAccess)/sizeof(TABLE_UNIT_TYPE) ) ++extern COMMANDS_PROPERTIES CallTable[]; ++ ++ ++UINT8 ProcessCommandProperties(PARSER_TEMP_DATA STACK_BASED * pParserTempData) ++{ ++ UINT8 opcode=((COMMAND_HEADER*)pParserTempData->pWorkingTableData->IP)->Opcode; ++ pParserTempData->pWorkingTableData->IP+=CallTable[opcode].headersize; ++ pParserTempData->ParametersType.Destination=CallTable[opcode].destination; ++ pParserTempData->ParametersType.Source = pParserTempData->pCmd->Header.Attribute.Source; ++ pParserTempData->CD_Mask.SrcAlignment=pParserTempData->pCmd->Header.Attribute.SourceAlignment; ++ pParserTempData->CD_Mask.DestAlignment=pParserTempData->pCmd->Header.Attribute.DestinationAlignment; ++ return opcode; ++} ++ ++UINT16* GetCommandMasterTablePointer(DEVICE_DATA STACK_BASED* pDeviceData) ++{ ++ UINT16 *MasterTableOffset; ++#ifndef DISABLE_EASF ++ if (pDeviceData->format == TABLE_FORMAT_EASF) ++ { ++ /* ++ make MasterTableOffset point to EASF_ASIC_SETUP_TABLE structure, including usSize. ++ */ ++ MasterTableOffset = (UINT16 *) (pDeviceData->pBIOS_Image+((EASF_ASIC_DESCRIPTOR*)pDeviceData->pBIOS_Image)->usAsicSetupTable_Offset); ++ } else ++#endif ++ { ++#ifndef UEFI_BUILD ++ MasterTableOffset = (UINT16 *)(*(UINT16 *)(pDeviceData->pBIOS_Image+OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER) + pDeviceData->pBIOS_Image); ++ MasterTableOffset = (UINT16 *)((ULONG)((ATOM_ROM_HEADER *)MasterTableOffset)->usMasterCommandTableOffset + pDeviceData->pBIOS_Image ); ++ MasterTableOffset =(UINT16 *) &(((ATOM_MASTER_COMMAND_TABLE *)MasterTableOffset)->ListOfCommandTables); ++#else ++ MasterTableOffset = (UINT16 *)(&(GetCommandMasterTable( )->ListOfCommandTables)); ++#endif ++ } ++ return MasterTableOffset; ++} ++ ++UINT16* GetDataMasterTablePointer(DEVICE_DATA STACK_BASED* pDeviceData) ++{ ++ UINT16 *MasterTableOffset; ++ ++#ifndef UEFI_BUILD ++ MasterTableOffset = (UINT16 *)(*(UINT16 *)(pDeviceData->pBIOS_Image+OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER) + pDeviceData->pBIOS_Image); ++ MasterTableOffset = (UINT16 *)((ULONG)((ATOM_ROM_HEADER *)MasterTableOffset)->usMasterDataTableOffset + pDeviceData->pBIOS_Image ); ++ MasterTableOffset =(UINT16 *) &(((ATOM_MASTER_DATA_TABLE *)MasterTableOffset)->ListOfDataTables); ++#else ++ MasterTableOffset = (UINT16 *)(&(GetDataMasterTable( )->ListOfDataTables)); ++#endif ++ return MasterTableOffset; ++} ++ ++ ++UINT8 GetTrueIndexInMasterTable(PARSER_TEMP_DATA STACK_BASED * pParserTempData, UINT8 IndexInMasterTable) ++{ ++#ifndef DISABLE_EASF ++ UINT16 i; ++ if ( pParserTempData->pDeviceData->format == TABLE_FORMAT_EASF) ++ { ++/* ++ Consider EASF_ASIC_SETUP_TABLE structure pointed by pParserTempData->pCmd as UINT16[] ++ ((UINT16*)pParserTempData->pCmd)[0] = EASF_ASIC_SETUP_TABLE.usSize; ++ ((UINT16*)pParserTempData->pCmd)[1+n*4] = usFunctionID; ++ usFunctionID has to be shifted left by 2 before compare it to the value provided by caller. ++*/ ++ for (i=1; (i < ((UINT16*)pParserTempData->pCmd)[0] >> 1);i+=4) ++ if ((UINT8)(((UINT16*)pParserTempData->pCmd)[i] << 2)==(IndexInMasterTable & EASF_TABLE_INDEX_MASK)) return (i+1+(IndexInMasterTable & EASF_TABLE_ATTR_MASK)); ++ return 1; ++ } else ++#endif ++ { ++ return IndexInMasterTable; ++ } ++} ++ ++CD_STATUS ParseTable(DEVICE_DATA STACK_BASED* pDeviceData, UINT8 IndexInMasterTable) ++{ ++ PARSER_TEMP_DATA ParserTempData; ++ WORKING_TABLE_DATA STACK_BASED* prevWorkingTableData; ++ ++ ParserTempData.pDeviceData=(DEVICE_DATA*)pDeviceData; ++#ifndef DISABLE_EASF ++ if (pDeviceData->format == TABLE_FORMAT_EASF) ++ { ++ ParserTempData.IndirectIOTablePointer = 0; ++ } else ++#endif ++ { ++ ParserTempData.pCmd=(GENERIC_ATTRIBUTE_COMMAND*)GetDataMasterTablePointer(pDeviceData); ++ ParserTempData.IndirectIOTablePointer=(UINT8*)((ULONG)(((PTABLE_UNIT_TYPE)ParserTempData.pCmd)[INDIRECT_IO_TABLE]) + pDeviceData->pBIOS_Image); ++ ParserTempData.IndirectIOTablePointer+=sizeof(ATOM_COMMON_TABLE_HEADER); ++ } ++ ++ ParserTempData.pCmd=(GENERIC_ATTRIBUTE_COMMAND*)GetCommandMasterTablePointer(pDeviceData); ++ IndexInMasterTable=GetTrueIndexInMasterTable((PARSER_TEMP_DATA STACK_BASED *)&ParserTempData,IndexInMasterTable); ++ if(((PTABLE_UNIT_TYPE)ParserTempData.pCmd)[IndexInMasterTable]!=0 ) // if the offset is not ZERO ++ { ++ ParserTempData.CommandSpecific.IndexInMasterTable=IndexInMasterTable; ++ ParserTempData.Multipurpose.CurrentPort=ATI_RegsPort; ++ ParserTempData.CurrentPortID=INDIRECT_IO_MM; ++ ParserTempData.CurrentRegBlock=0; ++ ParserTempData.CurrentFB_Window=0; ++ prevWorkingTableData=NULL; ++ ParserTempData.Status=CD_CALL_TABLE; ++ ++ do{ ++ ++ if (ParserTempData.Status==CD_CALL_TABLE) ++ { ++ IndexInMasterTable=ParserTempData.CommandSpecific.IndexInMasterTable; ++ if(((PTABLE_UNIT_TYPE)ParserTempData.pCmd)[IndexInMasterTable]!=0) // if the offset is not ZERO ++ { ++#ifndef UEFI_BUILD ++ ParserTempData.pWorkingTableData =(WORKING_TABLE_DATA STACK_BASED*) AllocateWorkSpace(pDeviceData, ++ ((ATOM_COMMON_ROM_COMMAND_TABLE_HEADER*)(((PTABLE_UNIT_TYPE)ParserTempData.pCmd)[IndexInMasterTable]+pDeviceData->pBIOS_Image))->TableAttribute.WS_SizeInBytes+sizeof(WORKING_TABLE_DATA)); ++#else ++ ParserTempData.pWorkingTableData =(WORKING_TABLE_DATA STACK_BASED*) AllocateWorkSpace(pDeviceData, ++ ((ATOM_COMMON_ROM_COMMAND_TABLE_HEADER*)(((PTABLE_UNIT_TYPE)ParserTempData.pCmd)[IndexInMasterTable]))->TableAttribute.WS_SizeInBytes+sizeof(WORKING_TABLE_DATA)); ++#endif ++ if (ParserTempData.pWorkingTableData!=NULL) ++ { ++ ParserTempData.pWorkingTableData->pWorkSpace=(WORKSPACE_POINTER STACK_BASED*)((UINT8*)ParserTempData.pWorkingTableData+sizeof(WORKING_TABLE_DATA)); ++#ifndef UEFI_BUILD ++ ParserTempData.pWorkingTableData->pTableHead = (UINT8 *)(((PTABLE_UNIT_TYPE)ParserTempData.pCmd)[IndexInMasterTable]+pDeviceData->pBIOS_Image); ++#else ++ ParserTempData.pWorkingTableData->pTableHead = (UINT8 *)(((PTABLE_UNIT_TYPE)ParserTempData.pCmd)[IndexInMasterTable]); ++#endif ++ ParserTempData.pWorkingTableData->IP=((UINT8*)ParserTempData.pWorkingTableData->pTableHead)+sizeof(ATOM_COMMON_ROM_COMMAND_TABLE_HEADER); ++ ParserTempData.pWorkingTableData->prevWorkingTableData=prevWorkingTableData; ++ prevWorkingTableData=ParserTempData.pWorkingTableData; ++ ParserTempData.Status = CD_SUCCESS; ++ } else ParserTempData.Status = CD_UNEXPECTED_BEHAVIOR; ++ } else ParserTempData.Status = CD_EXEC_TABLE_NOT_FOUND; ++ } ++ if (!CD_ERROR(ParserTempData.Status)) ++ { ++ ParserTempData.Status = CD_SUCCESS; ++ while (!CD_ERROR_OR_COMPLETED(ParserTempData.Status)) ++ { ++ ++ if (IS_COMMAND_VALID(((COMMAND_HEADER*)ParserTempData.pWorkingTableData->IP)->Opcode)) ++ { ++ ParserTempData.pCmd = (GENERIC_ATTRIBUTE_COMMAND*)ParserTempData.pWorkingTableData->IP; ++ ++ if (IS_END_OF_TABLE(((COMMAND_HEADER*)ParserTempData.pWorkingTableData->IP)->Opcode)) ++ { ++ ParserTempData.Status=CD_COMPLETED; ++ prevWorkingTableData=ParserTempData.pWorkingTableData->prevWorkingTableData; ++ ++ FreeWorkSpace(pDeviceData, ParserTempData.pWorkingTableData); ++ ParserTempData.pWorkingTableData=prevWorkingTableData; ++ if (prevWorkingTableData!=NULL) ++ { ++ ParserTempData.pDeviceData->pParameterSpace-= ++ (((ATOM_COMMON_ROM_COMMAND_TABLE_HEADER*)ParserTempData.pWorkingTableData-> ++ pTableHead)->TableAttribute.PS_SizeInBytes>>2); ++ } ++ // if there is a parent table where to return, then restore PS_pointer to the original state ++ } ++ else ++ { ++ IndexInMasterTable=ProcessCommandProperties((PARSER_TEMP_DATA STACK_BASED *)&ParserTempData); ++ (*CallTable[IndexInMasterTable].function)((PARSER_TEMP_DATA STACK_BASED *)&ParserTempData); ++#if (PARSER_TYPE!=DRIVER_TYPE_PARSER) ++ BIOS_STACK_MODIFIER(); ++#endif ++ } ++ } ++ else ++ { ++ ParserTempData.Status=CD_INVALID_OPCODE; ++ break; ++ } ++ ++ } // while ++ } // if ++ else ++ break; ++ } while (prevWorkingTableData!=NULL); ++ if (ParserTempData.Status == CD_COMPLETED) return CD_SUCCESS; ++ return ParserTempData.Status; ++ } else return CD_SUCCESS; ++} ++ ++// EOF ++ +diff --git a/src/AtomBios/hwserv_drv.c b/src/AtomBios/hwserv_drv.c +new file mode 100644 +index 0000000..a5f5a5b +--- /dev/null ++++ b/src/AtomBios/hwserv_drv.c +@@ -0,0 +1,348 @@ ++/* ++ * Copyright 2006-2007 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in ++ * all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++/** ++ ++Module Name: ++ ++ hwserv_drv.c ++ ++Abstract: ++ ++ Functions defined in the Command Decoder Specification document ++ ++Revision History: ++ ++ NEG:27.09.2002 Initiated. ++--*/ ++#include "CD_binding.h" ++#include "CD_hw_services.h" ++ ++//trace settings ++#if DEBUG_OUTPUT_DEVICE & 1 ++ #define TRACE_USING_STDERR //define it to use stderr as trace output, ++#endif ++#if DEBUG_OUTPUT_DEVICE & 2 ++ #define TRACE_USING_RS232 ++#endif ++#if DEBUG_OUTPUT_DEVICE & 4 ++ #define TRACE_USING_LPT ++#endif ++ ++ ++#if DEBUG_PARSER == 4 ++ #define IO_TRACE //IO access trace switch, undefine it to turn off ++ #define PCI_TRACE //PCI access trace switch, undefine it to turn off ++ #define MEM_TRACE //MEM access trace switch, undefine it to turn off ++#endif ++ ++UINT32 CailReadATIRegister(VOID*,UINT32); ++VOID CailWriteATIRegister(VOID*,UINT32,UINT32); ++VOID* CailAllocateMemory(VOID*,UINT16); ++VOID CailReleaseMemory(VOID *,VOID *); ++VOID CailDelayMicroSeconds(VOID *,UINT32 ); ++VOID CailReadPCIConfigData(VOID*,VOID*,UINT32,UINT16); ++VOID CailWritePCIConfigData(VOID*,VOID*,UINT32,UINT16); ++UINT32 CailReadFBData(VOID*,UINT32); ++VOID CailWriteFBData(VOID*,UINT32,UINT32); ++ULONG CailReadPLL(VOID *Context ,ULONG Address); ++VOID CailWritePLL(VOID *Context,ULONG Address,ULONG Data); ++ULONG CailReadMC(VOID *Context ,ULONG Address); ++VOID CailWriteMC(VOID *Context ,ULONG Address,ULONG Data); ++ ++ ++#if DEBUG_PARSER>0 ++VOID CailVideoDebugPrint(VOID*,ULONG_PTR, UINT16); ++#endif ++// Delay function ++#if ( defined ENABLE_PARSER_DELAY || defined ENABLE_ALL_SERVICE_FUNCTIONS ) ++ ++VOID DelayMilliseconds(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) ++{ ++ CailDelayMicroSeconds(pWorkingTableData->pDeviceData->CAIL,pWorkingTableData->SourceData32*1000); ++} ++ ++VOID DelayMicroseconds(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) ++{ ++ CailDelayMicroSeconds(pWorkingTableData->pDeviceData->CAIL,pWorkingTableData->SourceData32); ++} ++#endif ++ ++VOID PostCharOutput(PARSER_TEMP_DATA STACK_BASED * pParserTempData) ++{ ++} ++ ++VOID CallerDebugFunc(PARSER_TEMP_DATA STACK_BASED * pParserTempData) ++{ ++} ++ ++ ++// PCI READ Access ++ ++#if ( defined ENABLE_PARSER_PCIREAD8 || defined ENABLE_ALL_SERVICE_FUNCTIONS ) ++UINT8 ReadPCIReg8(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) ++{ ++ UINT8 rvl; ++ CailReadPCIConfigData(pWorkingTableData->pDeviceData->CAIL,&rvl,pWorkingTableData->Index,sizeof(UINT8)); ++ return rvl; ++} ++#endif ++ ++ ++#if ( defined ENABLE_PARSER_PCIREAD16 || defined ENABLE_ALL_SERVICE_FUNCTIONS ) ++UINT16 ReadPCIReg16(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) ++{ ++ ++ UINT16 rvl; ++ CailReadPCIConfigData(pWorkingTableData->pDeviceData->CAIL,&rvl,pWorkingTableData->Index,sizeof(UINT16)); ++ return rvl; ++ ++} ++#endif ++ ++ ++ ++#if ( defined ENABLE_PARSER_PCIREAD32 || defined ENABLE_ALL_SERVICE_FUNCTIONS ) ++UINT32 ReadPCIReg32 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) ++{ ++ ++ UINT32 rvl; ++ CailReadPCIConfigData(pWorkingTableData->pDeviceData->CAIL,&rvl,pWorkingTableData->Index,sizeof(UINT32)); ++ return rvl; ++} ++#endif ++ ++ ++// PCI WRITE Access ++ ++#if ( defined ENABLE_PARSER_PCIWRITE8 || defined ENABLE_ALL_SERVICE_FUNCTIONS ) ++VOID WritePCIReg8 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) ++{ ++ ++ CailWritePCIConfigData(pWorkingTableData->pDeviceData->CAIL,&(pWorkingTableData->DestData32),pWorkingTableData->Index,sizeof(UINT8)); ++ ++} ++ ++#endif ++ ++ ++#if ( defined ENABLE_PARSER_PCIWRITE16 || defined ENABLE_ALL_SERVICE_FUNCTIONS ) ++VOID WritePCIReg16 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) ++{ ++ ++ CailWritePCIConfigData(pWorkingTableData->pDeviceData->CAIL,&(pWorkingTableData->DestData32),pWorkingTableData->Index,sizeof(UINT16)); ++} ++ ++#endif ++ ++ ++#if ( defined ENABLE_PARSER_PCIWRITE32 || defined ENABLE_ALL_SERVICE_FUNCTIONS ) ++VOID WritePCIReg32 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) ++{ ++ CailWritePCIConfigData(pWorkingTableData->pDeviceData->CAIL,&(pWorkingTableData->DestData32),pWorkingTableData->Index,sizeof(UINT32)); ++} ++#endif ++ ++ ++ ++ ++// System IO Access ++#if ( defined ENABLE_PARSER_SYS_IOREAD8 || defined ENABLE_ALL_SERVICE_FUNCTIONS ) ++UINT8 ReadSysIOReg8 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) ++{ ++ UINT8 rvl; ++ rvl=0; ++ //rvl= (UINT8) ReadGenericPciCfg(dev,reg,sizeof(UINT8)); ++ return rvl; ++} ++#endif ++ ++ ++#if ( defined ENABLE_PARSER_SYS_IOREAD16 || defined ENABLE_ALL_SERVICE_FUNCTIONS ) ++UINT16 ReadSysIOReg16(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) ++{ ++ ++ UINT16 rvl; ++ rvl=0; ++ //rvl= (UINT16) ReadGenericPciCfg(dev,reg,sizeof(UINT16)); ++ return rvl; ++ ++} ++#endif ++ ++ ++ ++#if ( defined ENABLE_PARSER_SYS_IOREAD32 || defined ENABLE_ALL_SERVICE_FUNCTIONS ) ++UINT32 ReadSysIOReg32 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) ++{ ++ ++ UINT32 rvl; ++ rvl=0; ++ //rvl= (UINT32) ReadGenericPciCfg(dev,reg,sizeof(UINT32)); ++ return rvl; ++} ++#endif ++ ++ ++// PCI WRITE Access ++ ++#if ( defined ENABLE_PARSER_SYS_IOWRITE8 || defined ENABLE_ALL_SERVICE_FUNCTIONS ) ++VOID WriteSysIOReg8 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) ++{ ++ ++ //WriteGenericPciCfg(dev,reg,sizeof(UINT8),(UINT32)value); ++} ++ ++#endif ++ ++ ++#if ( defined ENABLE_PARSER_SYS_IOWRITE16 || defined ENABLE_ALL_SERVICE_FUNCTIONS ) ++VOID WriteSysIOReg16 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) ++{ ++ ++ //WriteGenericPciCfg(dev,reg,sizeof(UINT16),(UINT32)value); ++} ++ ++#endif ++ ++ ++#if ( defined ENABLE_PARSER_SYS_IOWRITE32 || defined ENABLE_ALL_SERVICE_FUNCTIONS ) ++VOID WriteSysIOReg32 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) ++{ ++ //WriteGenericPciCfg(dev,reg,sizeof(UINT32),(UINT32)value); ++} ++#endif ++ ++// ATI Registers Memory Mapped Access ++ ++#if ( defined ENABLE_PARSER_REGISTERS_MEMORY_ACCESS || defined ENABLE_ALL_SERVICE_FUNCTIONS) ++ ++UINT32 ReadReg32 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) ++{ ++ return CailReadATIRegister(pWorkingTableData->pDeviceData->CAIL,pWorkingTableData->Index); ++} ++ ++VOID WriteReg32(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) ++{ ++ CailWriteATIRegister(pWorkingTableData->pDeviceData->CAIL,(UINT16)pWorkingTableData->Index,pWorkingTableData->DestData32 ); ++} ++ ++ ++VOID ReadIndReg32 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) ++{ ++ pWorkingTableData->IndirectData = CailReadATIRegister(pWorkingTableData->pDeviceData->CAIL,*(UINT16*)(pWorkingTableData->IndirectIOTablePointer+1)); ++} ++ ++VOID WriteIndReg32(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) ++{ ++ CailWriteATIRegister(pWorkingTableData->pDeviceData->CAIL,*(UINT16*)(pWorkingTableData->IndirectIOTablePointer+1),pWorkingTableData->IndirectData ); ++} ++ ++#endif ++ ++// ATI Registers IO Mapped Access ++ ++#if ( defined ENABLE_PARSER_REGISTERS_IO_ACCESS || defined ENABLE_ALL_SERVICE_FUNCTIONS ) ++UINT32 ReadRegIO (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) ++{ ++ //return CailReadATIRegister(pWorkingTableData->pDeviceData->CAIL,pWorkingTableData->Index); ++ return 0; ++} ++VOID WriteRegIO(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) ++{ ++ // return CailWriteATIRegister(pWorkingTableData->pDeviceData->CAIL,pWorkingTableData->Index,pWorkingTableData->DestData32 ); ++} ++#endif ++ ++// access to Frame buffer, dummy function, need more information to implement it ++UINT32 ReadFrameBuffer32 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) ++{ ++ ++ return CailReadFBData(pWorkingTableData->pDeviceData->CAIL, (pWorkingTableData->Index <<2 )); ++ ++} ++ ++VOID WriteFrameBuffer32(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) ++{ ++ CailWriteFBData(pWorkingTableData->pDeviceData->CAIL,(pWorkingTableData->Index <<2), pWorkingTableData->DestData32); ++ ++} ++ ++ ++VOID *AllocateMemory(DEVICE_DATA *pDeviceData , UINT16 MemSize) ++{ ++ if(MemSize) ++ return(CailAllocateMemory(pDeviceData->CAIL,MemSize)); ++ else ++ return NULL; ++} ++ ++ ++VOID ReleaseMemory(DEVICE_DATA *pDeviceData , WORKING_TABLE_DATA* pWorkingTableData) ++{ ++ if( pWorkingTableData) ++ CailReleaseMemory(pDeviceData->CAIL, pWorkingTableData); ++} ++ ++ ++UINT32 ReadMC32(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) ++{ ++ UINT32 ReadData; ++ ReadData=(UINT32)CailReadMC(pWorkingTableData->pDeviceData->CAIL,pWorkingTableData->Index); ++ return ReadData; ++} ++ ++VOID WriteMC32(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) ++{ ++ CailWriteMC(pWorkingTableData->pDeviceData->CAIL,pWorkingTableData->Index,pWorkingTableData->DestData32); ++} ++ ++UINT32 ReadPLL32(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) ++{ ++ UINT32 ReadData; ++ ReadData=(UINT32)CailReadPLL(pWorkingTableData->pDeviceData->CAIL,pWorkingTableData->Index); ++ return ReadData; ++ ++} ++ ++VOID WritePLL32(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) ++{ ++ CailWritePLL(pWorkingTableData->pDeviceData->CAIL,pWorkingTableData->Index,pWorkingTableData->DestData32); ++ ++} ++ ++ ++ ++#if DEBUG_PARSER>0 ++VOID CD_print_string (DEVICE_DATA *pDeviceData, UINT8 *str) ++{ ++ CailVideoDebugPrint( pDeviceData->CAIL, (ULONG_PTR) str, PARSER_STRINGS); ++} ++ ++VOID CD_print_value (DEVICE_DATA *pDeviceData, ULONG_PTR value, UINT16 value_type ) ++{ ++ CailVideoDebugPrint( pDeviceData->CAIL, (ULONG_PTR)value, value_type); ++} ++ ++#endif ++ ++// EOF +diff --git a/src/AtomBios/includes/CD_Common_Types.h b/src/AtomBios/includes/CD_Common_Types.h +new file mode 100644 +index 0000000..44a0b35 +--- /dev/null ++++ b/src/AtomBios/includes/CD_Common_Types.h +@@ -0,0 +1,154 @@ ++/* ++ * Copyright 2006-2007 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in ++ * all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++/*++ ++ ++Module Name: ++ ++ CD_Common_Types.h ++ ++Abstract: ++ ++ Defines common data types to use across platforms/SW components ++ ++Revision History: ++ ++ NEG:17.09.2002 Initiated. ++--*/ ++#ifndef _COMMON_TYPES_H_ ++ #define _COMMON_TYPES_H_ ++ ++ #ifndef LINUX ++ #if _MSC_EXTENSIONS ++ ++ // ++ // use Microsoft* C complier dependent interger width types ++ // ++ // typedef unsigned __int64 uint64_t; ++ // typedef __int64 int64_t; ++ typedef unsigned __int32 uint32_t; ++ typedef __int32 int32_t; ++#elif defined (__linux__) || defined (__NetBSD__) || defined(__sun) || defined(__OpenBSD__) || defined (__FreeBSD__) ++ typedef unsigned int uint32_t; ++ typedef int int32_t; ++ #else ++ typedef unsigned long uint32_t; ++ typedef signed long int32_t; ++ #endif ++ typedef unsigned char uint8_t; ++#if (defined(__sun) && defined(_CHAR_IS_SIGNED)) ++ typedef char int8_t; ++#else ++ typedef signed char int8_t; ++#endif ++ typedef unsigned short uint16_t; ++ typedef signed short int16_t; ++ #endif ++#ifndef UEFI_BUILD ++ typedef signed int intn_t; ++ typedef unsigned int uintn_t; ++#else ++#ifndef EFIX64 ++ typedef signed int intn_t; ++ typedef unsigned int uintn_t; ++#endif ++#endif ++#ifndef FGL_LINUX ++#pragma warning ( disable : 4142 ) ++#endif ++ ++ ++#ifndef VOID ++typedef void VOID; ++#endif ++#ifndef UEFI_BUILD ++ typedef intn_t INTN; ++ typedef uintn_t UINTN; ++#else ++#ifndef EFIX64 ++ typedef intn_t INTN; ++ typedef uintn_t UINTN; ++#endif ++#endif ++#ifndef BOOLEAN ++typedef uint8_t BOOLEAN; ++#endif ++#ifndef INT8 ++typedef int8_t INT8; ++#endif ++#ifndef UINT8 ++typedef uint8_t UINT8; ++#endif ++#ifndef INT16 ++typedef int16_t INT16; ++#endif ++#ifndef UINT16 ++typedef uint16_t UINT16; ++#endif ++#ifndef INT32 ++typedef int32_t INT32; ++#endif ++#ifndef UINT32 ++typedef uint32_t UINT32; ++#endif ++//typedef int64_t INT64; ++//typedef uint64_t UINT64; ++typedef uint8_t CHAR8; ++typedef uint16_t CHAR16; ++#ifndef USHORT ++typedef UINT16 USHORT; ++#endif ++#ifndef UCHAR ++typedef UINT8 UCHAR; ++#endif ++#ifndef ULONG ++typedef UINT32 ULONG; ++#endif ++ ++#ifndef _WIN64 ++#ifndef ULONG_PTR ++typedef unsigned long ULONG_PTR; ++#endif // ULONG_PTR ++#endif // _WIN64 ++ ++//#define FAR __far ++#ifndef TRUE ++ #define TRUE ((BOOLEAN) 1 == 1) ++#endif ++ ++#ifndef FALSE ++ #define FALSE ((BOOLEAN) 0 == 1) ++#endif ++ ++#ifndef NULL ++ #define NULL ((VOID *) 0) ++#endif ++ ++//typedef UINTN CD_STATUS; ++ ++ ++#ifndef FGL_LINUX ++#pragma warning ( default : 4142 ) ++#endif ++#endif // _COMMON_TYPES_H_ ++ ++// EOF +diff --git a/src/AtomBios/includes/CD_Definitions.h b/src/AtomBios/includes/CD_Definitions.h +new file mode 100644 +index 0000000..98fd495 +--- /dev/null ++++ b/src/AtomBios/includes/CD_Definitions.h +@@ -0,0 +1,49 @@ ++/* ++ * Copyright 2006-2007 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in ++ * all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++/*++ ++ ++Module Name: ++ ++CD_Definitions.h ++ ++Abstract: ++ ++Defines Script Language commands ++ ++Revision History: ++ ++NEG:27.08.2002 Initiated. ++--*/ ++ ++#include "CD_Structs.h" ++#ifndef _CD_DEFINITIONS_H ++#define _CD_DEFINITIONS_H_ ++#ifdef DRIVER_PARSER ++VOID *AllocateMemory(VOID *, UINT16); ++VOID ReleaseMemory(DEVICE_DATA * , WORKING_TABLE_DATA* ); ++#endif ++CD_STATUS ParseTable(DEVICE_DATA* pDeviceData, UINT8 IndexInMasterTable); ++//CD_STATUS CD_MainLoop(PARSER_TEMP_DATA_POINTER pParserTempData); ++CD_STATUS Main_Loop(DEVICE_DATA* pDeviceData,UINT16 *MasterTableOffset,UINT8 IndexInMasterTable); ++UINT16* GetCommandMasterTablePointer(DEVICE_DATA* pDeviceData); ++#endif //CD_DEFINITIONS +diff --git a/src/AtomBios/includes/CD_Opcodes.h b/src/AtomBios/includes/CD_Opcodes.h +new file mode 100644 +index 0000000..2f3bec5 +--- /dev/null ++++ b/src/AtomBios/includes/CD_Opcodes.h +@@ -0,0 +1,181 @@ ++/* ++ * Copyright 2006-2007 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in ++ * all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++/*++ ++ ++Module Name: ++ ++CD_OPCODEs.h ++ ++Abstract: ++ ++Defines Command Decoder OPCODEs ++ ++Revision History: ++ ++NEG:24.09.2002 Initiated. ++--*/ ++#ifndef _CD_OPCODES_H_ ++#define _CD_OPCODES_H_ ++ ++typedef enum _OPCODE { ++ Reserved_00= 0, // 0 = 0x00 ++ // MOVE_ group ++ MOVE_REG_OPCODE, // 1 = 0x01 ++ FirstValidCommand=MOVE_REG_OPCODE, ++ MOVE_PS_OPCODE, // 2 = 0x02 ++ MOVE_WS_OPCODE, // 3 = 0x03 ++ MOVE_FB_OPCODE, // 4 = 0x04 ++ MOVE_PLL_OPCODE, // 5 = 0x05 ++ MOVE_MC_OPCODE, // 6 = 0x06 ++ // Logic group ++ AND_REG_OPCODE, // 7 = 0x07 ++ AND_PS_OPCODE, // 8 = 0x08 ++ AND_WS_OPCODE, // 9 = 0x09 ++ AND_FB_OPCODE, // 10 = 0x0A ++ AND_PLL_OPCODE, // 11 = 0x0B ++ AND_MC_OPCODE, // 12 = 0x0C ++ OR_REG_OPCODE, // 13 = 0x0D ++ OR_PS_OPCODE, // 14 = 0x0E ++ OR_WS_OPCODE, // 15 = 0x0F ++ OR_FB_OPCODE, // 16 = 0x10 ++ OR_PLL_OPCODE, // 17 = 0x11 ++ OR_MC_OPCODE, // 18 = 0x12 ++ SHIFT_LEFT_REG_OPCODE, // 19 = 0x13 ++ SHIFT_LEFT_PS_OPCODE, // 20 = 0x14 ++ SHIFT_LEFT_WS_OPCODE, // 21 = 0x15 ++ SHIFT_LEFT_FB_OPCODE, // 22 = 0x16 ++ SHIFT_LEFT_PLL_OPCODE, // 23 = 0x17 ++ SHIFT_LEFT_MC_OPCODE, // 24 = 0x18 ++ SHIFT_RIGHT_REG_OPCODE, // 25 = 0x19 ++ SHIFT_RIGHT_PS_OPCODE, // 26 = 0x1A ++ SHIFT_RIGHT_WS_OPCODE, // 27 = 0x1B ++ SHIFT_RIGHT_FB_OPCODE, // 28 = 0x1C ++ SHIFT_RIGHT_PLL_OPCODE, // 29 = 0x1D ++ SHIFT_RIGHT_MC_OPCODE, // 30 = 0x1E ++ // Arithmetic group ++ MUL_REG_OPCODE, // 31 = 0x1F ++ MUL_PS_OPCODE, // 32 = 0x20 ++ MUL_WS_OPCODE, // 33 = 0x21 ++ MUL_FB_OPCODE, // 34 = 0x22 ++ MUL_PLL_OPCODE, // 35 = 0x23 ++ MUL_MC_OPCODE, // 36 = 0x24 ++ DIV_REG_OPCODE, // 37 = 0x25 ++ DIV_PS_OPCODE, // 38 = 0x26 ++ DIV_WS_OPCODE, // 39 = 0x27 ++ DIV_FB_OPCODE, // 40 = 0x28 ++ DIV_PLL_OPCODE, // 41 = 0x29 ++ DIV_MC_OPCODE, // 42 = 0x2A ++ ADD_REG_OPCODE, // 43 = 0x2B ++ ADD_PS_OPCODE, // 44 = 0x2C ++ ADD_WS_OPCODE, // 45 = 0x2D ++ ADD_FB_OPCODE, // 46 = 0x2E ++ ADD_PLL_OPCODE, // 47 = 0x2F ++ ADD_MC_OPCODE, // 48 = 0x30 ++ SUB_REG_OPCODE, // 49 = 0x31 ++ SUB_PS_OPCODE, // 50 = 0x32 ++ SUB_WS_OPCODE, // 51 = 0x33 ++ SUB_FB_OPCODE, // 52 = 0x34 ++ SUB_PLL_OPCODE, // 53 = 0x35 ++ SUB_MC_OPCODE, // 54 = 0x36 ++ // Control grouop ++ SET_ATI_PORT_OPCODE, // 55 = 0x37 ++ SET_PCI_PORT_OPCODE, // 56 = 0x38 ++ SET_SYS_IO_PORT_OPCODE, // 57 = 0x39 ++ SET_REG_BLOCK_OPCODE, // 58 = 0x3A ++ SET_FB_BASE_OPCODE, // 59 = 0x3B ++ COMPARE_REG_OPCODE, // 60 = 0x3C ++ COMPARE_PS_OPCODE, // 61 = 0x3D ++ COMPARE_WS_OPCODE, // 62 = 0x3E ++ COMPARE_FB_OPCODE, // 63 = 0x3F ++ COMPARE_PLL_OPCODE, // 64 = 0x40 ++ COMPARE_MC_OPCODE, // 65 = 0x41 ++ SWITCH_OPCODE, // 66 = 0x42 ++ JUMP__OPCODE, // 67 = 0x43 ++ JUMP_EQUAL_OPCODE, // 68 = 0x44 ++ JUMP_BELOW_OPCODE, // 69 = 0x45 ++ JUMP_ABOVE_OPCODE, // 70 = 0x46 ++ JUMP_BELOW_OR_EQUAL_OPCODE, // 71 = 0x47 ++ JUMP_ABOVE_OR_EQUAL_OPCODE, // 72 = 0x48 ++ JUMP_NOT_EQUAL_OPCODE, // 73 = 0x49 ++ TEST_REG_OPCODE, // 74 = 0x4A ++ TEST_PS_OPCODE, // 75 = 0x4B ++ TEST_WS_OPCODE, // 76 = 0x4C ++ TEST_FB_OPCODE, // 77 = 0x4D ++ TEST_PLL_OPCODE, // 78 = 0x4E ++ TEST_MC_OPCODE, // 79 = 0x4F ++ DELAY_MILLISEC_OPCODE, // 80 = 0x50 ++ DELAY_MICROSEC_OPCODE, // 81 = 0x51 ++ CALL_TABLE_OPCODE, // 82 = 0x52 ++ REPEAT_OPCODE, // 83 = 0x53 ++ // Miscellaneous group ++ CLEAR_REG_OPCODE, // 84 = 0x54 ++ CLEAR_PS_OPCODE, // 85 = 0x55 ++ CLEAR_WS_OPCODE, // 86 = 0x56 ++ CLEAR_FB_OPCODE, // 87 = 0x57 ++ CLEAR_PLL_OPCODE, // 88 = 0x58 ++ CLEAR_MC_OPCODE, // 89 = 0x59 ++ NOP_OPCODE, // 90 = 0x5A ++ EOT_OPCODE, // 91 = 0x5B ++ MASK_REG_OPCODE, // 92 = 0x5C ++ MASK_PS_OPCODE, // 93 = 0x5D ++ MASK_WS_OPCODE, // 94 = 0x5E ++ MASK_FB_OPCODE, // 95 = 0x5F ++ MASK_PLL_OPCODE, // 96 = 0x60 ++ MASK_MC_OPCODE, // 97 = 0x61 ++ // BIOS dedicated group ++ POST_CARD_OPCODE, // 98 = 0x62 ++ BEEP_OPCODE, // 99 = 0x63 ++ SAVE_REG_OPCODE, // 100 = 0x64 ++ RESTORE_REG_OPCODE, // 101 = 0x65 ++ SET_DATA_BLOCK_OPCODE, // 102 = 0x66 ++ ++ XOR_REG_OPCODE, // 103 = 0x67 ++ XOR_PS_OPCODE, // 104 = 0x68 ++ XOR_WS_OPCODE, // 105 = 0x69 ++ XOR_FB_OPCODE, // 106 = 0x6a ++ XOR_PLL_OPCODE, // 107 = 0x6b ++ XOR_MC_OPCODE, // 108 = 0x6c ++ ++ SHL_REG_OPCODE, // 109 = 0x6d ++ SHL_PS_OPCODE, // 110 = 0x6e ++ SHL_WS_OPCODE, // 111 = 0x6f ++ SHL_FB_OPCODE, // 112 = 0x70 ++ SHL_PLL_OPCODE, // 113 = 0x71 ++ SHL_MC_OPCODE, // 114 = 0x72 ++ ++ SHR_REG_OPCODE, // 115 = 0x73 ++ SHR_PS_OPCODE, // 116 = 0x74 ++ SHR_WS_OPCODE, // 117 = 0x75 ++ SHR_FB_OPCODE, // 118 = 0x76 ++ SHR_PLL_OPCODE, // 119 = 0x77 ++ SHR_MC_OPCODE, // 120 = 0x78 ++ ++ DEBUG_OPCODE, // 121 = 0x79 ++ CTB_DS_OPCODE, // 122 = 0x7A ++ ++ LastValidCommand = CTB_DS_OPCODE, ++ // Extension specificaTOR ++ Extension = 0x80, // 128 = 0x80 // Next byte is an OPCODE as well ++ Reserved_FF = 255 // 255 = 0xFF ++}OPCODE; ++#endif // _CD_OPCODES_H_ +diff --git a/src/AtomBios/includes/CD_Structs.h b/src/AtomBios/includes/CD_Structs.h +new file mode 100644 +index 0000000..c43f81d +--- /dev/null ++++ b/src/AtomBios/includes/CD_Structs.h +@@ -0,0 +1,464 @@ ++/* ++ * Copyright 2006-2007 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in ++ * all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++/*++ ++ ++Module Name: ++ ++CD_Struct.h ++ ++Abstract: ++ ++Defines Script Language commands ++ ++Revision History: ++ ++NEG:26.08.2002 Initiated. ++--*/ ++ ++#include "CD_binding.h" ++#ifndef _CD_STRUCTS_H_ ++#define _CD_STRUCTS_H_ ++ ++#ifdef UEFI_BUILD ++typedef UINT16** PTABLE_UNIT_TYPE; ++typedef UINTN TABLE_UNIT_TYPE; ++#else ++typedef UINT16* PTABLE_UNIT_TYPE; ++typedef UINT16 TABLE_UNIT_TYPE; ++#endif ++ ++#include //This important file is dynamically generated based on the ASIC!!!! ++ ++#define PARSER_MAJOR_REVISION 5 ++#define PARSER_MINOR_REVISION 0 ++ ++//#include "atombios.h" ++#if (PARSER_TYPE==DRIVER_TYPE_PARSER) ++#ifdef FGL_LINUX ++#pragma pack(push,1) ++#else ++#pragma pack(push) ++#pragma pack(1) ++#endif ++#endif ++ ++#include "CD_Common_Types.h" ++#include "CD_Opcodes.h" ++typedef UINT16 WORK_SPACE_SIZE; ++typedef enum _CD_STATUS{ ++ CD_SUCCESS, ++ CD_CALL_TABLE, ++ CD_COMPLETED=0x10, ++ CD_GENERAL_ERROR=0x80, ++ CD_INVALID_OPCODE, ++ CD_NOT_IMPLEMENTED, ++ CD_EXEC_TABLE_NOT_FOUND, ++ CD_EXEC_PARAMETER_ERROR, ++ CD_EXEC_PARSER_ERROR, ++ CD_INVALID_DESTINATION_TYPE, ++ CD_UNEXPECTED_BEHAVIOR, ++ CD_INVALID_SWITCH_OPERAND_SIZE ++}CD_STATUS; ++ ++#define PARSER_STRINGS 0 ++#define PARSER_DEC 1 ++#define PARSER_HEX 2 ++ ++#define DB_CURRENT_COMMAND_TABLE 0xFF ++ ++#define TABLE_FORMAT_BIOS 0 ++#define TABLE_FORMAT_EASF 1 ++ ++#define EASF_TABLE_INDEX_MASK 0xfc ++#define EASF_TABLE_ATTR_MASK 0x03 ++ ++#define CD_ERROR(a) (((INTN) (a)) > CD_COMPLETED) ++#define CD_ERROR_OR_COMPLETED(a) (((INTN) (a)) > CD_SUCCESS) ++ ++ ++#if (BIOS_PARSER==1) ++#ifdef _H2INC ++#define STACK_BASED ++#else ++extern __segment farstack; ++#define STACK_BASED __based(farstack) ++#endif ++#else ++#define STACK_BASED ++#endif ++ ++typedef enum _COMPARE_FLAGS{ ++ Below, ++ Equal, ++ Above, ++ NotEqual, ++ Overflow, ++ NoCondition ++}COMPARE_FLAGS; ++ ++typedef UINT16 IO_BASE_ADDR; ++ ++typedef struct _BUS_DEV_FUNC_PCI_ADDR{ ++ UINT8 Register; ++ UINT8 Function; ++ UINT8 Device; ++ UINT8 Bus; ++} BUS_DEV_FUNC_PCI_ADDR; ++ ++typedef struct _BUS_DEV_FUNC{ ++ UINT8 Function : 3; ++ UINT8 Device : 5; ++ UINT8 Bus; ++} BUS_DEV_FUNC; ++ ++#ifndef UEFI_BUILD ++typedef struct _PCI_CONFIG_ACCESS_CF8{ ++ UINT32 Reg : 8; ++ UINT32 Func : 3; ++ UINT32 Dev : 5; ++ UINT32 Bus : 8; ++ UINT32 Reserved: 7; ++ UINT32 Enable : 1; ++} PCI_CONFIG_ACCESS_CF8; ++#endif ++ ++typedef enum _MEM_RESOURCE { ++ Stack_Resource, ++ FrameBuffer_Resource, ++ BIOS_Image_Resource ++}MEM_RESOURCE; ++ ++typedef enum _PORTS{ ++ ATI_RegsPort, ++ PCI_Port, ++ SystemIO_Port ++}PORTS; ++ ++typedef enum _OPERAND_TYPE { ++ typeRegister, ++ typeParamSpace, ++ typeWorkSpace, ++ typeFrameBuffer, ++ typeIndirect, ++ typeDirect, ++ typePLL, ++ typeMC ++}OPERAND_TYPE; ++ ++typedef enum _DESTINATION_OPERAND_TYPE { ++ destRegister, ++ destParamSpace, ++ destWorkSpace, ++ destFrameBuffer, ++ destPLL, ++ destMC ++}DESTINATION_OPERAND_TYPE; ++ ++typedef enum _SOURCE_OPERAND_TYPE { ++ sourceRegister, ++ sourceParamSpace, ++ sourceWorkSpace, ++ sourceFrameBuffer, ++ sourceIndirect, ++ sourceDirect, ++ sourcePLL, ++ sourceMC ++}SOURCE_OPERAND_TYPE; ++ ++typedef enum _ALIGNMENT_TYPE { ++ alignmentDword, ++ alignmentLowerWord, ++ alignmentMiddleWord, ++ alignmentUpperWord, ++ alignmentByte0, ++ alignmentByte1, ++ alignmentByte2, ++ alignmentByte3 ++}ALIGNMENT_TYPE; ++ ++ ++#define INDIRECT_IO_READ 0 ++#define INDIRECT_IO_WRITE 0x80 ++#define INDIRECT_IO_MM 0 ++#define INDIRECT_IO_PLL 1 ++#define INDIRECT_IO_MC 2 ++ ++typedef struct _PARAMETERS_TYPE{ ++ UINT8 Destination; ++ UINT8 Source; ++}PARAMETERS_TYPE; ++/* The following structures don't used to allocate any type of objects(variables). ++ they are serve the only purpose: Get proper access to data(commands), found in the tables*/ ++typedef struct _PA_BYTE_BYTE{ ++ UINT8 PA_Destination; ++ UINT8 PA_Source; ++ UINT8 PA_Padding[8]; ++}PA_BYTE_BYTE; ++typedef struct _PA_BYTE_WORD{ ++ UINT8 PA_Destination; ++ UINT16 PA_Source; ++ UINT8 PA_Padding[7]; ++}PA_BYTE_WORD; ++typedef struct _PA_BYTE_DWORD{ ++ UINT8 PA_Destination; ++ UINT32 PA_Source; ++ UINT8 PA_Padding[5]; ++}PA_BYTE_DWORD; ++typedef struct _PA_WORD_BYTE{ ++ UINT16 PA_Destination; ++ UINT8 PA_Source; ++ UINT8 PA_Padding[7]; ++}PA_WORD_BYTE; ++typedef struct _PA_WORD_WORD{ ++ UINT16 PA_Destination; ++ UINT16 PA_Source; ++ UINT8 PA_Padding[6]; ++}PA_WORD_WORD; ++typedef struct _PA_WORD_DWORD{ ++ UINT16 PA_Destination; ++ UINT32 PA_Source; ++ UINT8 PA_Padding[4]; ++}PA_WORD_DWORD; ++typedef struct _PA_WORD_XX{ ++ UINT16 PA_Destination; ++ UINT8 PA_Padding[8]; ++}PA_WORD_XX; ++typedef struct _PA_BYTE_XX{ ++ UINT8 PA_Destination; ++ UINT8 PA_Padding[9]; ++}PA_BYTE_XX; ++/*The following 6 definitions used for Mask operation*/ ++typedef struct _PA_BYTE_BYTE_BYTE{ ++ UINT8 PA_Destination; ++ UINT8 PA_AndMaskByte; ++ UINT8 PA_OrMaskByte; ++ UINT8 PA_Padding[7]; ++}PA_BYTE_BYTE_BYTE; ++typedef struct _PA_BYTE_WORD_WORD{ ++ UINT8 PA_Destination; ++ UINT16 PA_AndMaskWord; ++ UINT16 PA_OrMaskWord; ++ UINT8 PA_Padding[5]; ++}PA_BYTE_WORD_WORD; ++typedef struct _PA_BYTE_DWORD_DWORD{ ++ UINT8 PA_Destination; ++ UINT32 PA_AndMaskDword; ++ UINT32 PA_OrMaskDword; ++ UINT8 PA_Padding; ++}PA_BYTE_DWORD_DWORD; ++typedef struct _PA_WORD_BYTE_BYTE{ ++ UINT16 PA_Destination; ++ UINT8 PA_AndMaskByte; ++ UINT8 PA_OrMaskByte; ++ UINT8 PA_Padding[6]; ++}PA_WORD_BYTE_BYTE; ++typedef struct _PA_WORD_WORD_WORD{ ++ UINT16 PA_Destination; ++ UINT16 PA_AndMaskWord; ++ UINT16 PA_OrMaskWord; ++ UINT8 PA_Padding[4]; ++}PA_WORD_WORD_WORD; ++typedef struct _PA_WORD_DWORD_DWORD{ ++ UINT16 PA_Destination; ++ UINT32 PA_AndMaskDword; ++ UINT32 PA_OrMaskDword; ++}PA_WORD_DWORD_DWORD; ++ ++ ++typedef union _PARAMETER_ACCESS { ++ PA_BYTE_XX ByteXX; ++ PA_BYTE_BYTE ByteByte; ++ PA_BYTE_WORD ByteWord; ++ PA_BYTE_DWORD ByteDword; ++ PA_WORD_BYTE WordByte; ++ PA_WORD_WORD WordWord; ++ PA_WORD_DWORD WordDword; ++ PA_WORD_XX WordXX; ++/*The following 6 definitions used for Mask operation*/ ++ PA_BYTE_BYTE_BYTE ByteByteAndByteOr; ++ PA_BYTE_WORD_WORD ByteWordAndWordOr; ++ PA_BYTE_DWORD_DWORD ByteDwordAndDwordOr; ++ PA_WORD_BYTE_BYTE WordByteAndByteOr; ++ PA_WORD_WORD_WORD WordWordAndWordOr; ++ PA_WORD_DWORD_DWORD WordDwordAndDwordOr; ++}PARAMETER_ACCESS; ++ ++typedef struct _COMMAND_ATTRIBUTE { ++ UINT8 Source:3; ++ UINT8 SourceAlignment:3; ++ UINT8 DestinationAlignment:2; ++}COMMAND_ATTRIBUTE; ++ ++typedef struct _SOURCE_DESTINATION_ALIGNMENT{ ++ UINT8 DestAlignment; ++ UINT8 SrcAlignment; ++}SOURCE_DESTINATION_ALIGNMENT; ++typedef struct _MULTIPLICATION_RESULT{ ++ UINT32 Low32Bit; ++ UINT32 High32Bit; ++}MULTIPLICATION_RESULT; ++typedef struct _DIVISION_RESULT{ ++ UINT32 Quotient32; ++ UINT32 Reminder32; ++}DIVISION_RESULT; ++typedef union _DIVISION_MULTIPLICATION_RESULT{ ++ MULTIPLICATION_RESULT Multiplication; ++ DIVISION_RESULT Division; ++}DIVISION_MULTIPLICATION_RESULT; ++typedef struct _COMMAND_HEADER { ++ UINT8 Opcode; ++ COMMAND_ATTRIBUTE Attribute; ++}COMMAND_HEADER; ++ ++typedef struct _GENERIC_ATTRIBUTE_COMMAND{ ++ COMMAND_HEADER Header; ++ PARAMETER_ACCESS Parameters; ++} GENERIC_ATTRIBUTE_COMMAND; ++ ++typedef struct _COMMAND_TYPE_1{ ++ UINT8 Opcode; ++ PARAMETER_ACCESS Parameters; ++} COMMAND_TYPE_1; ++ ++typedef struct _COMMAND_TYPE_OPCODE_OFFSET16{ ++ UINT8 Opcode; ++ UINT16 CD_Offset16; ++} COMMAND_TYPE_OPCODE_OFFSET16; ++ ++typedef struct _COMMAND_TYPE_OPCODE_OFFSET32{ ++ UINT8 Opcode; ++ UINT32 CD_Offset32; ++} COMMAND_TYPE_OPCODE_OFFSET32; ++ ++typedef struct _COMMAND_TYPE_OPCODE_VALUE_BYTE{ ++ UINT8 Opcode; ++ UINT8 Value; ++} COMMAND_TYPE_OPCODE_VALUE_BYTE; ++ ++typedef union _COMMAND_SPECIFIC_UNION{ ++ UINT8 ContinueSwitch; ++ UINT8 ControlOperandSourcePosition; ++ UINT8 IndexInMasterTable; ++} COMMAND_SPECIFIC_UNION; ++ ++ ++typedef struct _CD_GENERIC_BYTE{ ++ UINT16 CommandType:3; ++ UINT16 CurrentParameterSize:3; ++ UINT16 CommandAccessType:3; ++ UINT16 CurrentPort:2; ++ UINT16 PS_SizeInDwordsUsedByCallingTable:5; ++}CD_GENERIC_BYTE; ++ ++typedef UINT8 COMMAND_TYPE_OPCODE_ONLY; ++ ++typedef UINT8 COMMAND_HEADER_POINTER; ++ ++ ++#if (PARSER_TYPE==BIOS_TYPE_PARSER) ++ ++typedef struct _DEVICE_DATA { ++ UINT32 STACK_BASED *pParameterSpace; ++ UINT8 *pBIOS_Image; ++ UINT8 format; ++#if (IO_INTERFACE==PARSER_INTERFACE) ++ IO_BASE_ADDR IOBase; ++#endif ++} DEVICE_DATA; ++ ++#else ++ ++typedef struct _DEVICE_DATA { ++ UINT32 *pParameterSpace; ++ VOID *CAIL; ++ UINT8 *pBIOS_Image; ++ UINT32 format; ++} DEVICE_DATA; ++ ++#endif ++ ++struct _PARSER_TEMP_DATA; ++typedef UINT32 WORKSPACE_POINTER; ++ ++struct _WORKING_TABLE_DATA{ ++ UINT8 * pTableHead; ++ COMMAND_HEADER_POINTER * IP; // Commands pointer ++ WORKSPACE_POINTER STACK_BASED * pWorkSpace; ++ struct _WORKING_TABLE_DATA STACK_BASED * prevWorkingTableData; ++}; ++ ++ ++ ++typedef struct _PARSER_TEMP_DATA{ ++ DEVICE_DATA STACK_BASED *pDeviceData; ++ struct _WORKING_TABLE_DATA STACK_BASED *pWorkingTableData; ++ UINT32 SourceData32; ++ UINT32 DestData32; ++ DIVISION_MULTIPLICATION_RESULT MultiplicationOrDivision; ++ UINT32 Index; ++ UINT32 CurrentFB_Window; ++ UINT32 IndirectData; ++ UINT16 CurrentRegBlock; ++ TABLE_UNIT_TYPE CurrentDataBlock; ++ UINT16 AttributesData; ++// UINT8 *IndirectIOTable; ++ UINT8 *IndirectIOTablePointer; ++ GENERIC_ATTRIBUTE_COMMAND *pCmd; //CurrentCommand; ++ SOURCE_DESTINATION_ALIGNMENT CD_Mask; ++ PARAMETERS_TYPE ParametersType; ++ CD_GENERIC_BYTE Multipurpose; ++ UINT8 CompareFlags; ++ COMMAND_SPECIFIC_UNION CommandSpecific; ++ CD_STATUS Status; ++ UINT8 Shift2MaskConverter; ++ UINT8 CurrentPortID; ++} PARSER_TEMP_DATA; ++ ++ ++typedef struct _WORKING_TABLE_DATA WORKING_TABLE_DATA; ++ ++ ++ ++typedef VOID (*COMMANDS_DECODER)(PARSER_TEMP_DATA STACK_BASED * pParserTempData); ++typedef VOID (*WRITE_IO_FUNCTION)(PARSER_TEMP_DATA STACK_BASED * pParserTempData); ++typedef UINT32 (*READ_IO_FUNCTION)(PARSER_TEMP_DATA STACK_BASED * pParserTempData); ++typedef UINT32 (*CD_GET_PARAMETERS)(PARSER_TEMP_DATA STACK_BASED * pParserTempData); ++ ++typedef struct _COMMANDS_PROPERTIES ++{ ++ COMMANDS_DECODER function; ++ UINT8 destination; ++ UINT8 headersize; ++} COMMANDS_PROPERTIES; ++ ++typedef struct _INDIRECT_IO_PARSER_COMMANDS ++{ ++ COMMANDS_DECODER func; ++ UINT8 csize; ++} INDIRECT_IO_PARSER_COMMANDS; ++ ++#if (PARSER_TYPE==DRIVER_TYPE_PARSER) ++#pragma pack(pop) ++#endif ++ ++#endif +diff --git a/src/AtomBios/includes/CD_binding.h b/src/AtomBios/includes/CD_binding.h +new file mode 100644 +index 0000000..7b021d3 +--- /dev/null ++++ b/src/AtomBios/includes/CD_binding.h +@@ -0,0 +1,46 @@ ++/* ++ * Copyright 2006-2007 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in ++ * all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++#ifdef NT_BUILD ++#ifdef LH_BUILD ++#include ++#else ++#include ++#endif // LH_BUILD ++#endif // NT_BUILD ++ ++ ++#if ((defined DBG) || (defined DEBUG)) ++#define DEBUG_PARSER 1 // enable parser debug output ++#endif ++ ++#define USE_SWITCH_COMMAND 1 ++#define DRIVER_TYPE_PARSER 0x48 ++ ++#define PARSER_TYPE DRIVER_TYPE_PARSER ++ ++#define AllocateWorkSpace(x,y) AllocateMemory(pDeviceData,y) ++#define FreeWorkSpace(x,y) ReleaseMemory(x,y) ++ ++#define RELATIVE_TO_BIOS_IMAGE( x ) ((ULONG_PTR)x + (ULONG_PTR)((DEVICE_DATA*)pParserTempData->pDeviceData->pBIOS_Image)) ++#define RELATIVE_TO_TABLE( x ) (x + (UCHAR *)(pParserTempData->pWorkingTableData->pTableHead)) ++ +diff --git a/src/AtomBios/includes/CD_hw_services.h b/src/AtomBios/includes/CD_hw_services.h +new file mode 100644 +index 0000000..529fde5 +--- /dev/null ++++ b/src/AtomBios/includes/CD_hw_services.h +@@ -0,0 +1,318 @@ ++/* ++ * Copyright 2006-2007 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in ++ * all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++#ifndef _HW_SERVICES_INTERFACE_ ++#define _HW_SERVICES_INTERFACE_ ++ ++#include "CD_Common_Types.h" ++#include "CD_Structs.h" ++ ++ ++// CD - from Command Decoder ++typedef UINT16 CD_REG_INDEX; ++typedef UINT8 CD_PCI_OFFSET; ++typedef UINT16 CD_FB_OFFSET; ++typedef UINT16 CD_SYS_IO_PORT; ++typedef UINT8 CD_MEM_TYPE; ++typedef UINT8 CD_MEM_SIZE; ++ ++typedef VOID * CD_VIRT_ADDR; ++typedef UINT32 CD_PHYS_ADDR; ++typedef UINT32 CD_IO_ADDR; ++ ++/***********************ATI Registers access routines**************************/ ++ ++ VOID ReadIndReg32(PARSER_TEMP_DATA STACK_BASED * pParserTempData); ++ ++ VOID WriteIndReg32(PARSER_TEMP_DATA STACK_BASED * pParserTempData); ++ ++ UINT32 ReadReg32(PARSER_TEMP_DATA STACK_BASED * pParserTempData); ++ ++ VOID WriteReg32(PARSER_TEMP_DATA STACK_BASED * pParserTempData); ++ ++ UINT32 ReadPLL32(PARSER_TEMP_DATA STACK_BASED * pParserTempData); ++ ++ VOID WritePLL32(PARSER_TEMP_DATA STACK_BASED * pParserTempData); ++ ++ UINT32 ReadMC32(PARSER_TEMP_DATA STACK_BASED * pParserTempData); ++ ++ VOID WriteMC32(PARSER_TEMP_DATA STACK_BASED * pParserTempData); ++ ++/************************PCI Registers access routines*************************/ ++ ++ UINT8 ReadPCIReg8(PARSER_TEMP_DATA STACK_BASED * pParserTempData); ++ ++ UINT16 ReadPCIReg16(PARSER_TEMP_DATA STACK_BASED * pParserTempData); ++ ++ UINT32 ReadPCIReg32(PARSER_TEMP_DATA STACK_BASED * pParserTempData); ++ ++ VOID WritePCIReg8(PARSER_TEMP_DATA STACK_BASED * pParserTempData); ++ ++ VOID WritePCIReg16(PARSER_TEMP_DATA STACK_BASED * pParserTempData); ++ ++ VOID WritePCIReg32(PARSER_TEMP_DATA STACK_BASED * pParserTempData); ++ ++/***************************Frame buffer access routines************************/ ++ ++ UINT32 ReadFrameBuffer32(PARSER_TEMP_DATA STACK_BASED * pParserTempData); ++ ++ VOID WriteFrameBuffer32(PARSER_TEMP_DATA STACK_BASED * pParserTempData); ++ ++/******************System IO Registers access routines********************/ ++ ++ UINT8 ReadSysIOReg8(PARSER_TEMP_DATA STACK_BASED * pParserTempData); ++ ++ UINT16 ReadSysIOReg16(PARSER_TEMP_DATA STACK_BASED * pParserTempData); ++ ++ UINT32 ReadSysIOReg32(PARSER_TEMP_DATA STACK_BASED * pParserTempData); ++ ++ VOID WriteSysIOReg8(PARSER_TEMP_DATA STACK_BASED * pParserTempData); ++ ++ VOID WriteSysIOReg16(PARSER_TEMP_DATA STACK_BASED * pParserTempData); ++ ++ VOID WriteSysIOReg32(PARSER_TEMP_DATA STACK_BASED * pParserTempData); ++ ++/****************************Delay routines****************************************/ ++ ++ VOID DelayMicroseconds(PARSER_TEMP_DATA STACK_BASED * pParserTempData); // take WORKING_TABLE_DATA->SourceData32 as a delay value ++ ++ VOID DelayMilliseconds(PARSER_TEMP_DATA STACK_BASED * pParserTempData); ++ ++ VOID PostCharOutput(PARSER_TEMP_DATA STACK_BASED * pParserTempData); ++ ++ VOID CallerDebugFunc(PARSER_TEMP_DATA STACK_BASED * pParserTempData); ++ ++ ++//************************Tracing/Debugging routines and macroses******************/ ++#define KEYPRESSED -1 ++ ++#if (DEBUG_PARSER != 0) ++ ++#ifdef DRIVER_PARSER ++ ++VOID CD_print_string (DEVICE_DATA STACK_BASED *pDeviceData, UINT8 *str); ++VOID CD_print_value (DEVICE_DATA STACK_BASED *pDeviceData, ULONG_PTR value, UINT16 value_type ); ++ ++// Level 1 : can use WorkingTableData or pDeviceData ++#define CD_TRACE_DL1(string) CD_print_string(pDeviceData, string); ++#define CD_TRACETAB_DL1(string) CD_TRACE_DL1("\n");CD_TRACE_DL1(string) ++#define CD_TRACEDEC_DL1(value) CD_print_value( pDeviceData, (ULONG_PTR)value, PARSER_DEC); ++#define CD_TRACEHEX_DL1(value) CD_print_value( pDeviceData, (ULONG_PTR)value, PARSER_HEX); ++ ++// Level 2:can use pWorkingTableData ++#define CD_TRACE_DL2(string) CD_print_string( pWorkingTableData->pParserTempData->pDeviceData, string); ++#define CD_TRACETAB_DL2(string) CD_TRACE_DL2("\n");CD_TRACE_DL2(string) ++#define CD_TRACEDEC_DL2(value) CD_print_value( pWorkingTableData->pParserTempData->pDeviceData, (ULONG_PTR)value, PARSER_DEC); ++#define CD_TRACEHEX_DL2(value) CD_print_value( pWorkingTableData->pParserTempData->pDeviceData, (ULONG_PTR)value, PARSER_HEX); ++ ++// Level 3:can use pWorkingTableData ++#define CD_TRACE_DL3(string) CD_print_string( pWorkingTableData->pParserTempData->pDeviceData, string); ++#define CD_TRACETAB_DL3(string) CD_TRACE_DL3("\n");CD_TRACE_DL3(string) ++#define CD_TRACEDEC_DL3(value) CD_print_value( pWorkingTableData->pParserTempData->pDeviceData, value, PARSER_DEC); ++#define CD_TRACEHEX_DL3(value) CD_print_value( pWorkingTableData->pParserTempData->pDeviceData, value, PARSER_HEX); ++ ++#define CD_TRACE(string) ++#define CD_WAIT(what) ++#define CD_BREAKPOINT() ++ ++#else ++ ++ ++VOID CD_assert (UINT8 *file, INTN lineno); //output file/line to debug console ++VOID CD_postcode(UINT8 value); //output post code to debug console ++VOID CD_print (UINT8 *str); //output text to debug console ++VOID CD_print_dec(UINTN value); //output value in decimal format to debug console ++VOID CD_print_hex(UINT32 value, UINT8 len); //output value in hexadecimal format to debug console ++VOID CD_print_buf(UINT8 *p, UINTN len); //output dump of memory to debug console ++VOID CD_wait(INT32 what); //wait for KEYPRESSED=-1 or Delay value expires ++VOID CD_breakpoint(); //insert int3 opcode or 0xF1 (for American Arium) ++ ++#define CD_ASSERT(condition) if(!(condition)) CD_assert(__FILE__, __LINE__) ++#define CD_POSTCODE(value) CD_postcode(value) ++#define CD_TRACE(string) CD_print(string) ++#define CD_TRACETAB(string) CD_print(string) ++#define CD_TRACEDEC(value) CD_print_dec( (UINTN)(value)) ++#define CD_TRACEHEX(value) CD_print_hex( (UINT32)(value), sizeof(value) ) ++#define CD_TRACEBUF(pointer, len) CD_print_buf( (UINT8 *)(pointer), (UINTN) len) ++#define CD_WAIT(what) CD_wait((INT32)what) ++#define CD_BREAKPOINT() CD_breakpoint() ++ ++#if (DEBUG_PARSER == 4) ++#define CD_ASSERT_DL4(condition) if(!(condition)) CD_assert(__FILE__, __LINE__) ++#define CD_POSTCODE_DL4(value) CD_postcode(value) ++#define CD_TRACE_DL4(string) CD_print(string) ++#define CD_TRACETAB_DL4(string) CD_print("\n\t\t");CD_print(string) ++#define CD_TRACEDEC_DL4(value) CD_print_dec( (UINTN)(value)) ++#define CD_TRACEHEX_DL4(value) CD_print_hex( (UINT32)(value), sizeof(value) ) ++#define CD_TRACEBUF_DL4(pointer, len) CD_print_buf( (UINT8 *)(pointer), (UINTN) len) ++#define CD_WAIT_DL4(what) CD_wait((INT32)what) ++#define CD_BREAKPOINT_DL4() CD_breakpoint() ++#else ++#define CD_ASSERT_DL4(condition) ++#define CD_POSTCODE_DL4(value) ++#define CD_TRACE_DL4(string) ++#define CD_TRACETAB_DL4(string) ++#define CD_TRACEDEC_DL4(value) ++#define CD_TRACEHEX_DL4(value) ++#define CD_TRACEBUF_DL4(pointer, len) ++#define CD_WAIT_DL4(what) ++#define CD_BREAKPOINT_DL4() ++#endif ++ ++#if (DEBUG_PARSER >= 3) ++#define CD_ASSERT_DL3(condition) if(!(condition)) CD_assert(__FILE__, __LINE__) ++#define CD_POSTCODE_DL3(value) CD_postcode(value) ++#define CD_TRACE_DL3(string) CD_print(string) ++#define CD_TRACETAB_DL3(string) CD_print("\n\t\t");CD_print(string) ++#define CD_TRACEDEC_DL3(value) CD_print_dec( (UINTN)(value)) ++#define CD_TRACEHEX_DL3(value) CD_print_hex( (UINT32)(value), sizeof(value) ) ++#define CD_TRACEBUF_DL3(pointer, len) CD_print_buf( (UINT8 *)(pointer), (UINTN) len) ++#define CD_WAIT_DL3(what) CD_wait((INT32)what) ++#define CD_BREAKPOINT_DL3() CD_breakpoint() ++#else ++#define CD_ASSERT_DL3(condition) ++#define CD_POSTCODE_DL3(value) ++#define CD_TRACE_DL3(string) ++#define CD_TRACETAB_DL3(string) ++#define CD_TRACEDEC_DL3(value) ++#define CD_TRACEHEX_DL3(value) ++#define CD_TRACEBUF_DL3(pointer, len) ++#define CD_WAIT_DL3(what) ++#define CD_BREAKPOINT_DL3() ++#endif ++ ++ ++#if (DEBUG_PARSER >= 2) ++#define CD_ASSERT_DL2(condition) if(!(condition)) CD_assert(__FILE__, __LINE__) ++#define CD_POSTCODE_DL2(value) CD_postcode(value) ++#define CD_TRACE_DL2(string) CD_print(string) ++#define CD_TRACETAB_DL2(string) CD_print("\n\t");CD_print(string) ++#define CD_TRACEDEC_DL2(value) CD_print_dec( (UINTN)(value)) ++#define CD_TRACEHEX_DL2(value) CD_print_hex( (UINT32)(value), sizeof(value) ) ++#define CD_TRACEBUF_DL2(pointer, len) CD_print_buf( (UINT8 *)(pointer), (UINTN) len) ++#define CD_WAIT_DL2(what) CD_wait((INT32)what) ++#define CD_BREAKPOINT_DL2() CD_breakpoint() ++#else ++#define CD_ASSERT_DL2(condition) ++#define CD_POSTCODE_DL2(value) ++#define CD_TRACE_DL2(string) ++#define CD_TRACETAB_DL2(string) ++#define CD_TRACEDEC_DL2(value) ++#define CD_TRACEHEX_DL2(value) ++#define CD_TRACEBUF_DL2(pointer, len) ++#define CD_WAIT_DL2(what) ++#define CD_BREAKPOINT_DL2() ++#endif ++ ++ ++#if (DEBUG_PARSER >= 1) ++#define CD_ASSERT_DL1(condition) if(!(condition)) CD_assert(__FILE__, __LINE__) ++#define CD_POSTCODE_DL1(value) CD_postcode(value) ++#define CD_TRACE_DL1(string) CD_print(string) ++#define CD_TRACETAB_DL1(string) CD_print("\n");CD_print(string) ++#define CD_TRACEDEC_DL1(value) CD_print_dec( (UINTN)(value)) ++#define CD_TRACEHEX_DL1(value) CD_print_hex( (UINT32)(value), sizeof(value) ) ++#define CD_TRACEBUF_DL1(pointer, len) CD_print_buf( (UINT8 *)(pointer), (UINTN) len) ++#define CD_WAIT_DL1(what) CD_wait((INT32)what) ++#define CD_BREAKPOINT_DL1() CD_breakpoint() ++#else ++#define CD_ASSERT_DL1(condition) ++#define CD_POSTCODE_DL1(value) ++#define CD_TRACE_DL1(string) ++#define CD_TRACETAB_DL1(string) ++#define CD_TRACEDEC_DL1(value) ++#define CD_TRACEHEX_DL1(value) ++#define CD_TRACEBUF_DL1(pointer, len) ++#define CD_WAIT_DL1(what) ++#define CD_BREAKPOINT_DL1() ++#endif ++ ++#endif //#ifdef DRIVER_PARSER ++ ++ ++#else ++ ++#define CD_ASSERT(condition) ++#define CD_POSTCODE(value) ++#define CD_TRACE(string) ++#define CD_TRACEDEC(value) ++#define CD_TRACEHEX(value) ++#define CD_TRACEBUF(pointer, len) ++#define CD_WAIT(what) ++#define CD_BREAKPOINT() ++ ++#define CD_ASSERT_DL4(condition) ++#define CD_POSTCODE_DL4(value) ++#define CD_TRACE_DL4(string) ++#define CD_TRACETAB_DL4(string) ++#define CD_TRACEDEC_DL4(value) ++#define CD_TRACEHEX_DL4(value) ++#define CD_TRACEBUF_DL4(pointer, len) ++#define CD_WAIT_DL4(what) ++#define CD_BREAKPOINT_DL4() ++ ++#define CD_ASSERT_DL3(condition) ++#define CD_POSTCODE_DL3(value) ++#define CD_TRACE_DL3(string) ++#define CD_TRACETAB_DL3(string) ++#define CD_TRACEDEC_DL3(value) ++#define CD_TRACEHEX_DL3(value) ++#define CD_TRACEBUF_DL3(pointer, len) ++#define CD_WAIT_DL3(what) ++#define CD_BREAKPOINT_DL3() ++ ++#define CD_ASSERT_DL2(condition) ++#define CD_POSTCODE_DL2(value) ++#define CD_TRACE_DL2(string) ++#define CD_TRACETAB_DL2(string) ++#define CD_TRACEDEC_DL2(value) ++#define CD_TRACEHEX_DL2(value) ++#define CD_TRACEBUF_DL2(pointer, len) ++#define CD_WAIT_DL2(what) ++#define CD_BREAKPOINT_DL2() ++ ++#define CD_ASSERT_DL1(condition) ++#define CD_POSTCODE_DL1(value) ++#define CD_TRACE_DL1(string) ++#define CD_TRACETAB_DL1(string) ++#define CD_TRACEDEC_DL1(value) ++#define CD_TRACEHEX_DL1(value) ++#define CD_TRACEBUF_DL1(pointer, len) ++#define CD_WAIT_DL1(what) ++#define CD_BREAKPOINT_DL1() ++ ++ ++#endif //#if (DEBUG_PARSER > 0) ++ ++ ++#ifdef CHECKSTACK ++VOID CD_fillstack(UINT16 size); ++UINT16 CD_checkstack(UINT16 size); ++#define CD_CHECKSTACK(stacksize) CD_checkstack(stacksize) ++#define CD_FILLSTACK(stacksize) CD_fillstack(stacksize) ++#else ++#define CD_CHECKSTACK(stacksize) 0 ++#define CD_FILLSTACK(stacksize) ++#endif ++ ++ ++#endif +diff --git a/src/AtomBios/includes/Decoder.h b/src/AtomBios/includes/Decoder.h +new file mode 100644 +index 0000000..24c25fc +--- /dev/null ++++ b/src/AtomBios/includes/Decoder.h +@@ -0,0 +1,86 @@ ++/* ++ * Copyright 2006-2007 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in ++ * all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++/*++ ++ ++Module Name: ++ ++Decoder.h ++ ++Abstract: ++ ++Includes all helper headers ++ ++Revision History: ++ ++NEG:27.08.2002 Initiated. ++--*/ ++#ifndef _DECODER_H_ ++#define _DECODER_H_ ++#define WS_QUOTIENT_C 64 ++#define WS_REMINDER_C (WS_QUOTIENT_C+1) ++#define WS_DATAPTR_C (WS_REMINDER_C+1) ++#define WS_SHIFT_C (WS_DATAPTR_C+1) ++#define WS_OR_MASK_C (WS_SHIFT_C+1) ++#define WS_AND_MASK_C (WS_OR_MASK_C+1) ++#define WS_FB_WINDOW_C (WS_AND_MASK_C+1) ++#define WS_ATTRIBUTES_C (WS_FB_WINDOW_C+1) ++#define PARSER_VERSION_MAJOR 0x00000000 ++#define PARSER_VERSION_MINOR 0x0000000E ++#define PARSER_VERSION (PARSER_VERSION_MAJOR | PARSER_VERSION_MINOR) ++#include "CD_binding.h" ++#include "CD_Common_Types.h" ++#include "CD_hw_services.h" ++#include "CD_Structs.h" ++#include "CD_Definitions.h" ++#include "CD_Opcodes.h" ++ ++#define SOURCE_ONLY_CMD_TYPE 0//0xFE ++#define SOURCE_DESTINATION_CMD_TYPE 1//0xFD ++#define DESTINATION_ONLY_CMD_TYPE 2//0xFC ++ ++#define ACCESS_TYPE_BYTE 0//0xF9 ++#define ACCESS_TYPE_WORD 1//0xF8 ++#define ACCESS_TYPE_DWORD 2//0xF7 ++#define SWITCH_TYPE_ACCESS 3//0xF6 ++ ++#define CD_CONTINUE 0//0xFB ++#define CD_STOP 1//0xFA ++ ++ ++#define IS_END_OF_TABLE(cmd) ((cmd) == EOT_OPCODE) ++#define IS_COMMAND_VALID(cmd) (((cmd)<=LastValidCommand)&&((cmd)>=FirstValidCommand)) ++#define IS_IT_SHIFT_COMMAND(Opcode) ((Opcode<=SHIFT_RIGHT_MC_OPCODE)&&(Opcode>=SHIFT_LEFT_REG_OPCODE)) ++#define IS_IT_XXXX_COMMAND(Group, Opcode) ((Opcode<=Group##_MC_OPCODE)&&(Opcode>=Group##_REG_OPCODE)) ++#define CheckCaseAndAdjustIP_Macro(size) \ ++ if (pParserTempData->SourceData32==(UINT32)((CASE_OFFSET*)pParserTempData->pWorkingTableData->IP)->XX_Access.size##.Access.Value){\ ++ pParserTempData->CommandSpecific.ContinueSwitch = CD_STOP;\ ++ pParserTempData->pWorkingTableData->IP =(COMMAND_HEADER_POINTER *) RELATIVE_TO_TABLE(((CASE_OFFSET*)pParserTempData->pWorkingTableData->IP)->XX_Access.size##.Access.JumpOffset);\ ++ }else{\ ++ pParserTempData->pWorkingTableData->IP+=(sizeof (CASE_##size##ACCESS)\ ++ +sizeof(((CASE_OFFSET*)pParserTempData->pWorkingTableData->IP)->CaseSignature));\ ++ } ++ ++#endif ++/* pWorkingTableData->pCmd->Header.Attribute.SourceAlignment=alignmentLowerWord;\*/ ++ ++// EOF +diff --git a/src/AtomBios/includes/ObjectID.h b/src/AtomBios/includes/ObjectID.h +new file mode 100644 +index 0000000..a630c69 +--- /dev/null ++++ b/src/AtomBios/includes/ObjectID.h +@@ -0,0 +1,448 @@ ++/* ++* Copyright 2006-2007 Advanced Micro Devices, Inc. ++* ++* Permission is hereby granted, free of charge, to any person obtaining a ++* copy of this software and associated documentation files (the "Software"), ++* to deal in the Software without restriction, including without limitation ++* the rights to use, copy, modify, merge, publish, distribute, sublicense, ++* and/or sell copies of the Software, and to permit persons to whom the ++* Software is furnished to do so, subject to the following conditions: ++* ++* The above copyright notice and this permission notice shall be included in ++* all copies or substantial portions of the Software. ++* ++* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR ++* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++* OTHER DEALINGS IN THE SOFTWARE. ++*/ ++/* based on stg/asic_reg/drivers/inc/asic_reg/ObjectID.h ver 23 */ ++ ++#ifndef _OBJECTID_H ++#define _OBJECTID_H ++ ++#if defined(_X86_) ++#pragma pack(1) ++#endif ++ ++/****************************************************/ ++/* Graphics Object Type Definition */ ++/****************************************************/ ++#define GRAPH_OBJECT_TYPE_NONE 0x0 ++#define GRAPH_OBJECT_TYPE_GPU 0x1 ++#define GRAPH_OBJECT_TYPE_ENCODER 0x2 ++#define GRAPH_OBJECT_TYPE_CONNECTOR 0x3 ++#define GRAPH_OBJECT_TYPE_ROUTER 0x4 ++/* deleted */ ++ ++/****************************************************/ ++/* Encoder Object ID Definition */ ++/****************************************************/ ++#define ENCODER_OBJECT_ID_NONE 0x00 ++ ++/* Radeon Class Display Hardware */ ++#define ENCODER_OBJECT_ID_INTERNAL_LVDS 0x01 ++#define ENCODER_OBJECT_ID_INTERNAL_TMDS1 0x02 ++#define ENCODER_OBJECT_ID_INTERNAL_TMDS2 0x03 ++#define ENCODER_OBJECT_ID_INTERNAL_DAC1 0x04 ++#define ENCODER_OBJECT_ID_INTERNAL_DAC2 0x05 /* TV/CV DAC */ ++#define ENCODER_OBJECT_ID_INTERNAL_SDVOA 0x06 ++#define ENCODER_OBJECT_ID_INTERNAL_SDVOB 0x07 ++ ++/* External Third Party Encoders */ ++#define ENCODER_OBJECT_ID_SI170B 0x08 ++#define ENCODER_OBJECT_ID_CH7303 0x09 ++#define ENCODER_OBJECT_ID_CH7301 0x0A ++#define ENCODER_OBJECT_ID_INTERNAL_DVO1 0x0B /* This belongs to Radeon Class Display Hardware */ ++#define ENCODER_OBJECT_ID_EXTERNAL_SDVOA 0x0C ++#define ENCODER_OBJECT_ID_EXTERNAL_SDVOB 0x0D ++#define ENCODER_OBJECT_ID_TITFP513 0x0E ++#define ENCODER_OBJECT_ID_INTERNAL_LVTM1 0x0F /* not used for Radeon */ ++#define ENCODER_OBJECT_ID_VT1623 0x10 ++#define ENCODER_OBJECT_ID_HDMI_SI1930 0x11 ++#define ENCODER_OBJECT_ID_HDMI_INTERNAL 0x12 ++/* Kaleidoscope (KLDSCP) Class Display Hardware (internal) */ ++#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1 0x13 ++#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1 0x14 ++#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1 0x15 ++#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2 0x16 /* Shared with CV/TV and CRT */ ++#define ENCODER_OBJECT_ID_SI178 0X17 /* External TMDS (dual link, no HDCP.) */ ++#define ENCODER_OBJECT_ID_MVPU_FPGA 0x18 /* MVPU FPGA chip */ ++#define ENCODER_OBJECT_ID_INTERNAL_DDI 0x19 ++#define ENCODER_OBJECT_ID_VT1625 0x1A ++#define ENCODER_OBJECT_ID_HDMI_SI1932 0x1B ++#define ENCODER_OBJECT_ID_DP_AN9801 0x1C ++#define ENCODER_OBJECT_ID_DP_DP501 0x1D ++ ++/****************************************************/ ++/* Connector Object ID Definition */ ++/****************************************************/ ++#define CONNECTOR_OBJECT_ID_NONE 0x00 ++#define CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I 0x01 ++#define CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I 0x02 ++#define CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D 0x03 ++#define CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D 0x04 ++#define CONNECTOR_OBJECT_ID_VGA 0x05 ++#define CONNECTOR_OBJECT_ID_COMPOSITE 0x06 ++#define CONNECTOR_OBJECT_ID_SVIDEO 0x07 ++#define CONNECTOR_OBJECT_ID_YPbPr 0x08 ++#define CONNECTOR_OBJECT_ID_D_CONNECTOR 0x09 ++#define CONNECTOR_OBJECT_ID_9PIN_DIN 0x0A /* Supports both CV & TV */ ++#define CONNECTOR_OBJECT_ID_SCART 0x0B ++#define CONNECTOR_OBJECT_ID_HDMI_TYPE_A 0x0C ++#define CONNECTOR_OBJECT_ID_HDMI_TYPE_B 0x0D ++#define CONNECTOR_OBJECT_ID_LVDS 0x0E ++#define CONNECTOR_OBJECT_ID_7PIN_DIN 0x0F ++#define CONNECTOR_OBJECT_ID_PCIE_CONNECTOR 0x10 ++#define CONNECTOR_OBJECT_ID_CROSSFIRE 0x11 ++#define CONNECTOR_OBJECT_ID_HARDCODE_DVI 0x12 ++#define CONNECTOR_OBJECT_ID_DISPLAYPORT 0x13 ++ ++/* deleted */ ++ ++/****************************************************/ ++/* Router Object ID Definition */ ++/****************************************************/ ++#define ROUTER_OBJECT_ID_NONE 0x00 ++#define ROUTER_OBJECT_ID_I2C_EXTENDER_CNTL 0x01 ++ ++/****************************************************/ ++// Graphics Object ENUM ID Definition */ ++/****************************************************/ ++#define GRAPH_OBJECT_ENUM_ID1 0x01 ++#define GRAPH_OBJECT_ENUM_ID2 0x02 ++#define GRAPH_OBJECT_ENUM_ID3 0x03 ++#define GRAPH_OBJECT_ENUM_ID4 0x04 ++ ++/****************************************************/ ++/* Graphics Object ID Bit definition */ ++/****************************************************/ ++#define OBJECT_ID_MASK 0x00FF ++#define ENUM_ID_MASK 0x0700 ++#define RESERVED1_ID_MASK 0x0800 ++#define OBJECT_TYPE_MASK 0x7000 ++#define RESERVED2_ID_MASK 0x8000 ++ ++#define OBJECT_ID_SHIFT 0x00 ++#define ENUM_ID_SHIFT 0x08 ++#define OBJECT_TYPE_SHIFT 0x0C ++ ++ ++/****************************************************/ ++/* Graphics Object family definition */ ++/****************************************************/ ++#define CONSTRUCTOBJECTFAMILYID(GRAPHICS_OBJECT_TYPE, GRAPHICS_OBJECT_ID) (GRAPHICS_OBJECT_TYPE << OBJECT_TYPE_SHIFT | \ ++ GRAPHICS_OBJECT_ID << OBJECT_ID_SHIFT) ++/****************************************************/ ++/* GPU Object ID definition - Shared with BIOS */ ++/****************************************************/ ++#define GPU_ENUM_ID1 ( GRAPH_OBJECT_TYPE_GPU << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT) ++ ++/****************************************************/ ++/* Encoder Object ID definition - Shared with BIOS */ ++/****************************************************/ ++/* ++#define ENCODER_INTERNAL_LVDS_ENUM_ID1 0x2101 ++#define ENCODER_INTERNAL_TMDS1_ENUM_ID1 0x2102 ++#define ENCODER_INTERNAL_TMDS2_ENUM_ID1 0x2103 ++#define ENCODER_INTERNAL_DAC1_ENUM_ID1 0x2104 ++#define ENCODER_INTERNAL_DAC2_ENUM_ID1 0x2105 ++#define ENCODER_INTERNAL_SDVOA_ENUM_ID1 0x2106 ++#define ENCODER_INTERNAL_SDVOB_ENUM_ID1 0x2107 ++#define ENCODER_SIL170B_ENUM_ID1 0x2108 ++#define ENCODER_CH7303_ENUM_ID1 0x2109 ++#define ENCODER_CH7301_ENUM_ID1 0x210A ++#define ENCODER_INTERNAL_DVO1_ENUM_ID1 0x210B ++#define ENCODER_EXTERNAL_SDVOA_ENUM_ID1 0x210C ++#define ENCODER_EXTERNAL_SDVOB_ENUM_ID1 0x210D ++#define ENCODER_TITFP513_ENUM_ID1 0x210E ++#define ENCODER_INTERNAL_LVTM1_ENUM_ID1 0x210F ++#define ENCODER_VT1623_ENUM_ID1 0x2110 ++#define ENCODER_HDMI_SI1930_ENUM_ID1 0x2111 ++#define ENCODER_HDMI_INTERNAL_ENUM_ID1 0x2112 ++#define ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1 0x2113 ++#define ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1 0x2114 ++#define ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1 0x2115 ++#define ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1 0x2116 ++#define ENCODER_SI178_ENUM_ID1 0x2117 ++#define ENCODER_MVPU_FPGA_ENUM_ID1 0x2118 ++#define ENCODER_INTERNAL_DDI_ENUM_ID1 0x2119 ++#define ENCODER_VT1625_ENUM_ID1 0x211A ++*/ ++#define ENCODER_INTERNAL_LVDS_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ ENCODER_OBJECT_ID_INTERNAL_LVDS << OBJECT_ID_SHIFT) ++ ++#define ENCODER_INTERNAL_TMDS1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ ENCODER_OBJECT_ID_INTERNAL_TMDS1 << OBJECT_ID_SHIFT) ++ ++#define ENCODER_INTERNAL_TMDS2_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ ENCODER_OBJECT_ID_INTERNAL_TMDS2 << OBJECT_ID_SHIFT) ++ ++#define ENCODER_INTERNAL_DAC1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ ENCODER_OBJECT_ID_INTERNAL_DAC1 << OBJECT_ID_SHIFT) ++ ++#define ENCODER_INTERNAL_DAC2_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ ENCODER_OBJECT_ID_INTERNAL_DAC2 << OBJECT_ID_SHIFT) ++ ++#define ENCODER_INTERNAL_SDVOA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ ENCODER_OBJECT_ID_INTERNAL_SDVOA << OBJECT_ID_SHIFT) ++ ++#define ENCODER_INTERNAL_SDVOA_ENUM_ID2 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ ++ ENCODER_OBJECT_ID_INTERNAL_SDVOA << OBJECT_ID_SHIFT) ++ ++#define ENCODER_INTERNAL_SDVOB_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ ENCODER_OBJECT_ID_INTERNAL_SDVOB << OBJECT_ID_SHIFT) ++ ++#define ENCODER_SIL170B_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ ENCODER_OBJECT_ID_SI170B << OBJECT_ID_SHIFT) ++ ++#define ENCODER_CH7303_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ ENCODER_OBJECT_ID_CH7303 << OBJECT_ID_SHIFT) ++ ++#define ENCODER_CH7301_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ ENCODER_OBJECT_ID_CH7301 << OBJECT_ID_SHIFT) ++ ++#define ENCODER_INTERNAL_DVO1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ ENCODER_OBJECT_ID_INTERNAL_DVO1 << OBJECT_ID_SHIFT) ++ ++#define ENCODER_EXTERNAL_SDVOA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ ENCODER_OBJECT_ID_EXTERNAL_SDVOA << OBJECT_ID_SHIFT) ++ ++#define ENCODER_EXTERNAL_SDVOA_ENUM_ID2 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ ++ ENCODER_OBJECT_ID_EXTERNAL_SDVOA << OBJECT_ID_SHIFT) ++ ++ ++#define ENCODER_EXTERNAL_SDVOB_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ ENCODER_OBJECT_ID_EXTERNAL_SDVOB << OBJECT_ID_SHIFT) ++ ++ ++#define ENCODER_TITFP513_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ ENCODER_OBJECT_ID_TITFP513 << OBJECT_ID_SHIFT) ++ ++#define ENCODER_INTERNAL_LVTM1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ ENCODER_OBJECT_ID_INTERNAL_LVTM1 << OBJECT_ID_SHIFT) ++ ++#define ENCODER_VT1623_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ ENCODER_OBJECT_ID_VT1623 << OBJECT_ID_SHIFT) ++ ++#define ENCODER_HDMI_SI1930_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ ENCODER_OBJECT_ID_HDMI_SI1930 << OBJECT_ID_SHIFT) ++ ++#define ENCODER_HDMI_INTERNAL_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ ENCODER_OBJECT_ID_HDMI_INTERNAL << OBJECT_ID_SHIFT) ++ ++#define ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1 << OBJECT_ID_SHIFT) ++ ++ ++#define ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID2 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ ++ ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1 << OBJECT_ID_SHIFT) ++ ++ ++#define ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1 << OBJECT_ID_SHIFT) ++ ++#define ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1 << OBJECT_ID_SHIFT) ++ ++#define ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2 << OBJECT_ID_SHIFT) // Shared with CV/TV and CRT ++ ++#define ENCODER_SI178_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ ENCODER_OBJECT_ID_SI178 << OBJECT_ID_SHIFT) ++ ++#define ENCODER_MVPU_FPGA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ ENCODER_OBJECT_ID_MVPU_FPGA << OBJECT_ID_SHIFT) ++ ++#define ENCODER_INTERNAL_DDI_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ ENCODER_OBJECT_ID_INTERNAL_DDI << OBJECT_ID_SHIFT) ++ ++#define ENCODER_VT1625_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ ENCODER_OBJECT_ID_VT1625 << OBJECT_ID_SHIFT) ++ ++#define ENCODER_HDMI_SI1932_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ ENCODER_OBJECT_ID_HDMI_SI1932 << OBJECT_ID_SHIFT) ++ ++#define ENCODER_DP_DP501_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ ENCODER_OBJECT_ID_DP_DP501 << OBJECT_ID_SHIFT) ++ ++#define ENCODER_DP_AN9801_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ ENCODER_OBJECT_ID_DP_AN9801 << OBJECT_ID_SHIFT) ++/****************************************************/ ++/* Connector Object ID definition - Shared with BIOS */ ++/****************************************************/ ++/* ++#define CONNECTOR_SINGLE_LINK_DVI_I_ENUM_ID1 0x3101 ++#define CONNECTOR_DUAL_LINK_DVI_I_ENUM_ID1 0x3102 ++#define CONNECTOR_SINGLE_LINK_DVI_D_ENUM_ID1 0x3103 ++#define CONNECTOR_DUAL_LINK_DVI_D_ENUM_ID1 0x3104 ++#define CONNECTOR_VGA_ENUM_ID1 0x3105 ++#define CONNECTOR_COMPOSITE_ENUM_ID1 0x3106 ++#define CONNECTOR_SVIDEO_ENUM_ID1 0x3107 ++#define CONNECTOR_YPbPr_ENUM_ID1 0x3108 ++#define CONNECTOR_D_CONNECTORE_ENUM_ID1 0x3109 ++#define CONNECTOR_9PIN_DIN_ENUM_ID1 0x310A ++#define CONNECTOR_SCART_ENUM_ID1 0x310B ++#define CONNECTOR_HDMI_TYPE_A_ENUM_ID1 0x310C ++#define CONNECTOR_HDMI_TYPE_B_ENUM_ID1 0x310D ++#define CONNECTOR_LVDS_ENUM_ID1 0x310E ++#define CONNECTOR_7PIN_DIN_ENUM_ID1 0x310F ++#define CONNECTOR_PCIE_CONNECTOR_ENUM_ID1 0x3110 ++*/ ++#define CONNECTOR_LVDS_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ CONNECTOR_OBJECT_ID_LVDS << OBJECT_ID_SHIFT) ++ ++#define CONNECTOR_SINGLE_LINK_DVI_I_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I << OBJECT_ID_SHIFT) ++ ++#define CONNECTOR_SINGLE_LINK_DVI_I_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ ++ CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I << OBJECT_ID_SHIFT) ++ ++#define CONNECTOR_DUAL_LINK_DVI_I_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I << OBJECT_ID_SHIFT) ++ ++#define CONNECTOR_DUAL_LINK_DVI_I_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ ++ CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I << OBJECT_ID_SHIFT) ++ ++#define CONNECTOR_SINGLE_LINK_DVI_D_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D << OBJECT_ID_SHIFT) ++ ++#define CONNECTOR_DUAL_LINK_DVI_D_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D << OBJECT_ID_SHIFT) ++ ++#define CONNECTOR_VGA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ CONNECTOR_OBJECT_ID_VGA << OBJECT_ID_SHIFT) ++ ++#define CONNECTOR_COMPOSITE_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ CONNECTOR_OBJECT_ID_COMPOSITE << OBJECT_ID_SHIFT) ++ ++#define CONNECTOR_SVIDEO_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ CONNECTOR_OBJECT_ID_SVIDEO << OBJECT_ID_SHIFT) ++ ++#define CONNECTOR_YPbPr_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ CONNECTOR_OBJECT_ID_YPbPr << OBJECT_ID_SHIFT) ++ ++#define CONNECTOR_D_CONNECTOR_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ CONNECTOR_OBJECT_ID_D_CONNECTOR << OBJECT_ID_SHIFT) ++ ++#define CONNECTOR_9PIN_DIN_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ CONNECTOR_OBJECT_ID_9PIN_DIN << OBJECT_ID_SHIFT) ++ ++#define CONNECTOR_SCART_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ CONNECTOR_OBJECT_ID_SCART << OBJECT_ID_SHIFT) ++ ++#define CONNECTOR_HDMI_TYPE_A_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ CONNECTOR_OBJECT_ID_HDMI_TYPE_A << OBJECT_ID_SHIFT) ++ ++#define CONNECTOR_HDMI_TYPE_B_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ CONNECTOR_OBJECT_ID_HDMI_TYPE_B << OBJECT_ID_SHIFT) ++ ++#define CONNECTOR_7PIN_DIN_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ CONNECTOR_OBJECT_ID_7PIN_DIN << OBJECT_ID_SHIFT) ++ ++#define CONNECTOR_PCIE_CONNECTOR_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ CONNECTOR_OBJECT_ID_PCIE_CONNECTOR << OBJECT_ID_SHIFT) ++ ++#define CONNECTOR_CROSSFIRE_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ CONNECTOR_OBJECT_ID_CROSSFIRE << OBJECT_ID_SHIFT) ++ ++#define CONNECTOR_CROSSFIRE_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ ++ CONNECTOR_OBJECT_ID_CROSSFIRE << OBJECT_ID_SHIFT) ++ ++ ++#define CONNECTOR_HARDCODE_DVI_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ CONNECTOR_OBJECT_ID_HARDCODE_DVI << OBJECT_ID_SHIFT) ++ ++#define CONNECTOR_HARDCODE_DVI_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ ++ CONNECTOR_OBJECT_ID_HARDCODE_DVI << OBJECT_ID_SHIFT) ++ ++#define CONNECTOR_DISPLAYPORT_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT) ++/****************************************************/ ++/* Router Object ID definition - Shared with BIOS */ ++/****************************************************/ ++#define ROUTER_I2C_EXTENDER_CNTL_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ROUTER << OBJECT_TYPE_SHIFT |\ ++ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ++ ROUTER_OBJECT_ID_I2C_EXTENDER_CNTL << OBJECT_ID_SHIFT) ++ ++/* deleted */ ++ ++/****************************************************/ ++/* Object Cap definition - Shared with BIOS */ ++/****************************************************/ ++#define GRAPHICS_OBJECT_CAP_I2C 0x00000001L ++#define GRAPHICS_OBJECT_CAP_TABLE_ID 0x00000002L ++ ++ ++#define GRAPHICS_OBJECT_I2CCOMMAND_TABLE_ID 0x01 ++#define GRAPHICS_OBJECT_HOTPLUGDETECTIONINTERUPT_TABLE_ID 0x02 ++#define GRAPHICS_OBJECT_ENCODER_OUTPUT_PROTECTION_TABLE_ID 0x03 ++ ++#if defined(_X86_) ++#pragma pack() ++#endif ++ ++#endif /*GRAPHICTYPE */ ++ ++ ++ ++ +diff --git a/src/AtomBios/includes/atombios.h b/src/AtomBios/includes/atombios.h +new file mode 100644 +index 0000000..e58e302 +--- /dev/null ++++ b/src/AtomBios/includes/atombios.h +@@ -0,0 +1,4306 @@ ++/* ++ * Copyright 2006-2007 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in ++ * all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++ ++/****************************************************************************/ ++/*Portion I: Definitions shared between VBIOS and Driver */ ++/****************************************************************************/ ++ ++ ++#ifndef _ATOMBIOS_H ++#define _ATOMBIOS_H ++ ++#define ATOM_VERSION_MAJOR 0x00020000 ++#define ATOM_VERSION_MINOR 0x00000002 ++ ++#define ATOM_HEADER_VERSION (ATOM_VERSION_MAJOR | ATOM_VERSION_MINOR) ++ ++ ++#ifdef _H2INC ++ #ifndef ULONG ++ typedef unsigned long ULONG; ++ #endif ++ ++ #ifndef UCHAR ++ typedef unsigned char UCHAR; ++ #endif ++ ++ #ifndef USHORT ++ typedef unsigned short USHORT; ++ #endif ++#endif ++ ++#define ATOM_DAC_A 0 ++#define ATOM_DAC_B 1 ++#define ATOM_EXT_DAC 2 ++ ++#define ATOM_CRTC1 0 ++#define ATOM_CRTC2 1 ++ ++#define ATOM_DIGA 0 ++#define ATOM_DIGB 1 ++ ++#define ATOM_PPLL1 0 ++#define ATOM_PPLL2 1 ++ ++#define ATOM_SCALER1 0 ++#define ATOM_SCALER2 1 ++ ++#define ATOM_SCALER_DISABLE 0 ++#define ATOM_SCALER_CENTER 1 ++#define ATOM_SCALER_EXPANSION 2 ++#define ATOM_SCALER_MULTI_EX 3 ++ ++#define ATOM_DISABLE 0 ++#define ATOM_ENABLE 1 ++#define ATOM_LCD_BLOFF (ATOM_DISABLE+2) ++#define ATOM_LCD_BLON (ATOM_ENABLE+2) ++#define ATOM_LCD_BL_BRIGHTNESS_CONTROL (ATOM_ENABLE+3) ++#define ATOM_LCD_SELFTEST_START (ATOM_DISABLE+5) ++#define ATOM_LCD_SELFTEST_STOP (ATOM_ENABLE+5) ++#define ATOM_ENCODER_INIT (ATOM_DISABLE+7) ++ ++#define ATOM_BLANKING 1 ++#define ATOM_BLANKING_OFF 0 ++ ++#define ATOM_CURSOR1 0 ++#define ATOM_CURSOR2 1 ++ ++#define ATOM_ICON1 0 ++#define ATOM_ICON2 1 ++ ++#define ATOM_CRT1 0 ++#define ATOM_CRT2 1 ++ ++#define ATOM_TV_NTSC 1 ++#define ATOM_TV_NTSCJ 2 ++#define ATOM_TV_PAL 3 ++#define ATOM_TV_PALM 4 ++#define ATOM_TV_PALCN 5 ++#define ATOM_TV_PALN 6 ++#define ATOM_TV_PAL60 7 ++#define ATOM_TV_SECAM 8 ++#define ATOM_TV_CV 16 ++ ++#define ATOM_DAC1_PS2 1 ++#define ATOM_DAC1_CV 2 ++#define ATOM_DAC1_NTSC 3 ++#define ATOM_DAC1_PAL 4 ++ ++#define ATOM_DAC2_PS2 ATOM_DAC1_PS2 ++#define ATOM_DAC2_CV ATOM_DAC1_CV ++#define ATOM_DAC2_NTSC ATOM_DAC1_NTSC ++#define ATOM_DAC2_PAL ATOM_DAC1_PAL ++ ++#define ATOM_PM_ON 0 ++#define ATOM_PM_STANDBY 1 ++#define ATOM_PM_SUSPEND 2 ++#define ATOM_PM_OFF 3 ++ ++/* Bit0:{=0:single, =1:dual}, ++ Bit1 {=0:666RGB, =1:888RGB}, ++ Bit2:3:{Grey level} ++ Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888}*/ ++ ++#define ATOM_PANEL_MISC_DUAL 0x00000001 ++#define ATOM_PANEL_MISC_888RGB 0x00000002 ++#define ATOM_PANEL_MISC_GREY_LEVEL 0x0000000C ++#define ATOM_PANEL_MISC_FPDI 0x00000010 ++#define ATOM_PANEL_MISC_GREY_LEVEL_SHIFT 2 ++#define ATOM_PANEL_MISC_SPATIAL 0x00000020 ++#define ATOM_PANEL_MISC_TEMPORAL 0x00000040 ++#define ATOM_PANEL_MISC_API_ENABLED 0x00000080 ++ ++ ++#define MEMTYPE_DDR1 "DDR1" ++#define MEMTYPE_DDR2 "DDR2" ++#define MEMTYPE_DDR3 "DDR3" ++#define MEMTYPE_DDR4 "DDR4" ++ ++#define ASIC_BUS_TYPE_PCI "PCI" ++#define ASIC_BUS_TYPE_AGP "AGP" ++#define ASIC_BUS_TYPE_PCIE "PCI_EXPRESS" ++ ++/* Maximum size of that FireGL flag string */ ++ ++#define ATOM_FIREGL_FLAG_STRING "FGL" //Flag used to enable FireGL Support ++#define ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING 3 //sizeof( ATOM_FIREGL_FLAG_STRING ) ++ ++#define ATOM_FAKE_DESKTOP_STRING "DSK" //Flag used to enable mobile ASIC on Desktop ++#define ATOM_MAX_SIZE_OF_FAKE_DESKTOP_STRING ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING ++ ++#define ATOM_M54T_FLAG_STRING "M54T" //Flag used to enable M54T Support ++#define ATOM_MAX_SIZE_OF_M54T_FLAG_STRING 4 //sizeof( ATOM_M54T_FLAG_STRING ) ++ ++#define HW_ASSISTED_I2C_STATUS_FAILURE 2 ++#define HW_ASSISTED_I2C_STATUS_SUCCESS 1 ++ ++#pragma pack(1) /* BIOS data must use byte aligment */ ++ ++/* Define offset to location of ROM header. */ ++ ++#define OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER 0x00000048L ++#define OFFSET_TO_ATOM_ROM_IMAGE_SIZE 0x00000002L ++ ++#define OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE 0x94 ++#define MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE 20 /* including the terminator 0x0! */ ++#define OFFSET_TO_GET_ATOMBIOS_STRINGS_NUMBER 0x002f ++#define OFFSET_TO_GET_ATOMBIOS_STRINGS_START 0x006e ++ ++/* Common header for all ROM Data tables. ++ Every table pointed _ATOM_MASTER_DATA_TABLE has this common header. ++ And the pointer actually points to this header. */ ++ ++typedef struct _ATOM_COMMON_TABLE_HEADER ++{ ++ USHORT usStructureSize; ++ UCHAR ucTableFormatRevision; /*Change it when the Parser is not backward compatible */ ++ UCHAR ucTableContentRevision; /*Change it only when the table needs to change but the firmware */ ++ /*Image can't be updated, while Driver needs to carry the new table! */ ++}ATOM_COMMON_TABLE_HEADER; ++ ++typedef struct _ATOM_ROM_HEADER ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ UCHAR uaFirmWareSignature[4]; /*Signature to distinguish between Atombios and non-atombios, ++ atombios should init it as "ATOM", don't change the position */ ++ USHORT usBiosRuntimeSegmentAddress; ++ USHORT usProtectedModeInfoOffset; ++ USHORT usConfigFilenameOffset; ++ USHORT usCRC_BlockOffset; ++ USHORT usBIOS_BootupMessageOffset; ++ USHORT usInt10Offset; ++ USHORT usPciBusDevInitCode; ++ USHORT usIoBaseAddress; ++ USHORT usSubsystemVendorID; ++ USHORT usSubsystemID; ++ USHORT usPCI_InfoOffset; ++ USHORT usMasterCommandTableOffset; /*Offset for SW to get all command table offsets, Don't change the position */ ++ USHORT usMasterDataTableOffset; /*Offset for SW to get all data table offsets, Don't change the position */ ++ UCHAR ucExtendedFunctionCode; ++ UCHAR ucReserved; ++}ATOM_ROM_HEADER; ++ ++/*==============================Command Table Portion==================================== */ ++ ++#ifdef UEFI_BUILD ++ #define UTEMP USHORT ++ #define USHORT void* ++#endif ++ ++typedef struct _ATOM_MASTER_LIST_OF_COMMAND_TABLES{ ++ USHORT ASIC_Init; //Function Table, used by various SW components,latest version 1.1 ++ USHORT GetDisplaySurfaceSize; //Atomic Table, Used by Bios when enabling HW ICON ++ USHORT ASIC_RegistersInit; //Atomic Table, indirectly used by various SW components,called from ASIC_Init ++ USHORT VRAM_BlockVenderDetection; ++ USHORT SetClocksRatio; ++ USHORT MemoryControllerInit; //Atomic Table, indirectly used by various SW components,called from ASIC_Init ++ USHORT EnableCRTCMemReq; //Function Table,directly used by various SW components,latest version 2.1 ++ USHORT MemoryParamAdjust; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock if needed ++ USHORT DVOEncoderControl; //Function Table,directly used by various SW components,latest version 1.2 ++ USHORT GPIOPinControl; //Atomic Table, only used by Bios ++ USHORT SetEngineClock; //Function Table,directly used by various SW components,latest version 1.1 ++ USHORT SetMemoryClock; //Function Table,directly used by various SW components,latest version 1.1 ++ USHORT SetPixelClock; //Function Table,directly used by various SW components,latest version 1.2 ++ USHORT DynamicClockGating; //Atomic Table, indirectly used by various SW components,called from ASIC_Init ++ USHORT ResetMemoryDLL; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock ++ USHORT ResetMemoryDevice; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock ++ USHORT MemoryPLLInit; ++ USHORT AdjustDisplayPll; //only used by Bios ++ USHORT AdjustMemoryController; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock ++ USHORT EnableASIC_StaticPwrMgt; //Atomic Table, only used by Bios ++ USHORT ASIC_StaticPwrMgtStatusChange; //Obsolete , only used by Bios ++ USHORT DAC_LoadDetection; //Atomic Table, directly used by various SW components,latest version 1.2 ++ USHORT LVTMAEncoderControl; //Atomic Table,directly used by various SW components,latest version 1.3 ++ USHORT LCD1OutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 ++ USHORT DAC1EncoderControl; //Atomic Table, directly used by various SW components,latest version 1.1 ++ USHORT DAC2EncoderControl; //Atomic Table, directly used by various SW components,latest version 1.1 ++ USHORT DVOOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 ++ USHORT CV1OutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 ++ USHORT GetConditionalGoldenSetting; //only used by Bios ++ USHORT TVEncoderControl; //Function Table,directly used by various SW components,latest version 1.1 ++ USHORT TMDSAEncoderControl; //Atomic Table, directly used by various SW components,latest version 1.3 ++ USHORT LVDSEncoderControl; //Atomic Table, directly used by various SW components,latest version 1.3 ++ USHORT TV1OutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 ++ USHORT EnableScaler; //Atomic Table, used only by Bios ++ USHORT BlankCRTC; //Atomic Table, directly used by various SW components,latest version 1.1 ++ USHORT EnableCRTC; //Atomic Table, directly used by various SW components,latest version 1.1 ++ USHORT GetPixelClock; //Atomic Table, directly used by various SW components,latest version 1.1 ++ USHORT EnableVGA_Render; //Function Table,directly used by various SW components,latest version 1.1 ++ USHORT EnableVGA_Access; //Obsolete , only used by Bios ++ USHORT SetCRTC_Timing; //Atomic Table, directly used by various SW components,latest version 1.1 ++ USHORT SetCRTC_OverScan; //Atomic Table, used by various SW components,latest version 1.1 ++ USHORT SetCRTC_Replication; //Atomic Table, used only by Bios ++ USHORT SelectCRTC_Source; //Atomic Table, directly used by various SW components,latest version 1.1 ++ USHORT EnableGraphSurfaces; //Atomic Table, used only by Bios ++ USHORT UpdateCRTC_DoubleBufferRegisters; ++ USHORT LUT_AutoFill; //Atomic Table, only used by Bios ++ USHORT EnableHW_IconCursor; //Atomic Table, only used by Bios ++ USHORT GetMemoryClock; //Atomic Table, directly used by various SW components,latest version 1.1 ++ USHORT GetEngineClock; //Atomic Table, directly used by various SW components,latest version 1.1 ++ USHORT SetCRTC_UsingDTDTiming; //Atomic Table, directly used by various SW components,latest version 1.1 ++ USHORT ExternalEncoderControl; //Atomic Table, directly used by various SW components,latest version 2.1 ++ USHORT LVTMAOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 ++ USHORT VRAM_BlockDetectionByStrap; ++ USHORT MemoryCleanUp; //Atomic Table, only used by Bios ++ USHORT ReadEDIDFromHWAssistedI2C; //Function Table,only used by Bios ++ USHORT WriteOneByteToHWAssistedI2C; //Function Table,indirectly used by various SW components ++ USHORT ReadHWAssistedI2CStatus; //Atomic Table, indirectly used by various SW components ++ USHORT SpeedFanControl; //Function Table,indirectly used by various SW components,called from ASIC_Init ++ USHORT PowerConnectorDetection; //Atomic Table, directly used by various SW components,latest version 1.1 ++ USHORT MC_Synchronization; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock ++ USHORT ComputeMemoryEnginePLL; //Atomic Table, indirectly used by various SW components,called from SetMemory/EngineClock ++ USHORT MemoryRefreshConversion; //Atomic Table, indirectly used by various SW components,called from SetMemory or SetEngineClock ++ USHORT VRAM_GetCurrentInfoBlock; ++ USHORT DynamicMemorySettings; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock ++ USHORT MemoryTraining; ++ USHORT EnableSpreadSpectrumOnPPLL; //Atomic Table, directly used by various SW components,latest version 1.2 ++ USHORT TMDSAOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 ++ USHORT SetVoltage; //Function Table,directly and/or indirectly used by various SW components,latest version 1.1 ++ USHORT DAC1OutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 ++ USHORT DAC2OutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 ++ USHORT SetupHWAssistedI2CStatus; //Function Table,only used by Bios, obsolete soon.Switch to use "ReadEDIDFromHWAssistedI2C" ++ USHORT ClockSource; //Atomic Table, indirectly used by various SW components,called from ASIC_Init ++ USHORT MemoryDeviceInit; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock ++ USHORT EnableYUV; //Atomic Table, indirectly used by various SW components,called from EnableVGARender ++ USHORT DIG1EncoderControl; //Atomic Table,directly used by various SW components,latest version 1.1 ++ USHORT DIG2EncoderControl; //Atomic Table,directly used by various SW components,latest version 1.1 ++ USHORT DIG1TransmitterControl; //Atomic Table,directly used by various SW components,latest version 1.1 ++ USHORT DIG2TransmitterControl; //Atomic Table,directly used by various SW components,latest version 1.1 ++ USHORT ProcessAuxChannelTransaction; //Function Table,only used by Bios ++ USHORT DPEncoderService; //Function Table,only used by Bios ++}ATOM_MASTER_LIST_OF_COMMAND_TABLES; ++ ++#define UNIPHYTransmitterControl DIG1TransmitterControl ++#define LVTMATransmitterControl DIG2TransmitterControl ++#define SetCRTC_DPM_State GetConditionalGoldenSetting ++ ++typedef struct _ATOM_MASTER_COMMAND_TABLE ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ ATOM_MASTER_LIST_OF_COMMAND_TABLES ListOfCommandTables; ++}ATOM_MASTER_COMMAND_TABLE; ++ ++typedef struct _ATOM_TABLE_ATTRIBUTE ++{ ++ USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword), ++ USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword), ++ USHORT UpdatedByUtility:1; //[15]=Table updated by utility flag ++}ATOM_TABLE_ATTRIBUTE; ++ ++// Common header for all command tables. ++//Every table pointed by _ATOM_MASTER_COMMAND_TABLE has this common header. ++//And the pointer actually points to this header. ++ ++typedef struct _ATOM_COMMON_ROM_COMMAND_TABLE_HEADER ++{ ++ ATOM_COMMON_TABLE_HEADER CommonHeader; ++ ATOM_TABLE_ATTRIBUTE TableAttribute; ++}ATOM_COMMON_ROM_COMMAND_TABLE_HEADER; ++ ++ ++typedef struct _ASIC_INIT_PARAMETERS ++{ ++ ULONG ulDefaultEngineClock; //In 10Khz unit ++ ULONG ulDefaultMemoryClock; //In 10Khz unit ++}ASIC_INIT_PARAMETERS; ++ ++#define COMPUTE_MEMORY_PLL_PARAM 1 ++#define COMPUTE_ENGINE_PLL_PARAM 2 ++ ++typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS ++{ ++ ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Div and ref_div ++ UCHAR ucAction; //0:reserved //1:Memory //2:Engine ++ UCHAR ucReserved; //may expand to return larger Fbdiv later ++ UCHAR ucFbDiv; //return value ++ UCHAR ucPostDiv; //return value ++}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS; ++ ++typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 ++{ ++ ULONG ulClock; //When return, [23:0] return real clock ++ UCHAR ucAction; //0:reserved;COMPUTE_MEMORY_PLL_PARAM:Memory;COMPUTE_ENGINE_PLL_PARAM:Engine. it return ref_div to be written to register ++ USHORT usFbDiv; //return Feedback value to be written to register ++ UCHAR ucPostDiv; //return post div to be written to register ++}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2; ++#define COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS ++ ++ ++#define SET_CLOCK_FREQ_MASK 0x00FFFFFF //Clock change tables only take bit [23:0] as the requested clock value ++#define USE_NON_BUS_CLOCK_MASK 0x01000000 //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa) ++#define USE_MEMORY_SELF_REFRESH_MASK 0x02000000 //Only applicable to memory clock change, when set, using memory self refresh during clock transition ++#define SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE 0x04000000 //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change ++#define FIRST_TIME_CHANGE_CLOCK 0x08000000 //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup ++#define SKIP_SW_PROGRAM_PLL 0x10000000 //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL ++#define USE_SS_ENABLED_PIXEL_CLOCK USE_NON_BUS_CLOCK_MASK ++ ++#define b3USE_NON_BUS_CLOCK_MASK 0x01 //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa) ++#define b3USE_MEMORY_SELF_REFRESH 0x02 //Only applicable to memory clock change, when set, using memory self refresh during clock transition ++#define b3SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE 0x04 //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change ++#define b3FIRST_TIME_CHANGE_CLOCK 0x08 //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup ++#define b3SKIP_SW_PROGRAM_PLL 0x10 //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL ++ ++typedef struct _SET_ENGINE_CLOCK_PARAMETERS ++{ ++ ULONG ulTargetEngineClock; //In 10Khz unit ++}SET_ENGINE_CLOCK_PARAMETERS; ++ ++typedef struct _SET_ENGINE_CLOCK_PS_ALLOCATION ++{ ++ ULONG ulTargetEngineClock; //In 10Khz unit ++ COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved; ++}SET_ENGINE_CLOCK_PS_ALLOCATION; ++ ++ ++typedef struct _SET_MEMORY_CLOCK_PARAMETERS ++{ ++ ULONG ulTargetMemoryClock; //In 10Khz unit ++}SET_MEMORY_CLOCK_PARAMETERS; ++ ++typedef struct _SET_MEMORY_CLOCK_PS_ALLOCATION ++{ ++ ULONG ulTargetMemoryClock; //In 10Khz unit ++ COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved; ++}SET_MEMORY_CLOCK_PS_ALLOCATION; ++ ++typedef struct _ASIC_INIT_PS_ALLOCATION ++{ ++ ASIC_INIT_PARAMETERS sASICInitClocks; ++ SET_ENGINE_CLOCK_PS_ALLOCATION sReserved; //Caller doesn't need to init this structure ++}ASIC_INIT_PS_ALLOCATION; ++ ++ ++typedef struct _DYNAMIC_CLOCK_GATING_PARAMETERS ++{ ++ UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE ++ UCHAR ucPadding[3]; ++}DYNAMIC_CLOCK_GATING_PARAMETERS; ++#define DYNAMIC_CLOCK_GATING_PS_ALLOCATION DYNAMIC_CLOCK_GATING_PARAMETERS ++ ++ ++typedef struct _ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS ++{ ++ UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE ++ UCHAR ucPadding[3]; ++}ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS; ++#define ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS ++ ++ ++typedef struct _DAC_LOAD_DETECTION_PARAMETERS ++{ ++ USHORT usDeviceID; //{ATOM_DEVICE_CRTx_SUPPORT,ATOM_DEVICE_TVx_SUPPORT,ATOM_DEVICE_CVx_SUPPORT} ++ UCHAR ucDacType; //{ATOM_DAC_A,ATOM_DAC_B, ATOM_EXT_DAC} ++ UCHAR ucMisc; //Valid only when table revision =1.3 and above ++}DAC_LOAD_DETECTION_PARAMETERS; ++ ++// DAC_LOAD_DETECTION_PARAMETERS.ucMisc ++#define DAC_LOAD_MISC_YPrPb 0x01 ++ ++ ++typedef struct _DAC_LOAD_DETECTION_PS_ALLOCATION ++{ ++ DAC_LOAD_DETECTION_PARAMETERS sDacload; ++ ULONG Reserved[2];// Don't set this one, allocation for EXT DAC ++}DAC_LOAD_DETECTION_PS_ALLOCATION; ++ ++ ++typedef struct _DAC_ENCODER_CONTROL_PARAMETERS ++{ ++ USHORT usPixelClock; // in 10KHz; for bios convenient ++ UCHAR ucDacStandard; // See definition of ATOM_DACx_xxx ++ // 1: PS2 ++ UCHAR ucAction; // 0: turn off encoder ++ // 1: setup and turn on encoder ++}DAC_ENCODER_CONTROL_PARAMETERS; ++ ++#define DAC_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PARAMETERS ++ ++typedef struct _TV_ENCODER_CONTROL_PARAMETERS ++{ ++ USHORT usPixelClock; // in 10KHz; for bios convenient ++ UCHAR ucTvStandard; // See definition "ATOM_TV_NTSC ..." ++ UCHAR ucAction; // 0: turn off encoder ++ // 1: setup and turn on encoder ++}TV_ENCODER_CONTROL_PARAMETERS; ++ ++typedef struct _DIG_ENCODER_CONTROL_PARAMETERS ++{ ++ USHORT usPixelClock; // in 10KHz; for bios convenient ++ UCHAR ucConfig; ++ // [2] Link Select: ++ // =0: PHY linkA if bfLane<3 ++ // =1: PHY linkB if bfLanes<3 ++ // =0: PHY linkA+B if bfLanes=3 ++ // [3] Transmitter Sel ++ // =0: UNIPHY or PCIEPHY ++ // =1: LVTMA ++ UCHAR ucAction; // =0: turn off encoder ++ // =1: turn on encoder ++ union{ ++ UCHAR ucEncoderMode; ++ // =0: DP encoder ++ // =1: LVDS encoder ++ // =2: DVI encoder ++ // =3: HDMI encoder ++ // =4: SDVO encoder ++ UCHAR ucEncoderType; ++ }; ++ UCHAR ucLaneNum; // how many lanes to enable ++ UCHAR ucReserved[2]; ++}DIG_ENCODER_CONTROL_PARAMETERS; ++#define DIG_ENCODER_CONTROL_PS_ALLOCATION DIG_ENCODER_CONTROL_PARAMETERS ++#define EXTERNAL_ENCODER_CONTROL_PARAMETER DIG_ENCODER_CONTROL_PARAMETERS ++#define EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION DIG_ENCODER_CONTROL_PS_ALLOCATION ++ ++//ucConfig ++#define ATOM_ENCODER_CONFIG_LINK_SEL_MASK 0x04 ++#define ATOM_ENCODER_CONFIG_LINKA 0x00 ++#define ATOM_ENCODER_CONFIG_LINKB 0x04 ++#define ATOM_ENCODER_CONFIG_LINKA_B ATOM_TRANSMITTER_CONFIG_LINKA ++#define ATOM_ENCODER_CONFIG_TRANSMITTER_SEL_MASK 0x08 ++#define ATOM_ENCODER_CONFIG_UNIPHY 0x00 ++#define ATOM_ENCODER_CONFIG_LVTMA 0x08 ++#define ATOM_ENCODER_CONFIG_TRANSMITTER1 0x00 ++#define ATOM_ENCODER_CONFIG_TRANSMITTER2 0x08 ++#define ATOM_ENCODER_CONFIG_DIGB 0x80 // VBIOS Internal use, outside SW should set this bit=0 ++// ucAction ++// ATOM_ENABLE: Enable Encoder ++// ATOM_DISABLE: Disable Encoder ++ ++//ucEncoderMode ++#define ATOM_ENCODER_MODE_DP 0 ++#define ATOM_ENCODER_MODE_LVDS 1 ++#define ATOM_ENCODER_MODE_DVI 2 ++#define ATOM_ENCODER_MODE_HDMI 3 ++#define ATOM_ENCODER_MODE_SDVO 4 ++#define ATOM_ENCODER_MODE_TV 13 ++#define ATOM_ENCODER_MODE_CV 14 ++#define ATOM_ENCODER_MODE_CRT 15 ++ ++typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS ++{ ++ union ++ { ++ USHORT usPixelClock; // in 10KHz; for bios convenient ++ USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h ++ }; ++ UCHAR ucConfig; ++ // [0]=0: 4 lane Link, ++ // =1: 8 lane Link ( Dual Links TMDS ) ++ // [1]=0: InCoherent mode ++ // =1: Coherent Mode ++ // [2] Link Select: ++ // =0: PHY linkA if bfLane<3 ++ // =1: PHY linkB if bfLanes<3 ++ // =0: PHY linkA+B if bfLanes=3 ++ // [5:4]PCIE lane Sel ++ // =0: lane 0~3 or 0~7 ++ // =1: lane 4~7 ++ // =2: lane 8~11 or 8~15 ++ // =3: lane 12~15 ++ UCHAR ucAction; // =0: turn off encoder ++ // =1: turn on encoder ++ UCHAR ucReserved[4]; ++}DIG_TRANSMITTER_CONTROL_PARAMETERS; ++ ++#define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION DIG_TRANSMITTER_CONTROL_PARAMETERS ++ ++//ucInitInfo ++#define ATOM_TRAMITTER_INITINFO_CONNECTOR_MASK 0x00ff ++ ++//ucConfig ++#define ATOM_TRANSMITTER_CONFIG_8LANE_LINK 0x01 ++#define ATOM_TRANSMITTER_CONFIG_COHERENT 0x02 ++#define ATOM_TRANSMITTER_CONFIG_LINK_SEL_MASK 0x04 ++#define ATOM_TRANSMITTER_CONFIG_LINKA 0x00 ++#define ATOM_TRANSMITTER_CONFIG_LINKB 0x04 ++#define ATOM_TRANSMITTER_CONFIG_LINKA_B ATOM_TRANSMITTER_CONFIG_LINKA ++#define ATOM_TRANSMITTER_CONFIG_CLKSRC_MASK 0x30 ++#define ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL 0x00 ++#define ATOM_TRANSMITTER_CONFIG_CLKSRC_PCIE 0x20 ++#define ATOM_TRANSMITTER_CONFIG_CLKSRC_XTALIN 0x30 ++#define ATOM_TRANSMITTER_CONFIG_LANE_SEL_MASK 0xc0 ++#define ATOM_TRANSMITTER_CONFIG_LANE_0_3 0x00 ++#define ATOM_TRANSMITTER_CONFIG_LANE_0_7 0x00 ++#define ATOM_TRANSMITTER_CONFIG_LANE_4_7 0x40 ++#define ATOM_TRANSMITTER_CONFIG_LANE_8_11 0x80 ++#define ATOM_TRANSMITTER_CONFIG_LANE_8_15 0x80 ++#define ATOM_TRANSMITTER_CONFIG_LANE_12_15 0xc0 ++ ++//ucAction ++#define ATOM_TRANSMITTER_ACTION_DISABLE 0 ++#define ATOM_TRANSMITTER_ACTION_ENABLE 1 ++#define ATOM_TRANSMITTER_ACTION_LCD_BLOFF 2 ++#define ATOM_TRANSMITTER_ACTION_LCD_BLON 3 ++#define ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL 4 ++#define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_START 5 ++#define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_STOP 6 ++#define ATOM_TRANSMITTER_ACTION_INIT 7 ++#define ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT 8 ++#define ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT 9 ++#define ATOM_TRANSMITTER_ACTION_SETUP 10 ++ ++ ++/****************************Device Output Control Command Table Definitions**********************/ ++typedef struct _DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS ++{ ++ UCHAR ucAction; // Possible input:ATOM_ENABLE||ATOMDISABLE ++ // When the display is LCD, in addition to above: ++ // ATOM_LCD_BLOFF|| ATOM_LCD_BLON ||ATOM_LCD_BL_BRIGHTNESS_CONTROL||ATOM_LCD_SELFTEST_START|| ++ // ATOM_LCD_SELFTEST_STOP ++ ++ UCHAR aucPadding[3]; // padding to DWORD aligned ++}DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS; ++ ++#define DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS ++ ++ ++#define CRT1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS ++#define CRT1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION ++ ++#define CRT2_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS ++#define CRT2_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION ++ ++#define CV1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS ++#define CV1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION ++ ++#define TV1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS ++#define TV1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION ++ ++#define DFP1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS ++#define DFP1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION ++ ++#define DFP2_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS ++#define DFP2_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION ++ ++#define LCD1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS ++#define LCD1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION ++ ++#define DVO_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS ++#define DVO_OUTPUT_CONTROL_PS_ALLOCATION DIG_TRANSMITTER_CONTROL_PS_ALLOCATION ++#define DVO_OUTPUT_CONTROL_PARAMETERS_V3 DIG_TRANSMITTER_CONTROL_PARAMETERS ++ ++/**************************************************************************/ ++typedef struct _BLANK_CRTC_PARAMETERS ++{ ++ UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 ++ UCHAR ucBlanking; // ATOM_BLANKING or ATOM_BLANKINGOFF ++ USHORT usBlackColorRCr; ++ USHORT usBlackColorGY; ++ USHORT usBlackColorBCb; ++}BLANK_CRTC_PARAMETERS; ++#define BLANK_CRTC_PS_ALLOCATION BLANK_CRTC_PARAMETERS ++ ++ ++typedef struct _ENABLE_CRTC_PARAMETERS ++{ ++ UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 ++ UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE ++ UCHAR ucPadding[2]; ++}ENABLE_CRTC_PARAMETERS; ++#define ENABLE_CRTC_PS_ALLOCATION ENABLE_CRTC_PARAMETERS ++ ++ ++typedef struct _SET_CRTC_OVERSCAN_PARAMETERS ++{ ++ USHORT usOverscanRight; // right ++ USHORT usOverscanLeft; // left ++ USHORT usOverscanBottom; // bottom ++ USHORT usOverscanTop; // top ++ UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 ++ UCHAR ucPadding[3]; ++}SET_CRTC_OVERSCAN_PARAMETERS; ++#define SET_CRTC_OVERSCAN_PS_ALLOCATION SET_CRTC_OVERSCAN_PARAMETERS ++ ++ ++typedef struct _SET_CRTC_REPLICATION_PARAMETERS ++{ ++ UCHAR ucH_Replication; // horizontal replication ++ UCHAR ucV_Replication; // vertical replication ++ UCHAR usCRTC; // ATOM_CRTC1 or ATOM_CRTC2 ++ UCHAR ucPadding; ++}SET_CRTC_REPLICATION_PARAMETERS; ++#define SET_CRTC_REPLICATION_PS_ALLOCATION SET_CRTC_REPLICATION_PARAMETERS ++ ++ ++typedef struct _SELECT_CRTC_SOURCE_PARAMETERS ++{ ++ UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 ++ UCHAR ucDevice; // ATOM_DEVICE_CRT1|ATOM_DEVICE_CRT2|.... ++ UCHAR ucPadding[2]; ++}SELECT_CRTC_SOURCE_PARAMETERS; ++#define SELECT_CRTC_SOURCE_PS_ALLOCATION SELECT_CRTC_SOURCE_PARAMETERS ++ ++typedef struct _SELECT_CRTC_SOURCE_PARAMETERS_V2 ++{ ++ UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 ++ UCHAR ucEncoderID; // DAC1/DAC2/TVOUT/DIG1/DIG2/DVO ++ UCHAR ucEncodeMode; // Encoding mode, only valid when using DIG1/DIG2/DVO ++ UCHAR ucPadding; ++}SELECT_CRTC_SOURCE_PARAMETERS_V2; ++ ++//ucEncoderID ++//#define ASIC_INT_DAC1_ENCODER_ID 0x00 ++//#define ASIC_INT_TV_ENCODER_ID 0x02 ++//#define ASIC_INT_DIG1_ENCODER_ID 0x03 ++//#define ASIC_INT_DAC2_ENCODER_ID 0x04 ++//#define ASIC_EXT_TV_ENCODER_ID 0x06 ++//#define ASIC_INT_DVO_ENCODER_ID 0x07 ++//#define ASIC_INT_DIG2_ENCODER_ID 0x09 ++//#define ASIC_EXT_DIG_ENCODER_ID 0x05 ++ ++//ucEncodeMode ++//#define ATOM_ENCODER_MODE_DP 0 ++//#define ATOM_ENCODER_MODE_LVDS 1 ++//#define ATOM_ENCODER_MODE_DVI 2 ++//#define ATOM_ENCODER_MODE_HDMI 3 ++//#define ATOM_ENCODER_MODE_SDVO 4 ++//#define ATOM_ENCODER_MODE_TV 13 ++//#define ATOM_ENCODER_MODE_CV 14 ++//#define ATOM_ENCODER_MODE_CRT 15 ++ ++//Major revision=1., Minor revision=1 ++typedef struct _PIXEL_CLOCK_PARAMETERS ++{ ++ USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div) ++ // 0 means disable PPLL ++ USHORT usRefDiv; // Reference divider ++ USHORT usFbDiv; // feedback divider ++ UCHAR ucPostDiv; // post divider ++ UCHAR ucFracFbDiv; // fractional feedback divider ++ UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2 ++ UCHAR ucRefDivSrc; // ATOM_PJITTER or ATO_NONPJITTER ++ UCHAR ucCRTC; // Which CRTC uses this Ppll ++ UCHAR ucPadding; ++}PIXEL_CLOCK_PARAMETERS; ++ ++ ++//Major revision=1., Minor revision=2, add ucMiscIfno ++//ucMiscInfo: ++#define MISC_FORCE_REPROG_PIXEL_CLOCK 0x1 ++#define MISC_DEVICE_INDEX_MASK 0xF0 ++#define MISC_DEVICE_INDEX_SHIFT 4 ++ ++typedef struct _PIXEL_CLOCK_PARAMETERS_V2 ++{ ++ USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div) ++ // 0 means disable PPLL ++ USHORT usRefDiv; // Reference divider ++ USHORT usFbDiv; // feedback divider ++ UCHAR ucPostDiv; // post divider ++ UCHAR ucFracFbDiv; // fractional feedback divider ++ UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2 ++ UCHAR ucRefDivSrc; // ATOM_PJITTER or ATO_NONPJITTER ++ UCHAR ucCRTC; // Which CRTC uses this Ppll ++ UCHAR ucMiscInfo; // Different bits for different purpose, bit [7:4] as device index, bit[0]=Force prog ++}PIXEL_CLOCK_PARAMETERS_V2; ++ ++//Major revision=1., Minor revision=3, structure/definition change ++//ucEncoderMode: ++//ATOM_ENCODER_MODE_DP ++//ATOM_ENOCDER_MODE_LVDS ++//ATOM_ENOCDER_MODE_DVI ++//ATOM_ENOCDER_MODE_HDMI ++//ATOM_ENOCDER_MODE_SDVO ++//ATOM_ENCODER_MODE_TV 13 ++//ATOM_ENCODER_MODE_CV 14 ++//ATOM_ENCODER_MODE_CRT 15 ++ ++//ucMiscInfo: also changed, see below ++#define PIXEL_CLOCK_MISC_FORCE_PROG_PPLL 0x01 ++#define PIXEL_CLOCK_MISC_VGA_MODE 0x02 ++#define PIXEL_CLOCK_MISC_CRTC_SEL_MASK 0x04 ++#define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1 0x00 ++#define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2 0x04 ++ ++typedef struct _PIXEL_CLOCK_PARAMETERS_V3 ++{ ++ USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div) ++ // 0 means disable PPLL. For VGA PPLL,make sure this value is not 0. ++ USHORT usRefDiv; // Reference divider ++ USHORT usFbDiv; // feedback divider ++ UCHAR ucPostDiv; // post divider ++ UCHAR ucFracFbDiv; // fractional feedback divider ++ UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2 ++ UCHAR ucTransmitterId; // graphic encoder id defined in objectId.h ++ UCHAR ucEncoderMode; // encoder type defined as ATOM_ENCODER_MODE_DP/DVI/HDMI/ ++ UCHAR ucMiscInfo; // bit[0]=Force program, bit[1]= set pclk for VGA, b[2]= CRTC sel ++}PIXEL_CLOCK_PARAMETERS_V3; ++ ++#define PIXEL_CLOCK_PARAMETERS_LAST PIXEL_CLOCK_PARAMETERS_V2 ++#define GET_PIXEL_CLOCK_PS_ALLOCATION PIXEL_CLOCK_PARAMETERS_LAST ++ ++typedef struct _ADJUST_DISPLAY_PLL_PARAMETERS ++{ ++ USHORT usPixelClock; ++ UCHAR ucTransmitterID; ++ UCHAR ucEncodeMode; ++ union ++ { ++ UCHAR ucDVOConfig; //if DVO, need passing link rate and output 12bitlow or 24bit ++ UCHAR ucConfig; //if none DVO, not defined yet ++ }; ++ UCHAR ucReserved[3]; ++}ADJUST_DISPLAY_PLL_PARAMETERS; ++ ++#define ADJUST_DISPLAY_PLL_PS_ALLOCATION ADJUST_DISPLAY_PLL_PARAMETERS ++ ++typedef struct _ENABLE_YUV_PARAMETERS ++{ ++ UCHAR ucEnable; // ATOM_ENABLE:Enable YUV or ATOM_DISABLE:Disable YUV (RGB) ++ UCHAR ucCRTC; // Which CRTC needs this YUV or RGB format ++ UCHAR ucPadding[2]; ++}ENABLE_YUV_PARAMETERS; ++#define ENABLE_YUV_PS_ALLOCATION ENABLE_YUV_PARAMETERS ++ ++typedef struct _GET_MEMORY_CLOCK_PARAMETERS ++{ ++ ULONG ulReturnMemoryClock; // current memory speed in 10KHz unit ++} GET_MEMORY_CLOCK_PARAMETERS; ++#define GET_MEMORY_CLOCK_PS_ALLOCATION GET_MEMORY_CLOCK_PARAMETERS ++ ++ ++typedef struct _GET_ENGINE_CLOCK_PARAMETERS ++{ ++ ULONG ulReturnEngineClock; // current engine speed in 10KHz unit ++} GET_ENGINE_CLOCK_PARAMETERS; ++#define GET_ENGINE_CLOCK_PS_ALLOCATION GET_ENGINE_CLOCK_PARAMETERS ++ ++ ++//Maxium 8 bytes,the data read in will be placed in the parameter space. ++//Read operaion successeful when the paramter space is non-zero, otherwise read operation failed ++typedef struct _READ_EDID_FROM_HW_I2C_DATA_PARAMETERS ++{ ++ USHORT usPrescale; //Ratio between Engine clock and I2C clock ++ USHORT usVRAMAddress; //Adress in Frame Buffer where to pace raw EDID ++ USHORT usStatus; //When use output: lower byte EDID checksum, high byte hardware status ++ //WHen use input: lower byte as 'byte to read':currently limited to 128byte or 1byte ++ UCHAR ucSlaveAddr; //Read from which slave ++ UCHAR ucLineNumber; //Read from which HW assisted line ++}READ_EDID_FROM_HW_I2C_DATA_PARAMETERS; ++#define READ_EDID_FROM_HW_I2C_DATA_PS_ALLOCATION READ_EDID_FROM_HW_I2C_DATA_PARAMETERS ++ ++ ++#define ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSDATABYTE 0 ++#define ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSTWODATABYTES 1 ++#define ATOM_WRITE_I2C_FORMAT_PSCOUNTER_PSOFFSET_IDDATABLOCK 2 ++#define ATOM_WRITE_I2C_FORMAT_PSCOUNTER_IDOFFSET_PLUS_IDDATABLOCK 3 ++#define ATOM_WRITE_I2C_FORMAT_IDCOUNTER_IDOFFSET_IDDATABLOCK 4 ++ ++typedef struct _WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS ++{ ++ USHORT usPrescale; //Ratio between Engine clock and I2C clock ++ USHORT usByteOffset; //Write to which byte ++ //Upper portion of usByteOffset is Format of data ++ //1bytePS+offsetPS ++ //2bytesPS+offsetPS ++ //blockID+offsetPS ++ //blockID+offsetID ++ //blockID+counterID+offsetID ++ UCHAR ucData; //PS data1 ++ UCHAR ucStatus; //Status byte 1=success, 2=failure, Also is used as PS data2 ++ UCHAR ucSlaveAddr; //Write to which slave ++ UCHAR ucLineNumber; //Write from which HW assisted line ++}WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS; ++ ++#define WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS ++ ++typedef struct _SET_UP_HW_I2C_DATA_PARAMETERS ++{ ++ USHORT usPrescale; //Ratio between Engine clock and I2C clock ++ UCHAR ucSlaveAddr; //Write to which slave ++ UCHAR ucLineNumber; //Write from which HW assisted line ++}SET_UP_HW_I2C_DATA_PARAMETERS; ++ ++ ++/**************************************************************************/ ++#define SPEED_FAN_CONTROL_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS ++ ++typedef struct _POWER_CONNECTOR_DETECTION_PARAMETERS ++{ ++ UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected ++ UCHAR ucPwrBehaviorId; ++ USHORT usPwrBudget; //how much power currently boot to in unit of watt ++}POWER_CONNECTOR_DETECTION_PARAMETERS; ++ ++typedef struct POWER_CONNECTOR_DETECTION_PS_ALLOCATION ++{ ++ UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected ++ UCHAR ucReserved; ++ USHORT usPwrBudget; //how much power currently boot to in unit of watt ++ WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; ++}POWER_CONNECTOR_DETECTION_PS_ALLOCATION; ++ ++/****************************LVDS SS Command Table Definitions**********************/ ++typedef struct _ENABLE_LVDS_SS_PARAMETERS ++{ ++ USHORT usSpreadSpectrumPercentage; ++ UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD ++ UCHAR ucSpreadSpectrumStepSize_Delay; //bits3:2 SS_STEP_SIZE; bit 6:4 SS_DELAY ++ UCHAR ucEnable; //ATOM_ENABLE or ATOM_DISABLE ++ UCHAR ucPadding[3]; ++}ENABLE_LVDS_SS_PARAMETERS; ++ ++//ucTableFormatRevision=1,ucTableContentRevision=2 ++typedef struct _ENABLE_LVDS_SS_PARAMETERS_V2 ++{ ++ USHORT usSpreadSpectrumPercentage; ++ UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD ++ UCHAR ucSpreadSpectrumStep; // ++ UCHAR ucEnable; //ATOM_ENABLE or ATOM_DISABLE ++ UCHAR ucSpreadSpectrumDelay; ++ UCHAR ucSpreadSpectrumRange; ++ UCHAR ucPadding; ++}ENABLE_LVDS_SS_PARAMETERS_V2; ++ ++//This new structure is based on ENABLE_LVDS_SS_PARAMETERS but expands to SS on PPLL, so other devices can use SS. ++typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL ++{ ++ USHORT usSpreadSpectrumPercentage; ++ UCHAR ucSpreadSpectrumType; // Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD ++ UCHAR ucSpreadSpectrumStep; // ++ UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE ++ UCHAR ucSpreadSpectrumDelay; ++ UCHAR ucSpreadSpectrumRange; ++ UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2 ++}ENABLE_SPREAD_SPECTRUM_ON_PPLL; ++ ++#define ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION ENABLE_SPREAD_SPECTRUM_ON_PPLL ++ ++/**************************************************************************/ ++ ++typedef struct _SET_PIXEL_CLOCK_PS_ALLOCATION ++{ ++ PIXEL_CLOCK_PARAMETERS sPCLKInput; ++ ENABLE_SPREAD_SPECTRUM_ON_PPLL sReserved;//Caller doesn't need to init this portion ++}SET_PIXEL_CLOCK_PS_ALLOCATION; ++ ++#define ENABLE_VGA_RENDER_PS_ALLOCATION SET_PIXEL_CLOCK_PS_ALLOCATION ++ ++typedef struct _MEMORY_TRAINING_PARAMETERS ++{ ++ ULONG ulTargetMemoryClock; //In 10Khz unit ++}MEMORY_TRAINING_PARAMETERS; ++#define MEMORY_TRAINING_PS_ALLOCATION MEMORY_TRAINING_PARAMETERS ++ ++ ++ ++/****************************LVDS and other encoder command table definitions **********************/ ++typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS ++{ ++ USHORT usPixelClock; // in 10KHz; for bios convenient ++ UCHAR ucMisc; // bit0=0: Enable single link ++ // =1: Enable dual link ++ // Bit1=0: 666RGB ++ // =1: 888RGB ++ UCHAR ucAction; // 0: turn off encoder ++ // 1: setup and turn on encoder ++}LVDS_ENCODER_CONTROL_PARAMETERS; ++ ++#define LVDS_ENCODER_CONTROL_PS_ALLOCATION LVDS_ENCODER_CONTROL_PARAMETERS ++ ++#define TMDS1_ENCODER_CONTROL_PARAMETERS LVDS_ENCODER_CONTROL_PARAMETERS ++#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION TMDS1_ENCODER_CONTROL_PARAMETERS ++ ++#define TMDS2_ENCODER_CONTROL_PARAMETERS TMDS1_ENCODER_CONTROL_PARAMETERS ++#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION TMDS2_ENCODER_CONTROL_PARAMETERS ++ ++typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS ++{ ++ UCHAR ucEnable; // Enable or Disable External TMDS encoder ++ UCHAR ucMisc; // Bit0=0:Enable Single link;=1:Enable Dual link;Bit1 {=0:666RGB, =1:888RGB} ++ UCHAR ucPadding[2]; ++}ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS; ++ ++typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ++{ ++ ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS sXTmdsEncoder; ++ WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion ++}ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION; ++ ++ ++//ucTableFormatRevision=1,ucTableContentRevision=2 ++typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS_V2 ++{ ++ USHORT usPixelClock; // in 10KHz; for bios convenient ++ UCHAR ucMisc; // see PANEL_ENCODER_MISC_xx defintions below ++ UCHAR ucAction; // 0: turn off encoder ++ // 1: setup and turn on encoder ++ UCHAR ucTruncate; // bit0=0: Disable truncate ++ // =1: Enable truncate ++ // bit4=0: 666RGB ++ // =1: 888RGB ++ UCHAR ucSpatial; // bit0=0: Disable spatial dithering ++ // =1: Enable spatial dithering ++ // bit4=0: 666RGB ++ // =1: 888RGB ++ UCHAR ucTemporal; // bit0=0: Disable temporal dithering ++ // =1: Enable temporal dithering ++ // bit4=0: 666RGB ++ // =1: 888RGB ++ // bit5=0: Gray level 2 ++ // =1: Gray level 4 ++ UCHAR ucFRC; // bit4=0: 25FRC_SEL pattern E ++ // =1: 25FRC_SEL pattern F ++ // bit6:5=0: 50FRC_SEL pattern A ++ // =1: 50FRC_SEL pattern B ++ // =2: 50FRC_SEL pattern C ++ // =3: 50FRC_SEL pattern D ++ // bit7=0: 75FRC_SEL pattern E ++ // =1: 75FRC_SEL pattern F ++}LVDS_ENCODER_CONTROL_PARAMETERS_V2; ++ ++#define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2 ++ ++#define TMDS1_ENCODER_CONTROL_PARAMETERS_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2 ++#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V2 ++ ++#define TMDS2_ENCODER_CONTROL_PARAMETERS_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V2 ++#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS2_ENCODER_CONTROL_PARAMETERS_V2 ++#define ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2 ++ ++typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2 ++{ ++ ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2 sXTmdsEncoder; ++ WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion ++}ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2; ++ ++ ++//ucTableFormatRevision=1,ucTableContentRevision=3 ++ ++//ucDVOConfig: ++#define DVO_ENCODER_CONFIG_RATE_SEL 0x01 ++#define DVO_ENCODER_CONFIG_DDR_SPEED 0x00 ++#define DVO_ENCODER_CONFIG_SDR_SPEED 0x01 ++#define DVO_ENCODER_CONFIG_OUTPUT_SEL 0x0c ++#define DVO_ENCODER_CONFIG_LOW12BIT 0x00 ++#define DVO_ENCODER_CONFIG_UPPER12BIT 0x04 ++#define DVO_ENCODER_CONFIG_24BIT 0x08 ++ ++typedef struct _DVO_ENCODER_CONTROL_PARAMETERS_V3 ++{ ++ USHORT usPixelClock; ++ UCHAR ucDVOConfig; ++ UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT ++ UCHAR ucReseved[4]; ++}DVO_ENCODER_CONTROL_PARAMETERS_V3; ++#define DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 DVO_ENCODER_CONTROL_PARAMETERS_V3 ++ ++//ucTableFormatRevision=1 ++//ucTableContentRevision=3 structure is not changed but usMisc add bit 1 as another input for ++// bit1=0: non-coherent mode ++// =1: coherent mode ++ ++#define LVDS_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V2 ++#define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3 ++ ++#define TMDS1_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3 ++#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS1_ENCODER_CONTROL_PARAMETERS_V3 ++ ++#define TMDS2_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3 ++#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS2_ENCODER_CONTROL_PARAMETERS_V3 ++ ++//========================================================================================== ++//Only change is here next time when changing encoder parameter definitions again! ++#define LVDS_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3 ++#define LVDS_ENCODER_CONTROL_PS_ALLOCATION_LAST LVDS_ENCODER_CONTROL_PARAMETERS_LAST ++ ++#define TMDS1_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3 ++#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS1_ENCODER_CONTROL_PARAMETERS_LAST ++ ++#define TMDS2_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3 ++#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS2_ENCODER_CONTROL_PARAMETERS_LAST ++ ++#define DVO_ENCODER_CONTROL_PARAMETERS_LAST DVO_ENCODER_CONTROL_PARAMETERS ++#define DVO_ENCODER_CONTROL_PS_ALLOCATION_LAST DVO_ENCODER_CONTROL_PS_ALLOCATION ++ ++//========================================================================================== ++#define PANEL_ENCODER_MISC_DUAL 0x01 ++#define PANEL_ENCODER_MISC_COHERENT 0x02 ++#define PANEL_ENCODER_MISC_TMDS_LINKB 0x04 ++#define PANEL_ENCODER_MISC_HDMI_TYPE 0x08 ++ ++#define PANEL_ENCODER_ACTION_DISABLE ATOM_DISABLE ++#define PANEL_ENCODER_ACTION_ENABLE ATOM_ENABLE ++#define PANEL_ENCODER_ACTION_COHERENTSEQ (ATOM_ENABLE+1) ++ ++#define PANEL_ENCODER_TRUNCATE_EN 0x01 ++#define PANEL_ENCODER_TRUNCATE_DEPTH 0x10 ++#define PANEL_ENCODER_SPATIAL_DITHER_EN 0x01 ++#define PANEL_ENCODER_SPATIAL_DITHER_DEPTH 0x10 ++#define PANEL_ENCODER_TEMPORAL_DITHER_EN 0x01 ++#define PANEL_ENCODER_TEMPORAL_DITHER_DEPTH 0x10 ++#define PANEL_ENCODER_TEMPORAL_LEVEL_4 0x20 ++#define PANEL_ENCODER_25FRC_MASK 0x10 ++#define PANEL_ENCODER_25FRC_E 0x00 ++#define PANEL_ENCODER_25FRC_F 0x10 ++#define PANEL_ENCODER_50FRC_MASK 0x60 ++#define PANEL_ENCODER_50FRC_A 0x00 ++#define PANEL_ENCODER_50FRC_B 0x20 ++#define PANEL_ENCODER_50FRC_C 0x40 ++#define PANEL_ENCODER_50FRC_D 0x60 ++#define PANEL_ENCODER_75FRC_MASK 0x80 ++#define PANEL_ENCODER_75FRC_E 0x00 ++#define PANEL_ENCODER_75FRC_F 0x80 ++ ++/**************************************************************************/ ++ ++#define SET_VOLTAGE_TYPE_ASIC_VDDC 1 ++#define SET_VOLTAGE_TYPE_ASIC_MVDDC 2 ++#define SET_VOLTAGE_TYPE_ASIC_MVDDQ 3 ++#define SET_VOLTAGE_TYPE_ASIC_VDDCI 4 ++ ++#define SET_ASIC_VOLTAGE_MODE_ALL_SOURCE 0x1 ++#define SET_ASIC_VOLTAGE_MODE_SOURCE_A 0x2 ++#define SET_ASIC_VOLTAGE_MODE_SOURCE_B 0x4 ++ ++#define SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE 0x0 ++#define SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL 0x1 ++#define SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK 0x2 ++ ++typedef struct _SET_VOLTAGE_PARAMETERS ++{ ++ UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ ++ UCHAR ucVoltageMode; // To set all, to set source A or source B or ... ++ UCHAR ucVoltageIndex; // An index to tell which voltage level ++ UCHAR ucReserved; ++}SET_VOLTAGE_PARAMETERS; ++ ++ ++typedef struct _SET_VOLTAGE_PARAMETERS_V2 ++{ ++ UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ ++ UCHAR ucVoltageMode; // Not used, maybe use for state machine for differen power mode ++ USHORT usVoltageLevel; // real voltage level ++}SET_VOLTAGE_PARAMETERS_V2; ++ ++ ++typedef struct _SET_VOLTAGE_PS_ALLOCATION ++{ ++ SET_VOLTAGE_PARAMETERS sASICSetVoltage; ++ WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; ++}SET_VOLTAGE_PS_ALLOCATION; ++ ++typedef struct _TV_ENCODER_CONTROL_PS_ALLOCATION ++{ ++ TV_ENCODER_CONTROL_PARAMETERS sTVEncoder; ++ WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; // Don't set this one ++}TV_ENCODER_CONTROL_PS_ALLOCATION; ++ ++//==============================Data Table Portion==================================== ++ ++#ifdef UEFI_BUILD ++ #define UTEMP USHORT ++ #define USHORT void* ++#endif ++ ++typedef struct _ATOM_MASTER_LIST_OF_DATA_TABLES ++{ ++ USHORT UtilityPipeLine; // Offest for the utility to get parser info,Don't change this position! ++ USHORT MultimediaCapabilityInfo; // Only used by MM Lib,latest version 1.1, not configuable from Bios, need to include the table to build Bios ++ USHORT MultimediaConfigInfo; // Only used by MM Lib,latest version 2.1, not configuable from Bios, need to include the table to build Bios ++ USHORT StandardVESA_Timing; // Only used by Bios ++ USHORT FirmwareInfo; // Shared by various SW components,latest version 1.4 ++ USHORT DAC_Info; // Will be obsolete from R600 ++ USHORT LVDS_Info; // Shared by various SW components,latest version 1.1 ++ USHORT TMDS_Info; // Will be obsolete from R600 ++ USHORT AnalogTV_Info; // Shared by various SW components,latest version 1.1 ++ USHORT SupportedDevicesInfo; // Will be obsolete from R600 ++ USHORT GPIO_I2C_Info; // Shared by various SW components,latest version 1.2 will be used from R600 ++ USHORT VRAM_UsageByFirmware; // Shared by various SW components,latest version 1.3 will be used from R600 ++ USHORT GPIO_Pin_LUT; // Shared by various SW components,latest version 1.1 ++ USHORT VESA_ToInternalModeLUT; // Only used by Bios ++ USHORT ComponentVideoInfo; // Shared by various SW components,latest version 2.1 will be used from R600 ++ USHORT PowerPlayInfo; // Shared by various SW components,latest version 2.1,new design from R600 ++ USHORT CompassionateData; // Will be obsolete from R600 ++ USHORT SaveRestoreInfo; // Only used by Bios ++ USHORT PPLL_SS_Info; // Shared by various SW components,latest version 1.2, used to call SS_Info, change to new name because of int ASIC SS info ++ USHORT OemInfo; // Defined and used by external SW, should be obsolete soon ++ USHORT XTMDS_Info; // Will be obsolete from R600 ++ USHORT MclkSS_Info; // Shared by various SW components,latest version 1.1, only enabled when ext SS chip is used ++ USHORT Object_Header; // Shared by various SW components,latest version 1.1 ++ USHORT IndirectIOAccess; // Only used by Bios,this table position can't change at all!! ++ USHORT MC_InitParameter; // Only used by command table ++ USHORT ASIC_VDDC_Info; // Will be obsolete from R600 ++ USHORT ASIC_InternalSS_Info; // New tabel name from R600, used to be called "ASIC_MVDDC_Info" ++ USHORT TV_VideoMode; // Only used by command table ++ USHORT VRAM_Info; // Only used by command table, latest version 1.3 ++ USHORT MemoryTrainingInfo; // Used for VBIOS and Diag utility for memory training purpose since R600. the new table rev start from 2.1 ++ USHORT IntegratedSystemInfo; // Shared by various SW components ++ USHORT ASIC_ProfilingInfo; // New table name from R600, used to be called "ASIC_VDDCI_Info" for pre-R600 ++ USHORT VoltageObjectInfo; // Shared by various SW components, latest version 1.1 ++ USHORT PowerSourceInfo; // Shared by various SW components, latest versoin 1.1 ++}ATOM_MASTER_LIST_OF_DATA_TABLES; ++ ++#ifdef UEFI_BUILD ++ #define USHORT UTEMP ++#endif ++ ++ ++typedef struct _ATOM_MASTER_DATA_TABLE ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ ATOM_MASTER_LIST_OF_DATA_TABLES ListOfDataTables; ++}ATOM_MASTER_DATA_TABLE; ++ ++ ++typedef struct _ATOM_MULTIMEDIA_CAPABILITY_INFO ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ ULONG ulSignature; // HW info table signature string "$ATI" ++ UCHAR ucI2C_Type; // I2C type (normal GP_IO, ImpactTV GP_IO, Dedicated I2C pin, etc) ++ UCHAR ucTV_OutInfo; // Type of TV out supported (3:0) and video out crystal frequency (6:4) and TV data port (7) ++ UCHAR ucVideoPortInfo; // Provides the video port capabilities ++ UCHAR ucHostPortInfo; // Provides host port configuration information ++}ATOM_MULTIMEDIA_CAPABILITY_INFO; ++ ++ ++typedef struct _ATOM_MULTIMEDIA_CONFIG_INFO ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ ULONG ulSignature; // MM info table signature sting "$MMT" ++ UCHAR ucTunerInfo; // Type of tuner installed on the adapter (4:0) and video input for tuner (7:5) ++ UCHAR ucAudioChipInfo; // List the audio chip type (3:0) product type (4) and OEM revision (7:5) ++ UCHAR ucProductID; // Defines as OEM ID or ATI board ID dependent on product type setting ++ UCHAR ucMiscInfo1; // Tuner voltage (1:0) HW teletext support (3:2) FM audio decoder (5:4) reserved (6) audio scrambling (7) ++ UCHAR ucMiscInfo2; // I2S input config (0) I2S output config (1) I2S Audio Chip (4:2) SPDIF Output Config (5) reserved (7:6) ++ UCHAR ucMiscInfo3; // Video Decoder Type (3:0) Video In Standard/Crystal (7:4) ++ UCHAR ucMiscInfo4; // Video Decoder Host Config (2:0) reserved (7:3) ++ UCHAR ucVideoInput0Info;// Video Input 0 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) ++ UCHAR ucVideoInput1Info;// Video Input 1 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) ++ UCHAR ucVideoInput2Info;// Video Input 2 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) ++ UCHAR ucVideoInput3Info;// Video Input 3 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) ++ UCHAR ucVideoInput4Info;// Video Input 4 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) ++}ATOM_MULTIMEDIA_CONFIG_INFO; ++ ++/****************************Firmware Info Table Definitions**********************/ ++ ++// usBIOSCapability Defintion: ++// Bit 0 = 0: Bios image is not Posted, =1:Bios image is Posted; ++// Bit 1 = 0: Dual CRTC is not supported, =1: Dual CRTC is supported; ++// Bit 2 = 0: Extended Desktop is not supported, =1: Extended Desktop is supported; ++// Others: Reserved ++#define ATOM_BIOS_INFO_ATOM_FIRMWARE_POSTED 0x0001 ++#define ATOM_BIOS_INFO_DUAL_CRTC_SUPPORT 0x0002 ++#define ATOM_BIOS_INFO_EXTENDED_DESKTOP_SUPPORT 0x0004 ++#define ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT 0x0008 ++#define ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT 0x0010 ++#define ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU 0x0020 ++#define ATOM_BIOS_INFO_WMI_SUPPORT 0x0040 ++#define ATOM_BIOS_INFO_PPMODE_ASSIGNGED_BY_SYSTEM 0x0080 ++#define ATOM_BIOS_INFO_HYPERMEMORY_SUPPORT 0x0100 ++#define ATOM_BIOS_INFO_HYPERMEMORY_SIZE_MASK 0x1E00 ++#define ATOM_BIOS_INFO_VPOST_WITHOUT_FIRST_MODE_SET 0x2000 ++#define ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE 0x4000 ++ ++ ++#ifndef _H2INC ++ ++//Please don't add or expand this bitfield structure below, this one will retire soon.! ++typedef struct _ATOM_FIRMWARE_CAPABILITY ++{ ++ USHORT FirmwarePosted:1; ++ USHORT DualCRTC_Support:1; ++ USHORT ExtendedDesktopSupport:1; ++ USHORT MemoryClockSS_Support:1; ++ USHORT EngineClockSS_Support:1; ++ USHORT GPUControlsBL:1; ++ USHORT WMI_SUPPORT:1; ++ USHORT PPMode_Assigned:1; ++ USHORT HyperMemory_Support:1; ++ USHORT HyperMemory_Size:4; ++ USHORT Reserved:3; ++}ATOM_FIRMWARE_CAPABILITY; ++ ++typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS ++{ ++ ATOM_FIRMWARE_CAPABILITY sbfAccess; ++ USHORT susAccess; ++}ATOM_FIRMWARE_CAPABILITY_ACCESS; ++ ++#else ++ ++typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS ++{ ++ USHORT susAccess; ++}ATOM_FIRMWARE_CAPABILITY_ACCESS; ++ ++#endif ++ ++typedef struct _ATOM_FIRMWARE_INFO ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ ULONG ulFirmwareRevision; ++ ULONG ulDefaultEngineClock; //In 10Khz unit ++ ULONG ulDefaultMemoryClock; //In 10Khz unit ++ ULONG ulDriverTargetEngineClock; //In 10Khz unit ++ ULONG ulDriverTargetMemoryClock; //In 10Khz unit ++ ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit ++ ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit ++ ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit ++ ULONG ulASICMaxEngineClock; //In 10Khz unit ++ ULONG ulASICMaxMemoryClock; //In 10Khz unit ++ UCHAR ucASICMaxTemperature; ++ UCHAR ucPadding[3]; //Don't use them ++ ULONG aulReservedForBIOS[3]; //Don't use them ++ USHORT usMinEngineClockPLL_Input; //In 10Khz unit ++ USHORT usMaxEngineClockPLL_Input; //In 10Khz unit ++ USHORT usMinEngineClockPLL_Output; //In 10Khz unit ++ USHORT usMinMemoryClockPLL_Input; //In 10Khz unit ++ USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit ++ USHORT usMinMemoryClockPLL_Output; //In 10Khz unit ++ USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk ++ USHORT usMinPixelClockPLL_Input; //In 10Khz unit ++ USHORT usMaxPixelClockPLL_Input; //In 10Khz unit ++ USHORT usMinPixelClockPLL_Output; //In 10Khz unit, the definitions above can't change!!! ++ ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; ++ USHORT usReferenceClock; //In 10Khz unit ++ USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit ++ UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit ++ UCHAR ucDesign_ID; //Indicate what is the board design ++ UCHAR ucMemoryModule_ID; //Indicate what is the board design ++}ATOM_FIRMWARE_INFO; ++ ++typedef struct _ATOM_FIRMWARE_INFO_V1_2 ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ ULONG ulFirmwareRevision; ++ ULONG ulDefaultEngineClock; //In 10Khz unit ++ ULONG ulDefaultMemoryClock; //In 10Khz unit ++ ULONG ulDriverTargetEngineClock; //In 10Khz unit ++ ULONG ulDriverTargetMemoryClock; //In 10Khz unit ++ ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit ++ ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit ++ ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit ++ ULONG ulASICMaxEngineClock; //In 10Khz unit ++ ULONG ulASICMaxMemoryClock; //In 10Khz unit ++ UCHAR ucASICMaxTemperature; ++ UCHAR ucMinAllowedBL_Level; ++ UCHAR ucPadding[2]; //Don't use them ++ ULONG aulReservedForBIOS[2]; //Don't use them ++ ULONG ulMinPixelClockPLL_Output; //In 10Khz unit ++ USHORT usMinEngineClockPLL_Input; //In 10Khz unit ++ USHORT usMaxEngineClockPLL_Input; //In 10Khz unit ++ USHORT usMinEngineClockPLL_Output; //In 10Khz unit ++ USHORT usMinMemoryClockPLL_Input; //In 10Khz unit ++ USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit ++ USHORT usMinMemoryClockPLL_Output; //In 10Khz unit ++ USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk ++ USHORT usMinPixelClockPLL_Input; //In 10Khz unit ++ USHORT usMaxPixelClockPLL_Input; //In 10Khz unit ++ USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output ++ ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; ++ USHORT usReferenceClock; //In 10Khz unit ++ USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit ++ UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit ++ UCHAR ucDesign_ID; //Indicate what is the board design ++ UCHAR ucMemoryModule_ID; //Indicate what is the board design ++}ATOM_FIRMWARE_INFO_V1_2; ++ ++typedef struct _ATOM_FIRMWARE_INFO_V1_3 ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ ULONG ulFirmwareRevision; ++ ULONG ulDefaultEngineClock; //In 10Khz unit ++ ULONG ulDefaultMemoryClock; //In 10Khz unit ++ ULONG ulDriverTargetEngineClock; //In 10Khz unit ++ ULONG ulDriverTargetMemoryClock; //In 10Khz unit ++ ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit ++ ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit ++ ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit ++ ULONG ulASICMaxEngineClock; //In 10Khz unit ++ ULONG ulASICMaxMemoryClock; //In 10Khz unit ++ UCHAR ucASICMaxTemperature; ++ UCHAR ucMinAllowedBL_Level; ++ UCHAR ucPadding[2]; //Don't use them ++ ULONG aulReservedForBIOS; //Don't use them ++ ULONG ul3DAccelerationEngineClock;//In 10Khz unit ++ ULONG ulMinPixelClockPLL_Output; //In 10Khz unit ++ USHORT usMinEngineClockPLL_Input; //In 10Khz unit ++ USHORT usMaxEngineClockPLL_Input; //In 10Khz unit ++ USHORT usMinEngineClockPLL_Output; //In 10Khz unit ++ USHORT usMinMemoryClockPLL_Input; //In 10Khz unit ++ USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit ++ USHORT usMinMemoryClockPLL_Output; //In 10Khz unit ++ USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk ++ USHORT usMinPixelClockPLL_Input; //In 10Khz unit ++ USHORT usMaxPixelClockPLL_Input; //In 10Khz unit ++ USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output ++ ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; ++ USHORT usReferenceClock; //In 10Khz unit ++ USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit ++ UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit ++ UCHAR ucDesign_ID; //Indicate what is the board design ++ UCHAR ucMemoryModule_ID; //Indicate what is the board design ++}ATOM_FIRMWARE_INFO_V1_3; ++ ++typedef struct _ATOM_FIRMWARE_INFO_V1_4 ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ ULONG ulFirmwareRevision; ++ ULONG ulDefaultEngineClock; //In 10Khz unit ++ ULONG ulDefaultMemoryClock; //In 10Khz unit ++ ULONG ulDriverTargetEngineClock; //In 10Khz unit ++ ULONG ulDriverTargetMemoryClock; //In 10Khz unit ++ ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit ++ ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit ++ ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit ++ ULONG ulASICMaxEngineClock; //In 10Khz unit ++ ULONG ulASICMaxMemoryClock; //In 10Khz unit ++ UCHAR ucASICMaxTemperature; ++ UCHAR ucMinAllowedBL_Level; ++ USHORT usBootUpVDDCVoltage; //In MV unit ++ USHORT usLcdMinPixelClockPLL_Output; // In MHz unit ++ USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit ++ ULONG ul3DAccelerationEngineClock;//In 10Khz unit ++ ULONG ulMinPixelClockPLL_Output; //In 10Khz unit ++ USHORT usMinEngineClockPLL_Input; //In 10Khz unit ++ USHORT usMaxEngineClockPLL_Input; //In 10Khz unit ++ USHORT usMinEngineClockPLL_Output; //In 10Khz unit ++ USHORT usMinMemoryClockPLL_Input; //In 10Khz unit ++ USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit ++ USHORT usMinMemoryClockPLL_Output; //In 10Khz unit ++ USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk ++ USHORT usMinPixelClockPLL_Input; //In 10Khz unit ++ USHORT usMaxPixelClockPLL_Input; //In 10Khz unit ++ USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output ++ ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; ++ USHORT usReferenceClock; //In 10Khz unit ++ USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit ++ UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit ++ UCHAR ucDesign_ID; //Indicate what is the board design ++ UCHAR ucMemoryModule_ID; //Indicate what is the board design ++}ATOM_FIRMWARE_INFO_V1_4; ++ ++#define ATOM_FIRMWARE_INFO_LAST ATOM_FIRMWARE_INFO_V1_4 ++ ++#define IGP_CAP_FLAG_DYNAMIC_CLOCK_EN 0x2 ++#define IGP_CAP_FLAG_AC_CARD 0x4 ++#define IGP_CAP_FLAG_SDVO_CARD 0x8 ++#define IGP_CAP_FLAG_POSTDIV_BY_2_MODE 0x10 ++ ++typedef struct _ATOM_INTEGRATED_SYSTEM_INFO ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ ULONG ulBootUpEngineClock; //in 10kHz unit ++ ULONG ulBootUpMemoryClock; //in 10kHz unit ++ ULONG ulMaxSystemMemoryClock; //in 10kHz unit ++ ULONG ulMinSystemMemoryClock; //in 10kHz unit ++ UCHAR ucNumberOfCyclesInPeriodHi; ++ UCHAR ucLCDTimingSel; //=0:not valid.!=0 sel this timing descriptor from LCD EDID. ++ USHORT usReserved1; ++ USHORT usInterNBVoltageLow; //An intermidiate PMW value to set the voltage ++ USHORT usInterNBVoltageHigh; //Another intermidiate PMW value to set the voltage ++ ULONG ulReserved[2]; ++ ++ USHORT usFSBClock; //In MHz unit ++ USHORT usCapabilityFlag; //Bit0=1 indicates the fake HDMI support,Bit1=0/1 for Dynamic clocking dis/enable ++ //Bit[3:2]== 0:No PCIE card, 1:AC card, 2:SDVO card ++ //Bit[4]==1: P/2 mode, ==0: P/1 mode ++ USHORT usPCIENBCfgReg7; //bit[7:0]=MUX_Sel, bit[9:8]=MUX_SEL_LEVEL2, bit[10]=Lane_Reversal ++ USHORT usK8MemoryClock; //in MHz unit ++ USHORT usK8SyncStartDelay; //in 0.01 us unit ++ USHORT usK8DataReturnTime; //in 0.01 us unit ++ UCHAR ucMaxNBVoltage; ++ UCHAR ucMinNBVoltage; ++ UCHAR ucMemoryType; //[7:4]=1:DDR1;=2:DDR2;=3:DDR3.[3:0] is reserved ++ UCHAR ucNumberOfCyclesInPeriod; //CG.FVTHROT_PWM_CTRL_REG0.NumberOfCyclesInPeriod ++ UCHAR ucStartingPWM_HighTime; //CG.FVTHROT_PWM_CTRL_REG0.StartingPWM_HighTime ++ UCHAR ucHTLinkWidth; //16 bit vs. 8 bit ++ UCHAR ucMaxNBVoltageHigh; ++ UCHAR ucMinNBVoltageHigh; ++}ATOM_INTEGRATED_SYSTEM_INFO; ++ ++/* Explanation on entries in ATOM_INTEGRATED_SYSTEM_INFO ++ulBootUpMemoryClock: For Intel IGP,it's the UMA system memory clock ++ For AMD IGP,it's 0 if no SidePort memory installed or it's the boot-up SidePort memory clock ++ulMaxSystemMemoryClock: For Intel IGP,it's the Max freq from memory SPD if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0 ++ For AMD IGP,for now this can be 0 ++ulMinSystemMemoryClock: For Intel IGP,it's 133MHz if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0 ++ For AMD IGP,for now this can be 0 ++ ++usFSBClock: For Intel IGP,it's FSB Freq ++ For AMD IGP,it's HT Link Speed ++ ++usK8MemoryClock: For AMD IGP only. For RevF CPU, set it to 200 ++usK8SyncStartDelay: For AMD IGP only. Memory access latency in K8, required for watermark calculation ++usK8DataReturnTime: For AMD IGP only. Memory access latency in K8, required for watermark calculation ++ ++VC:Voltage Control ++ucMaxNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all. ++ucMinNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all. ++ ++ucNumberOfCyclesInPeriod: Indicate how many cycles when PWM duty is 100%. low 8 bits of the value. ++ucNumberOfCyclesInPeriodHi: Indicate how many cycles when PWM duty is 100%. high 8 bits of the value.If the PWM has an inverter,set bit [7]==1,otherwise set it 0 ++ ++ucMaxNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all. ++ucMinNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all. ++ ++ ++usInterNBVoltageLow: Voltage regulator dependent PWM value. The value makes the the voltage >=Min NB voltage but <=InterNBVoltageHigh. Set this to 0x0000 if VC without PWM or no VC at all. ++usInterNBVoltageHigh: Voltage regulator dependent PWM value. The value makes the the voltage >=InterNBVoltageLow but <=Max NB voltage.Set this to 0x0000 if VC without PWM or no VC at all. ++*/ ++ ++ ++/* ++The following IGP table is introduced from RS780, which is supposed to be put by SBIOS in FB before IGP VBIOS starts VPOST; ++Then VBIOS will copy the whole structure to its image so all GPU SW components can access this data structure to get whatever they need. ++The enough reservation should allow us to never change table revisions. Whenever needed, a GPU SW component can use reserved portion for new data entries. ++ ++SW components can access the IGP system infor structure in the same way as before ++*/ ++ ++ ++typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ ULONG ulBootUpEngineClock; //in 10kHz unit ++ ULONG ulReserved1[2]; //must be 0x0 for the reserved ++ ULONG ulBootUpUMAClock; //in 10kHz unit ++ ULONG ulBootUpSidePortClock; //in 10kHz unit ++ ULONG ulReserved2[8]; //must be 0x0 for the reserved ++ ULONG ulBootUpReqDisplayVector; ++ ULONG ulOtherDisplayMisc; ++ ULONG ulDDISlot1Config; ++ ULONG ulDDISlot2Config; ++ UCHAR ucMemoryType; //[7:4]=1:DDR1;=2:DDR2;=3:DDR3.[3:0] is reserved ++ UCHAR ucReserved; //must be 0x0 for the reserved ++ UCHAR ucDockingPinBit; ++ UCHAR ucDockingPinPolarity; ++ ULONG ulDockingPinCFGInfo; ++ ULONG ulCPUCapInfo; ++ ULONG ulReserved3[107]; //must be 0x0 ++}ATOM_INTEGRATED_SYSTEM_INFO_V2; ++ ++/* ++ulBootUpEngineClock: Boot-up Engine Clock in 10Khz; ++ulBootUpUMAClock: Boot-up UMA Clock in 10Khz; it must be 0x0 when UMA is not present ++ulBootUpSidePortClock: Boot-up SidePort Clock in 10Khz; it must be 0x0 when SidePort Memory is not present ++ ++ ++ulBootUpReqDisplayVector: This dword is a bit vector indicates what display devices are requested during boot-up. Refer to ATOM_DEVICE_xxx_SUPPORT for the bit vector definitions. ++ ++ulOtherDisplayMisc: [15:8]- Bootup LCD Expansion selection; 0-center, 1-full panel size expansion; ++ [7:0] - BootupTV standard selection; This is a bit vector to indicate what TV standards are supported by the system. Refer to ucTVSuppportedStd definition; ++ ++ulDDISlot1Config: Describes the PCIE lane configuration on this DDI PCIE slot (ADD2 card) or connector (Mobile design). ++ [3:0] - Bit vector to indicate PCIE lane config of the DDI slot/connector on chassis (bit 0=1 lane 3:0; bit 1=1 lane 7:4; bit 2=1 lane 11:8; bit 3=1 lane 15:12) ++ [7:4] - Bit vector to indicate PCIE lane config of the same DDI slot/connector on docking station (bit 0=1 lane 3:0; bit 1=1 lane 7:4; bit 2=1 lane 11:8; bit 3=1 lane 15:12) ++ [15:8] - Lane configuration attribute; ++ [31:16]- Reserved ++ ++ulDDISlot2Config: Same as Slot1 ++ ++ulDockingPinCFGInfo: [15:0]-Bus/Device/Function # to CFG to read this Docking Pin; [31:16]-reg offset in CFG to read this pin ++ucDockingPinBit: which bit in this register to read the pin status; ++ucDockingPinPolarity:Polarity of the pin when docked; ++ ++ulCPUCapInfo: TBD ++ ++*/ ++ ++#define ATOM_CRT_INT_ENCODER1_INDEX 0x00000000 ++#define ATOM_LCD_INT_ENCODER1_INDEX 0x00000001 ++#define ATOM_TV_INT_ENCODER1_INDEX 0x00000002 ++#define ATOM_DFP_INT_ENCODER1_INDEX 0x00000003 ++#define ATOM_CRT_INT_ENCODER2_INDEX 0x00000004 ++#define ATOM_LCD_EXT_ENCODER1_INDEX 0x00000005 ++#define ATOM_TV_EXT_ENCODER1_INDEX 0x00000006 ++#define ATOM_DFP_EXT_ENCODER1_INDEX 0x00000007 ++#define ATOM_CV_INT_ENCODER1_INDEX 0x00000008 ++#define ATOM_DFP_INT_ENCODER2_INDEX 0x00000009 ++#define ATOM_CRT_EXT_ENCODER1_INDEX 0x0000000A ++#define ATOM_CV_EXT_ENCODER1_INDEX 0x0000000B ++#define ATOM_DFP_INT_ENCODER3_INDEX 0x0000000C ++#define ATOM_DFP_INT_ENCODER4_INDEX 0x0000000D ++ ++// define ASIC internal encoder id ( bit vector ) ++#define ASIC_INT_DAC1_ENCODER_ID 0x00 ++#define ASIC_INT_TV_ENCODER_ID 0x02 ++#define ASIC_INT_DIG1_ENCODER_ID 0x03 ++#define ASIC_INT_DAC2_ENCODER_ID 0x04 ++#define ASIC_EXT_TV_ENCODER_ID 0x06 ++#define ASIC_INT_DVO_ENCODER_ID 0x07 ++#define ASIC_INT_DIG2_ENCODER_ID 0x09 ++#define ASIC_EXT_DIG_ENCODER_ID 0x05 ++ ++//define Encoder attribute ++#define ATOM_ANALOG_ENCODER 0 ++#define ATOM_DIGITAL_ENCODER 1 ++ ++#define ATOM_DEVICE_CRT1_INDEX 0x00000000 ++#define ATOM_DEVICE_LCD1_INDEX 0x00000001 ++#define ATOM_DEVICE_TV1_INDEX 0x00000002 ++#define ATOM_DEVICE_DFP1_INDEX 0x00000003 ++#define ATOM_DEVICE_CRT2_INDEX 0x00000004 ++#define ATOM_DEVICE_LCD2_INDEX 0x00000005 ++#define ATOM_DEVICE_TV2_INDEX 0x00000006 ++#define ATOM_DEVICE_DFP2_INDEX 0x00000007 ++#define ATOM_DEVICE_CV_INDEX 0x00000008 ++#define ATOM_DEVICE_DFP3_INDEX 0x00000009 ++#define ATOM_DEVICE_RESERVEDA_INDEX 0x0000000A ++#define ATOM_DEVICE_RESERVEDB_INDEX 0x0000000B ++#define ATOM_DEVICE_RESERVEDC_INDEX 0x0000000C ++#define ATOM_DEVICE_RESERVEDD_INDEX 0x0000000D ++#define ATOM_DEVICE_RESERVEDE_INDEX 0x0000000E ++#define ATOM_DEVICE_RESERVEDF_INDEX 0x0000000F ++#define ATOM_MAX_SUPPORTED_DEVICE_INFO (ATOM_DEVICE_CV_INDEX+2) ++#define ATOM_MAX_SUPPORTED_DEVICE_INFO_2 ATOM_MAX_SUPPORTED_DEVICE_INFO ++#define ATOM_MAX_SUPPORTED_DEVICE (ATOM_DEVICE_RESERVEDF_INDEX+1) ++ ++#define ATOM_DEVICE_CRT1_SUPPORT (0x1L << ATOM_DEVICE_CRT1_INDEX ) ++#define ATOM_DEVICE_LCD1_SUPPORT (0x1L << ATOM_DEVICE_LCD1_INDEX ) ++#define ATOM_DEVICE_TV1_SUPPORT (0x1L << ATOM_DEVICE_TV1_INDEX ) ++#define ATOM_DEVICE_DFP1_SUPPORT (0x1L << ATOM_DEVICE_DFP1_INDEX) ++#define ATOM_DEVICE_CRT2_SUPPORT (0x1L << ATOM_DEVICE_CRT2_INDEX ) ++#define ATOM_DEVICE_LCD2_SUPPORT (0x1L << ATOM_DEVICE_LCD2_INDEX ) ++#define ATOM_DEVICE_TV2_SUPPORT (0x1L << ATOM_DEVICE_TV2_INDEX ) ++#define ATOM_DEVICE_DFP2_SUPPORT (0x1L << ATOM_DEVICE_DFP2_INDEX) ++#define ATOM_DEVICE_CV_SUPPORT (0x1L << ATOM_DEVICE_CV_INDEX ) ++#define ATOM_DEVICE_DFP3_SUPPORT (0x1L << ATOM_DEVICE_DFP3_INDEX ) ++ ++#define ATOM_DEVICE_CRT_SUPPORT ATOM_DEVICE_CRT1_SUPPORT | ATOM_DEVICE_CRT2_SUPPORT ++#define ATOM_DEVICE_DFP_SUPPORT ATOM_DEVICE_DFP1_SUPPORT | ATOM_DEVICE_DFP2_SUPPORT | ATOM_DEVICE_DFP3_SUPPORT ++#define ATOM_DEVICE_TV_SUPPORT ATOM_DEVICE_TV1_SUPPORT | ATOM_DEVICE_TV2_SUPPORT ++#define ATOM_DEVICE_LCD_SUPPORT ATOM_DEVICE_LCD1_SUPPORT | ATOM_DEVICE_LCD2_SUPPORT ++ ++#define ATOM_DEVICE_CONNECTOR_TYPE_MASK 0x000000F0 ++#define ATOM_DEVICE_CONNECTOR_TYPE_SHIFT 0x00000004 ++#define ATOM_DEVICE_CONNECTOR_VGA 0x00000001 ++#define ATOM_DEVICE_CONNECTOR_DVI_I 0x00000002 ++#define ATOM_DEVICE_CONNECTOR_DVI_D 0x00000003 ++#define ATOM_DEVICE_CONNECTOR_DVI_A 0x00000004 ++#define ATOM_DEVICE_CONNECTOR_SVIDEO 0x00000005 ++#define ATOM_DEVICE_CONNECTOR_COMPOSITE 0x00000006 ++#define ATOM_DEVICE_CONNECTOR_LVDS 0x00000007 ++#define ATOM_DEVICE_CONNECTOR_DIGI_LINK 0x00000008 ++#define ATOM_DEVICE_CONNECTOR_SCART 0x00000009 ++#define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_A 0x0000000A ++#define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_B 0x0000000B ++#define ATOM_DEVICE_CONNECTOR_CASE_1 0x0000000E ++#define ATOM_DEVICE_CONNECTOR_DISPLAYPORT 0x0000000F ++ ++ ++#define ATOM_DEVICE_DAC_INFO_MASK 0x0000000F ++#define ATOM_DEVICE_DAC_INFO_SHIFT 0x00000000 ++#define ATOM_DEVICE_DAC_INFO_NODAC 0x00000000 ++#define ATOM_DEVICE_DAC_INFO_DACA 0x00000001 ++#define ATOM_DEVICE_DAC_INFO_DACB 0x00000002 ++#define ATOM_DEVICE_DAC_INFO_EXDAC 0x00000003 ++ ++#define ATOM_DEVICE_I2C_ID_NOI2C 0x00000000 ++ ++#define ATOM_DEVICE_I2C_LINEMUX_MASK 0x0000000F ++#define ATOM_DEVICE_I2C_LINEMUX_SHIFT 0x00000000 ++ ++#define ATOM_DEVICE_I2C_ID_MASK 0x00000070 ++#define ATOM_DEVICE_I2C_ID_SHIFT 0x00000004 ++#define ATOM_DEVICE_I2C_ID_IS_FOR_NON_MM_USE 0x00000001 ++#define ATOM_DEVICE_I2C_ID_IS_FOR_MM_USE 0x00000002 ++#define ATOM_DEVICE_I2C_ID_IS_FOR_SDVO_USE 0x00000003 //For IGP RS600 ++#define ATOM_DEVICE_I2C_ID_IS_FOR_DAC_SCL 0x00000004 //For IGP RS690 ++ ++#define ATOM_DEVICE_I2C_HARDWARE_CAP_MASK 0x00000080 ++#define ATOM_DEVICE_I2C_HARDWARE_CAP_SHIFT 0x00000007 ++#define ATOM_DEVICE_USES_SOFTWARE_ASSISTED_I2C 0x00000000 ++#define ATOM_DEVICE_USES_HARDWARE_ASSISTED_I2C 0x00000001 ++ ++// usDeviceSupport: ++// Bits0 = 0 - no CRT1 support= 1- CRT1 is supported ++// Bit 1 = 0 - no LCD1 support= 1- LCD1 is supported ++// Bit 2 = 0 - no TV1 support= 1- TV1 is supported ++// Bit 3 = 0 - no DFP1 support= 1- DFP1 is supported ++// Bit 4 = 0 - no CRT2 support= 1- CRT2 is supported ++// Bit 5 = 0 - no LCD2 support= 1- LCD2 is supported ++// Bit 6 = 0 - no TV2 support= 1- TV2 is supported ++// Bit 7 = 0 - no DFP2 support= 1- DFP2 is supported ++// Bit 8 = 0 - no CV support= 1- CV is supported ++// Bit 9 = 0 - no DFP3 support= 1- DFP3 is supported ++// Byte1 (Supported Device Info) ++// Bit 0 = = 0 - no CV support= 1- CV is supported ++// ++// ++ ++// ucI2C_ConfigID ++// [7:0] - I2C LINE Associate ID ++// = 0 - no I2C ++// [7] - HW_Cap = 1, [6:0]=HW assisted I2C ID(HW line selection) ++// = 0, [6:0]=SW assisted I2C ID ++// [6-4] - HW_ENGINE_ID = 1, HW engine for NON multimedia use ++// = 2, HW engine for Multimedia use ++// = 3-7 Reserved for future I2C engines ++// [3-0] - I2C_LINE_MUX = A Mux number when it's HW assisted I2C or GPIO ID when it's SW I2C ++ ++ ++typedef struct _ATOM_I2C_ID_CONFIG ++{ ++ UCHAR bfI2C_LineMux:4; ++ UCHAR bfHW_EngineID:3; ++ UCHAR bfHW_Capable:1; ++}ATOM_I2C_ID_CONFIG; ++ ++typedef union _ATOM_I2C_ID_CONFIG_ACCESS ++{ ++ ATOM_I2C_ID_CONFIG sbfAccess; ++ UCHAR ucAccess; ++}ATOM_I2C_ID_CONFIG_ACCESS; ++ ++ ++typedef struct _ATOM_GPIO_I2C_ASSIGMENT ++{ ++ USHORT usClkMaskRegisterIndex; ++ USHORT usClkEnRegisterIndex; ++ USHORT usClkY_RegisterIndex; ++ USHORT usClkA_RegisterIndex; ++ USHORT usDataMaskRegisterIndex; ++ USHORT usDataEnRegisterIndex; ++ USHORT usDataY_RegisterIndex; ++ USHORT usDataA_RegisterIndex; ++ ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; ++ UCHAR ucClkMaskShift; ++ UCHAR ucClkEnShift; ++ UCHAR ucClkY_Shift; ++ UCHAR ucClkA_Shift; ++ UCHAR ucDataMaskShift; ++ UCHAR ucDataEnShift; ++ UCHAR ucDataY_Shift; ++ UCHAR ucDataA_Shift; ++ UCHAR ucReserved1; ++ UCHAR ucReserved2; ++}ATOM_GPIO_I2C_ASSIGMENT; ++ ++typedef struct _ATOM_GPIO_I2C_INFO ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ ATOM_GPIO_I2C_ASSIGMENT asGPIO_Info[ATOM_MAX_SUPPORTED_DEVICE]; ++}ATOM_GPIO_I2C_INFO; ++ ++ ++#ifndef _H2INC ++ ++//Please don't add or expand this bitfield structure below, this one will retire soon.! ++typedef struct _ATOM_MODE_MISC_INFO ++{ ++ USHORT HorizontalCutOff:1; ++ USHORT HSyncPolarity:1; //0=Active High, 1=Active Low ++ USHORT VSyncPolarity:1; //0=Active High, 1=Active Low ++ USHORT VerticalCutOff:1; ++ USHORT H_ReplicationBy2:1; ++ USHORT V_ReplicationBy2:1; ++ USHORT CompositeSync:1; ++ USHORT Interlace:1; ++ USHORT DoubleClock:1; ++ USHORT RGB888:1; ++ USHORT Reserved:6; ++}ATOM_MODE_MISC_INFO; ++ ++typedef union _ATOM_MODE_MISC_INFO_ACCESS ++{ ++ ATOM_MODE_MISC_INFO sbfAccess; ++ USHORT usAccess; ++}ATOM_MODE_MISC_INFO_ACCESS; ++ ++#else ++ ++typedef union _ATOM_MODE_MISC_INFO_ACCESS ++{ ++ USHORT usAccess; ++}ATOM_MODE_MISC_INFO_ACCESS; ++ ++#endif ++ ++// usModeMiscInfo- ++#define ATOM_H_CUTOFF 0x01 ++#define ATOM_HSYNC_POLARITY 0x02 //0=Active High, 1=Active Low ++#define ATOM_VSYNC_POLARITY 0x04 //0=Active High, 1=Active Low ++#define ATOM_V_CUTOFF 0x08 ++#define ATOM_H_REPLICATIONBY2 0x10 ++#define ATOM_V_REPLICATIONBY2 0x20 ++#define ATOM_COMPOSITESYNC 0x40 ++#define ATOM_INTERLACE 0x80 ++#define ATOM_DOUBLE_CLOCK_MODE 0x100 ++#define ATOM_RGB888_MODE 0x200 ++ ++//usRefreshRate- ++#define ATOM_REFRESH_43 43 ++#define ATOM_REFRESH_47 47 ++#define ATOM_REFRESH_56 56 ++#define ATOM_REFRESH_60 60 ++#define ATOM_REFRESH_65 65 ++#define ATOM_REFRESH_70 70 ++#define ATOM_REFRESH_72 72 ++#define ATOM_REFRESH_75 75 ++#define ATOM_REFRESH_85 85 ++ ++// ATOM_MODE_TIMING data are exactly the same as VESA timing data. ++// Translation from EDID to ATOM_MODE_TIMING, use the following formula. ++// ++// VESA_HTOTAL = VESA_ACTIVE + 2* VESA_BORDER + VESA_BLANK ++// = EDID_HA + EDID_HBL ++// VESA_HDISP = VESA_ACTIVE = EDID_HA ++// VESA_HSYNC_START = VESA_ACTIVE + VESA_BORDER + VESA_FRONT_PORCH ++// = EDID_HA + EDID_HSO ++// VESA_HSYNC_WIDTH = VESA_HSYNC_TIME = EDID_HSPW ++// VESA_BORDER = EDID_BORDER ++ ++ ++typedef struct _SET_CRTC_USING_DTD_TIMING_PARAMETERS ++{ ++ USHORT usH_Size; ++ USHORT usH_Blanking_Time; ++ USHORT usV_Size; ++ USHORT usV_Blanking_Time; ++ USHORT usH_SyncOffset; ++ USHORT usH_SyncWidth; ++ USHORT usV_SyncOffset; ++ USHORT usV_SyncWidth; ++ ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; ++ UCHAR ucH_Border; // From DFP EDID ++ UCHAR ucV_Border; ++ UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 ++ UCHAR ucPadding[3]; ++}SET_CRTC_USING_DTD_TIMING_PARAMETERS; ++ ++typedef struct _SET_CRTC_TIMING_PARAMETERS ++{ ++ USHORT usH_Total; // horizontal total ++ USHORT usH_Disp; // horizontal display ++ USHORT usH_SyncStart; // horozontal Sync start ++ USHORT usH_SyncWidth; // horizontal Sync width ++ USHORT usV_Total; // vertical total ++ USHORT usV_Disp; // vertical display ++ USHORT usV_SyncStart; // vertical Sync start ++ USHORT usV_SyncWidth; // vertical Sync width ++ ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; ++ UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 ++ UCHAR ucOverscanRight; // right ++ UCHAR ucOverscanLeft; // left ++ UCHAR ucOverscanBottom; // bottom ++ UCHAR ucOverscanTop; // top ++ UCHAR ucReserved; ++}SET_CRTC_TIMING_PARAMETERS; ++#define SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION SET_CRTC_TIMING_PARAMETERS ++ ++ ++typedef struct _ATOM_MODE_TIMING ++{ ++ USHORT usCRTC_H_Total; ++ USHORT usCRTC_H_Disp; ++ USHORT usCRTC_H_SyncStart; ++ USHORT usCRTC_H_SyncWidth; ++ USHORT usCRTC_V_Total; ++ USHORT usCRTC_V_Disp; ++ USHORT usCRTC_V_SyncStart; ++ USHORT usCRTC_V_SyncWidth; ++ USHORT usPixelClock; //in 10Khz unit ++ ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; ++ USHORT usCRTC_OverscanRight; ++ USHORT usCRTC_OverscanLeft; ++ USHORT usCRTC_OverscanBottom; ++ USHORT usCRTC_OverscanTop; ++ USHORT usReserve; ++ UCHAR ucInternalModeNumber; ++ UCHAR ucRefreshRate; ++}ATOM_MODE_TIMING; ++ ++ ++typedef struct _ATOM_DTD_FORMAT ++{ ++ USHORT usPixClk; ++ USHORT usHActive; ++ USHORT usHBlanking_Time; ++ USHORT usVActive; ++ USHORT usVBlanking_Time; ++ USHORT usHSyncOffset; ++ USHORT usHSyncWidth; ++ USHORT usVSyncOffset; ++ USHORT usVSyncWidth; ++ USHORT usImageHSize; ++ USHORT usImageVSize; ++ UCHAR ucHBorder; ++ UCHAR ucVBorder; ++ ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; ++ UCHAR ucReserved1; ++ UCHAR ucReserved2; ++}ATOM_DTD_FORMAT; ++ ++#define SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004 ++#define SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008 ++#define SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010 ++#define SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020 ++ ++/****************************LVDS Info Table Definitions **********************/ ++//ucTableFormatRevision=1 ++//ucTableContentRevision=1 ++typedef struct _ATOM_LVDS_INFO ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ ATOM_DTD_FORMAT sLCDTiming; ++ USHORT usModePatchTableOffset; ++ USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec. ++ USHORT usOffDelayInMs; ++ UCHAR ucPowerSequenceDigOntoDEin10Ms; ++ UCHAR ucPowerSequenceDEtoBLOnin10Ms; ++ UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level} ++ // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888} ++ // Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled} ++ // Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled} ++ UCHAR ucPanelDefaultRefreshRate; ++ UCHAR ucPanelIdentification; ++ UCHAR ucSS_Id; ++}ATOM_LVDS_INFO; ++ ++//ucTableFormatRevision=1 ++//ucTableContentRevision=2 ++typedef struct _ATOM_LVDS_INFO_V12 ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ ATOM_DTD_FORMAT sLCDTiming; ++ USHORT usExtInfoTableOffset; ++ USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec. ++ USHORT usOffDelayInMs; ++ UCHAR ucPowerSequenceDigOntoDEin10Ms; ++ UCHAR ucPowerSequenceDEtoBLOnin10Ms; ++ UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level} ++ // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888} ++ // Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled} ++ // Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled} ++ UCHAR ucPanelDefaultRefreshRate; ++ UCHAR ucPanelIdentification; ++ UCHAR ucSS_Id; ++ USHORT usLCDVenderID; ++ USHORT usLCDProductID; ++ UCHAR ucLCDPanel_SpecialHandlingCap; ++ UCHAR ucPanelInfoSize; // start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable ++ UCHAR ucReserved[2]; ++}ATOM_LVDS_INFO_V12; ++ ++#define ATOM_LVDS_INFO_LAST ATOM_LVDS_INFO_V12 ++ ++typedef struct _ATOM_PATCH_RECORD_MODE ++{ ++ UCHAR ucRecordType; ++ USHORT usHDisp; ++ USHORT usVDisp; ++}ATOM_PATCH_RECORD_MODE; ++ ++typedef struct _ATOM_LCD_RTS_RECORD ++{ ++ UCHAR ucRecordType; ++ UCHAR ucRTSValue; ++}ATOM_LCD_RTS_RECORD; ++ ++//!! If the record below exits, it shoud always be the first record for easy use in command table!!! ++typedef struct _ATOM_LCD_MODE_CONTROL_CAP ++{ ++ UCHAR ucRecordType; ++ USHORT usLCDCap; ++}ATOM_LCD_MODE_CONTROL_CAP; ++ ++#define LCD_MODE_CAP_BL_OFF 1 ++#define LCD_MODE_CAP_CRTC_OFF 2 ++#define LCD_MODE_CAP_PANEL_OFF 4 ++ ++typedef struct _ATOM_FAKE_EDID_PATCH_RECORD ++{ ++ UCHAR ucRecordType; ++ UCHAR ucFakeEDIDLength; ++ UCHAR ucFakeEDIDString[1]; // This actually has ucFakeEdidLength elements. ++} ATOM_FAKE_EDID_PATCH_RECORD; ++ ++typedef struct _ATOM_PANEL_RESOLUTION_PATCH_RECORD ++{ ++ UCHAR ucRecordType; ++ USHORT usHSize; ++ USHORT usVSize; ++}ATOM_PANEL_RESOLUTION_PATCH_RECORD; ++ ++#define LCD_MODE_PATCH_RECORD_MODE_TYPE 1 ++#define LCD_RTS_RECORD_TYPE 2 ++#define LCD_CAP_RECORD_TYPE 3 ++#define LCD_FAKE_EDID_PATCH_RECORD_TYPE 4 ++#define LCD_PANEL_RESOLUTION_RECORD_TYPE 5 ++#define ATOM_RECORD_END_TYPE 0xFF ++ ++/****************************Spread Spectrum Info Table Definitions **********************/ ++ ++//ucTableFormatRevision=1 ++//ucTableContentRevision=2 ++typedef struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT ++{ ++ USHORT usSpreadSpectrumPercentage; ++ UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD ++ UCHAR ucSS_Step; ++ UCHAR ucSS_Delay; ++ UCHAR ucSS_Id; ++ UCHAR ucRecommandedRef_Div; ++ UCHAR ucSS_Range; //it was reserved for V11 ++}ATOM_SPREAD_SPECTRUM_ASSIGNMENT; ++ ++#define ATOM_MAX_SS_ENTRY 16 ++#define ATOM_DP_SS_ID1 0x0f1 // SS modulation freq=30k ++#define ATOM_DP_SS_ID2 0x0f2 // SS modulation freq=33k ++ ++ ++#define ATOM_SS_DOWN_SPREAD_MODE_MASK 0x00000000 ++#define ATOM_SS_DOWN_SPREAD_MODE 0x00000000 ++#define ATOM_SS_CENTRE_SPREAD_MODE_MASK 0x00000001 ++#define ATOM_SS_CENTRE_SPREAD_MODE 0x00000001 ++#define ATOM_INTERNAL_SS_MASK 0x00000000 ++#define ATOM_EXTERNAL_SS_MASK 0x00000002 ++#define EXEC_SS_STEP_SIZE_SHIFT 2 ++#define EXEC_SS_DELAY_SHIFT 4 ++#define ACTIVEDATA_TO_BLON_DELAY_SHIFT 4 ++ ++typedef struct _ATOM_SPREAD_SPECTRUM_INFO ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ ATOM_SPREAD_SPECTRUM_ASSIGNMENT asSS_Info[ATOM_MAX_SS_ENTRY]; ++}ATOM_SPREAD_SPECTRUM_INFO; ++ ++ ++ ++ ++//ucTVBootUpDefaultStd definiton: ++ ++//ATOM_TV_NTSC 1 ++//ATOM_TV_NTSCJ 2 ++//ATOM_TV_PAL 3 ++//ATOM_TV_PALM 4 ++//ATOM_TV_PALCN 5 ++//ATOM_TV_PALN 6 ++//ATOM_TV_PAL60 7 ++//ATOM_TV_SECAM 8 ++ ++ ++//ucTVSuppportedStd definition: ++#define NTSC_SUPPORT 0x1 ++#define NTSCJ_SUPPORT 0x2 ++ ++#define PAL_SUPPORT 0x4 ++#define PALM_SUPPORT 0x8 ++#define PALCN_SUPPORT 0x10 ++#define PALN_SUPPORT 0x20 ++#define PAL60_SUPPORT 0x40 ++#define SECAM_SUPPORT 0x80 ++ ++#define MAX_SUPPORTED_TV_TIMING 2 ++ ++typedef struct _ATOM_ANALOG_TV_INFO ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ UCHAR ucTV_SuppportedStandard; ++ UCHAR ucTV_BootUpDefaultStandard; ++ UCHAR ucExt_TV_ASIC_ID; ++ UCHAR ucExt_TV_ASIC_SlaveAddr; ++ ATOM_MODE_TIMING aModeTimings[MAX_SUPPORTED_TV_TIMING]; ++}ATOM_ANALOG_TV_INFO; ++ ++ ++/**************************************************************************/ ++// VRAM usage and their defintions ++ ++// One chunk of VRAM used by Bios are for HWICON surfaces,EDID data. ++// Current Mode timing and Dail Timing and/or STD timing data EACH device. They can be broken down as below. ++// All the addresses below are the offsets from the frame buffer start.They all MUST be Dword aligned! ++// To driver: The physical address of this memory portion=mmFB_START(4K aligned)+ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR ++// To Bios: ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR->MM_INDEX ++ ++#ifndef VESA_MEMORY_IN_64K_BLOCK ++#define VESA_MEMORY_IN_64K_BLOCK 0x100 //256*64K=16Mb (Max. VESA memory is 16Mb!) ++#endif ++ ++#define ATOM_EDID_RAW_DATASIZE 256 //In Bytes ++#define ATOM_HWICON_SURFACE_SIZE 4096 //In Bytes ++#define ATOM_HWICON_INFOTABLE_SIZE 32 ++#define MAX_DTD_MODE_IN_VRAM 6 ++#define ATOM_DTD_MODE_SUPPORT_TBL_SIZE (MAX_DTD_MODE_IN_VRAM*28) //28= (SIZEOF ATOM_DTD_FORMAT) ++#define ATOM_STD_MODE_SUPPORT_TBL_SIZE 32*8 //32 is a predefined number,8= (SIZEOF ATOM_STD_FORMAT) ++#define DFP_ENCODER_TYPE_OFFSET 0x80 ++#define DP_ENCODER_LANE_NUMBER 0x84 ++#define DP_ENCODER_LINK_RATE 0x88 ++ ++#define ATOM_HWICON1_SURFACE_ADDR 0 ++#define ATOM_HWICON2_SURFACE_ADDR (ATOM_HWICON1_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE) ++#define ATOM_HWICON_INFOTABLE_ADDR (ATOM_HWICON2_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE) ++#define ATOM_CRT1_EDID_ADDR (ATOM_HWICON_INFOTABLE_ADDR + ATOM_HWICON_INFOTABLE_SIZE) ++#define ATOM_CRT1_DTD_MODE_TBL_ADDR (ATOM_CRT1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) ++#define ATOM_CRT1_STD_MODE_TBL_ADDR (ATOM_CRT1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) ++ ++#define ATOM_LCD1_EDID_ADDR (ATOM_CRT1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) ++#define ATOM_LCD1_DTD_MODE_TBL_ADDR (ATOM_LCD1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) ++#define ATOM_LCD1_STD_MODE_TBL_ADDR (ATOM_LCD1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) ++ ++#define ATOM_TV1_DTD_MODE_TBL_ADDR (ATOM_LCD1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) ++ ++#define ATOM_DFP1_EDID_ADDR (ATOM_TV1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) ++#define ATOM_DFP1_DTD_MODE_TBL_ADDR (ATOM_DFP1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) ++#define ATOM_DFP1_STD_MODE_TBL_ADDR (ATOM_DFP1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) ++ ++#define ATOM_CRT2_EDID_ADDR (ATOM_DFP1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) ++#define ATOM_CRT2_DTD_MODE_TBL_ADDR (ATOM_CRT2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) ++#define ATOM_CRT2_STD_MODE_TBL_ADDR (ATOM_CRT2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) ++ ++#define ATOM_LCD2_EDID_ADDR (ATOM_CRT2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) ++#define ATOM_LCD2_DTD_MODE_TBL_ADDR (ATOM_LCD2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) ++#define ATOM_LCD2_STD_MODE_TBL_ADDR (ATOM_LCD2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) ++ ++#define ATOM_TV2_EDID_ADDR (ATOM_LCD2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) ++#define ATOM_TV2_DTD_MODE_TBL_ADDR (ATOM_TV2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) ++#define ATOM_TV2_STD_MODE_TBL_ADDR (ATOM_TV2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) ++ ++#define ATOM_DFP2_EDID_ADDR (ATOM_TV2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) ++#define ATOM_DFP2_DTD_MODE_TBL_ADDR (ATOM_DFP2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) ++#define ATOM_DFP2_STD_MODE_TBL_ADDR (ATOM_DFP2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) ++ ++#define ATOM_CV_EDID_ADDR (ATOM_DFP2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) ++#define ATOM_CV_DTD_MODE_TBL_ADDR (ATOM_CV_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) ++#define ATOM_CV_STD_MODE_TBL_ADDR (ATOM_CV_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) ++ ++#define ATOM_DFP3_EDID_ADDR (ATOM_CV_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) ++#define ATOM_DFP3_DTD_MODE_TBL_ADDR (ATOM_DFP3_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) ++#define ATOM_DFP3_STD_MODE_TBL_ADDR (ATOM_DFP3_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) ++ ++#define ATOM_DP_TRAINING_TBL_ADDR (ATOM_DFP3_STD_MODE_TBL_ADDR+ATOM_STD_MODE_SUPPORT_TBL_SIZE) ++ ++#define ATOM_STACK_STORAGE_START (ATOM_DP_TRAINING_TBL_ADDR+256) ++#define ATOM_STACK_STORAGE_END ATOM_STACK_STORAGE_START+512 ++ ++//The size below is in Kb! ++#define ATOM_VRAM_RESERVE_SIZE ((((ATOM_STACK_STORAGE_END - ATOM_HWICON1_SURFACE_ADDR)>>10)+4)&0xFFFC) ++ ++#define ATOM_VRAM_OPERATION_FLAGS_MASK 0xC0000000L ++#define ATOM_VRAM_OPERATION_FLAGS_SHIFT 30 ++#define ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION 0x1 ++#define ATOM_VRAM_BLOCK_NEEDS_RESERVATION 0x0 ++ ++#define ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO 1 ++ ++typedef struct _ATOM_FIRMWARE_VRAM_RESERVE_INFO ++{ ++ ULONG ulStartAddrUsedByFirmware; ++ USHORT usFirmwareUseInKb; ++ USHORT usReserved; ++}ATOM_FIRMWARE_VRAM_RESERVE_INFO; ++ ++typedef struct _ATOM_VRAM_USAGE_BY_FIRMWARE ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ ATOM_FIRMWARE_VRAM_RESERVE_INFO asFirmwareVramReserveInfo[ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO]; ++}ATOM_VRAM_USAGE_BY_FIRMWARE; ++ ++/**************************************************************************/ ++//GPIO Pin lut table definition ++typedef struct _ATOM_GPIO_PIN_ASSIGNMENT ++{ ++ USHORT usGpioPin_AIndex; ++ UCHAR ucGpioPinBitShift; ++ UCHAR ucGPIO_ID; ++}ATOM_GPIO_PIN_ASSIGNMENT; ++ ++typedef struct _ATOM_GPIO_PIN_LUT ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ ATOM_GPIO_PIN_ASSIGNMENT asGPIO_Pin[1]; ++}ATOM_GPIO_PIN_LUT; ++ ++/**************************************************************************/ ++ ++ ++#define GPIO_PIN_ACTIVE_HIGH 0x1 ++ ++#define MAX_SUPPORTED_CV_STANDARDS 5 ++ ++// definitions for ATOM_D_INFO.ucSettings ++#define ATOM_GPIO_SETTINGS_BITSHIFT_MASK 0x1F // [4:0] ++#define ATOM_GPIO_SETTINGS_RESERVED_MASK 0x60 // [6:5] = must be zeroed out ++#define ATOM_GPIO_SETTINGS_ACTIVE_MASK 0x80 // [7] ++ ++typedef struct _ATOM_GPIO_INFO ++{ ++ USHORT usAOffset; ++ UCHAR ucSettings; ++ UCHAR ucReserved; ++}ATOM_GPIO_INFO; ++ ++// definitions for ATOM_COMPONENT_VIDEO_INFO.ucMiscInfo (bit vector) ++#define ATOM_CV_RESTRICT_FORMAT_SELECTION 0x2 ++ ++// definitions for ATOM_COMPONENT_VIDEO_INFO.uc480i/uc480p/uc720p/uc1080i ++#define ATOM_GPIO_DEFAULT_MODE_EN 0x80 //[7]; ++#define ATOM_GPIO_SETTING_PERMODE_MASK 0x7F //[6:0] ++ ++// definitions for ATOM_COMPONENT_VIDEO_INFO.ucLetterBoxMode ++//Line 3 out put 5V. ++#define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_A 0x01 //represent gpio 3 state for 16:9 ++#define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_B 0x02 //represent gpio 4 state for 16:9 ++#define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_SHIFT 0x0 ++ ++//Line 3 out put 2.2V ++#define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_A 0x04 //represent gpio 3 state for 4:3 Letter box ++#define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_B 0x08 //represent gpio 4 state for 4:3 Letter box ++#define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_SHIFT 0x2 ++ ++//Line 3 out put 0V ++#define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_A 0x10 //represent gpio 3 state for 4:3 ++#define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_B 0x20 //represent gpio 4 state for 4:3 ++#define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_SHIFT 0x4 ++ ++#define ATOM_CV_LINE3_ASPECTRATIO_MASK 0x3F // bit [5:0] ++ ++#define ATOM_CV_LINE3_ASPECTRATIO_EXIST 0x80 //bit 7 ++ ++//GPIO bit index in gpio setting per mode value, also represend the block no. in gpio blocks. ++#define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_A 3 //bit 3 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode. ++#define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_B 4 //bit 4 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode. ++ ++ ++typedef struct _ATOM_COMPONENT_VIDEO_INFO ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ USHORT usMask_PinRegisterIndex; ++ USHORT usEN_PinRegisterIndex; ++ USHORT usY_PinRegisterIndex; ++ USHORT usA_PinRegisterIndex; ++ UCHAR ucBitShift; ++ UCHAR ucPinActiveState; //ucPinActiveState: Bit0=1 active high, =0 active low ++ ATOM_DTD_FORMAT sReserved; // must be zeroed out ++ UCHAR ucMiscInfo; ++ UCHAR uc480i; ++ UCHAR uc480p; ++ UCHAR uc720p; ++ UCHAR uc1080i; ++ UCHAR ucLetterBoxMode; ++ UCHAR ucReserved[3]; ++ UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC type connector ++ ATOM_GPIO_INFO aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS]; ++ ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_CV_STANDARDS]; ++}ATOM_COMPONENT_VIDEO_INFO; ++ ++//ucTableFormatRevision=2 ++//ucTableContentRevision=1 ++typedef struct _ATOM_COMPONENT_VIDEO_INFO_V21 ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ UCHAR ucMiscInfo; ++ UCHAR uc480i; ++ UCHAR uc480p; ++ UCHAR uc720p; ++ UCHAR uc1080i; ++ UCHAR ucReserved; ++ UCHAR ucLetterBoxMode; ++ UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC type connector ++ ATOM_GPIO_INFO aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS]; ++ ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_CV_STANDARDS]; ++}ATOM_COMPONENT_VIDEO_INFO_V21; ++ ++#define ATOM_COMPONENT_VIDEO_INFO_LAST ATOM_COMPONENT_VIDEO_INFO_V21 ++ ++/**************************************************************************/ ++//Object table starts here ++typedef struct _ATOM_OBJECT_HEADER ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ USHORT usDeviceSupport; ++ USHORT usConnectorObjectTableOffset; ++ USHORT usRouterObjectTableOffset; ++ USHORT usEncoderObjectTableOffset; ++ USHORT usProtectionObjectTableOffset; //only available when Protection block is independent. ++ USHORT usDisplayPathTableOffset; ++}ATOM_OBJECT_HEADER; ++ ++ ++typedef struct _ATOM_DISPLAY_OBJECT_PATH ++{ ++ USHORT usDeviceTag; //supported device ++ USHORT usSize; //the size of ATOM_DISPLAY_OBJECT_PATH ++ USHORT usConnObjectId; //Connector Object ID ++ USHORT usGPUObjectId; //GPU ID ++ USHORT usGraphicObjIds[1]; //1st Encoder Obj source from GPU to last Graphic Obj destinate to connector. ++}ATOM_DISPLAY_OBJECT_PATH; ++ ++typedef struct _ATOM_DISPLAY_OBJECT_PATH_TABLE ++{ ++ UCHAR ucNumOfDispPath; ++ UCHAR ucVersion; ++ UCHAR ucPadding[2]; ++ ATOM_DISPLAY_OBJECT_PATH asDispPath[1]; ++}ATOM_DISPLAY_OBJECT_PATH_TABLE; ++ ++ ++typedef struct _ATOM_OBJECT //each object has this structure ++{ ++ USHORT usObjectID; ++ USHORT usSrcDstTableOffset; ++ USHORT usRecordOffset; //this pointing to a bunch of records defined below ++ USHORT usReserved; ++}ATOM_OBJECT; ++ ++typedef struct _ATOM_OBJECT_TABLE //Above 4 object table offset pointing to a bunch of objects all have this structure ++{ ++ UCHAR ucNumberOfObjects; ++ UCHAR ucPadding[3]; ++ ATOM_OBJECT asObjects[1]; ++}ATOM_OBJECT_TABLE; ++ ++typedef struct _ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT //usSrcDstTableOffset pointing to this structure ++{ ++ UCHAR ucNumberOfSrc; ++ USHORT usSrcObjectID[1]; ++ UCHAR ucNumberOfDst; ++ USHORT usDstObjectID[1]; ++}ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT; ++ ++ ++//Related definitions, all records are differnt but they have a commond header ++typedef struct _ATOM_COMMON_RECORD_HEADER ++{ ++ UCHAR ucRecordType; //An emun to indicate the record type ++ UCHAR ucRecordSize; //The size of the whole record in byte ++}ATOM_COMMON_RECORD_HEADER; ++ ++ ++#define ATOM_I2C_RECORD_TYPE 1 ++#define ATOM_HPD_INT_RECORD_TYPE 2 ++#define ATOM_OUTPUT_PROTECTION_RECORD_TYPE 3 ++#define ATOM_CONNECTOR_DEVICE_TAG_RECORD_TYPE 4 ++#define ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD_TYPE 5 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE ++#define ATOM_ENCODER_FPGA_CONTROL_RECORD_TYPE 6 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE ++#define ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD_TYPE 7 ++#define ATOM_JTAG_RECORD_TYPE 8 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE ++#define ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE 9 ++#define ATOM_ENCODER_DVO_CF_RECORD_TYPE 10 ++#define ATOM_CONNECTOR_CF_RECORD_TYPE 11 ++#define ATOM_CONNECTOR_HARDCODE_DTD_RECORD_TYPE 12 ++#define ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE 13 ++#define ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE 14 ++#define ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE 15 ++ ++//Must be updated when new record type is added,equal to that record definition! ++#define ATOM_MAX_OBJECT_RECORD_NUMBER ATOM_CONNECTOR_CF_RECORD_TYPE ++ ++typedef struct _ATOM_I2C_RECORD ++{ ++ ATOM_COMMON_RECORD_HEADER sheader; ++ ATOM_I2C_ID_CONFIG sucI2cId; ++ UCHAR ucI2CAddr; //The slave address, it's 0 when the record is attached to connector for DDC ++}ATOM_I2C_RECORD; ++ ++typedef struct _ATOM_HPD_INT_RECORD ++{ ++ ATOM_COMMON_RECORD_HEADER sheader; ++ UCHAR ucHPDIntGPIOID; //Corresponding block in GPIO_PIN_INFO table gives the pin info ++ UCHAR ucPluggged_PinState; ++}ATOM_HPD_INT_RECORD; ++ ++ ++typedef struct _ATOM_OUTPUT_PROTECTION_RECORD ++{ ++ ATOM_COMMON_RECORD_HEADER sheader; ++ UCHAR ucProtectionFlag; ++ UCHAR ucReserved; ++}ATOM_OUTPUT_PROTECTION_RECORD; ++ ++typedef struct _ATOM_CONNECTOR_DEVICE_TAG ++{ ++ ULONG ulACPIDeviceEnum; //Reserved for now ++ USHORT usDeviceID; //This Id is same as "ATOM_DEVICE_XXX_SUPPORT" ++ USHORT usPadding; ++}ATOM_CONNECTOR_DEVICE_TAG; ++ ++typedef struct _ATOM_CONNECTOR_DEVICE_TAG_RECORD ++{ ++ ATOM_COMMON_RECORD_HEADER sheader; ++ UCHAR ucNumberOfDevice; ++ UCHAR ucReserved; ++ ATOM_CONNECTOR_DEVICE_TAG asDeviceTag[1]; //This Id is same as "ATOM_DEVICE_XXX_SUPPORT", 1 is only for allocation ++}ATOM_CONNECTOR_DEVICE_TAG_RECORD; ++ ++ ++typedef struct _ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD ++{ ++ ATOM_COMMON_RECORD_HEADER sheader; ++ UCHAR ucConfigGPIOID; ++ UCHAR ucConfigGPIOState; //Set to 1 when it's active high to enable external flow in ++ UCHAR ucFlowinGPIPID; ++ UCHAR ucExtInGPIPID; ++}ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD; ++ ++typedef struct _ATOM_ENCODER_FPGA_CONTROL_RECORD ++{ ++ ATOM_COMMON_RECORD_HEADER sheader; ++ UCHAR ucCTL1GPIO_ID; ++ UCHAR ucCTL1GPIOState; //Set to 1 when it's active high ++ UCHAR ucCTL2GPIO_ID; ++ UCHAR ucCTL2GPIOState; //Set to 1 when it's active high ++ UCHAR ucCTL3GPIO_ID; ++ UCHAR ucCTL3GPIOState; //Set to 1 when it's active high ++ UCHAR ucCTLFPGA_IN_ID; ++ UCHAR ucPadding[3]; ++}ATOM_ENCODER_FPGA_CONTROL_RECORD; ++ ++typedef struct _ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD ++{ ++ ATOM_COMMON_RECORD_HEADER sheader; ++ UCHAR ucGPIOID; //Corresponding block in GPIO_PIN_INFO table gives the pin info ++ UCHAR ucTVActiveState; //Indicating when the pin==0 or 1 when TV is connected ++}ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD; ++ ++typedef struct _ATOM_JTAG_RECORD ++{ ++ ATOM_COMMON_RECORD_HEADER sheader; ++ UCHAR ucTMSGPIO_ID; ++ UCHAR ucTMSGPIOState; //Set to 1 when it's active high ++ UCHAR ucTCKGPIO_ID; ++ UCHAR ucTCKGPIOState; //Set to 1 when it's active high ++ UCHAR ucTDOGPIO_ID; ++ UCHAR ucTDOGPIOState; //Set to 1 when it's active high ++ UCHAR ucTDIGPIO_ID; ++ UCHAR ucTDIGPIOState; //Set to 1 when it's active high ++ UCHAR ucPadding[2]; ++}ATOM_JTAG_RECORD; ++ ++ ++//The following generic object gpio pin control record type will replace JTAG_RECORD/FPGA_CONTROL_RECORD/DVI_EXT_INPUT_RECORD above gradually ++typedef struct _ATOM_GPIO_PIN_CONTROL_PAIR ++{ ++ UCHAR ucGPIOID; // GPIO_ID, find the corresponding ID in GPIO_LUT table ++ UCHAR ucGPIO_PinState; // Pin state showing how to set-up the pin ++}ATOM_GPIO_PIN_CONTROL_PAIR; ++ ++typedef struct _ATOM_OBJECT_GPIO_CNTL_RECORD ++{ ++ ATOM_COMMON_RECORD_HEADER sheader; ++ UCHAR ucFlags; // Future expnadibility ++ UCHAR ucNumberOfPins; // Number of GPIO pins used to control the object ++ ATOM_GPIO_PIN_CONTROL_PAIR asGpio[1]; // the real gpio pin pair determined by number of pins ucNumberOfPins ++}ATOM_OBJECT_GPIO_CNTL_RECORD; ++ ++//Definitions for GPIO pin state ++#define GPIO_PIN_TYPE_INPUT 0x00 ++#define GPIO_PIN_TYPE_OUTPUT 0x10 ++#define GPIO_PIN_TYPE_HW_CONTROL 0x20 ++ ++//For GPIO_PIN_TYPE_OUTPUT the following is defined ++#define GPIO_PIN_OUTPUT_STATE_MASK 0x01 ++#define GPIO_PIN_OUTPUT_STATE_SHIFT 0 ++#define GPIO_PIN_STATE_ACTIVE_LOW 0x0 ++#define GPIO_PIN_STATE_ACTIVE_HIGH 0x1 ++ ++typedef struct _ATOM_ENCODER_DVO_CF_RECORD ++{ ++ ATOM_COMMON_RECORD_HEADER sheader; ++ ULONG ulStrengthControl; // DVOA strength control for CF ++ UCHAR ucPadding[2]; ++}ATOM_ENCODER_DVO_CF_RECORD; ++ ++// value for ATOM_CONNECTOR_CF_RECORD.ucConnectedDvoBundle ++#define ATOM_CONNECTOR_CF_RECORD_CONNECTED_UPPER12BITBUNDLEA 1 ++#define ATOM_CONNECTOR_CF_RECORD_CONNECTED_LOWER12BITBUNDLEB 2 ++ ++typedef struct _ATOM_CONNECTOR_CF_RECORD ++{ ++ ATOM_COMMON_RECORD_HEADER sheader; ++ USHORT usMaxPixClk; ++ UCHAR ucFlowCntlGpioId; ++ UCHAR ucSwapCntlGpioId; ++ UCHAR ucConnectedDvoBundle; ++ UCHAR ucPadding; ++}ATOM_CONNECTOR_CF_RECORD; ++ ++typedef struct _ATOM_CONNECTOR_HARDCODE_DTD_RECORD ++{ ++ ATOM_COMMON_RECORD_HEADER sheader; ++ ATOM_DTD_FORMAT asTiming; ++}ATOM_CONNECTOR_HARDCODE_DTD_RECORD; ++ ++typedef struct _ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD ++{ ++ ATOM_COMMON_RECORD_HEADER sheader; //ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE ++ UCHAR ucSubConnectorType; //CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D|X_ID_DUAL_LINK_DVI_D|HDMI_TYPE_A ++ UCHAR ucReserved; ++}ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD; ++ ++ ++typedef struct _ATOM_ROUTER_DDC_PATH_SELECT_RECORD ++{ ++ ATOM_COMMON_RECORD_HEADER sheader; ++ UCHAR ucMuxType; //decide the number of ucMuxState, =0, no pin state, =1: single state with complement, >1: multiple state ++ UCHAR ucMuxControlPin; ++ UCHAR ucMuxState[2]; //for alligment purpose ++}ATOM_ROUTER_DDC_PATH_SELECT_RECORD; ++ ++typedef struct _ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD ++{ ++ ATOM_COMMON_RECORD_HEADER sheader; ++ UCHAR ucMuxType; ++ UCHAR ucMuxControlPin; ++ UCHAR ucMuxState[2]; //for alligment purpose ++}ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD; ++ ++// define ucMuxType ++#define ATOM_ROUTER_MUX_PIN_STATE_MASK 0x0f ++#define ATOM_ROUTER_MUX_PIN_SINGLE_STATE_COMPLEMENT 0x01 ++ ++/**************************************************************************/ ++//ASIC voltage data table starts here ++ ++typedef struct _ATOM_VOLTAGE_INFO_HEADER ++{ ++ USHORT usVDDCBaseLevel; //In number of 50mv unit ++ USHORT usReserved; //For possible extension table offset ++ UCHAR ucNumOfVoltageEntries; ++ UCHAR ucBytesPerVoltageEntry; ++ UCHAR ucVoltageStep; //Indicating in how many mv increament is one step, 0.5mv unit ++ UCHAR ucDefaultVoltageEntry; ++ UCHAR ucVoltageControlI2cLine; ++ UCHAR ucVoltageControlAddress; ++ UCHAR ucVoltageControlOffset; ++}ATOM_VOLTAGE_INFO_HEADER; ++ ++typedef struct _ATOM_VOLTAGE_INFO ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ ATOM_VOLTAGE_INFO_HEADER viHeader; ++ UCHAR ucVoltageEntries[64]; //64 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries*ucBytesPerVoltageEntry ++}ATOM_VOLTAGE_INFO; ++ ++ ++typedef struct _ATOM_VOLTAGE_FORMULA ++{ ++ USHORT usVoltageBaseLevel; // In number of 1mv unit ++ USHORT usVoltageStep; // Indicating in how many mv increament is one step, 1mv unit ++ UCHAR ucNumOfVoltageEntries; // Number of Voltage Entry, which indicate max Voltage ++ UCHAR ucFlag; // bit0=0 :step is 1mv =1 0.5mv ++ UCHAR ucBaseVID; // if there is no lookup table, VID= BaseVID + ( Vol - BaseLevle ) /VoltageStep ++ UCHAR ucReserved; ++ UCHAR ucVIDAdjustEntries[32]; // 32 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries ++}ATOM_VOLTAGE_FORMULA; ++ ++typedef struct _ATOM_VOLTAGE_CONTROL ++{ ++ UCHAR ucVoltageControlId; //Indicate it is controlled by I2C or GPIO or HW state machine ++ UCHAR ucVoltageControlI2cLine; ++ UCHAR ucVoltageControlAddress; ++ UCHAR ucVoltageControlOffset; ++ USHORT usGpioPin_AIndex; //GPIO_PAD register index ++ UCHAR ucGpioPinBitShift[9]; //at most 8 pin support 255 VIDs, termintate with 0xff ++ UCHAR ucReserved; ++}ATOM_VOLTAGE_CONTROL; ++ ++// Define ucVoltageControlId ++#define VOLTAGE_CONTROLLED_BY_HW 0x00 ++#define VOLTAGE_CONTROLLED_BY_I2C_MASK 0x7F ++#define VOLTAGE_CONTROLLED_BY_GPIO 0x80 ++#define VOLTAGE_CONTROL_ID_LM64 0x01 //I2C control, used for R5xx Core Voltage ++#define VOLTAGE_CONTROL_ID_DAC 0x02 //I2C control, used for R5xx/R6xx MVDDC,MVDDQ or VDDCI ++#define VOLTAGE_CONTROL_ID_VT116xM 0x03 //I2C control, used for R6xx Core Voltage ++#define VOLTAGE_CONTROL_ID_DS4402 0x04 ++ ++typedef struct _ATOM_VOLTAGE_OBJECT ++{ ++ UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI ++ UCHAR ucSize; //Size of Object ++ ATOM_VOLTAGE_CONTROL asControl; //describ how to control ++ ATOM_VOLTAGE_FORMULA asFormula; //Indicate How to convert real Voltage to VID ++}ATOM_VOLTAGE_OBJECT; ++ ++typedef struct _ATOM_VOLTAGE_OBJECT_INFO ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ ATOM_VOLTAGE_OBJECT asVoltageObj[3]; //Info for Voltage control ++}ATOM_VOLTAGE_OBJECT_INFO; ++ ++typedef struct _ATOM_LEAKID_VOLTAGE ++{ ++ UCHAR ucLeakageId; ++ UCHAR ucReserved; ++ USHORT usVoltage; ++}ATOM_LEAKID_VOLTAGE; ++ ++typedef struct _ATOM_ASIC_PROFILE_VOLTAGE ++{ ++ UCHAR ucProfileId; ++ UCHAR ucReserved; ++ USHORT usSize; ++ USHORT usEfuseSpareStartAddr; ++ USHORT usFuseIndex[8]; //from LSB to MSB, Max 8bit,end of 0xffff if less than 8 efuse id, ++ ATOM_LEAKID_VOLTAGE asLeakVol[2]; //Leakid and relatd voltage ++}ATOM_ASIC_PROFILE_VOLTAGE; ++ ++//ucProfileId ++#define ATOM_ASIC_PROFILE_ID_EFUSE_VOLTAGE 1 ++#define ATOM_ASIC_PROFILE_ID_EFUSE_PERFORMANCE_VOLTAGE 1 ++#define ATOM_ASIC_PROFILE_ID_EFUSE_THERMAL_VOLTAGE 2 ++ ++typedef struct _ATOM_ASIC_PROFILING_INFO ++{ ++ ATOM_COMMON_TABLE_HEADER asHeader; ++ ATOM_ASIC_PROFILE_VOLTAGE asVoltage; ++}ATOM_ASIC_PROFILING_INFO; ++ ++typedef struct _ATOM_POWER_SOURCE_OBJECT ++{ ++ UCHAR ucPwrSrcId; // Power source ++ UCHAR ucPwrSensorType; // GPIO, I2C or none ++ UCHAR ucPwrSensId; // if GPIO detect, it is GPIO id, if I2C detect, it is I2C id ++ UCHAR ucPwrSensSlaveAddr; // Slave address if I2C detect ++ UCHAR ucPwrSensRegIndex; // I2C register Index if I2C detect ++ UCHAR ucPwrSensRegBitMask; // detect which bit is used if I2C detect ++ UCHAR ucPwrSensActiveState; // high active or low active ++ UCHAR ucReserve[3]; // reserve ++ USHORT usSensPwr; // in unit of watt ++}ATOM_POWER_SOURCE_OBJECT; ++ ++typedef struct _ATOM_POWER_SOURCE_INFO ++{ ++ ATOM_COMMON_TABLE_HEADER asHeader; ++ UCHAR asPwrbehave[16]; ++ ATOM_POWER_SOURCE_OBJECT asPwrObj[1]; ++}ATOM_POWER_SOURCE_INFO; ++ ++ ++//Define ucPwrSrcId ++#define POWERSOURCE_PCIE_ID1 0x00 ++#define POWERSOURCE_6PIN_CONNECTOR_ID1 0x01 ++#define POWERSOURCE_8PIN_CONNECTOR_ID1 0x02 ++#define POWERSOURCE_6PIN_CONNECTOR_ID2 0x04 ++#define POWERSOURCE_8PIN_CONNECTOR_ID2 0x08 ++ ++//define ucPwrSensorId ++#define POWER_SENSOR_ALWAYS 0x00 ++#define POWER_SENSOR_GPIO 0x01 ++#define POWER_SENSOR_I2C 0x02 ++ ++/**************************************************************************/ ++// This portion is only used when ext thermal chip or engine/memory clock SS chip is populated on a design ++//Memory SS Info Table ++//Define Memory Clock SS chip ID ++#define ICS91719 1 ++#define ICS91720 2 ++ ++//Define one structure to inform SW a "block of data" writing to external SS chip via I2C protocol ++typedef struct _ATOM_I2C_DATA_RECORD ++{ ++ UCHAR ucNunberOfBytes; //Indicates how many bytes SW needs to write to the external ASIC for one block, besides to "Start" and "Stop" ++ UCHAR ucI2CData[1]; //I2C data in bytes, should be less than 16 bytes usually ++}ATOM_I2C_DATA_RECORD; ++ ++ ++//Define one structure to inform SW how many blocks of data writing to external SS chip via I2C protocol, in addition to other information ++typedef struct _ATOM_I2C_DEVICE_SETUP_INFO ++{ ++ ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; //I2C line and HW/SW assisted cap. ++ UCHAR ucSSChipID; //SS chip being used ++ UCHAR ucSSChipSlaveAddr; //Slave Address to set up this SS chip ++ UCHAR ucNumOfI2CDataRecords; //number of data block ++ ATOM_I2C_DATA_RECORD asI2CData[1]; ++}ATOM_I2C_DEVICE_SETUP_INFO; ++ ++//========================================================================================== ++typedef struct _ATOM_ASIC_MVDD_INFO ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ ATOM_I2C_DEVICE_SETUP_INFO asI2CSetup[1]; ++}ATOM_ASIC_MVDD_INFO; ++ ++//========================================================================================== ++#define ATOM_MCLK_SS_INFO ATOM_ASIC_MVDD_INFO ++ ++//========================================================================================== ++/**************************************************************************/ ++ ++typedef struct _ATOM_ASIC_SS_ASSIGNMENT ++{ ++ ULONG ulTargetClockRange; //Clock Out frequence (VCO ), in unit of 10Khz ++ USHORT usSpreadSpectrumPercentage; //in unit of 0.01% ++ USHORT usSpreadRateInKhz; //in unit of kHz, modulation freq ++ UCHAR ucClockIndication; //Indicate which clock source needs SS ++ UCHAR ucSpreadSpectrumMode; //Bit1=0 Down Spread,=1 Center Spread. ++ UCHAR ucReserved[2]; ++}ATOM_ASIC_SS_ASSIGNMENT; ++ ++//Define ucSpreadSpectrumType ++#define ASIC_INTERNAL_MEMORY_SS 1 ++#define ASIC_INTERNAL_ENGINE_SS 2 ++#define ASIC_INTERNAL_UVD_SS 3 ++ ++typedef struct _ATOM_ASIC_INTERNAL_SS_INFO{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ ATOM_ASIC_SS_ASSIGNMENT asSpreadSpectrum[4]; ++}ATOM_ASIC_INTERNAL_SS_INFO; ++ ++//==============================Scratch Pad Definition Portion=============================== ++#define ATOM_DEVICE_CONNECT_INFO_DEF 0 ++#define ATOM_ROM_LOCATION_DEF 1 ++#define ATOM_TV_STANDARD_DEF 2 ++#define ATOM_ACTIVE_INFO_DEF 3 ++#define ATOM_LCD_INFO_DEF 4 ++#define ATOM_DOS_REQ_INFO_DEF 5 ++#define ATOM_ACC_CHANGE_INFO_DEF 6 ++#define ATOM_DOS_MODE_INFO_DEF 7 ++#define ATOM_I2C_CHANNEL_STATUS_DEF 8 ++#define ATOM_I2C_CHANNEL_STATUS1_DEF 9 ++ ++ ++// BIOS_0_SCRATCH Definition ++#define ATOM_S0_CRT1_MONO 0x00000001L ++#define ATOM_S0_CRT1_COLOR 0x00000002L ++#define ATOM_S0_CRT1_MASK (ATOM_S0_CRT1_MONO+ATOM_S0_CRT1_COLOR) ++ ++#define ATOM_S0_TV1_COMPOSITE_A 0x00000004L ++#define ATOM_S0_TV1_SVIDEO_A 0x00000008L ++#define ATOM_S0_TV1_MASK_A (ATOM_S0_TV1_COMPOSITE_A+ATOM_S0_TV1_SVIDEO_A) ++ ++#define ATOM_S0_CV_A 0x00000010L ++#define ATOM_S0_CV_DIN_A 0x00000020L ++#define ATOM_S0_CV_MASK_A (ATOM_S0_CV_A+ATOM_S0_CV_DIN_A) ++ ++ ++#define ATOM_S0_CRT2_MONO 0x00000100L ++#define ATOM_S0_CRT2_COLOR 0x00000200L ++#define ATOM_S0_CRT2_MASK (ATOM_S0_CRT2_MONO+ATOM_S0_CRT2_COLOR) ++ ++#define ATOM_S0_TV1_COMPOSITE 0x00000400L ++#define ATOM_S0_TV1_SVIDEO 0x00000800L ++#define ATOM_S0_TV1_SCART 0x00004000L ++#define ATOM_S0_TV1_MASK (ATOM_S0_TV1_COMPOSITE+ATOM_S0_TV1_SVIDEO+ATOM_S0_TV1_SCART) ++ ++#define ATOM_S0_CV 0x00001000L ++#define ATOM_S0_CV_DIN 0x00002000L ++#define ATOM_S0_CV_MASK (ATOM_S0_CV+ATOM_S0_CV_DIN) ++ ++ ++#define ATOM_S0_DFP1 0x00010000L ++#define ATOM_S0_DFP2 0x00020000L ++#define ATOM_S0_LCD1 0x00040000L ++#define ATOM_S0_LCD2 0x00080000L ++#define ATOM_S0_TV2 0x00100000L ++#define ATOM_S0_DFP3 0x00200000L ++ ++#define ATOM_S0_FAD_REGISTER_BUG 0x02000000L // If set, indicates we are running a PCIE asic with ++ // the FAD/HDP reg access bug. Bit is read by DAL ++ ++#define ATOM_S0_THERMAL_STATE_MASK 0x1C000000L ++#define ATOM_S0_THERMAL_STATE_SHIFT 26 ++ ++#define ATOM_S0_SYSTEM_POWER_STATE_MASK 0xE0000000L ++#define ATOM_S0_SYSTEM_POWER_STATE_SHIFT 29 ++ ++#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_AC 1 ++#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_DC 2 ++#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LITEAC 3 ++ ++//Byte aligned defintion for BIOS usage ++#define ATOM_S0_CRT1_MONOb0 0x01 ++#define ATOM_S0_CRT1_COLORb0 0x02 ++#define ATOM_S0_CRT1_MASKb0 (ATOM_S0_CRT1_MONOb0+ATOM_S0_CRT1_COLORb0) ++ ++#define ATOM_S0_TV1_COMPOSITEb0 0x04 ++#define ATOM_S0_TV1_SVIDEOb0 0x08 ++#define ATOM_S0_TV1_MASKb0 (ATOM_S0_TV1_COMPOSITEb0+ATOM_S0_TV1_SVIDEOb0) ++ ++#define ATOM_S0_CVb0 0x10 ++#define ATOM_S0_CV_DINb0 0x20 ++#define ATOM_S0_CV_MASKb0 (ATOM_S0_CVb0+ATOM_S0_CV_DINb0) ++ ++#define ATOM_S0_CRT2_MONOb1 0x01 ++#define ATOM_S0_CRT2_COLORb1 0x02 ++#define ATOM_S0_CRT2_MASKb1 (ATOM_S0_CRT2_MONOb1+ATOM_S0_CRT2_COLORb1) ++ ++#define ATOM_S0_TV1_COMPOSITEb1 0x04 ++#define ATOM_S0_TV1_SVIDEOb1 0x08 ++#define ATOM_S0_TV1_SCARTb1 0x40 ++#define ATOM_S0_TV1_MASKb1 (ATOM_S0_TV1_COMPOSITEb1+ATOM_S0_TV1_SVIDEOb1+ATOM_S0_TV1_SCARTb1) ++ ++#define ATOM_S0_CVb1 0x10 ++#define ATOM_S0_CV_DINb1 0x20 ++#define ATOM_S0_CV_MASKb1 (ATOM_S0_CVb1+ATOM_S0_CV_DINb1) ++ ++#define ATOM_S0_DFP1b2 0x01 ++#define ATOM_S0_DFP2b2 0x02 ++#define ATOM_S0_LCD1b2 0x04 ++#define ATOM_S0_LCD2b2 0x08 ++#define ATOM_S0_TV2b2 0x10 ++#define ATOM_S0_DFP3b2 0x20 ++ ++#define ATOM_S0_THERMAL_STATE_MASKb3 0x1C ++#define ATOM_S0_THERMAL_STATE_SHIFTb3 2 ++ ++#define ATOM_S0_SYSTEM_POWER_STATE_MASKb3 0xE0 ++#define ATOM_S0_LCD1_SHIFT 18 ++ ++// BIOS_1_SCRATCH Definition ++#define ATOM_S1_ROM_LOCATION_MASK 0x0000FFFFL ++#define ATOM_S1_PCI_BUS_DEV_MASK 0xFFFF0000L ++ ++ ++// BIOS_2_SCRATCH Definition ++#define ATOM_S2_TV1_STANDARD_MASK 0x0000000FL ++#define ATOM_S2_CURRENT_BL_LEVEL_MASK 0x0000FF00L ++#define ATOM_S2_CURRENT_BL_LEVEL_SHIFT 8 ++ ++#define ATOM_S2_CRT1_DPMS_STATE 0x00010000L ++#define ATOM_S2_LCD1_DPMS_STATE 0x00020000L ++#define ATOM_S2_TV1_DPMS_STATE 0x00040000L ++#define ATOM_S2_DFP1_DPMS_STATE 0x00080000L ++#define ATOM_S2_CRT2_DPMS_STATE 0x00100000L ++#define ATOM_S2_LCD2_DPMS_STATE 0x00200000L ++#define ATOM_S2_TV2_DPMS_STATE 0x00400000L ++#define ATOM_S2_DFP2_DPMS_STATE 0x00800000L ++#define ATOM_S2_CV_DPMS_STATE 0x01000000L ++#define ATOM_S2_DFP3_DPMS_STATE 0x02000000L ++ ++#define ATOM_S2_DEVICE_DPMS_STATE (ATOM_S2_CRT1_DPMS_STATE+ATOM_S2_LCD1_DPMS_STATE+ATOM_S2_TV1_DPMS_STATE+\ ++ ATOM_S2_DFP1I_DPMS_STATE+ATOM_S2_CRT2_DPMS_STATE+ATOM_S2_LCD2_DPMS_STATE+\ ++ ATOM_S2_TV2_DPMS_STATE+ATOM_S2_DFP1X_DPMS_STATE+ATOM_S2_CV_DPMS_STATE+\ ++ ATOM_S2_DFP3_DPMS_STATE) ++ ++ ++#define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK 0x0C000000L ++#define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK_SHIFT 26 ++#define ATOM_S2_FORCEDLOWPWRMODE_STATE_CHANGE 0x10000000L ++ ++#define ATOM_S2_VRI_BRIGHT_ENABLE 0x20000000L ++ ++#define ATOM_S2_DISPLAY_ROTATION_0_DEGREE 0x0 ++#define ATOM_S2_DISPLAY_ROTATION_90_DEGREE 0x1 ++#define ATOM_S2_DISPLAY_ROTATION_180_DEGREE 0x2 ++#define ATOM_S2_DISPLAY_ROTATION_270_DEGREE 0x3 ++#define ATOM_S2_DISPLAY_ROTATION_DEGREE_SHIFT 30 ++#define ATOM_S2_DISPLAY_ROTATION_ANGLE_MASK 0xC0000000L ++ ++ ++//Byte aligned defintion for BIOS usage ++#define ATOM_S2_TV1_STANDARD_MASKb0 0x0F ++#define ATOM_S2_CURRENT_BL_LEVEL_MASKb1 0xFF ++#define ATOM_S2_CRT1_DPMS_STATEb2 0x01 ++#define ATOM_S2_LCD1_DPMS_STATEb2 0x02 ++#define ATOM_S2_TV1_DPMS_STATEb2 0x04 ++#define ATOM_S2_DFP1_DPMS_STATEb2 0x08 ++#define ATOM_S2_CRT2_DPMS_STATEb2 0x10 ++#define ATOM_S2_LCD2_DPMS_STATEb2 0x20 ++#define ATOM_S2_TV2_DPMS_STATEb2 0x40 ++#define ATOM_S2_DFP2_DPMS_STATEb2 0x80 ++#define ATOM_S2_CV_DPMS_STATEb3 0x01 ++#define ATOM_S2_DFP3_DPMS_STATEb3 0x02 ++ ++#define ATOM_S2_DEVICE_DPMS_MASKw1 0x3FF ++#define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASKb3 0x0C ++#define ATOM_S2_FORCEDLOWPWRMODE_STATE_CHANGEb3 0x10 ++#define ATOM_S2_VRI_BRIGHT_ENABLEb3 0x20 ++#define ATOM_S2_ROTATION_STATE_MASKb3 0xC0 ++ ++ ++// BIOS_3_SCRATCH Definition ++#define ATOM_S3_CRT1_ACTIVE 0x00000001L ++#define ATOM_S3_LCD1_ACTIVE 0x00000002L ++#define ATOM_S3_TV1_ACTIVE 0x00000004L ++#define ATOM_S3_DFP1_ACTIVE 0x00000008L ++#define ATOM_S3_CRT2_ACTIVE 0x00000010L ++#define ATOM_S3_LCD2_ACTIVE 0x00000020L ++#define ATOM_S3_TV2_ACTIVE 0x00000040L ++#define ATOM_S3_DFP2_ACTIVE 0x00000080L ++#define ATOM_S3_CV_ACTIVE 0x00000100L ++#define ATOM_S3_DFP3_ACTIVE 0x00000200L ++ ++#define ATOM_S3_DEVICE_ACTIVE_MASK 0x000003FFL ++ ++#define ATOM_S3_CRT1_CRTC_ACTIVE 0x00010000L ++#define ATOM_S3_LCD1_CRTC_ACTIVE 0x00020000L ++#define ATOM_S3_TV1_CRTC_ACTIVE 0x00040000L ++#define ATOM_S3_DFP1_CRTC_ACTIVE 0x00080000L ++#define ATOM_S3_CRT2_CRTC_ACTIVE 0x00100000L ++#define ATOM_S3_LCD2_CRTC_ACTIVE 0x00200000L ++#define ATOM_S3_TV2_CRTC_ACTIVE 0x00400000L ++#define ATOM_S3_DFP2_CRTC_ACTIVE 0x00800000L ++#define ATOM_S3_CV_CRTC_ACTIVE 0x01000000L ++#define ATOM_S3_DFP3_CRTC_ACTIVE 0x02000000L ++ ++#define ATOM_S3_DEVICE_CRTC_ACTIVE_MASK 0x03FF0000L ++#define ATOM_S3_ASIC_GUI_ENGINE_HUNG 0x20000000L ++#define ATOM_S3_ALLOW_FAST_PWR_SWITCH 0x40000000L ++#define ATOM_S3_RQST_GPU_USE_MIN_PWR 0x80000000L ++ ++//Byte aligned defintion for BIOS usage ++#define ATOM_S3_CRT1_ACTIVEb0 0x01 ++#define ATOM_S3_LCD1_ACTIVEb0 0x02 ++#define ATOM_S3_TV1_ACTIVEb0 0x04 ++#define ATOM_S3_DFP1_ACTIVEb0 0x08 ++#define ATOM_S3_CRT2_ACTIVEb0 0x10 ++#define ATOM_S3_LCD2_ACTIVEb0 0x20 ++#define ATOM_S3_TV2_ACTIVEb0 0x40 ++#define ATOM_S3_DFP2_ACTIVEb0 0x80 ++#define ATOM_S3_CV_ACTIVEb1 0x01 ++#define ATOM_S3_DFP3_ACTIVEb1 0x02 ++ ++#define ATOM_S3_ACTIVE_CRTC1w0 0x3FF ++ ++#define ATOM_S3_CRT1_CRTC_ACTIVEb2 0x01 ++#define ATOM_S3_LCD1_CRTC_ACTIVEb2 0x02 ++#define ATOM_S3_TV1_CRTC_ACTIVEb2 0x04 ++#define ATOM_S3_DFP1_CRTC_ACTIVEb2 0x08 ++#define ATOM_S3_CRT2_CRTC_ACTIVEb2 0x10 ++#define ATOM_S3_LCD2_CRTC_ACTIVEb2 0x20 ++#define ATOM_S3_TV2_CRTC_ACTIVEb2 0x40 ++#define ATOM_S3_DFP2_CRTC_ACTIVEb2 0x80 ++#define ATOM_S3_CV_CRTC_ACTIVEb3 0x01 ++#define ATOM_S3_DFP3_CRTC_ACTIVEb3 0x02 ++ ++#define ATOM_S3_ACTIVE_CRTC2w1 0x3FF ++ ++#define ATOM_S3_ASIC_GUI_ENGINE_HUNGb3 0x20 ++#define ATOM_S3_ALLOW_FAST_PWR_SWITCHb3 0x40 ++#define ATOM_S3_RQST_GPU_USE_MIN_PWRb3 0x80 ++ ++// BIOS_4_SCRATCH Definition ++#define ATOM_S4_LCD1_PANEL_ID_MASK 0x000000FFL ++#define ATOM_S4_LCD1_REFRESH_MASK 0x0000FF00L ++#define ATOM_S4_LCD1_REFRESH_SHIFT 8 ++ ++ ++//Byte aligned defintion for BIOS usage ++#define ATOM_S4_LCD1_PANEL_ID_MASKb0 0x0FF ++#define ATOM_S4_LCD1_REFRESH_MASKb1 ATOM_S4_LCD1_PANEL_ID_MASKb0 ++#define ATOM_S4_VRAM_INFO_MASKb2 ATOM_S4_LCD1_PANEL_ID_MASKb0 ++ ++ ++// BIOS_5_SCRATCH Definition, BIOS_5_SCRATCH is used by Firmware only !!!! ++#define ATOM_S5_DOS_REQ_CRT1b0 0x01 ++#define ATOM_S5_DOS_REQ_LCD1b0 0x02 ++#define ATOM_S5_DOS_REQ_TV1b0 0x04 ++#define ATOM_S5_DOS_REQ_DFP1b0 0x08 ++#define ATOM_S5_DOS_REQ_CRT2b0 0x10 ++#define ATOM_S5_DOS_REQ_LCD2b0 0x20 ++#define ATOM_S5_DOS_REQ_TV2b0 0x40 ++#define ATOM_S5_DOS_REQ_DFP2b0 0x80 ++#define ATOM_S5_DOS_REQ_CVb1 0x01 ++#define ATOM_S5_DOS_REQ_DFP3b1 0x02 ++ ++#define ATOM_S5_DOS_REQ_DEVICEw0 0x03FF ++ ++#define ATOM_S5_DOS_REQ_CRT1 0x0001 ++#define ATOM_S5_DOS_REQ_LCD1 0x0002 ++#define ATOM_S5_DOS_REQ_TV1 0x0004 ++#define ATOM_S5_DOS_REQ_DFP1 0x0008 ++#define ATOM_S5_DOS_REQ_CRT2 0x0010 ++#define ATOM_S5_DOS_REQ_LCD2 0x0020 ++#define ATOM_S5_DOS_REQ_TV2 0x0040 ++#define ATOM_S5_DOS_REQ_DFP2 0x0080 ++#define ATOM_S5_DOS_REQ_CV 0x0100 ++#define ATOM_S5_DOS_REQ_DFP3 0x0200 ++ ++#define ATOM_S5_DOS_FORCE_CRT1b2 ATOM_S5_DOS_REQ_CRT1b0 ++#define ATOM_S5_DOS_FORCE_TV1b2 ATOM_S5_DOS_REQ_TV1b0 ++#define ATOM_S5_DOS_FORCE_CRT2b2 ATOM_S5_DOS_REQ_CRT2b0 ++#define ATOM_S5_DOS_FORCE_CVb3 ATOM_S5_DOS_REQ_CVb1 ++#define ATOM_S5_DOS_FORCE_DEVICEw1 (ATOM_S5_DOS_FORCE_CRT1b2+ATOM_S5_DOS_FORCE_TV1b2+ATOM_S5_DOS_FORCE_CRT2b2+\ ++ (ATOM_S5_DOS_FORCE_CVb3<<8)) ++ ++// BIOS_6_SCRATCH Definition ++#define ATOM_S6_DEVICE_CHANGE 0x00000001L ++#define ATOM_S6_SCALER_CHANGE 0x00000002L ++#define ATOM_S6_LID_CHANGE 0x00000004L ++#define ATOM_S6_DOCKING_CHANGE 0x00000008L ++#define ATOM_S6_ACC_MODE 0x00000010L ++#define ATOM_S6_EXT_DESKTOP_MODE 0x00000020L ++#define ATOM_S6_LID_STATE 0x00000040L ++#define ATOM_S6_DOCK_STATE 0x00000080L ++#define ATOM_S6_CRITICAL_STATE 0x00000100L ++#define ATOM_S6_HW_I2C_BUSY_STATE 0x00000200L ++#define ATOM_S6_THERMAL_STATE_CHANGE 0x00000400L ++#define ATOM_S6_INTERRUPT_SET_BY_BIOS 0x00000800L ++#define ATOM_S6_REQ_LCD_EXPANSION_FULL 0x00001000L //Normal expansion Request bit for LCD ++#define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIO 0x00002000L //Aspect ratio expansion Request bit for LCD ++ ++#define ATOM_S6_DISPLAY_STATE_CHANGE 0x00004000L //This bit is recycled when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_H_expansion ++#define ATOM_S6_I2C_STATE_CHANGE 0x00008000L //This bit is recycled,when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_V_expansion ++ ++ ++#define ATOM_S6_ACC_REQ_CRT1 0x00010000L ++#define ATOM_S6_ACC_REQ_LCD1 0x00020000L ++#define ATOM_S6_ACC_REQ_TV1 0x00040000L ++#define ATOM_S6_ACC_REQ_DFP1 0x00080000L ++#define ATOM_S6_ACC_REQ_CRT2 0x00100000L ++#define ATOM_S6_ACC_REQ_LCD2 0x00200000L ++#define ATOM_S6_ACC_REQ_TV2 0x00400000L ++#define ATOM_S6_ACC_REQ_DFP2 0x00800000L ++#define ATOM_S6_ACC_REQ_CV 0x01000000L ++#define ATOM_S6_ACC_REQ_DFP3 0x02000000L ++ ++#define ATOM_S6_ACC_REQ_MASK 0x03FF0000L ++#define ATOM_S6_SYSTEM_POWER_MODE_CHANGE 0x10000000L ++#define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH 0x20000000L ++#define ATOM_S6_VRI_BRIGHTNESS_CHANGE 0x40000000L ++#define ATOM_S6_CONFIG_DISPLAY_CHANGE_MASK 0x80000000L ++ ++//Byte aligned defintion for BIOS usage ++#define ATOM_S6_DEVICE_CHANGEb0 0x01 ++#define ATOM_S6_SCALER_CHANGEb0 0x02 ++#define ATOM_S6_LID_CHANGEb0 0x04 ++#define ATOM_S6_DOCKING_CHANGEb0 0x08 ++#define ATOM_S6_ACC_MODEb0 0x10 ++#define ATOM_S6_EXT_DESKTOP_MODEb0 0x20 ++#define ATOM_S6_LID_STATEb0 0x40 ++#define ATOM_S6_DOCK_STATEb0 0x80 ++#define ATOM_S6_CRITICAL_STATEb1 0x01 ++#define ATOM_S6_HW_I2C_BUSY_STATEb1 0x02 ++#define ATOM_S6_THERMAL_STATE_CHANGEb1 0x04 ++#define ATOM_S6_INTERRUPT_SET_BY_BIOSb1 0x08 ++#define ATOM_S6_REQ_LCD_EXPANSION_FULLb1 0x10 ++#define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIOb1 0x20 ++ ++#define ATOM_S6_ACC_REQ_CRT1b2 0x01 ++#define ATOM_S6_ACC_REQ_LCD1b2 0x02 ++#define ATOM_S6_ACC_REQ_TV1b2 0x04 ++#define ATOM_S6_ACC_REQ_DFP1b2 0x08 ++#define ATOM_S6_ACC_REQ_CRT2b2 0x10 ++#define ATOM_S6_ACC_REQ_LCD2b2 0x20 ++#define ATOM_S6_ACC_REQ_TV2b2 0x40 ++#define ATOM_S6_ACC_REQ_DFP2b2 0x80 ++#define ATOM_S6_ACC_REQ_CVb3 0x01 ++#define ATOM_S6_ACC_REQ_DFP3b3 0x02 ++ ++#define ATOM_S6_ACC_REQ_DEVICEw1 ATOM_S5_DOS_REQ_DEVICEw0 ++#define ATOM_S6_SYSTEM_POWER_MODE_CHANGEb3 0x10 ++#define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCHb3 0x20 ++#define ATOM_S6_VRI_BRIGHTNESS_CHANGEb3 0x40 ++#define ATOM_S6_CONFIG_DISPLAY_CHANGEb3 0x80 ++ ++#define ATOM_S6_DEVICE_CHANGE_SHIFT 0 ++#define ATOM_S6_SCALER_CHANGE_SHIFT 1 ++#define ATOM_S6_LID_CHANGE_SHIFT 2 ++#define ATOM_S6_DOCKING_CHANGE_SHIFT 3 ++#define ATOM_S6_ACC_MODE_SHIFT 4 ++#define ATOM_S6_EXT_DESKTOP_MODE_SHIFT 5 ++#define ATOM_S6_LID_STATE_SHIFT 6 ++#define ATOM_S6_DOCK_STATE_SHIFT 7 ++#define ATOM_S6_CRITICAL_STATE_SHIFT 8 ++#define ATOM_S6_HW_I2C_BUSY_STATE_SHIFT 9 ++#define ATOM_S6_THERMAL_STATE_CHANGE_SHIFT 10 ++#define ATOM_S6_INTERRUPT_SET_BY_BIOS_SHIFT 11 ++#define ATOM_S6_REQ_SCALER_SHIFT 12 ++#define ATOM_S6_REQ_SCALER_ARATIO_SHIFT 13 ++#define ATOM_S6_DISPLAY_STATE_CHANGE_SHIFT 14 ++#define ATOM_S6_I2C_STATE_CHANGE_SHIFT 15 ++#define ATOM_S6_SYSTEM_POWER_MODE_CHANGE_SHIFT 28 ++#define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH_SHIFT 29 ++#define ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT 30 ++#define ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT 31 ++ ++// BIOS_7_SCRATCH Definition, BIOS_7_SCRATCH is used by Firmware only !!!! ++#define ATOM_S7_DOS_MODE_TYPEb0 0x03 ++#define ATOM_S7_DOS_MODE_VGAb0 0x00 ++#define ATOM_S7_DOS_MODE_VESAb0 0x01 ++#define ATOM_S7_DOS_MODE_EXTb0 0x02 ++#define ATOM_S7_DOS_MODE_PIXEL_DEPTHb0 0x0C ++#define ATOM_S7_DOS_MODE_PIXEL_FORMATb0 0xF0 ++#define ATOM_S7_DOS_8BIT_DAC_ENb1 0x01 ++#define ATOM_S7_DOS_MODE_NUMBERw1 0x0FFFF ++ ++#define ATOM_S7_DOS_8BIT_DAC_EN_SHIFT 8 ++ ++// BIOS_8_SCRATCH Definition ++#define ATOM_S8_I2C_CHANNEL_BUSY_MASK 0x00000FFFF ++#define ATOM_S8_I2C_HW_ENGINE_BUSY_MASK 0x0FFFF0000 ++ ++#define ATOM_S8_I2C_CHANNEL_BUSY_SHIFT 0 ++#define ATOM_S8_I2C_ENGINE_BUSY_SHIFT 16 ++ ++// BIOS_9_SCRATCH Definition ++#ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_MASK ++#define ATOM_S9_I2C_CHANNEL_COMPLETED_MASK 0x0000FFFF ++#endif ++#ifndef ATOM_S9_I2C_CHANNEL_ABORTED_MASK ++#define ATOM_S9_I2C_CHANNEL_ABORTED_MASK 0xFFFF0000 ++#endif ++#ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT ++#define ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT 0 ++#endif ++#ifndef ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT ++#define ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT 16 ++#endif ++ ++ ++#define ATOM_FLAG_SET 0x20 ++#define ATOM_FLAG_CLEAR 0 ++#define CLEAR_ATOM_S6_ACC_MODE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_ACC_MODE_SHIFT | ATOM_FLAG_CLEAR) ++#define SET_ATOM_S6_DEVICE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DEVICE_CHANGE_SHIFT | ATOM_FLAG_SET) ++#define SET_ATOM_S6_VRI_BRIGHTNESS_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT | ATOM_FLAG_SET) ++#define SET_ATOM_S6_SCALER_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_SCALER_CHANGE_SHIFT | ATOM_FLAG_SET) ++#define SET_ATOM_S6_LID_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_CHANGE_SHIFT | ATOM_FLAG_SET) ++ ++#define SET_ATOM_S6_LID_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_STATE_SHIFT | ATOM_FLAG_SET) ++#define CLEAR_ATOM_S6_LID_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_STATE_SHIFT | ATOM_FLAG_CLEAR) ++ ++#define SET_ATOM_S6_DOCK_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCKING_CHANGE_SHIFT | ATOM_FLAG_SET) ++#define SET_ATOM_S6_DOCK_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCK_STATE_SHIFT | ATOM_FLAG_SET) ++#define CLEAR_ATOM_S6_DOCK_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCK_STATE_SHIFT | ATOM_FLAG_CLEAR) ++ ++#define SET_ATOM_S6_THERMAL_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_THERMAL_STATE_CHANGE_SHIFT | ATOM_FLAG_SET) ++#define SET_ATOM_S6_SYSTEM_POWER_MODE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_SYSTEM_POWER_MODE_CHANGE_SHIFT | ATOM_FLAG_SET) ++#define SET_ATOM_S6_INTERRUPT_SET_BY_BIOS ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_INTERRUPT_SET_BY_BIOS_SHIFT | ATOM_FLAG_SET) ++ ++#define SET_ATOM_S6_CRITICAL_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_SET) ++#define CLEAR_ATOM_S6_CRITICAL_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_CLEAR) ++ ++#define SET_ATOM_S6_REQ_SCALER ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_SET) ++#define CLEAR_ATOM_S6_REQ_SCALER ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_CLEAR ) ++ ++#define SET_ATOM_S6_REQ_SCALER_ARATIO ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_ARATIO_SHIFT | ATOM_FLAG_SET ) ++#define CLEAR_ATOM_S6_REQ_SCALER_ARATIO ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_ARATIO_SHIFT | ATOM_FLAG_CLEAR ) ++ ++#define SET_ATOM_S6_I2C_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_I2C_STATE_CHANGE_SHIFT | ATOM_FLAG_SET ) ++ ++#define SET_ATOM_S6_DISPLAY_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DISPLAY_STATE_CHANGE_SHIFT | ATOM_FLAG_SET ) ++ ++#define SET_ATOM_S6_DEVICE_RECONFIG ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT | ATOM_FLAG_SET) ++#define CLEAR_ATOM_S0_LCD1 ((ATOM_DEVICE_CONNECT_INFO_DEF << 8 )| ATOM_S0_LCD1_SHIFT | ATOM_FLAG_CLEAR ) ++#define SET_ATOM_S7_DOS_8BIT_DAC_EN ((ATOM_DOS_MODE_INFO_DEF << 8 )|ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_SET ) ++#define CLEAR_ATOM_S7_DOS_8BIT_DAC_EN ((ATOM_DOS_MODE_INFO_DEF << 8 )|ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_CLEAR ) ++ ++/****************************************************************************/ ++//Portion II: Definitinos only used in Driver ++/****************************************************************************/ ++ ++// Macros used by driver ++ ++#define GetIndexIntoMasterTable(MasterOrData, FieldName) (((char*)(&((ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES*)0)->FieldName)-(char*)0)/sizeof(USHORT)) ++ ++#define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableFormatRevision)&0x3F) ++#define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableContentRevision)&0x3F) ++ ++#define GET_DATA_TABLE_MAJOR_REVISION GET_COMMAND_TABLE_COMMANDSET_REVISION ++#define GET_DATA_TABLE_MINOR_REVISION GET_COMMAND_TABLE_PARAMETER_REVISION ++ ++/****************************************************************************/ ++//Portion III: Definitinos only used in VBIOS ++/****************************************************************************/ ++#define ATOM_DAC_SRC 0x80 ++#define ATOM_SRC_DAC1 0 ++#define ATOM_SRC_DAC2 0x80 ++ ++ ++#ifdef UEFI_BUILD ++ #define USHORT UTEMP ++#endif ++ ++typedef struct _MEMORY_PLLINIT_PARAMETERS ++{ ++ ULONG ulTargetMemoryClock; //In 10Khz unit ++ UCHAR ucAction; //not define yet ++ UCHAR ucFbDiv_Hi; //Fbdiv Hi byte ++ UCHAR ucFbDiv; //FB value ++ UCHAR ucPostDiv; //Post div ++}MEMORY_PLLINIT_PARAMETERS; ++ ++#define MEMORY_PLLINIT_PS_ALLOCATION MEMORY_PLLINIT_PARAMETERS ++ ++ ++#define GPIO_PIN_WRITE 0x01 ++#define GPIO_PIN_READ 0x00 ++ ++typedef struct _GPIO_PIN_CONTROL_PARAMETERS ++{ ++ UCHAR ucGPIO_ID; //return value, read from GPIO pins ++ UCHAR ucGPIOBitShift; //define which bit in uGPIOBitVal need to be update ++ UCHAR ucGPIOBitVal; //Set/Reset corresponding bit defined in ucGPIOBitMask ++ UCHAR ucAction; //=GPIO_PIN_WRITE: Read; =GPIO_PIN_READ: Write ++}GPIO_PIN_CONTROL_PARAMETERS; ++ ++typedef struct _ENABLE_SCALER_PARAMETERS ++{ ++ UCHAR ucScaler; // ATOM_SCALER1, ATOM_SCALER2 ++ UCHAR ucEnable; // ATOM_SCALER_DISABLE or ATOM_SCALER_CENTER or ATOM_SCALER_EXPANSION ++ UCHAR ucPadding[2]; ++}ENABLE_SCALER_PARAMETERS; ++#define ENABLE_SCALER_PS_ALLOCATION ENABLE_SCALER_PARAMETERS ++ ++//ucEnable: ++#define SCALER_BYPASS_AUTO_CENTER_NO_REPLICATION 0 ++#define SCALER_BYPASS_AUTO_CENTER_AUTO_REPLICATION 1 ++#define SCALER_ENABLE_2TAP_ALPHA_MODE 2 ++#define SCALER_ENABLE_MULTITAP_MODE 3 ++ ++typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS ++{ ++ ULONG usHWIconHorzVertPosn; // Hardware Icon Vertical position ++ UCHAR ucHWIconVertOffset; // Hardware Icon Vertical offset ++ UCHAR ucHWIconHorzOffset; // Hardware Icon Horizontal offset ++ UCHAR ucSelection; // ATOM_CURSOR1 or ATOM_ICON1 or ATOM_CURSOR2 or ATOM_ICON2 ++ UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE ++}ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS; ++ ++typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION ++{ ++ ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS sEnableIcon; ++ ENABLE_CRTC_PARAMETERS sReserved; ++}ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION; ++ ++typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS ++{ ++ USHORT usHight; // Image Hight ++ USHORT usWidth; // Image Width ++ UCHAR ucSurface; // Surface 1 or 2 ++ UCHAR ucPadding[3]; ++}ENABLE_GRAPH_SURFACE_PARAMETERS; ++ ++typedef struct _ENABLE_GRAPH_SURFACE_PS_ALLOCATION ++{ ++ ENABLE_GRAPH_SURFACE_PARAMETERS sSetSurface; ++ ENABLE_YUV_PS_ALLOCATION sReserved; // Don't set this one ++}ENABLE_GRAPH_SURFACE_PS_ALLOCATION; ++ ++typedef struct _MEMORY_CLEAN_UP_PARAMETERS ++{ ++ USHORT usMemoryStart; //in 8Kb boundry, offset from memory base address ++ USHORT usMemorySize; //8Kb blocks aligned ++}MEMORY_CLEAN_UP_PARAMETERS; ++#define MEMORY_CLEAN_UP_PS_ALLOCATION MEMORY_CLEAN_UP_PARAMETERS ++ ++typedef struct _GET_DISPLAY_SURFACE_SIZE_PARAMETERS ++{ ++ USHORT usX_Size; //When use as input parameter, usX_Size indicates which CRTC ++ USHORT usY_Size; ++}GET_DISPLAY_SURFACE_SIZE_PARAMETERS; ++ ++typedef struct _INDIRECT_IO_ACCESS ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ UCHAR IOAccessSequence[256]; ++} INDIRECT_IO_ACCESS; ++ ++#define INDIRECT_READ 0x00 ++#define INDIRECT_WRITE 0x80 ++ ++#define INDIRECT_IO_MM 0 ++#define INDIRECT_IO_PLL 1 ++#define INDIRECT_IO_MC 2 ++#define INDIRECT_IO_PCIE 3 ++#define INDIRECT_IO_PCIEP 4 ++ ++#define INDIRECT_IO_PLL_READ INDIRECT_IO_PLL | INDIRECT_READ ++#define INDIRECT_IO_PLL_WRITE INDIRECT_IO_PLL | INDIRECT_WRITE ++#define INDIRECT_IO_MC_READ INDIRECT_IO_MC | INDIRECT_READ ++#define INDIRECT_IO_MC_WRITE INDIRECT_IO_MC | INDIRECT_WRITE ++#define INDIRECT_IO_PCIE_READ INDIRECT_IO_PCIE | INDIRECT_READ ++#define INDIRECT_IO_PCIE_WRITE INDIRECT_IO_PCIE | INDIRECT_WRITE ++#define INDIRECT_IO_PCIEP_READ INDIRECT_IO_PCIEP | INDIRECT_READ ++#define INDIRECT_IO_PCIEP_WRITE INDIRECT_IO_PCIEP | INDIRECT_WRITE ++ ++typedef struct _ATOM_OEM_INFO ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; ++}ATOM_OEM_INFO; ++ ++typedef struct _ATOM_TV_MODE ++{ ++ UCHAR ucVMode_Num; //Video mode number ++ UCHAR ucTV_Mode_Num; //Internal TV mode number ++}ATOM_TV_MODE; ++ ++typedef struct _ATOM_BIOS_INT_TVSTD_MODE ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ USHORT usTV_Mode_LUT_Offset; // Pointer to standard to internal number conversion table ++ USHORT usTV_FIFO_Offset; // Pointer to FIFO entry table ++ USHORT usNTSC_Tbl_Offset; // Pointer to SDTV_Mode_NTSC table ++ USHORT usPAL_Tbl_Offset; // Pointer to SDTV_Mode_PAL table ++ USHORT usCV_Tbl_Offset; // Pointer to SDTV_Mode_PAL table ++}ATOM_BIOS_INT_TVSTD_MODE; ++ ++ ++typedef struct _ATOM_TV_MODE_SCALER_PTR ++{ ++ USHORT ucFilter0_Offset; //Pointer to filter format 0 coefficients ++ USHORT usFilter1_Offset; //Pointer to filter format 0 coefficients ++ UCHAR ucTV_Mode_Num; ++}ATOM_TV_MODE_SCALER_PTR; ++ ++typedef struct _ATOM_STANDARD_VESA_TIMING ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ ATOM_MODE_TIMING aModeTimings[16]; // 16 is not the real array number, just for initial allocation ++}ATOM_STANDARD_VESA_TIMING; ++ ++ ++typedef struct _ATOM_STD_FORMAT ++{ ++ USHORT usSTD_HDisp; ++ USHORT usSTD_VDisp; ++ USHORT usSTD_RefreshRate; ++ USHORT usReserved; ++}ATOM_STD_FORMAT; ++ ++typedef struct _ATOM_VESA_TO_EXTENDED_MODE ++{ ++ USHORT usVESA_ModeNumber; ++ USHORT usExtendedModeNumber; ++}ATOM_VESA_TO_EXTENDED_MODE; ++ ++typedef struct _ATOM_VESA_TO_INTENAL_MODE_LUT ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ ATOM_VESA_TO_EXTENDED_MODE asVESA_ToExtendedModeInfo[76]; ++}ATOM_VESA_TO_INTENAL_MODE_LUT; ++ ++/*************** ATOM Memory Related Data Structure ***********************/ ++typedef struct _ATOM_MEMORY_VENDOR_BLOCK{ ++ UCHAR ucMemoryType; ++ UCHAR ucMemoryVendor; ++ UCHAR ucAdjMCId; ++ UCHAR ucDynClkId; ++ ULONG ulDllResetClkRange; ++}ATOM_MEMORY_VENDOR_BLOCK; ++ ++ ++typedef struct _ATOM_MEMORY_SETTING_ID_CONFIG{ ++ ULONG ulMemClockRange:24; ++ ULONG ucMemBlkId:8; ++}ATOM_MEMORY_SETTING_ID_CONFIG; ++ ++typedef union _ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS ++{ ++ ATOM_MEMORY_SETTING_ID_CONFIG slAccess; ++ ULONG ulAccess; ++}ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS; ++ ++ ++typedef struct _ATOM_MEMORY_SETTING_DATA_BLOCK{ ++ ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS ulMemoryID; ++ ULONG aulMemData[1]; ++}ATOM_MEMORY_SETTING_DATA_BLOCK; ++ ++ ++typedef struct _ATOM_INIT_REG_INDEX_FORMAT{ ++ USHORT usRegIndex; // MC register index ++ UCHAR ucPreRegDataLength; // offset in ATOM_INIT_REG_DATA_BLOCK.saRegDataBuf ++}ATOM_INIT_REG_INDEX_FORMAT; ++ ++ ++typedef struct _ATOM_INIT_REG_BLOCK{ ++ USHORT usRegIndexTblSize; //size of asRegIndexBuf ++ USHORT usRegDataBlkSize; //size of ATOM_MEMORY_SETTING_DATA_BLOCK ++ ATOM_INIT_REG_INDEX_FORMAT asRegIndexBuf[1]; ++ ATOM_MEMORY_SETTING_DATA_BLOCK asRegDataBuf[1]; ++}ATOM_INIT_REG_BLOCK; ++ ++#define END_OF_REG_INDEX_BLOCK 0x0ffff ++#define END_OF_REG_DATA_BLOCK 0x00000000 ++#define ATOM_INIT_REG_MASK_FLAG 0x80 ++#define CLOCK_RANGE_HIGHEST 0x00ffffff ++ ++#define VALUE_DWORD SIZEOF ULONG ++#define VALUE_SAME_AS_ABOVE 0 ++#define VALUE_MASK_DWORD 0x84 ++ ++typedef struct _ATOM_MC_INIT_PARAM_TABLE ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ USHORT usAdjustARB_SEQDataOffset; ++ USHORT usMCInitMemTypeTblOffset; ++ USHORT usMCInitCommonTblOffset; ++ USHORT usMCInitPowerDownTblOffset; ++ ULONG ulARB_SEQDataBuf[32]; ++ ATOM_INIT_REG_BLOCK asMCInitMemType; ++ ATOM_INIT_REG_BLOCK asMCInitCommon; ++}ATOM_MC_INIT_PARAM_TABLE; ++ ++ ++#define _4Mx16 0x2 ++#define _4Mx32 0x3 ++#define _8Mx16 0x12 ++#define _8Mx32 0x13 ++#define _16Mx16 0x22 ++#define _16Mx32 0x23 ++#define _32Mx16 0x32 ++ ++#define SAMSUNG 0x1 ++#define INFINEON 0x2 ++#define ELPIDA 0x3 ++#define ETRON 0x4 ++#define NANYA 0x5 ++#define HYNIX 0x6 ++#define MOSEL 0x7 ++#define WINBOND 0x8 ++#define ESMT 0x9 ++#define MICRO 0xF ++ ++#define ATOM_MAX_NUMBER_OF_VRAM_MODULE 16 ++ ++#define ATOM_VRAM_MODULE_MEMORY_VENDOR_ID_MASK 0xF ++typedef struct _ATOM_VRAM_MODULE_V1 ++{ ++ ULONG ulReserved; ++ USHORT usEMRSValue; ++ USHORT usMRSValue; ++ USHORT usReserved; ++ UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module ++ UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] reserved; ++ UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender ++ UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32... ++ UCHAR ucRow; // Number of Row,in power of 2; ++ UCHAR ucColumn; // Number of Column,in power of 2; ++ UCHAR ucBank; // Nunber of Bank; ++ UCHAR ucRank; // Number of Rank, in power of 2 ++ UCHAR ucChannelNum; // Number of channel; ++ UCHAR ucChannelConfig; // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2 ++ UCHAR ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data; ++ UCHAR ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data; ++ UCHAR ucReserved[2]; ++}ATOM_VRAM_MODULE_V1; ++ ++ ++typedef struct _ATOM_VRAM_MODULE_V2 ++{ ++ ULONG ulReserved; ++ ULONG ulFlags; // To enable/disable functionalities based on memory type ++ ULONG ulEngineClock; // Override of default engine clock for particular memory type ++ ULONG ulMemoryClock; // Override of default memory clock for particular memory type ++ USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type ++ USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type ++ USHORT usEMRSValue; ++ USHORT usMRSValue; ++ USHORT usReserved; ++ UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module ++ UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now; ++ UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed ++ UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32... ++ UCHAR ucRow; // Number of Row,in power of 2; ++ UCHAR ucColumn; // Number of Column,in power of 2; ++ UCHAR ucBank; // Nunber of Bank; ++ UCHAR ucRank; // Number of Rank, in power of 2 ++ UCHAR ucChannelNum; // Number of channel; ++ UCHAR ucChannelConfig; // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2 ++ UCHAR ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data; ++ UCHAR ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data; ++ UCHAR ucRefreshRateFactor; ++ UCHAR ucReserved[3]; ++}ATOM_VRAM_MODULE_V2; ++ ++ ++typedef struct _ATOM_MEMORY_TIMING_FORMAT ++{ ++ ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing ++ USHORT usMRS; // mode register ++ USHORT usEMRS; // extended mode register ++ UCHAR ucCL; // CAS latency ++ UCHAR ucWL; // WRITE Latency ++ UCHAR uctRAS; // tRAS ++ UCHAR uctRC; // tRC ++ UCHAR uctRFC; // tRFC ++ UCHAR uctRCDR; // tRCDR ++ UCHAR uctRCDW; // tRCDW ++ UCHAR uctRP; // tRP ++ UCHAR uctRRD; // tRRD ++ UCHAR uctWR; // tWR ++ UCHAR uctWTR; // tWTR ++ UCHAR uctPDIX; // tPDIX ++ UCHAR uctFAW; // tFAW ++ UCHAR uctAOND; // tAOND ++ UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon ++ UCHAR ucReserved; // ++}ATOM_MEMORY_TIMING_FORMAT; ++ ++#define MEM_TIMING_FLAG_APP_MODE 0x01 // =0 mid clock range =1 high clock range ++ ++typedef struct _ATOM_MEMORY_FORMAT ++{ ++ ULONG ulDllDisClock; // memory DLL will be disable when target memory clock is below this clock ++ USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type ++ USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type ++ UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now; ++ UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed ++ UCHAR ucRow; // Number of Row,in power of 2; ++ UCHAR ucColumn; // Number of Column,in power of 2; ++ UCHAR ucBank; // Nunber of Bank; ++ UCHAR ucRank; // Number of Rank, in power of 2 ++ UCHAR ucBurstSize; // burst size, 0= burst size=4 1= burst size=8 ++ UCHAR ucDllDisBit; // position of DLL Enable/Disable bit in EMRS ( Extended Mode Register ) ++ UCHAR ucRefreshRateFactor; // memory refresh rate in unit of ms ++ UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 ++ UCHAR ucPreamble; //[7:4] Write Preamble, [3:0] Read Preamble ++ UCHAR ucMemAttrib; // Memory Device Addribute, like RDBI/WDBI etc ++ ATOM_MEMORY_TIMING_FORMAT asMemTiming[5]; //Memory Timing block sort from lower clock to higher clock ++}ATOM_MEMORY_FORMAT; ++ ++ ++typedef struct _ATOM_VRAM_MODULE_V3 ++{ ++ ULONG ulChannelMapCfg; // board dependent paramenter:Channel combination ++ USHORT usSize; // size of ATOM_VRAM_MODULE_V3 ++ USHORT usDefaultMVDDQ; // board dependent parameter:Default Memory Core Voltage ++ USHORT usDefaultMVDDC; // board dependent parameter:Default Memory IO Voltage ++ UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module ++ UCHAR ucChannelNum; // board dependent parameter:Number of channel; ++ UCHAR ucChannelSize; // board dependent parameter:32bit or 64bit ++ UCHAR ucVREFI; // board dependnt parameter: EXT or INT +160mv to -140mv ++ UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters ++ UCHAR ucFlag; // To enable/disable functionalities based on memory type ++ ATOM_MEMORY_FORMAT asMemory; // describ all of video memory parameters from memory spec ++}ATOM_VRAM_MODULE_V3; ++ ++//ATOM_VRAM_MODULE_V3.ucFlag ++#define Mx_FLAG_RDBI_ENABLE 0x01 ++#define Mx_FLAG_WDBI_ENABLE 0x02 ++#define Mx_FLAG_DQ_QS_AUTO_CALI 0x04 ++#define Mx_FLAG_STROBE_SINGLE_END 0x08 ++#define Mx_FLAG_DIS_MEM_TRAINING 0x10 ++ ++//ATOM_VRAM_MODULE_V3.ucNPL_RT ++#define NPL_RT_MASK 0x0f ++#define BATTERY_ODT_MASK 0xc0 ++ ++#define ATOM_VRAM_MODULE ATOM_VRAM_MODULE_V3 ++ ++typedef struct _ATOM_VRAM_INFO_V2 ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ UCHAR ucNumOfVRAMModule; ++ ATOM_VRAM_MODULE aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; ++}ATOM_VRAM_INFO_V2; ++ ++typedef struct _ATOM_VRAM_INFO_V3 ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting ++ USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting ++ USHORT usRerseved; ++ UCHAR aVID_PinsShift[9]; // 8 bit strap maximum+terminator ++ UCHAR ucNumOfVRAMModule; ++ ATOM_VRAM_MODULE aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; ++ ATOM_INIT_REG_BLOCK asMemPatch; // for allocation ++ // ATOM_INIT_REG_BLOCK aMemAdjust; ++}ATOM_VRAM_INFO_V3; ++ ++#define ATOM_VRAM_INFO_LAST ATOM_VRAM_INFO_V3 ++ ++typedef struct _ATOM_VRAM_GPIO_DETECTION_INFO ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ UCHAR aVID_PinsShift[9]; //8 bit strap maximum+terminator ++}ATOM_VRAM_GPIO_DETECTION_INFO; ++ ++ ++typedef struct _ATOM_MEMORY_TRAINING_INFO ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ UCHAR ucTrainingLoop; ++ UCHAR ucReserved[3]; ++ ATOM_INIT_REG_BLOCK asMemTrainingSetting; ++}ATOM_MEMORY_TRAINING_INFO; ++ ++ ++typedef struct SW_I2C_CNTL_DATA_PARAMETERS ++{ ++ UCHAR ucControl; ++ UCHAR ucData; ++ UCHAR ucSatus; ++ UCHAR ucTemp; ++} SW_I2C_CNTL_DATA_PARAMETERS; ++ ++#define SW_I2C_CNTL_DATA_PS_ALLOCATION SW_I2C_CNTL_DATA_PARAMETERS ++ ++typedef struct _SW_I2C_IO_DATA_PARAMETERS ++{ ++ USHORT GPIO_Info; ++ UCHAR ucAct; ++ UCHAR ucData; ++ } SW_I2C_IO_DATA_PARAMETERS; ++ ++#define SW_I2C_IO_DATA_PS_ALLOCATION SW_I2C_IO_DATA_PARAMETERS ++ ++/****************************SW I2C CNTL DEFINITIONS**********************/ ++#define SW_I2C_IO_RESET 0 ++#define SW_I2C_IO_GET 1 ++#define SW_I2C_IO_DRIVE 2 ++#define SW_I2C_IO_SET 3 ++#define SW_I2C_IO_START 4 ++ ++#define SW_I2C_IO_CLOCK 0 ++#define SW_I2C_IO_DATA 0x80 ++ ++#define SW_I2C_IO_ZERO 0 ++#define SW_I2C_IO_ONE 0x100 ++ ++#define SW_I2C_CNTL_READ 0 ++#define SW_I2C_CNTL_WRITE 1 ++#define SW_I2C_CNTL_START 2 ++#define SW_I2C_CNTL_STOP 3 ++#define SW_I2C_CNTL_OPEN 4 ++#define SW_I2C_CNTL_CLOSE 5 ++#define SW_I2C_CNTL_WRITE1BIT 6 ++ ++//==============================VESA definition Portion=============================== ++#define VESA_OEM_PRODUCT_REV '01.00' ++#define VESA_MODE_ATTRIBUTE_MODE_SUPPORT 0xBB //refer to VBE spec p.32, no TTY support ++#define VESA_MODE_WIN_ATTRIBUTE 7 ++#define VESA_WIN_SIZE 64 ++ ++typedef struct _PTR_32_BIT_STRUCTURE ++{ ++ USHORT Offset16; ++ USHORT Segment16; ++} PTR_32_BIT_STRUCTURE; ++ ++typedef union _PTR_32_BIT_UNION ++{ ++ PTR_32_BIT_STRUCTURE SegmentOffset; ++ ULONG Ptr32_Bit; ++} PTR_32_BIT_UNION; ++ ++typedef struct _VBE_1_2_INFO_BLOCK_UPDATABLE ++{ ++ UCHAR VbeSignature[4]; ++ USHORT VbeVersion; ++ PTR_32_BIT_UNION OemStringPtr; ++ UCHAR Capabilities[4]; ++ PTR_32_BIT_UNION VideoModePtr; ++ USHORT TotalMemory; ++} VBE_1_2_INFO_BLOCK_UPDATABLE; ++ ++ ++typedef struct _VBE_2_0_INFO_BLOCK_UPDATABLE ++{ ++ VBE_1_2_INFO_BLOCK_UPDATABLE CommonBlock; ++ USHORT OemSoftRev; ++ PTR_32_BIT_UNION OemVendorNamePtr; ++ PTR_32_BIT_UNION OemProductNamePtr; ++ PTR_32_BIT_UNION OemProductRevPtr; ++} VBE_2_0_INFO_BLOCK_UPDATABLE; ++ ++typedef union _VBE_VERSION_UNION ++{ ++ VBE_2_0_INFO_BLOCK_UPDATABLE VBE_2_0_InfoBlock; ++ VBE_1_2_INFO_BLOCK_UPDATABLE VBE_1_2_InfoBlock; ++} VBE_VERSION_UNION; ++ ++typedef struct _VBE_INFO_BLOCK ++{ ++ VBE_VERSION_UNION UpdatableVBE_Info; ++ UCHAR Reserved[222]; ++ UCHAR OemData[256]; ++} VBE_INFO_BLOCK; ++ ++typedef struct _VBE_FP_INFO ++{ ++ USHORT HSize; ++ USHORT VSize; ++ USHORT FPType; ++ UCHAR RedBPP; ++ UCHAR GreenBPP; ++ UCHAR BlueBPP; ++ UCHAR ReservedBPP; ++ ULONG RsvdOffScrnMemSize; ++ ULONG RsvdOffScrnMEmPtr; ++ UCHAR Reserved[14]; ++} VBE_FP_INFO; ++ ++typedef struct _VESA_MODE_INFO_BLOCK ++{ ++// Mandatory information for all VBE revisions ++ USHORT ModeAttributes; // dw ? ; mode attributes ++ UCHAR WinAAttributes; // db ? ; window A attributes ++ UCHAR WinBAttributes; // db ? ; window B attributes ++ USHORT WinGranularity; // dw ? ; window granularity ++ USHORT WinSize; // dw ? ; window size ++ USHORT WinASegment; // dw ? ; window A start segment ++ USHORT WinBSegment; // dw ? ; window B start segment ++ ULONG WinFuncPtr; // dd ? ; real mode pointer to window function ++ USHORT BytesPerScanLine;// dw ? ; bytes per scan line ++ ++//; Mandatory information for VBE 1.2 and above ++ USHORT XResolution; // dw ? ; horizontal resolution in pixels or characters ++ USHORT YResolution; // dw ? ; vertical resolution in pixels or characters ++ UCHAR XCharSize; // db ? ; character cell width in pixels ++ UCHAR YCharSize; // db ? ; character cell height in pixels ++ UCHAR NumberOfPlanes; // db ? ; number of memory planes ++ UCHAR BitsPerPixel; // db ? ; bits per pixel ++ UCHAR NumberOfBanks; // db ? ; number of banks ++ UCHAR MemoryModel; // db ? ; memory model type ++ UCHAR BankSize; // db ? ; bank size in KB ++ UCHAR NumberOfImagePages;// db ? ; number of images ++ UCHAR ReservedForPageFunction;//db 1 ; reserved for page function ++ ++//; Direct Color fields(required for direct/6 and YUV/7 memory models) ++ UCHAR RedMaskSize; // db ? ; size of direct color red mask in bits ++ UCHAR RedFieldPosition; // db ? ; bit position of lsb of red mask ++ UCHAR GreenMaskSize; // db ? ; size of direct color green mask in bits ++ UCHAR GreenFieldPosition; // db ? ; bit position of lsb of green mask ++ UCHAR BlueMaskSize; // db ? ; size of direct color blue mask in bits ++ UCHAR BlueFieldPosition; // db ? ; bit position of lsb of blue mask ++ UCHAR RsvdMaskSize; // db ? ; size of direct color reserved mask in bits ++ UCHAR RsvdFieldPosition; // db ? ; bit position of lsb of reserved mask ++ UCHAR DirectColorModeInfo;// db ? ; direct color mode attributes ++ ++//; Mandatory information for VBE 2.0 and above ++ ULONG PhysBasePtr; // dd ? ; physical address for flat memory frame buffer ++ ULONG Reserved_1; // dd 0 ; reserved - always set to 0 ++ USHORT Reserved_2; // dw 0 ; reserved - always set to 0 ++ ++//; Mandatory information for VBE 3.0 and above ++ USHORT LinBytesPerScanLine; // dw ? ; bytes per scan line for linear modes ++ UCHAR BnkNumberOfImagePages;// db ? ; number of images for banked modes ++ UCHAR LinNumberOfImagPages; // db ? ; number of images for linear modes ++ UCHAR LinRedMaskSize; // db ? ; size of direct color red mask(linear modes) ++ UCHAR LinRedFieldPosition; // db ? ; bit position of lsb of red mask(linear modes) ++ UCHAR LinGreenMaskSize; // db ? ; size of direct color green mask(linear modes) ++ UCHAR LinGreenFieldPosition;// db ? ; bit position of lsb of green mask(linear modes) ++ UCHAR LinBlueMaskSize; // db ? ; size of direct color blue mask(linear modes) ++ UCHAR LinBlueFieldPosition; // db ? ; bit position of lsb of blue mask(linear modes) ++ UCHAR LinRsvdMaskSize; // db ? ; size of direct color reserved mask(linear modes) ++ UCHAR LinRsvdFieldPosition; // db ? ; bit position of lsb of reserved mask(linear modes) ++ ULONG MaxPixelClock; // dd ? ; maximum pixel clock(in Hz) for graphics mode ++ UCHAR Reserved; // db 190 dup (0) ++} VESA_MODE_INFO_BLOCK; ++ ++// BIOS function CALLS ++#define ATOM_BIOS_EXTENDED_FUNCTION_CODE 0xA0 // ATI Extended Function code ++#define ATOM_BIOS_FUNCTION_COP_MODE 0x00 ++#define ATOM_BIOS_FUNCTION_SHORT_QUERY1 0x04 ++#define ATOM_BIOS_FUNCTION_SHORT_QUERY2 0x05 ++#define ATOM_BIOS_FUNCTION_SHORT_QUERY3 0x06 ++#define ATOM_BIOS_FUNCTION_GET_DDC 0x0B ++#define ATOM_BIOS_FUNCTION_ASIC_DSTATE 0x0E ++#define ATOM_BIOS_FUNCTION_DEBUG_PLAY 0x0F ++#define ATOM_BIOS_FUNCTION_STV_STD 0x16 ++#define ATOM_BIOS_FUNCTION_DEVICE_DET 0x17 ++#define ATOM_BIOS_FUNCTION_DEVICE_SWITCH 0x18 ++ ++#define ATOM_BIOS_FUNCTION_PANEL_CONTROL 0x82 ++#define ATOM_BIOS_FUNCTION_OLD_DEVICE_DET 0x83 ++#define ATOM_BIOS_FUNCTION_OLD_DEVICE_SWITCH 0x84 ++#define ATOM_BIOS_FUNCTION_HW_ICON 0x8A ++#define ATOM_BIOS_FUNCTION_SET_CMOS 0x8B ++#define SUB_FUNCTION_UPDATE_DISPLAY_INFO 0x8000 // Sub function 80 ++#define SUB_FUNCTION_UPDATE_EXPANSION_INFO 0x8100 // Sub function 80 ++ ++#define ATOM_BIOS_FUNCTION_DISPLAY_INFO 0x8D ++#define ATOM_BIOS_FUNCTION_DEVICE_ON_OFF 0x8E ++#define ATOM_BIOS_FUNCTION_VIDEO_STATE 0x8F ++#define ATOM_SUB_FUNCTION_GET_CRITICAL_STATE 0x0300 // Sub function 03 ++#define ATOM_SUB_FUNCTION_GET_LIDSTATE 0x0700 // Sub function 7 ++#define ATOM_SUB_FUNCTION_THERMAL_STATE_NOTICE 0x1400 // Notify caller the current thermal state ++#define ATOM_SUB_FUNCTION_CRITICAL_STATE_NOTICE 0x8300 // Notify caller the current critical state ++#define ATOM_SUB_FUNCTION_SET_LIDSTATE 0x8500 // Sub function 85 ++#define ATOM_SUB_FUNCTION_GET_REQ_DISPLAY_FROM_SBIOS_MODE 0x8900// Sub function 89 ++#define ATOM_SUB_FUNCTION_INFORM_ADC_SUPPORT 0x9400 // Notify caller that ADC is supported ++ ++ ++#define ATOM_BIOS_FUNCTION_VESA_DPMS 0x4F10 // Set DPMS ++#define ATOM_SUB_FUNCTION_SET_DPMS 0x0001 // BL: Sub function 01 ++#define ATOM_SUB_FUNCTION_GET_DPMS 0x0002 // BL: Sub function 02 ++#define ATOM_PARAMETER_VESA_DPMS_ON 0x0000 // BH Parameter for DPMS ON. ++#define ATOM_PARAMETER_VESA_DPMS_STANDBY 0x0100 // BH Parameter for DPMS STANDBY ++#define ATOM_PARAMETER_VESA_DPMS_SUSPEND 0x0200 // BH Parameter for DPMS SUSPEND ++#define ATOM_PARAMETER_VESA_DPMS_OFF 0x0400 // BH Parameter for DPMS OFF ++#define ATOM_PARAMETER_VESA_DPMS_REDUCE_ON 0x0800 // BH Parameter for DPMS REDUCE ON (NOT SUPPORTED) ++ ++#define ATOM_BIOS_RETURN_CODE_MASK 0x0000FF00L ++#define ATOM_BIOS_REG_HIGH_MASK 0x0000FF00L ++#define ATOM_BIOS_REG_LOW_MASK 0x000000FFL ++ ++// structure used for VBIOS only ++ ++//DispOutInfoTable ++typedef struct _ASIC_TRANSMITTER_INFO ++{ ++ USHORT usTransmitterObjId; ++ USHORT usSupportDevice; ++ UCHAR ucTransmitterCmdTblId; ++ UCHAR ucConfig; ++ UCHAR ucEncoderID; //available 1st encoder ( default ) ++ UCHAR ucOptionEncoderID; //available 2nd encoder ( optional ) ++ UCHAR uc2ndEncoderID; ++ UCHAR ucReserved; ++}ASIC_TRANSMITTER_INFO; ++ ++typedef struct _ASIC_ENCODER_INFO ++{ ++ UCHAR ucEncoderID; ++ UCHAR ucEncoderConfig; ++ USHORT usEncoderCmdTblId; ++}ASIC_ENCODER_INFO; ++ ++typedef struct _ATOM_DISP_OUT_INFO ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ USHORT ptrTransmitterInfo; ++ USHORT ptrEncoderInfo; ++ ASIC_TRANSMITTER_INFO asTransmitterInfo[1]; ++ ASIC_ENCODER_INFO asEncoderInfo[1]; ++}ATOM_DISP_OUT_INFO; ++ ++// DispDevicePriorityInfo ++typedef struct _ATOM_DISPLAY_DEVICE_PRIORITY_INFO ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ USHORT asDevicePriority[16]; ++}ATOM_DISPLAY_DEVICE_PRIORITY_INFO; ++ ++//ProcessAuxChannelTransactionTable ++typedef struct _PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS ++{ ++ USHORT lpAuxRequest; ++ USHORT lpDataOut; ++ UCHAR ucChannelID; ++ union ++ { ++ UCHAR ucReplyStatus; ++ UCHAR ucDelay; ++ }; ++ UCHAR ucDataOutLen; ++ UCHAR ucReserved; ++}PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS; ++ ++#define PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS ++ ++//GetSinkType ++ ++typedef struct _DP_ENCODER_SERVICE_PARAMETERS ++{ ++ USHORT ucLinkClock; ++ union ++ { ++ UCHAR ucConfig; // for DP training command ++ UCHAR ucI2cId; // use for GET_SINK_TYPE command ++ }; ++ UCHAR ucAction; ++ UCHAR ucStatus; ++ UCHAR ucLaneNum; ++ UCHAR ucReserved[2]; ++}DP_ENCODER_SERVICE_PARAMETERS; ++ ++// ucAction ++#define ATOM_DP_ACTION_GET_SINK_TYPE 0x01 ++#define ATOM_DP_ACTION_TRAINING_START 0x02 ++#define ATOM_DP_ACTION_TRAINING_COMPLETE 0x03 ++#define ATOM_DP_ACTION_TRAINING_PATTERN_SEL 0x04 ++#define ATOM_DP_ACTION_SET_VSWING_PREEMP 0x05 ++#define ATOM_DP_ACTION_GET_VSWING_PREEMP 0x06 ++ ++// ucConfig ++#define ATOM_DP_CONFIG_ENCODER_SEL_MASK 0x03 ++#define ATOM_DP_CONFIG_DIG1_ENCODER 0x00 ++#define ATOM_DP_CONFIG_DIG2_ENCODER 0x01 ++#define ATOM_DP_CONFIG_EXTERNAL_ENCODER 0x02 ++#define ATOM_DP_CONFIG_LINK_SEL_MASK 0x04 ++#define ATOM_DP_CONFIG_LINK_A 0x00 ++#define ATOM_DP_CONFIG_LINK_B 0x04 ++ ++#define DP_ENCODER_SERVICE_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS ++ ++// DP_TRAINING_TABLE ++#define DPCD_SET_LINKRATE_LANENUM_PATTERN1_TBL_ADDR ATOM_DP_TRAINING_TBL_ADDR ++#define DPCD_SET_SS_CNTL_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 8 ) ++#define DPCD_SET_LANE_VSWING_PREEMP_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 16 ) ++#define DPCD_SET_TRAINING_PATTERN0_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 24 ) ++#define DPCD_SET_TRAINING_PATTERN2_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 32) ++#define DPCD_GET_LINKRATE_LANENUM_SS_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 40) ++#define DPCD_GET_LANE_STATUS_ADJUST_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 48) ++#define DP_I2C_AUX_DDC_WRITE_START_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 60) ++#define DP_I2C_AUX_DDC_WRITE_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 64) ++#define DP_I2C_AUX_DDC_READ_START_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 72) ++#define DP_I2C_AUX_DDC_READ_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 76) ++#define DP_I2C_AUX_DDC_READ_END_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 80) ++ ++ ++/****************************************************************************/ ++//Portion VI: Definitinos being oboselete ++/****************************************************************************/ ++ ++//========================================================================================== ++//Remove the definitions below when driver is ready! ++typedef struct _ATOM_DAC_INFO ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ USHORT usMaxFrequency; // in 10kHz unit ++ USHORT usReserved; ++}ATOM_DAC_INFO; ++ ++ ++typedef struct _COMPASSIONATE_DATA ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ ++ //============================== DAC1 portion ++ UCHAR ucDAC1_BG_Adjustment; ++ UCHAR ucDAC1_DAC_Adjustment; ++ USHORT usDAC1_FORCE_Data; ++ //============================== DAC2 portion ++ UCHAR ucDAC2_CRT2_BG_Adjustment; ++ UCHAR ucDAC2_CRT2_DAC_Adjustment; ++ USHORT usDAC2_CRT2_FORCE_Data; ++ USHORT usDAC2_CRT2_MUX_RegisterIndex; ++ UCHAR ucDAC2_CRT2_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low ++ UCHAR ucDAC2_NTSC_BG_Adjustment; ++ UCHAR ucDAC2_NTSC_DAC_Adjustment; ++ USHORT usDAC2_TV1_FORCE_Data; ++ USHORT usDAC2_TV1_MUX_RegisterIndex; ++ UCHAR ucDAC2_TV1_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low ++ UCHAR ucDAC2_CV_BG_Adjustment; ++ UCHAR ucDAC2_CV_DAC_Adjustment; ++ USHORT usDAC2_CV_FORCE_Data; ++ USHORT usDAC2_CV_MUX_RegisterIndex; ++ UCHAR ucDAC2_CV_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low ++ UCHAR ucDAC2_PAL_BG_Adjustment; ++ UCHAR ucDAC2_PAL_DAC_Adjustment; ++ USHORT usDAC2_TV2_FORCE_Data; ++}COMPASSIONATE_DATA; ++ ++/****************************Supported Device Info Table Definitions**********************/ ++// ucConnectInfo: ++// [7:4] - connector type ++// = 1 - VGA connector ++// = 2 - DVI-I ++// = 3 - DVI-D ++// = 4 - DVI-A ++// = 5 - SVIDEO ++// = 6 - COMPOSITE ++// = 7 - LVDS ++// = 8 - DIGITAL LINK ++// = 9 - SCART ++// = 0xA - HDMI_type A ++// = 0xB - HDMI_type B ++// = 0xE - Special case1 (DVI+DIN) ++// Others=TBD ++// [3:0] - DAC Associated ++// = 0 - no DAC ++// = 1 - DACA ++// = 2 - DACB ++// = 3 - External DAC ++// Others=TBD ++// ++ ++typedef struct _ATOM_CONNECTOR_INFO ++{ ++ UCHAR bfAssociatedDAC:4; ++ UCHAR bfConnectorType:4; ++}ATOM_CONNECTOR_INFO; ++ ++typedef union _ATOM_CONNECTOR_INFO_ACCESS ++{ ++ ATOM_CONNECTOR_INFO sbfAccess; ++ UCHAR ucAccess; ++}ATOM_CONNECTOR_INFO_ACCESS; ++ ++typedef struct _ATOM_CONNECTOR_INFO_I2C ++{ ++ ATOM_CONNECTOR_INFO_ACCESS sucConnectorInfo; ++ ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; ++}ATOM_CONNECTOR_INFO_I2C; ++ ++ ++typedef struct _ATOM_SUPPORTED_DEVICES_INFO ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ USHORT usDeviceSupport; ++ ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO]; ++}ATOM_SUPPORTED_DEVICES_INFO; ++ ++#define NO_INT_SRC_MAPPED 0xFF ++ ++typedef struct _ATOM_CONNECTOR_INC_SRC_BITMAP ++{ ++ UCHAR ucIntSrcBitmap; ++}ATOM_CONNECTOR_INC_SRC_BITMAP; ++ ++typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2 ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ USHORT usDeviceSupport; ++ ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2]; ++ ATOM_CONNECTOR_INC_SRC_BITMAP asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2]; ++}ATOM_SUPPORTED_DEVICES_INFO_2; ++ ++typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ USHORT usDeviceSupport; ++ ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE]; ++ ATOM_CONNECTOR_INC_SRC_BITMAP asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE]; ++}ATOM_SUPPORTED_DEVICES_INFO_2d1; ++ ++#define ATOM_SUPPORTED_DEVICES_INFO_LAST ATOM_SUPPORTED_DEVICES_INFO_2d1 ++ ++ ++ ++typedef struct _ATOM_MISC_CONTROL_INFO ++{ ++ USHORT usFrequency; ++ UCHAR ucPLL_ChargePump; // PLL charge-pump gain control ++ UCHAR ucPLL_DutyCycle; // PLL duty cycle control ++ UCHAR ucPLL_VCO_Gain; // PLL VCO gain control ++ UCHAR ucPLL_VoltageSwing; // PLL driver voltage swing control ++}ATOM_MISC_CONTROL_INFO; ++ ++ ++#define ATOM_MAX_MISC_INFO 4 ++ ++typedef struct _ATOM_TMDS_INFO ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ USHORT usMaxFrequency; // in 10Khz ++ ATOM_MISC_CONTROL_INFO asMiscInfo[ATOM_MAX_MISC_INFO]; ++}ATOM_TMDS_INFO; ++ ++ ++typedef struct _ATOM_ENCODER_ANALOG_ATTRIBUTE ++{ ++ UCHAR ucTVStandard; //Same as TV standards defined above, ++ UCHAR ucPadding[1]; ++}ATOM_ENCODER_ANALOG_ATTRIBUTE; ++ ++typedef struct _ATOM_ENCODER_DIGITAL_ATTRIBUTE ++{ ++ UCHAR ucAttribute; //Same as other digital encoder attributes defined above ++ UCHAR ucPadding[1]; ++}ATOM_ENCODER_DIGITAL_ATTRIBUTE; ++ ++typedef union _ATOM_ENCODER_ATTRIBUTE ++{ ++ ATOM_ENCODER_ANALOG_ATTRIBUTE sAlgAttrib; ++ ATOM_ENCODER_DIGITAL_ATTRIBUTE sDigAttrib; ++}ATOM_ENCODER_ATTRIBUTE; ++ ++ ++typedef struct _DVO_ENCODER_CONTROL_PARAMETERS ++{ ++ USHORT usPixelClock; ++ USHORT usEncoderID; ++ UCHAR ucDeviceType; //Use ATOM_DEVICE_xxx1_Index to indicate device type only. ++ UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT ++ ATOM_ENCODER_ATTRIBUTE usDevAttr; ++}DVO_ENCODER_CONTROL_PARAMETERS; ++ ++typedef struct _DVO_ENCODER_CONTROL_PS_ALLOCATION ++{ ++ DVO_ENCODER_CONTROL_PARAMETERS sDVOEncoder; ++ WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion ++}DVO_ENCODER_CONTROL_PS_ALLOCATION; ++ ++ ++#define ATOM_XTMDS_ASIC_SI164_ID 1 ++#define ATOM_XTMDS_ASIC_SI178_ID 2 ++#define ATOM_XTMDS_ASIC_TFP513_ID 3 ++#define ATOM_XTMDS_SUPPORTED_SINGLELINK 0x00000001 ++#define ATOM_XTMDS_SUPPORTED_DUALLINK 0x00000002 ++#define ATOM_XTMDS_MVPU_FPGA 0x00000004 ++ ++ ++typedef struct _ATOM_XTMDS_INFO ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ USHORT usSingleLinkMaxFrequency; ++ ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; //Point the ID on which I2C is used to control external chip ++ UCHAR ucXtransimitterID; ++ UCHAR ucSupportedLink; // Bit field, bit0=1, single link supported;bit1=1,dual link supported ++ UCHAR ucSequnceAlterID; // Even with the same external TMDS asic, it's possible that the program seqence alters ++ // due to design. This ID is used to alert driver that the sequence is not "standard"! ++ UCHAR ucMasterAddress; // Address to control Master xTMDS Chip ++ UCHAR ucSlaveAddress; // Address to control Slave xTMDS Chip ++}ATOM_XTMDS_INFO; ++ ++typedef struct _DFP_DPMS_STATUS_CHANGE_PARAMETERS ++{ ++ UCHAR ucEnable; // ATOM_ENABLE=On or ATOM_DISABLE=Off ++ UCHAR ucDevice; // ATOM_DEVICE_DFP1_INDEX.... ++ UCHAR ucPadding[2]; ++}DFP_DPMS_STATUS_CHANGE_PARAMETERS; ++ ++/****************************Legacy Power Play Table Definitions **********************/ ++ ++//Definitions for ulPowerPlayMiscInfo ++#define ATOM_PM_MISCINFO_SPLIT_CLOCK 0x00000000L ++#define ATOM_PM_MISCINFO_USING_MCLK_SRC 0x00000001L ++#define ATOM_PM_MISCINFO_USING_SCLK_SRC 0x00000002L ++ ++#define ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT 0x00000004L ++#define ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH 0x00000008L ++ ++#define ATOM_PM_MISCINFO_LOAD_PERFORMANCE_EN 0x00000010L ++ ++#define ATOM_PM_MISCINFO_ENGINE_CLOCK_CONTRL_EN 0x00000020L ++#define ATOM_PM_MISCINFO_MEMORY_CLOCK_CONTRL_EN 0x00000040L ++#define ATOM_PM_MISCINFO_PROGRAM_VOLTAGE 0x00000080L //When this bit set, ucVoltageDropIndex is not an index for GPIO pin, but a voltage ID that SW needs program ++ ++#define ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN 0x00000100L ++#define ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN 0x00000200L ++#define ATOM_PM_MISCINFO_ASIC_SLEEP_MODE_EN 0x00000400L ++#define ATOM_PM_MISCINFO_LOAD_BALANCE_EN 0x00000800L ++#define ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE 0x00001000L ++#define ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE 0x00002000L ++#define ATOM_PM_MISCINFO_LOW_LCD_REFRESH_RATE 0x00004000L ++ ++#define ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE 0x00008000L ++#define ATOM_PM_MISCINFO_OVER_CLOCK_MODE 0x00010000L ++#define ATOM_PM_MISCINFO_OVER_DRIVE_MODE 0x00020000L ++#define ATOM_PM_MISCINFO_POWER_SAVING_MODE 0x00040000L ++#define ATOM_PM_MISCINFO_THERMAL_DIODE_MODE 0x00080000L ++ ++#define ATOM_PM_MISCINFO_FRAME_MODULATION_MASK 0x00300000L //0-FM Disable, 1-2 level FM, 2-4 level FM, 3-Reserved ++#define ATOM_PM_MISCINFO_FRAME_MODULATION_SHIFT 20 ++ ++#define ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE 0x00400000L ++#define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2 0x00800000L ++#define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4 0x01000000L ++#define ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN 0x02000000L //When set, Dynamic ++#define ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN 0x04000000L //When set, Dynamic ++#define ATOM_PM_MISCINFO_3D_ACCELERATION_EN 0x08000000L //When set, This mode is for acceleated 3D mode ++ ++#define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_MASK 0x70000000L //1-Optimal Battery Life Group, 2-High Battery, 3-Balanced, 4-High Performance, 5- Optimal Performance (Default state with Default clocks) ++#define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_SHIFT 28 ++#define ATOM_PM_MISCINFO_ENABLE_BACK_BIAS 0x80000000L ++ ++#define ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE 0x00000001L ++#define ATOM_PM_MISCINFO2_MULTI_DISPLAY_SUPPORT 0x00000002L ++#define ATOM_PM_MISCINFO2_DYNAMIC_BACK_BIAS_EN 0x00000004L ++#define ATOM_PM_MISCINFO2_FS3D_OVERDRIVE_INFO 0x00000008L ++#define ATOM_PM_MISCINFO2_FORCEDLOWPWR_MODE 0x00000010L ++#define ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN 0x00000020L ++#define ATOM_PM_MISCINFO2_VIDEO_PLAYBACK_CAPABLE 0x00000040L //If this bit is set in multi-pp mode, then driver will pack up one with the minior power consumption. ++ //If it's not set in any pp mode, driver will use its default logic to pick a pp mode in video playback ++#define ATOM_PM_MISCINFO2_NOT_VALID_ON_DC 0x00000080L ++#define ATOM_PM_MISCINFO2_STUTTER_MODE_EN 0x00000100L ++#define ATOM_PM_MISCINFO2_UVD_SUPPORT_MODE 0x00000200L ++ ++//ucTableFormatRevision=1 ++//ucTableContentRevision=1 ++typedef struct _ATOM_POWERMODE_INFO ++{ ++ ULONG ulMiscInfo; //The power level should be arranged in ascending order ++ ULONG ulReserved1; // must set to 0 ++ ULONG ulReserved2; // must set to 0 ++ USHORT usEngineClock; ++ USHORT usMemoryClock; ++ UCHAR ucVoltageDropIndex; // index to GPIO table ++ UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate ++ UCHAR ucMinTemperature; ++ UCHAR ucMaxTemperature; ++ UCHAR ucNumPciELanes; // number of PCIE lanes ++}ATOM_POWERMODE_INFO; ++ ++//ucTableFormatRevision=2 ++//ucTableContentRevision=1 ++typedef struct _ATOM_POWERMODE_INFO_V2 ++{ ++ ULONG ulMiscInfo; //The power level should be arranged in ascending order ++ ULONG ulMiscInfo2; ++ ULONG ulEngineClock; ++ ULONG ulMemoryClock; ++ UCHAR ucVoltageDropIndex; // index to GPIO table ++ UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate ++ UCHAR ucMinTemperature; ++ UCHAR ucMaxTemperature; ++ UCHAR ucNumPciELanes; // number of PCIE lanes ++}ATOM_POWERMODE_INFO_V2; ++ ++//ucTableFormatRevision=2 ++//ucTableContentRevision=2 ++typedef struct _ATOM_POWERMODE_INFO_V3 ++{ ++ ULONG ulMiscInfo; //The power level should be arranged in ascending order ++ ULONG ulMiscInfo2; ++ ULONG ulEngineClock; ++ ULONG ulMemoryClock; ++ UCHAR ucVoltageDropIndex; // index to Core (VDDC) votage table ++ UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate ++ UCHAR ucMinTemperature; ++ UCHAR ucMaxTemperature; ++ UCHAR ucNumPciELanes; // number of PCIE lanes ++ UCHAR ucVDDCI_VoltageDropIndex; // index to VDDCI votage table ++}ATOM_POWERMODE_INFO_V3; ++ ++ ++#define ATOM_MAX_NUMBEROF_POWER_BLOCK 8 ++ ++#define ATOM_PP_OVERDRIVE_INTBITMAP_AUXWIN 0x01 ++#define ATOM_PP_OVERDRIVE_INTBITMAP_OVERDRIVE 0x02 ++ ++#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_LM63 0x01 ++#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ADM1032 0x02 ++#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ADM1030 0x03 ++#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_MUA6649 0x04 ++#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_LM64 0x05 ++#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_F75375 0x06 ++#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ASC7512 0x07 // Andigilog ++ ++ ++typedef struct _ATOM_POWERPLAY_INFO ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ UCHAR ucOverdriveThermalController; ++ UCHAR ucOverdriveI2cLine; ++ UCHAR ucOverdriveIntBitmap; ++ UCHAR ucOverdriveControllerAddress; ++ UCHAR ucSizeOfPowerModeEntry; ++ UCHAR ucNumOfPowerModeEntries; ++ ATOM_POWERMODE_INFO asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK]; ++}ATOM_POWERPLAY_INFO; ++ ++typedef struct _ATOM_POWERPLAY_INFO_V2 ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ UCHAR ucOverdriveThermalController; ++ UCHAR ucOverdriveI2cLine; ++ UCHAR ucOverdriveIntBitmap; ++ UCHAR ucOverdriveControllerAddress; ++ UCHAR ucSizeOfPowerModeEntry; ++ UCHAR ucNumOfPowerModeEntries; ++ ATOM_POWERMODE_INFO_V2 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK]; ++}ATOM_POWERPLAY_INFO_V2; ++ ++typedef struct _ATOM_POWERPLAY_INFO_V3 ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ UCHAR ucOverdriveThermalController; ++ UCHAR ucOverdriveI2cLine; ++ UCHAR ucOverdriveIntBitmap; ++ UCHAR ucOverdriveControllerAddress; ++ UCHAR ucSizeOfPowerModeEntry; ++ UCHAR ucNumOfPowerModeEntries; ++ ATOM_POWERMODE_INFO_V3 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK]; ++}ATOM_POWERPLAY_INFO_V3; ++ ++ ++ ++/**************************************************************************/ ++ ++ ++// Following definitions are for compatiblity issue in different SW components. ++#define ATOM_MASTER_DATA_TABLE_REVISION 0x01 ++#define Object_Info Object_Header ++#define AdjustARB_SEQ MC_InitParameter ++#define VRAM_GPIO_DetectionInfo VoltageObjectInfo ++#define ASIC_VDDCI_Info ASIC_ProfilingInfo ++#define ASIC_MVDDQ_Info MemoryTrainingInfo ++#define SS_Info PPLL_SS_Info ++#define ASIC_MVDDC_Info ASIC_InternalSS_Info ++#define DispDevicePriorityInfo SaveRestoreInfo ++#define DispOutInfo TV_VideoMode ++ ++ ++#define ATOM_ENCODER_OBJECT_TABLE ATOM_OBJECT_TABLE ++#define ATOM_CONNECTOR_OBJECT_TABLE ATOM_OBJECT_TABLE ++ ++#define ATOM_S3_SCALER2_ACTIVE_H 0x00004000L ++#define ATOM_S3_SCALER2_ACTIVE_V 0x00008000L ++#define ATOM_S6_REQ_SCALER2_H 0x00004000L ++#define ATOM_S6_REQ_SCALER2_V 0x00008000L ++ ++#define ATOM_S3_SCALER1_ACTIVE_H 0x00001000L ++#define ATOM_S3_SCALER1_ACTIVE_V 0x00002000L ++ ++#define ATOM_S6_REQ_SCALER1_H ATOM_S6_REQ_LCD_EXPANSION_FULL ++#define ATOM_S6_REQ_SCALER1_V ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIO ++ ++//New device naming, remove them when both DAL/VBIOS is ready ++#define DFP2I_OUTPUT_CONTROL_PARAMETERS CRT1_OUTPUT_CONTROL_PARAMETERS ++#define DFP2I_OUTPUT_CONTROL_PS_ALLOCATION DFP2I_OUTPUT_CONTROL_PARAMETERS ++ ++#define DFP1X_OUTPUT_CONTROL_PARAMETERS CRT1_OUTPUT_CONTROL_PARAMETERS ++#define DFP1X_OUTPUT_CONTROL_PS_ALLOCATION DFP1X_OUTPUT_CONTROL_PARAMETERS ++ ++#define DFP1I_OUTPUT_CONTROL_PARAMETERS DFP1_OUTPUT_CONTROL_PARAMETERS ++#define DFP1I_OUTPUT_CONTROL_PS_ALLOCATION DFP1_OUTPUT_CONTROL_PS_ALLOCATION ++ ++#define ATOM_DEVICE_DFP1I_SUPPORT ATOM_DEVICE_DFP1_SUPPORT ++#define ATOM_DEVICE_DFP1X_SUPPORT ATOM_DEVICE_DFP2_SUPPORT ++ ++#define ATOM_DEVICE_DFP1I_INDEX ATOM_DEVICE_DFP1_INDEX ++#define ATOM_DEVICE_DFP1X_INDEX ATOM_DEVICE_DFP2_INDEX ++ ++#define ATOM_DEVICE_DFP2I_INDEX 0x00000009 ++#define ATOM_DEVICE_DFP2I_SUPPORT (0x1L << ATOM_DEVICE_DFP2I_INDEX) ++ ++#define ATOM_S0_DFP1I ATOM_S0_DFP1 ++#define ATOM_S0_DFP1X ATOM_S0_DFP2 ++ ++#define ATOM_S0_DFP2I 0x00200000L ++#define ATOM_S0_DFP2Ib2 0x20 ++ ++#define ATOM_S2_DFP1I_DPMS_STATE ATOM_S2_DFP1_DPMS_STATE ++#define ATOM_S2_DFP1X_DPMS_STATE ATOM_S2_DFP2_DPMS_STATE ++ ++#define ATOM_S2_DFP2I_DPMS_STATE 0x02000000L ++#define ATOM_S2_DFP2I_DPMS_STATEb3 0x02 ++ ++#define ATOM_S3_DFP2I_ACTIVEb1 0x02 ++ ++#define ATOM_S3_DFP1I_ACTIVE ATOM_S3_DFP1_ACTIVE ++#define ATOM_S3_DFP1X_ACTIVE ATOM_S3_DFP2_ACTIVE ++ ++#define ATOM_S3_DFP2I_ACTIVE 0x00000200L ++ ++#define ATOM_S3_DFP1I_CRTC_ACTIVE ATOM_S3_DFP1_CRTC_ACTIVE ++#define ATOM_S3_DFP1X_CRTC_ACTIVE ATOM_S3_DFP2_CRTC_ACTIVE ++#define ATOM_S3_DFP2I_CRTC_ACTIVE 0x02000000L ++ ++#define ATOM_S3_DFP2I_CRTC_ACTIVEb3 0x02 ++#define ATOM_S5_DOS_REQ_DFP2Ib1 0x02 ++ ++#define ATOM_S5_DOS_REQ_DFP2I 0x0200 ++#define ATOM_S6_ACC_REQ_DFP1I ATOM_S6_ACC_REQ_DFP1 ++#define ATOM_S6_ACC_REQ_DFP1X ATOM_S6_ACC_REQ_DFP2 ++ ++#define ATOM_S6_ACC_REQ_DFP2Ib3 0x02 ++#define ATOM_S6_ACC_REQ_DFP2I 0x02000000L ++ ++#define TMDS1XEncoderControl DVOEncoderControl ++#define DFP1XOutputControl DVOOutputControl ++ ++#define ExternalDFPOutputControl DFP1XOutputControl ++#define EnableExternalTMDS_Encoder TMDS1XEncoderControl ++ ++#define DFP1IOutputControl TMDSAOutputControl ++#define DFP2IOutputControl LVTMAOutputControl ++ ++#define DAC1_ENCODER_CONTROL_PARAMETERS DAC_ENCODER_CONTROL_PARAMETERS ++#define DAC1_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PS_ALLOCATION ++ ++#define DAC2_ENCODER_CONTROL_PARAMETERS DAC_ENCODER_CONTROL_PARAMETERS ++#define DAC2_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PS_ALLOCATION ++ ++#define ucDac1Standard ucDacStandard ++#define ucDac2Standard ucDacStandard ++ ++#define TMDS1EncoderControl TMDSAEncoderControl ++#define TMDS2EncoderControl LVTMAEncoderControl ++ ++#define DFP1OutputControl TMDSAOutputControl ++#define DFP2OutputControl LVTMAOutputControl ++#define CRT1OutputControl DAC1OutputControl ++#define CRT2OutputControl DAC2OutputControl ++ ++//These two lines will be removed for sure in a few days, will follow up with Michael V. ++#define EnableLVDS_SS EnableSpreadSpectrumOnPPLL ++#define ENABLE_LVDS_SS_PARAMETERS_V3 ENABLE_SPREAD_SPECTRUM_ON_PPLL ++ ++/*********************************************************************************/ ++ ++//========================================================================================== ++ ++#pragma pack() // BIOS data must use byte aligment ++ ++#endif /* _ATOMBIOS_H */ +diff --git a/src/AtomBios/includes/regsdef.h b/src/AtomBios/includes/regsdef.h +new file mode 100644 +index 0000000..e557ac0 +--- /dev/null ++++ b/src/AtomBios/includes/regsdef.h +@@ -0,0 +1,25 @@ ++/* ++ * Copyright 2006-2007 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in ++ * all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++//This is a dummy file used by driver-parser during compilation. ++//Without this file, compatibility will be broken among ASICs and BIOs vs. driver ++//James H. Apr. 22/03 +diff --git a/src/Makefile.am b/src/Makefile.am +index 5152577..3e0352b 100644 +--- a/src/Makefile.am ++++ b/src/Makefile.am +@@ -32,6 +32,38 @@ R128_DRI_SRCS = r128_dri.c + RADEON_DRI_SRCS = radeon_dri.c + endif + ++RADEON_ATOMBIOS_SOURCES = \ ++ AtomBios/CD_Operations.c \ ++ AtomBios/Decoder.c \ ++ AtomBios/hwserv_drv.c \ ++ AtomBios/includes/atombios.h \ ++ AtomBios/includes/CD_binding.h \ ++ AtomBios/includes/CD_Common_Types.h \ ++ AtomBios/includes/CD_Definitions.h \ ++ AtomBios/includes/CD_hw_services.h \ ++ AtomBios/includes/CD_Opcodes.h \ ++ AtomBios/includes/CD_Structs.h \ ++ AtomBios/includes/Decoder.h \ ++ AtomBios/includes/ObjectID.h \ ++ AtomBios/includes/regsdef.h ++ ++XMODE_SRCS=\ ++ local_xf86Rename.h \ ++ parser/xf86Parser.h \ ++ parser/xf86Optrec.h \ ++ modes/xf86Modes.h \ ++ modes/xf86Modes.c \ ++ modes/xf86cvt.c \ ++ modes/xf86Crtc.h \ ++ modes/xf86Crtc.c \ ++ modes/xf86Cursors.c \ ++ modes/xf86EdidModes.c \ ++ modes/xf86RandR12.c \ ++ modes/xf86RandR12.h \ ++ modes/xf86Rename.h \ ++ modes/xf86Rotate.c \ ++ modes/xf86DiDGA.c ++ + if ATIMISC_CPIO + ATIMISC_CPIO_SOURCES = ativga.c ativgaio.c atibank.c atiwonder.c atiwonderio.c + endif +@@ -45,7 +77,8 @@ ATIMISC_EXA_SOURCES = atimach64exa.c + RADEON_EXA_SOURCES = radeon_exa.c + endif + +-AM_CFLAGS = @XORG_CFLAGS@ @DRI_CFLAGS@ ++AM_CFLAGS = @XORG_CFLAGS@ @DRI_CFLAGS@ @XMODES_CFLAGS@ -DDISABLE_EASF -DENABLE_ALL_SERVICE_FUNCTIONS -DATOM_BIOS -DATOM_BIOS_PARSER ++INCLUDES = -I$(srcdir)/AtomBios/includes + + ati_drv_la_LTLIBRARIES = ati_drv.la + ati_drv_la_LDFLAGS = -module -avoid-version +@@ -85,7 +118,13 @@ radeon_drv_la_SOURCES = \ + radeon_driver.c radeon_video.c radeon_bios.c radeon_mm_i2c.c \ + radeon_vip.c radeon_misc.c radeon_probe.c radeon_display.c \ + radeon_crtc.c radeon_output.c radeon_modes.c radeon_tv.c \ +- $(RADEON_DRI_SRCS) $(RADEON_EXA_SOURCES) ++ $(RADEON_ATOMBIOS_SOURCES) radeon_atombios.c radeon_atomwrapper.c \ ++ $(RADEON_DRI_SRCS) $(RADEON_EXA_SOURCES) atombios_output.c atombios_crtc.c ++ ++if XMODES ++radeon_drv_la_SOURCES += \ ++ $(XMODE_SRCS) ++endif + + theatre_detect_drv_la_LTLIBRARIES = theatre_detect_drv.la + theatre_detect_drv_la_LDFLAGS = -module -avoid-version +@@ -109,6 +148,7 @@ theatre200_drv_la_SOURCES = \ + theatre200.c theatre200_module.c + + EXTRA_DIST = \ ++ $(XMODE_SRCS) \ + atimach64render.c \ + radeon_render.c \ + radeon_accelfuncs.c \ +@@ -185,6 +225,7 @@ EXTRA_DIST = \ + radeon_version.h \ + radeon_video.h \ + radeon_tv.h \ ++ radeon_atomwrapper.h \ + theatre200.h \ + theatre_detect.h \ + theatre.h \ +@@ -196,4 +237,5 @@ EXTRA_DIST = \ + radeon_chipset_gen.h \ + radeon_pci_chipset_gen.h \ + pcidb/ati_pciids.csv \ +- pcidb/parse_pci_ids.pl ++ pcidb/parse_pci_ids.pl \ ++ radeon_atombios.h +diff --git a/src/ati_pciids_gen.h b/src/ati_pciids_gen.h +index ad54f64..53ae24c 100644 +--- a/src/ati_pciids_gen.h ++++ b/src/ati_pciids_gen.h +@@ -215,5 +215,137 @@ + #define PCI_CHIP_RV410_5E4C 0x5E4C + #define PCI_CHIP_RV410_5E4D 0x5E4D + #define PCI_CHIP_RV410_5E4F 0x5E4F ++#define PCI_CHIP_R520_7100 0x7100 ++#define PCI_CHIP_R520_7101 0x7101 ++#define PCI_CHIP_R520_7102 0x7102 ++#define PCI_CHIP_R520_7103 0x7103 ++#define PCI_CHIP_R520_7104 0x7104 ++#define PCI_CHIP_R520_7105 0x7105 ++#define PCI_CHIP_R520_7106 0x7106 ++#define PCI_CHIP_R520_7108 0x7108 ++#define PCI_CHIP_R520_7109 0x7109 ++#define PCI_CHIP_R520_710A 0x710A ++#define PCI_CHIP_R520_710B 0x710B ++#define PCI_CHIP_R520_710C 0x710C ++#define PCI_CHIP_R520_710E 0x710E ++#define PCI_CHIP_R520_710F 0x710F ++#define PCI_CHIP_RV515_7140 0x7140 ++#define PCI_CHIP_RV515_7141 0x7141 ++#define PCI_CHIP_RV515_7142 0x7142 ++#define PCI_CHIP_RV515_7143 0x7143 ++#define PCI_CHIP_RV515_7144 0x7144 ++#define PCI_CHIP_RV515_7145 0x7145 ++#define PCI_CHIP_RV515_7146 0x7146 ++#define PCI_CHIP_RV515_7147 0x7147 ++#define PCI_CHIP_RV515_7149 0x7149 ++#define PCI_CHIP_RV515_714A 0x714A ++#define PCI_CHIP_RV515_714B 0x714B ++#define PCI_CHIP_RV515_714C 0x714C ++#define PCI_CHIP_RV515_714D 0x714D ++#define PCI_CHIP_RV515_714E 0x714E ++#define PCI_CHIP_RV515_714F 0x714F ++#define PCI_CHIP_RV515_7151 0x7151 ++#define PCI_CHIP_RV515_7152 0x7152 ++#define PCI_CHIP_RV515_7153 0x7153 ++#define PCI_CHIP_RV515_715E 0x715E ++#define PCI_CHIP_RV515_715F 0x715F ++#define PCI_CHIP_RV515_7180 0x7180 ++#define PCI_CHIP_RV515_7181 0x7181 ++#define PCI_CHIP_RV515_7183 0x7183 ++#define PCI_CHIP_RV515_7186 0x7186 ++#define PCI_CHIP_RV515_7187 0x7187 ++#define PCI_CHIP_RV515_7188 0x7188 ++#define PCI_CHIP_RV515_718A 0x718A ++#define PCI_CHIP_RV515_718B 0x718B ++#define PCI_CHIP_RV515_718C 0x718C ++#define PCI_CHIP_RV515_718D 0x718D ++#define PCI_CHIP_RV515_718F 0x718F ++#define PCI_CHIP_RV515_7193 0x7193 ++#define PCI_CHIP_RV515_7196 0x7196 ++#define PCI_CHIP_RV515_719B 0x719B ++#define PCI_CHIP_RV515_719F 0x719F ++#define PCI_CHIP_RV530_71C0 0x71C0 ++#define PCI_CHIP_RV530_71C1 0x71C1 ++#define PCI_CHIP_RV530_71C2 0x71C2 ++#define PCI_CHIP_RV530_71C3 0x71C3 ++#define PCI_CHIP_RV530_71C4 0x71C4 ++#define PCI_CHIP_RV530_71C5 0x71C5 ++#define PCI_CHIP_RV530_71C6 0x71C6 ++#define PCI_CHIP_RV530_71C7 0x71C7 ++#define PCI_CHIP_RV530_71CD 0x71CD ++#define PCI_CHIP_RV530_71CE 0x71CE ++#define PCI_CHIP_RV530_71D2 0x71D2 ++#define PCI_CHIP_RV530_71D4 0x71D4 ++#define PCI_CHIP_RV530_71D5 0x71D5 ++#define PCI_CHIP_RV530_71D6 0x71D6 ++#define PCI_CHIP_RV530_71DA 0x71DA ++#define PCI_CHIP_RV530_71DE 0x71DE ++#define PCI_CHIP_RV530_7200 0x7200 ++#define PCI_CHIP_RV530_7210 0x7210 ++#define PCI_CHIP_RV530_7211 0x7211 ++#define PCI_CHIP_R580_7240 0x7240 ++#define PCI_CHIP_R580_7243 0x7243 ++#define PCI_CHIP_R580_7244 0x7244 ++#define PCI_CHIP_R580_7245 0x7245 ++#define PCI_CHIP_R580_7246 0x7246 ++#define PCI_CHIP_R580_7247 0x7247 ++#define PCI_CHIP_R580_7248 0x7248 ++#define PCI_CHIP_R580_7249 0x7249 ++#define PCI_CHIP_R580_724A 0x724A ++#define PCI_CHIP_R580_724B 0x724B ++#define PCI_CHIP_R580_724C 0x724C ++#define PCI_CHIP_R580_724D 0x724D ++#define PCI_CHIP_R580_724E 0x724E ++#define PCI_CHIP_R580_724F 0x724F ++#define PCI_CHIP_RV570_7280 0x7280 ++#define PCI_CHIP_RV560_7281 0x7281 ++#define PCI_CHIP_RV560_7283 0x7283 ++#define PCI_CHIP_R580_7284 0x7284 ++#define PCI_CHIP_RV560_7287 0x7287 ++#define PCI_CHIP_RV570_7288 0x7288 ++#define PCI_CHIP_RV570_7289 0x7289 ++#define PCI_CHIP_RV570_728B 0x728B ++#define PCI_CHIP_RV570_728C 0x728C ++#define PCI_CHIP_RV560_7290 0x7290 ++#define PCI_CHIP_RV560_7291 0x7291 ++#define PCI_CHIP_RV560_7293 0x7293 ++#define PCI_CHIP_RV560_7297 0x7297 + #define PCI_CHIP_RS350_7834 0x7834 + #define PCI_CHIP_RS350_7835 0x7835 ++#define PCI_CHIP_RS690_791E 0x791E ++#define PCI_CHIP_RS690_791F 0x791F ++#define PCI_CHIP_RS740_796C 0x796C ++#define PCI_CHIP_RS740_796D 0x796D ++#define PCI_CHIP_RS740_796E 0x796E ++#define PCI_CHIP_RS740_796F 0x796F ++#define PCI_CHIP_R600_9400 0x9400 ++#define PCI_CHIP_R600_9401 0x9401 ++#define PCI_CHIP_R600_9402 0x9402 ++#define PCI_CHIP_R600_9403 0x9403 ++#define PCI_CHIP_R600_9405 0x9405 ++#define PCI_CHIP_R600_940A 0x940A ++#define PCI_CHIP_R600_940B 0x940B ++#define PCI_CHIP_R600_940F 0x940F ++#define PCI_CHIP_RV610_94C0 0x94C0 ++#define PCI_CHIP_RV610_94C1 0x94C1 ++#define PCI_CHIP_RV610_94C3 0x94C3 ++#define PCI_CHIP_RV610_94C4 0x94C4 ++#define PCI_CHIP_RV610_94C5 0x94C5 ++#define PCI_CHIP_RV610_94C6 0x94C6 ++#define PCI_CHIP_RV610_94C7 0x94C7 ++#define PCI_CHIP_RV610_94C8 0x94C8 ++#define PCI_CHIP_RV610_94C9 0x94C9 ++#define PCI_CHIP_RV610_94CB 0x94CB ++#define PCI_CHIP_RV610_94CC 0x94CC ++#define PCI_CHIP_RV630_9580 0x9580 ++#define PCI_CHIP_RV630_9581 0x9581 ++#define PCI_CHIP_RV630_9583 0x9583 ++#define PCI_CHIP_RV630_9586 0x9586 ++#define PCI_CHIP_RV630_9587 0x9587 ++#define PCI_CHIP_RV630_9588 0x9588 ++#define PCI_CHIP_RV630_9589 0x9589 ++#define PCI_CHIP_RV630_958A 0x958A ++#define PCI_CHIP_RV630_958B 0x958B ++#define PCI_CHIP_RV630_958C 0x958C ++#define PCI_CHIP_RV630_958D 0x958D ++#define PCI_CHIP_RV630_958E 0x958E +diff --git a/src/atipciids.h b/src/atipciids.h +index f24f8fb..2953964 100644 +--- a/src/atipciids.h ++++ b/src/atipciids.h +@@ -40,6 +40,13 @@ + + #include "ati_pciids_gen.h" + ++#define PCI_CHIP_R520_7104 0x7104 ++#define PCI_CHIP_RV515_7142 0x7142 ++#define PCI_CHIP_RV515_7183 0x7183 ++#define PCI_CHIP_RV530_71C5 0x71C5 ++#define PCI_CHIP_R580_7249 0x7249 ++#define PCI_CHIP_RV570_7280 0x7280 ++ + /* Misc */ + #define PCI_CHIP_AMD761 0x700E + +diff --git a/src/atombios_crtc.c b/src/atombios_crtc.c +new file mode 100644 +index 0000000..e7ad4a9 +--- /dev/null ++++ b/src/atombios_crtc.c +@@ -0,0 +1,381 @@ ++ /* ++ * Copyright © 2007 Red Hat, Inc. ++ * ++ * PLL code is: ++ * Copyright 2007 Luc Verhaegen ++ * Copyright 2007 Matthias Hopf ++ * Copyright 2007 Egbert Eich ++ * Copyright 2007 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice (including the next ++ * paragraph) shall be included in all copies or substantial portions of the ++ * Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER ++ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, ++ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE ++ * SOFTWARE. ++ * ++ * Authors: ++ * Dave Airlie ++ * ++ */ ++/* ++ * avivo crtc handling functions. ++ */ ++#ifdef HAVE_CONFIG_H ++#include "config.h" ++#endif ++/* DPMS */ ++#define DPMS_SERVER ++#include ++ ++#include "radeon.h" ++#include "radeon_reg.h" ++#include "radeon_macros.h" ++#include "radeon_atombios.h" ++ ++#ifdef XF86DRI ++#define _XF86DRI_SERVER_ ++#include "radeon_dri.h" ++#include "radeon_sarea.h" ++#include "sarea.h" ++#endif ++ ++AtomBiosResult ++atombios_enable_crtc(atomBiosHandlePtr atomBIOS, int crtc, int state) ++{ ++ ENABLE_CRTC_PS_ALLOCATION crtc_data; ++ AtomBiosArgRec data; ++ unsigned char *space; ++ ++ crtc_data.ucCRTC = crtc; ++ crtc_data.ucEnable = state; ++ ++ data.exec.index = GetIndexIntoMasterTable(COMMAND, EnableCRTC); ++ data.exec.dataSpace = (void *)&space; ++ data.exec.pspace = &crtc_data; ++ ++ if (RHDAtomBiosFunc(atomBIOS->scrnIndex, atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) { ++ ErrorF("%s CRTC %d success\n", state? "Enable":"Disable", crtc); ++ return ATOM_SUCCESS ; ++ } ++ ++ ErrorF("Enable CRTC failed\n"); ++ return ATOM_NOT_IMPLEMENTED; ++} ++ ++AtomBiosResult ++atombios_blank_crtc(atomBiosHandlePtr atomBIOS, int crtc, int state) ++{ ++ BLANK_CRTC_PS_ALLOCATION crtc_data; ++ unsigned char *space; ++ AtomBiosArgRec data; ++ ++ memset(&crtc_data, 0, sizeof(crtc_data)); ++ crtc_data.ucCRTC = crtc; ++ crtc_data.ucBlanking = state; ++ ++ data.exec.index = offsetof(ATOM_MASTER_LIST_OF_COMMAND_TABLES, BlankCRTC) / sizeof(unsigned short); ++ data.exec.dataSpace = (void *)&space; ++ data.exec.pspace = &crtc_data; ++ ++ if (RHDAtomBiosFunc(atomBIOS->scrnIndex, atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) { ++ ErrorF("%s CRTC %d success\n", state? "Blank":"Unblank", crtc); ++ return ATOM_SUCCESS ; ++ } ++ ++ ErrorF("Blank CRTC failed\n"); ++ return ATOM_NOT_IMPLEMENTED; ++} ++ ++static void ++atombios_crtc_enable(xf86CrtcPtr crtc, int enable) ++{ ++ RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; ++ RADEONInfoPtr info = RADEONPTR(crtc->scrn); ++ ++ atombios_enable_crtc(info->atomBIOS, radeon_crtc->crtc_id, enable); ++ ++ //TODOavivo_wait_idle(avivo); ++} ++ ++void ++atombios_crtc_dpms(xf86CrtcPtr crtc, int mode) ++{ ++ RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; ++ RADEONInfoPtr info = RADEONPTR(crtc->scrn); ++ switch (mode) { ++ case DPMSModeOn: ++ case DPMSModeStandby: ++ case DPMSModeSuspend: ++ atombios_enable_crtc(info->atomBIOS, radeon_crtc->crtc_id, 1); ++ atombios_blank_crtc(info->atomBIOS, radeon_crtc->crtc_id, 0); ++ break; ++ case DPMSModeOff: ++ atombios_blank_crtc(info->atomBIOS, radeon_crtc->crtc_id, 1); ++ atombios_enable_crtc(info->atomBIOS, radeon_crtc->crtc_id, 0); ++ break; ++ } ++} ++ ++static AtomBiosResult ++atombios_set_crtc_timing(atomBiosHandlePtr atomBIOS, SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION *crtc_param) ++{ ++ AtomBiosArgRec data; ++ unsigned char *space; ++ ++ data.exec.index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing); ++ data.exec.dataSpace = (void *)&space; ++ data.exec.pspace = crtc_param; ++ ++ if (RHDAtomBiosFunc(atomBIOS->scrnIndex, atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) { ++ ErrorF("Set CRTC Timing success\n"); ++ return ATOM_SUCCESS ; ++ } ++ ++ ErrorF("Set CRTC Timing failed\n"); ++ return ATOM_NOT_IMPLEMENTED; ++} ++ ++void ++atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode) ++{ ++ RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; ++ RADEONInfoPtr info = RADEONPTR(crtc->scrn); ++ unsigned char *RADEONMMIO = info->MMIO; ++ int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock); ++ CARD32 sclock = mode->Clock; ++ CARD32 ref_div = 0, fb_div = 0, post_div = 0; ++ int major, minor; ++ SET_PIXEL_CLOCK_PS_ALLOCATION spc_param; ++ void *ptr; ++ AtomBiosArgRec data; ++ unsigned char *space; ++ RADEONSavePtr save = info->ModeReg; ++ ++ if (IS_AVIVO_VARIANT) { ++ CARD32 temp; ++ RADEONComputePLL(&info->pll, mode->Clock, &temp, &fb_div, &ref_div, &post_div, 0); ++ sclock = temp; ++ ++ /* disable spread spectrum clocking for now -- thanks Hedy Lamarr */ ++ if (radeon_crtc->crtc_id == 0) { ++ temp = INREG(AVIVO_P1PLL_INT_SS_CNTL); ++ OUTREG(AVIVO_P1PLL_INT_SS_CNTL, temp & ~1); ++ } else { ++ temp = INREG(AVIVO_P2PLL_INT_SS_CNTL); ++ OUTREG(AVIVO_P2PLL_INT_SS_CNTL, temp & ~1); ++ } ++ } else { ++ sclock = save->dot_clock_freq; ++ fb_div = save->feedback_div; ++ post_div = save->post_div; ++ ref_div = save->ppll_ref_div; ++ } ++ ++ xf86DrvMsg(crtc->scrn->scrnIndex, X_INFO, ++ "crtc(%d) Clock: mode %d, PLL %u\n", ++ radeon_crtc->crtc_id, mode->Clock, sclock * 10); ++ xf86DrvMsg(crtc->scrn->scrnIndex, X_INFO, ++ "crtc(%d) PLL : refdiv %u, fbdiv 0x%X(%u), pdiv %u\n", ++ radeon_crtc->crtc_id, ref_div, fb_div, fb_div, post_div); ++ ++ atombios_get_command_table_version(info->atomBIOS, index, &major, &minor); ++ ++ ErrorF("table is %d %d\n", major, minor); ++ switch(major) { ++ case 1: ++ switch(minor) { ++ case 1: ++ case 2: { ++ spc_param.sPCLKInput.usPixelClock = sclock; ++ spc_param.sPCLKInput.usRefDiv = ref_div; ++ spc_param.sPCLKInput.usFbDiv = fb_div; ++ spc_param.sPCLKInput.ucPostDiv = post_div; ++ spc_param.sPCLKInput.ucPpll = radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1; ++ spc_param.sPCLKInput.ucCRTC = radeon_crtc->crtc_id; ++ spc_param.sPCLKInput.ucRefDivSrc = 1; ++ ++ ptr = &spc_param; ++ break; ++ } ++ default: ++ ErrorF("Unknown table version\n"); ++ exit(-1); ++ } ++ break; ++ default: ++ ErrorF("Unknown table version\n"); ++ exit(-1); ++ } ++ ++ data.exec.index = GetIndexIntoMasterTable(COMMAND, SetPixelClock); ++ data.exec.dataSpace = (void *)&space; ++ data.exec.pspace = ptr; ++ ++ if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) { ++ ErrorF("Set CRTC PLL success\n"); ++ return; ++ } ++ ++ ErrorF("Set CRTC PLL failed\n"); ++ return; ++} ++ ++void ++atombios_crtc_mode_set(xf86CrtcPtr crtc, ++ DisplayModePtr mode, ++ DisplayModePtr adjusted_mode, ++ int x, int y) ++{ ++ ScrnInfoPtr pScrn = crtc->scrn; ++ RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; ++ RADEONInfoPtr info = RADEONPTR(pScrn); ++ unsigned char *RADEONMMIO = info->MMIO; ++ unsigned long fb_location = crtc->scrn->fbOffset + info->fbLocation; ++ Bool tilingOld = info->tilingEnabled; ++ ++ SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION crtc_timing; ++ ++ memset(&crtc_timing, 0, sizeof(crtc_timing)); ++ ++ if (info->allowColorTiling) { ++ info->tilingEnabled = (adjusted_mode->Flags & (V_DBLSCAN | V_INTERLACE)) ? FALSE : TRUE; ++#ifdef XF86DRI ++ if (info->directRenderingEnabled && (info->tilingEnabled != tilingOld)) { ++ RADEONSAREAPrivPtr pSAREAPriv; ++ if (RADEONDRISetParam(pScrn, RADEON_SETPARAM_SWITCH_TILING, (info->tilingEnabled ? 1 : 0)) < 0) ++ xf86DrvMsg(pScrn->scrnIndex, X_ERROR, ++ "[drm] failed changing tiling status\n"); ++ /* if this is called during ScreenInit() we don't have pScrn->pScreen yet */ ++ pSAREAPriv = DRIGetSAREAPrivate(screenInfo.screens[pScrn->scrnIndex]); ++ info->tilingEnabled = pSAREAPriv->tiling_enabled ? TRUE : FALSE; ++ } ++#endif ++ } ++ ++ crtc_timing.ucCRTC = radeon_crtc->crtc_id; ++ crtc_timing.usH_Total = adjusted_mode->CrtcHTotal; ++ crtc_timing.usH_Disp = adjusted_mode->CrtcHDisplay; ++ crtc_timing.usH_SyncStart = adjusted_mode->CrtcHSyncStart; ++ crtc_timing.usH_SyncWidth = adjusted_mode->CrtcHSyncEnd - adjusted_mode->CrtcHSyncStart; ++ ++ crtc_timing.usV_Total = adjusted_mode->CrtcVTotal; ++ crtc_timing.usV_Disp = adjusted_mode->CrtcVDisplay; ++ crtc_timing.usV_SyncStart = adjusted_mode->CrtcVSyncStart; ++ crtc_timing.usV_SyncWidth = adjusted_mode->CrtcVSyncEnd - adjusted_mode->CrtcVSyncStart; ++ ++ if (adjusted_mode->Flags & V_NVSYNC) ++ crtc_timing.susModeMiscInfo.usAccess |= ATOM_VSYNC_POLARITY; ++ ++ if (adjusted_mode->Flags & V_NHSYNC) ++ crtc_timing.susModeMiscInfo.usAccess |= ATOM_HSYNC_POLARITY; ++ ++ ErrorF("Mode %dx%d - %d %d %d\n", adjusted_mode->CrtcHDisplay, adjusted_mode->CrtcVDisplay, ++ adjusted_mode->CrtcHTotal, adjusted_mode->CrtcVTotal, adjusted_mode->Flags); ++ ++ RADEONInitMemMapRegisters(pScrn, info->ModeReg, info); ++ RADEONRestoreMemMapRegisters(pScrn, info->ModeReg); ++ ++ if (IS_AVIVO_VARIANT) { ++ radeon_crtc->fb_width = adjusted_mode->CrtcHDisplay; ++ radeon_crtc->fb_height = pScrn->virtualY; ++ radeon_crtc->fb_pitch = adjusted_mode->CrtcHDisplay; ++ radeon_crtc->fb_length = radeon_crtc->fb_pitch * radeon_crtc->fb_height * 4; ++ switch (crtc->scrn->bitsPerPixel) { ++ case 15: ++ radeon_crtc->fb_format = AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555; ++ break; ++ case 16: ++ radeon_crtc->fb_format = AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | AVIVO_D1GRPH_CONTROL_16BPP_RGB565; ++ break; ++ case 24: ++ case 32: ++ radeon_crtc->fb_format = AVIVO_D1GRPH_CONTROL_DEPTH_32BPP | AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888; ++ break; ++ default: ++ FatalError("Unsupported screen depth: %d\n", xf86GetDepth()); ++ } ++ ++ if (info->tilingEnabled && (crtc->rotatedData == NULL)) { ++ radeon_crtc->fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE; ++ } ++ ++ if (radeon_crtc->crtc_id == 0) ++ OUTREG(AVIVO_D1VGA_CONTROL, 0); ++ else ++ OUTREG(AVIVO_D2VGA_CONTROL, 0); ++ ++ /* setup fb format and location ++ */ ++ if (crtc->rotatedData != NULL) { ++ /* x/y offset is already included */ ++ x = 0; ++ y = 0; ++ fb_location = fb_location + (char *)crtc->rotatedData - (char *)info->FB; ++ } ++ ++ /* lock the grph regs */ ++ OUTREG(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, AVIVO_D1GRPH_UPDATE_LOCK); ++ ++ OUTREG(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, fb_location); ++ OUTREG(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, fb_location); ++ OUTREG(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, ++ radeon_crtc->fb_format); ++ ++ OUTREG(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); ++ OUTREG(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); ++ OUTREG(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0); ++ OUTREG(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0); ++ OUTREG(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, ++ crtc->scrn->virtualX); ++ OUTREG(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, ++ crtc->scrn->virtualY); ++ OUTREG(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, ++ crtc->scrn->displayWidth); ++ OUTREG(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1); ++ ++ /* unlock the grph regs */ ++ OUTREG(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, 0); ++ ++ /* lock the mode regs */ ++ OUTREG(AVIVO_D1SCL_UPDATE + radeon_crtc->crtc_offset, AVIVO_D1SCL_UPDATE_LOCK); ++ ++ OUTREG(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, ++ crtc->scrn->virtualY); ++ OUTREG(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset, (x << 16) | y); ++ OUTREG(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset, ++ (mode->HDisplay << 16) | mode->VDisplay); ++ /* unlock the mode regs */ ++ OUTREG(AVIVO_D1SCL_UPDATE + radeon_crtc->crtc_offset, 0); ++ ++ } ++ ++ atombios_crtc_set_pll(crtc, adjusted_mode); ++ ++ atombios_set_crtc_timing(info->atomBIOS, &crtc_timing); ++ ++ if (info->tilingEnabled != tilingOld) { ++ /* need to redraw front buffer, I guess this can be considered a hack ? */ ++ /* if this is called during ScreenInit() we don't have pScrn->pScreen yet */ ++ if (pScrn->pScreen) ++ xf86EnableDisableFBAccess(pScrn->scrnIndex, FALSE); ++ RADEONChangeSurfaces(pScrn); ++ if (pScrn->pScreen) ++ xf86EnableDisableFBAccess(pScrn->scrnIndex, TRUE); ++ /* xf86SetRootClip would do, but can't access that here */ ++ } ++ ++} ++ +diff --git a/src/atombios_output.c b/src/atombios_output.c +new file mode 100644 +index 0000000..f84afd0 +--- /dev/null ++++ b/src/atombios_output.c +@@ -0,0 +1,613 @@ ++/* ++ * Copyright © 2007 Red Hat, Inc. ++ * Copyright 2007 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice (including the next ++ * paragraph) shall be included in all copies or substantial portions of the ++ * Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER ++ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, ++ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE ++ * SOFTWARE. ++ * ++ * Authors: ++ * Dave Airlie ++ * Alex Deucher ++ * ++ */ ++ ++/* ++ * avivo output handling functions. ++ */ ++#ifdef HAVE_CONFIG_H ++#include "config.h" ++#endif ++/* DPMS */ ++#define DPMS_SERVER ++#include ++#include ++ ++#include "radeon.h" ++#include "radeon_reg.h" ++#include "radeon_macros.h" ++#include "radeon_atombios.h" ++ ++static int ++atombios_output_dac1_setup(xf86OutputPtr output, DisplayModePtr mode) ++{ ++ RADEONOutputPrivatePtr radeon_output = output->driver_private; ++ RADEONInfoPtr info = RADEONPTR(output->scrn); ++ DAC_ENCODER_CONTROL_PS_ALLOCATION disp_data; ++ AtomBiosArgRec data; ++ unsigned char *space; ++ ++ disp_data.ucAction = 1; ++ ++ if (radeon_output->MonType == MT_CRT) ++ disp_data.ucDacStandard = ATOM_DAC1_PS2; ++ else if (radeon_output->MonType == MT_CV) ++ disp_data.ucDacStandard = ATOM_DAC1_CV; ++ else if (OUTPUT_IS_TV) { ++ switch (radeon_output->tvStd) { ++ case TV_STD_NTSC: ++ case TV_STD_NTSC_J: ++ case TV_STD_PAL_60: ++ disp_data.ucDacStandard = ATOM_DAC1_NTSC; ++ break; ++ case TV_STD_PAL: ++ case TV_STD_PAL_M: ++ case TV_STD_SCART_PAL: ++ case TV_STD_SECAM: ++ case TV_STD_PAL_CN: ++ disp_data.ucDacStandard = ATOM_DAC1_PAL; ++ break; ++ default: ++ disp_data.ucDacStandard = ATOM_DAC1_NTSC; ++ break; ++ } ++ } ++ ++ disp_data.usPixelClock = mode->Clock / 10; ++ data.exec.index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl); ++ data.exec.dataSpace = (void *)&space; ++ data.exec.pspace = &disp_data; ++ ++ if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) { ++ ErrorF("Output DAC1 setup success\n"); ++ return ATOM_SUCCESS; ++ } ++ ++ ErrorF("Output DAC1 setup failed\n"); ++ return ATOM_NOT_IMPLEMENTED; ++ ++} ++ ++static int ++atombios_output_dac2_setup(xf86OutputPtr output, DisplayModePtr mode) ++{ ++ RADEONOutputPrivatePtr radeon_output = output->driver_private; ++ RADEONInfoPtr info = RADEONPTR(output->scrn); ++ DAC_ENCODER_CONTROL_PS_ALLOCATION disp_data; ++ AtomBiosArgRec data; ++ unsigned char *space; ++ ++ disp_data.ucAction = 1; ++ ++ if (radeon_output->MonType == MT_CRT) ++ disp_data.ucDacStandard = ATOM_DAC2_PS2; ++ else if (radeon_output->MonType == MT_CV) ++ disp_data.ucDacStandard = ATOM_DAC2_CV; ++ else if (OUTPUT_IS_TV) { ++ switch (radeon_output->tvStd) { ++ case TV_STD_NTSC: ++ case TV_STD_NTSC_J: ++ case TV_STD_PAL_60: ++ disp_data.ucDacStandard = ATOM_DAC2_NTSC; ++ break; ++ case TV_STD_PAL: ++ case TV_STD_PAL_M: ++ case TV_STD_SCART_PAL: ++ case TV_STD_SECAM: ++ case TV_STD_PAL_CN: ++ disp_data.ucDacStandard = ATOM_DAC2_PAL; ++ break; ++ default: ++ disp_data.ucDacStandard = ATOM_DAC2_NTSC; ++ break; ++ } ++ } ++ ++ disp_data.usPixelClock = mode->Clock / 10; ++ data.exec.index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl); ++ data.exec.dataSpace = (void *)&space; ++ data.exec.pspace = &disp_data; ++ ++ if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) { ++ ErrorF("Output DAC2 setup success\n"); ++ return ATOM_SUCCESS; ++ } ++ ++ ErrorF("Output DAC2 setup failed\n"); ++ return ATOM_NOT_IMPLEMENTED; ++ ++} ++ ++static int ++atombios_output_tv1_setup(xf86OutputPtr output, DisplayModePtr mode) ++{ ++ RADEONOutputPrivatePtr radeon_output = output->driver_private; ++ RADEONInfoPtr info = RADEONPTR(output->scrn); ++ TV_ENCODER_CONTROL_PS_ALLOCATION disp_data; ++ AtomBiosArgRec data; ++ unsigned char *space; ++ ++ disp_data.sTVEncoder.ucAction = 1; ++ ++ if (radeon_output->MonType == MT_CV) ++ disp_data.sTVEncoder.ucTvStandard = ATOM_TV_CV; ++ else { ++ switch (radeon_output->tvStd) { ++ case TV_STD_NTSC: ++ disp_data.sTVEncoder.ucTvStandard = ATOM_TV_NTSC; ++ break; ++ case TV_STD_PAL: ++ disp_data.sTVEncoder.ucTvStandard = ATOM_TV_PAL; ++ break; ++ case TV_STD_PAL_M: ++ disp_data.sTVEncoder.ucTvStandard = ATOM_TV_PALM; ++ break; ++ case TV_STD_PAL_60: ++ disp_data.sTVEncoder.ucTvStandard = ATOM_TV_PAL60; ++ break; ++ case TV_STD_NTSC_J: ++ disp_data.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ; ++ break; ++ case TV_STD_SCART_PAL: ++ disp_data.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */ ++ break; ++ case TV_STD_SECAM: ++ disp_data.sTVEncoder.ucTvStandard = ATOM_TV_SECAM; ++ break; ++ case TV_STD_PAL_CN: ++ disp_data.sTVEncoder.ucTvStandard = ATOM_TV_PALCN; ++ break; ++ default: ++ disp_data.sTVEncoder.ucTvStandard = ATOM_TV_NTSC; ++ break; ++ } ++ } ++ ++ disp_data.sTVEncoder.usPixelClock = mode->Clock / 10; ++ data.exec.index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl); ++ data.exec.dataSpace = (void *)&space; ++ data.exec.pspace = &disp_data; ++ ++ if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) { ++ ErrorF("Output TV1 setup success\n"); ++ return ATOM_SUCCESS; ++ } ++ ++ ErrorF("Output TV1 setup failed\n"); ++ return ATOM_NOT_IMPLEMENTED; ++ ++} ++ ++int ++atombios_external_tmds_setup(xf86OutputPtr output, DisplayModePtr mode) ++{ ++ RADEONInfoPtr info = RADEONPTR(output->scrn); ++ ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION disp_data; ++ AtomBiosArgRec data; ++ unsigned char *space; ++ ++ disp_data.sXTmdsEncoder.ucEnable = 1; ++ ++ if (mode->Clock > 165000) ++ disp_data.sXTmdsEncoder.ucMisc = 1; ++ else ++ disp_data.sXTmdsEncoder.ucMisc = 0; ++ ++ if (!info->dac6bits) ++ disp_data.sXTmdsEncoder.ucMisc |= (1 << 1); ++ ++ data.exec.index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl); ++ data.exec.dataSpace = (void *)&space; ++ data.exec.pspace = &disp_data; ++ ++ if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) { ++ ErrorF("External TMDS setup success\n"); ++ return ATOM_SUCCESS; ++ } ++ ++ ErrorF("External TMDS setup failed\n"); ++ return ATOM_NOT_IMPLEMENTED; ++} ++ ++static int ++atombios_output_tmds1_setup(xf86OutputPtr output, DisplayModePtr mode) ++{ ++ RADEONInfoPtr info = RADEONPTR(output->scrn); ++ TMDS1_ENCODER_CONTROL_PS_ALLOCATION disp_data; ++ AtomBiosArgRec data; ++ unsigned char *space; ++ ++ disp_data.ucAction = 1; ++ if (mode->Clock > 165000) ++ disp_data.ucMisc = 1; ++ else ++ disp_data.ucMisc = 0; ++ disp_data.usPixelClock = mode->Clock / 10; ++ data.exec.index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl); ++ data.exec.dataSpace = (void *)&space; ++ data.exec.pspace = &disp_data; ++ ++ if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) { ++ ErrorF("Output TMDS1 setup success\n"); ++ return ATOM_SUCCESS; ++ } ++ ++ ErrorF("Output TMDS1 setup failed\n"); ++ return ATOM_NOT_IMPLEMENTED; ++ ++} ++ ++static int ++atombios_output_tmds2_setup(xf86OutputPtr output, DisplayModePtr mode) ++{ ++ RADEONInfoPtr info = RADEONPTR(output->scrn); ++ TMDS2_ENCODER_CONTROL_PS_ALLOCATION disp_data; ++ AtomBiosArgRec data; ++ unsigned char *space; ++ ++ disp_data.ucAction = 1; ++ if (mode->Clock > 165000) ++ disp_data.ucMisc = 1; ++ else ++ disp_data.ucMisc = 0; ++ disp_data.usPixelClock = mode->Clock / 10; ++ data.exec.index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl); ++ data.exec.dataSpace = (void *)&space; ++ data.exec.pspace = &disp_data; ++ ++ if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) { ++ ErrorF("Output TMDS2 setup success\n"); ++ return ATOM_SUCCESS; ++ } ++ ++ ErrorF("Output TMDS2 setup failed\n"); ++ return ATOM_NOT_IMPLEMENTED; ++} ++ ++static int ++atombios_output_lvds_setup(xf86OutputPtr output, DisplayModePtr mode) ++{ ++ RADEONInfoPtr info = RADEONPTR(output->scrn); ++ LVDS_ENCODER_CONTROL_PS_ALLOCATION disp_data; ++ AtomBiosArgRec data; ++ unsigned char *space; ++ ++ disp_data.ucAction = 1; ++ if (mode->Clock > 165000) ++ disp_data.ucMisc = 1; ++ else ++ disp_data.ucMisc = 0; ++ disp_data.usPixelClock = mode->Clock / 10; ++ data.exec.index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl); ++ data.exec.dataSpace = (void *)&space; ++ data.exec.pspace = &disp_data; ++ ++ if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) { ++ ErrorF("Output LVDS setup success\n"); ++ return ATOM_SUCCESS; ++ } ++ ++ ErrorF("Output LVDS setup failed\n"); ++ return ATOM_NOT_IMPLEMENTED; ++} ++ ++static AtomBiosResult ++atombios_display_device_control(atomBiosHandlePtr atomBIOS, int device, Bool state) ++{ ++ DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION disp_data; ++ AtomBiosArgRec data; ++ unsigned char *space; ++ ++ disp_data.ucAction = state; ++ data.exec.index = device; ++ data.exec.dataSpace = (void *)&space; ++ data.exec.pspace = &disp_data; ++ ++ if (RHDAtomBiosFunc(atomBIOS->scrnIndex, atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) { ++ ErrorF("Output %d %s success\n", device, state? "enable":"disable"); ++ return ATOM_SUCCESS; ++ } ++ ++ ErrorF("Output %d %s failed\n", device, state? "enable":"disable"); ++ return ATOM_NOT_IMPLEMENTED; ++} ++ ++static void ++atombios_device_dpms(xf86OutputPtr output, int device, int mode) ++{ ++ RADEONInfoPtr info = RADEONPTR(output->scrn); ++ int index; ++ ++ switch (device) { ++ case ATOM_DEVICE_CRT1_SUPPORT: ++ index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl); ++ break; ++ case ATOM_DEVICE_CRT2_SUPPORT: ++ index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl); ++ break; ++ case ATOM_DEVICE_DFP1_SUPPORT: ++ index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl); ++ break; ++ case ATOM_DEVICE_DFP2_SUPPORT: ++ index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl); ++ break; ++ case ATOM_DEVICE_DFP3_SUPPORT: ++ index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl); ++ break; ++ case ATOM_DEVICE_LCD1_SUPPORT: ++ index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); ++ break; ++ case ATOM_DEVICE_TV1_SUPPORT: ++ index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); ++ break; ++ case ATOM_DEVICE_CV_SUPPORT: ++ index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); ++ break; ++ default: ++ return; ++ } ++ ++ switch (mode) { ++ case DPMSModeOn: ++ atombios_display_device_control(info->atomBIOS, index, ATOM_ENABLE); ++ break; ++ case DPMSModeStandby: ++ case DPMSModeSuspend: ++ case DPMSModeOff: ++ atombios_display_device_control(info->atomBIOS, index, ATOM_DISABLE); ++ break; ++ } ++} ++ ++void ++atombios_output_dpms(xf86OutputPtr output, int mode) ++{ ++ RADEONOutputPrivatePtr radeon_output = output->driver_private; ++ RADEONInfoPtr info = RADEONPTR(output->scrn); ++ unsigned char *RADEONMMIO = info->MMIO; ++ int tmp, count; ++ ++#if 1 ++ /* try to grab card lock or at least somethings that looks like a lock ++ * if it fails more than 5 times with 1000ms wait btw each try than we ++ * assume we can process. ++ */ ++ count = 0; ++ tmp = INREG(0x0028); ++ while((tmp & 0x100) && (count < 5)) { ++ tmp = INREG(0x0028); ++ count++; ++ usleep(1000); ++ } ++ if (count >= 5) { ++ xf86DrvMsg(output->scrn->scrnIndex, X_INFO, ++ "%s (WARNING) failed to grab card lock process anyway.\n", ++ __func__); ++ } ++ OUTREG(0x0028, tmp | 0x100); ++#endif ++ ++ ErrorF("AGD: output dpms %d\n", mode); ++ ++ if (radeon_output->MonType == MT_LCD) { ++ if (radeon_output->devices & ATOM_DEVICE_LCD1_SUPPORT) ++ atombios_device_dpms(output, ATOM_DEVICE_LCD1_SUPPORT, mode); ++ } else if (radeon_output->MonType == MT_DFP) { ++ ErrorF("AGD: tmds dpms\n"); ++ if (radeon_output->devices & ATOM_DEVICE_DFP1_SUPPORT) ++ atombios_device_dpms(output, ATOM_DEVICE_DFP1_SUPPORT, mode); ++ else if (radeon_output->devices & ATOM_DEVICE_DFP2_SUPPORT) ++ atombios_device_dpms(output, ATOM_DEVICE_DFP2_SUPPORT, mode); ++ else if (radeon_output->devices & ATOM_DEVICE_DFP3_SUPPORT) ++ atombios_device_dpms(output, ATOM_DEVICE_DFP3_SUPPORT, mode); ++ } else if (radeon_output->MonType == MT_CRT) { ++ ErrorF("AGD: dac dpms\n"); ++ if (radeon_output->devices & ATOM_DEVICE_CRT1_SUPPORT) ++ atombios_device_dpms(output, ATOM_DEVICE_CRT1_SUPPORT, mode); ++ else if (radeon_output->devices & ATOM_DEVICE_CRT2_SUPPORT) ++ atombios_device_dpms(output, ATOM_DEVICE_CRT2_SUPPORT, mode); ++ } ++ ++#if 1 ++ /* release card lock */ ++ tmp = INREG(0x0028); ++ OUTREG(0x0028, tmp & (~0x100)); ++#endif ++} ++ ++static void ++atombios_set_output_crtc_source(xf86OutputPtr output) ++{ ++ RADEONOutputPrivatePtr radeon_output = output->driver_private; ++ RADEONCrtcPrivatePtr radeon_crtc = output->crtc->driver_private; ++ RADEONInfoPtr info = RADEONPTR(output->scrn); ++ AtomBiosArgRec data; ++ unsigned char *space; ++ SELECT_CRTC_SOURCE_PS_ALLOCATION crtc_src_param; ++ int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source); ++ int major, minor; ++ ++ atombios_get_command_table_version(info->atomBIOS, index, &major, &minor); ++ ++ ErrorF("select crtc source table is %d %d\n", major, minor); ++ ++ crtc_src_param.ucCRTC = radeon_crtc->crtc_id; ++ crtc_src_param.ucDevice = 0; ++ ++ switch(major) { ++ case 1: { ++ switch(minor) { ++ case 0: ++ case 1: ++ default: ++ if (radeon_output->MonType == MT_CRT) { ++ if (radeon_output->devices & ATOM_DEVICE_CRT1_SUPPORT) ++ crtc_src_param.ucDevice = ATOM_DEVICE_CRT1_INDEX; ++ else if (radeon_output->devices & ATOM_DEVICE_CRT2_SUPPORT) ++ crtc_src_param.ucDevice = ATOM_DEVICE_CRT2_INDEX; ++ } else if (radeon_output->MonType == MT_DFP) { ++ if (radeon_output->devices & ATOM_DEVICE_DFP1_SUPPORT) ++ crtc_src_param.ucDevice = ATOM_DEVICE_DFP1_INDEX; ++ else if (radeon_output->devices & ATOM_DEVICE_DFP2_SUPPORT) ++ crtc_src_param.ucDevice = ATOM_DEVICE_DFP2_INDEX; ++ else if (radeon_output->devices & ATOM_DEVICE_DFP3_SUPPORT) ++ crtc_src_param.ucDevice = ATOM_DEVICE_DFP3_INDEX; ++ } else if (radeon_output->MonType == MT_LCD) { ++ if (radeon_output->devices & ATOM_DEVICE_LCD1_SUPPORT) ++ crtc_src_param.ucDevice = ATOM_DEVICE_LCD1_INDEX; ++ } ++ break; ++ } ++ break; ++ } ++ default: ++ break; ++ } ++ ++ ErrorF("device sourced: 0x%x\n", crtc_src_param.ucDevice); ++ ++ data.exec.index = index; ++ data.exec.dataSpace = (void *)&space; ++ data.exec.pspace = &crtc_src_param; ++ ++ if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) { ++ ErrorF("Set CRTC %d Source success\n", radeon_crtc->crtc_id); ++ return; ++ } ++ ++ ErrorF("Set CRTC Source failed\n"); ++ return; ++} ++ ++void ++atombios_output_mode_set(xf86OutputPtr output, ++ DisplayModePtr mode, ++ DisplayModePtr adjusted_mode) ++{ ++ RADEONOutputPrivatePtr radeon_output = output->driver_private; ++ ++ atombios_set_output_crtc_source(output); ++ ++ if (radeon_output->MonType == MT_CRT) { ++ if (radeon_output->devices & ATOM_DEVICE_CRT1_SUPPORT) ++ atombios_output_dac1_setup(output, adjusted_mode); ++ else if (radeon_output->devices & ATOM_DEVICE_CRT2_SUPPORT) ++ atombios_output_dac2_setup(output, adjusted_mode); ++ } else if (radeon_output->MonType == MT_DFP) { ++ if (radeon_output->devices & ATOM_DEVICE_DFP1_SUPPORT) ++ atombios_output_tmds1_setup(output, adjusted_mode); ++ else if (radeon_output->devices & ATOM_DEVICE_DFP2_SUPPORT) ++ atombios_external_tmds_setup(output, adjusted_mode); ++ else if (radeon_output->devices & ATOM_DEVICE_DFP3_SUPPORT) ++ atombios_output_tmds2_setup(output, adjusted_mode); ++ } else if (radeon_output->MonType == MT_LCD) { ++ if (radeon_output->devices & ATOM_DEVICE_LCD1_SUPPORT) ++ atombios_output_lvds_setup(output, adjusted_mode); ++ } else if (OUTPUT_IS_TV || (radeon_output->MonType == MT_CV)) { ++ atombios_output_dac2_setup(output, adjusted_mode); ++ atombios_output_tv1_setup(output, adjusted_mode); ++ } ++ ++} ++ ++static AtomBiosResult ++atom_bios_dac_load_detect(atomBiosHandlePtr atomBIOS, xf86OutputPtr output) ++{ ++ RADEONOutputPrivatePtr radeon_output = output->driver_private; ++ DAC_LOAD_DETECTION_PS_ALLOCATION dac_data; ++ AtomBiosArgRec data; ++ unsigned char *space; ++ ++ if (radeon_output->devices & ATOM_DEVICE_CRT1_SUPPORT) { ++ dac_data.sDacload.usDeviceID = ATOM_DEVICE_CRT1_SUPPORT; ++ dac_data.sDacload.ucDacType = ATOM_DAC_A; ++ } else if (radeon_output->devices & ATOM_DEVICE_CRT2_SUPPORT) { ++ dac_data.sDacload.usDeviceID = ATOM_DEVICE_CRT2_SUPPORT; ++ dac_data.sDacload.ucDacType = ATOM_DAC_B; ++ } else if (radeon_output->devices & ATOM_DEVICE_CV_SUPPORT) { ++ dac_data.sDacload.usDeviceID = ATOM_DEVICE_CV_SUPPORT; ++ dac_data.sDacload.ucDacType = ATOM_DAC_B; ++ } else if (radeon_output->devices & ATOM_DEVICE_TV1_SUPPORT) { ++ dac_data.sDacload.usDeviceID = ATOM_DEVICE_TV1_SUPPORT; ++ dac_data.sDacload.ucDacType = ATOM_DAC_B; ++ } else { ++ ErrorF("invalid output device for dac detection\n"); ++ return ATOM_NOT_IMPLEMENTED; ++ } ++ ++ dac_data.sDacload.ucMisc = 0; ++ ++ data.exec.index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection); ++ data.exec.dataSpace = (void *)&space; ++ data.exec.pspace = &dac_data; ++ ++ if (RHDAtomBiosFunc(atomBIOS->scrnIndex, atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) { ++ ++ ErrorF("Dac detection success\n"); ++ return ATOM_SUCCESS ; ++ } ++ ++ ErrorF("DAC detection failed\n"); ++ return ATOM_NOT_IMPLEMENTED; ++} ++ ++RADEONMonitorType ++atombios_dac_detect(ScrnInfoPtr pScrn, xf86OutputPtr output) ++{ ++ RADEONInfoPtr info = RADEONPTR(pScrn); ++ unsigned char *RADEONMMIO = info->MMIO; ++ RADEONOutputPrivatePtr radeon_output = output->driver_private; ++ RADEONMonitorType MonType = MT_NONE; ++ AtomBiosResult ret; ++ uint32_t bios_0_scratch; ++ ++ ret = atom_bios_dac_load_detect(info->atomBIOS, output); ++ if (ret == ATOM_SUCCESS) { ++ bios_0_scratch = INREG(RADEON_BIOS_0_SCRATCH); ++ ErrorF("DAC connect %08X\n", (unsigned int)bios_0_scratch); ++ ++ if (radeon_output->devices & ATOM_DEVICE_CRT1_SUPPORT) { ++ if (bios_0_scratch & ATOM_S0_CRT1_MASK) ++ MonType = MT_CRT; ++ } else if (radeon_output->devices & ATOM_DEVICE_CRT2_SUPPORT) { ++ if (bios_0_scratch & ATOM_S0_CRT2_MASK) ++ MonType = MT_CRT; ++ } else if (radeon_output->devices & ATOM_DEVICE_CV_SUPPORT) { ++ if (bios_0_scratch & (ATOM_S0_CV_MASK | ATOM_S0_CV_MASK_A)) ++ MonType = MT_CV; ++ } else if (radeon_output->devices & ATOM_DEVICE_TV1_SUPPORT) { ++ if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A)) ++ MonType = MT_CTV; ++ else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A)) ++ MonType = MT_STV; ++ } ++ } ++ ++ return MonType; ++} ++ +diff --git a/src/pcidb/ati_pciids.csv b/src/pcidb/ati_pciids.csv +index f201cc4..a62e8a5 100644 +--- a/src/pcidb/ati_pciids.csv ++++ b/src/pcidb/ati_pciids.csv +@@ -216,5 +216,137 @@ + "0x5E4C","RV410_5E4C","RV410",,,,,,"ATI Radeon X700 SE (RV410) (PCIE)" + "0x5E4D","RV410_5E4D","RV410",,,,,,"ATI Radeon X700 (RV410) (PCIE)" + "0x5E4F","RV410_5E4F","RV410",,,,,,"ATI Radeon X700 SE (RV410) (PCIE)" ++"0x7100","R520_7100","R520",,,,,,"ATI Radeon X1800" ++"0x7101","R520_7101","R520",1,,,,,"ATI Mobility Radeon X1800 XT" ++"0x7102","R520_7102","R520",1,,,,,"ATI Mobility Radeon X1800" ++"0x7103","R520_7103","R520",1,,,,,"ATI Mobility FireGL V7200" ++"0x7104","R520_7104","R520",,,,,,"ATI FireGL V7200" ++"0x7105","R520_7105","R520",,,,,,"ATI FireGL V5300" ++"0x7106","R520_7106","R520",1,,,,,"ATI Mobility FireGL V7100" ++"0x7108","R520_7108","R520",,,,,,"ATI Radeon X1800" ++"0x7109","R520_7109","R520",,,,,,"ATI Radeon X1800" ++"0x710A","R520_710A","R520",,,,,,"ATI Radeon X1800" ++"0x710B","R520_710B","R520",,,,,,"ATI Radeon X1800" ++"0x710C","R520_710C","R520",,,,,,"ATI Radeon X1800" ++"0x710E","R520_710E","R520",,,,,,"ATI FireGL V7300" ++"0x710F","R520_710F","R520",,,,,,"ATI FireGL V7350" ++"0x7140","RV515_7140","RV515",,,,,,"ATI Radeon X1600" ++"0x7141","RV515_7141","RV515",,,,,,"ATI RV505" ++"0x7142","RV515_7142","RV515",,,,,,"ATI Radeon X1300/X1550" ++"0x7143","RV515_7143","RV515",,,,,,"ATI Radeon X1550" ++"0x7144","RV515_7144","RV515",1,,,,,"ATI M54-GL" ++"0x7145","RV515_7145","RV515",1,,,,,"ATI Mobility Radeon X1400" ++"0x7146","RV515_7146","RV515",,,,,,"ATI Radeon X1300/X1550" ++"0x7147","RV515_7147","RV515",,,,,,"ATI Radeon X1550 64-bit" ++"0x7149","RV515_7149","RV515",1,,,,,"ATI Mobility Radeon X1300" ++"0x714A","RV515_714A","RV515",1,,,,,"ATI Mobility Radeon X1300" ++"0x714B","RV515_714B","RV515",1,,,,,"ATI Mobility Radeon X1300" ++"0x714C","RV515_714C","RV515",1,,,,,"ATI Mobility Radeon X1300" ++"0x714D","RV515_714D","RV515",,,,,,"ATI Radeon X1300" ++"0x714E","RV515_714E","RV515",,,,,,"ATI Radeon X1300" ++"0x714F","RV515_714F","RV515",,,,,,"ATI RV505" ++"0x7151","RV515_7151","RV515",,,,,,"ATI RV505" ++"0x7152","RV515_7152","RV515",,,,,,"ATI FireGL V3300" ++"0x7153","RV515_7153","RV515",,,,,,"ATI FireGL V3350" ++"0x715E","RV515_715E","RV515",,,,,,"ATI Radeon X1300" ++"0x715F","RV515_715F","RV515",,,,,,"ATI Radeon X1550 64-bit" ++"0x7180","RV515_7180","RV515",,,,,,"ATI Radeon X1300/X1550" ++"0x7181","RV515_7181","RV515",,,,,,"ATI Radeon X1600" ++"0x7183","RV515_7183","RV515",,,,,,"ATI Radeon X1300/X1550" ++"0x7186","RV515_7186","RV515",1,,,,,"ATI Mobility Radeon X1450" ++"0x7187","RV515_7187","RV515",,,,,,"ATI Radeon X1300/X1550" ++"0x7188","RV515_7188","RV515",1,,,,,"ATI Mobility Radeon X2300" ++"0x718A","RV515_718A","RV515",1,,,,,"ATI Mobility Radeon X2300" ++"0x718B","RV515_718B","RV515",1,,,,,"ATI Mobility Radeon X1350" ++"0x718C","RV515_718C","RV515",1,,,,,"ATI Mobility Radeon X1350" ++"0x718D","RV515_718D","RV515",1,,,,,"ATI Mobility Radeon X1450" ++"0x718F","RV515_718F","RV515",,,,,,"ATI Radeon X1300" ++"0x7193","RV515_7193","RV515",,,,,,"ATI Radeon X1550" ++"0x7196","RV515_7196","RV515",1,,,,,"ATI Mobility Radeon X1350" ++"0x719B","RV515_719B","RV515",,,,,,"ATI FireMV 2250" ++"0x719F","RV515_719F","RV515",,,,,,"ATI Radeon X1550 64-bit" ++"0x71C0","RV530_71C0","RV530",,,,,,"ATI Radeon X1600" ++"0x71C1","RV530_71C1","RV530",,,,,,"ATI Radeon X1650" ++"0x71C2","RV530_71C2","RV530",,,,,,"ATI Radeon X1600" ++"0x71C3","RV530_71C3","RV530",,,,,,"ATI Radeon X1600" ++"0x71C4","RV530_71C4","RV530",1,,,,,"ATI Mobility FireGL V5200" ++"0x71C5","RV530_71C5","RV530",1,,,,,"ATI Mobility Radeon X1600" ++"0x71C6","RV530_71C6","RV530",,,,,,"ATI Radeon X1650" ++"0x71C7","RV530_71C7","RV530",,,,,,"ATI Radeon X1650" ++"0x71CD","RV530_71CD","RV530",,,,,,"ATI Radeon X1600" ++"0x71CE","RV530_71CE","RV530",,,,,,"ATI Radeon X1300 XT/X1600 Pro" ++"0x71D2","RV530_71D2","RV530",,,,,,"ATI FireGL V3400" ++"0x71D4","RV530_71D4","RV530",1,,,,,"ATI Mobility FireGL V5250" ++"0x71D5","RV530_71D5","RV530",1,,,,,"ATI Mobility Radeon X1700" ++"0x71D6","RV530_71D6","RV530",1,,,,,"ATI Mobility Radeon X1700 XT" ++"0x71DA","RV530_71DA","RV530",,,,,,"ATI FireGL V5200" ++"0x71DE","RV530_71DE","RV530",1,,,,,"ATI Mobility Radeon X1700" ++"0x7200","RV530_7200","RV530",,,,,,"ATI Radeon X2300HD" ++"0x7210","RV530_7210","RV530",1,,,,,"ATI Mobility Radeon HD 2300" ++"0x7211","RV530_7211","RV530",1,,,,,"ATI Mobility Radeon HD 2300" ++"0x7240","R580_7240","R580",,,,,,"ATI Radeon X1950" ++"0x7243","R580_7243","R580",,,,,,"ATI Radeon X1900" ++"0x7244","R580_7244","R580",,,,,,"ATI Radeon X1950" ++"0x7245","R580_7245","R580",,,,,,"ATI Radeon X1900" ++"0x7246","R580_7246","R580",,,,,,"ATI Radeon X1900" ++"0x7247","R580_7247","R580",,,,,,"ATI Radeon X1900" ++"0x7248","R580_7248","R580",,,,,,"ATI Radeon X1900" ++"0x7249","R580_7249","R580",,,,,,"ATI Radeon X1900" ++"0x724A","R580_724A","R580",,,,,,"ATI Radeon X1900" ++"0x724B","R580_724B","R580",,,,,,"ATI Radeon X1900" ++"0x724C","R580_724C","R580",,,,,,"ATI Radeon X1900" ++"0x724D","R580_724D","R580",,,,,,"ATI Radeon X1900" ++"0x724E","R580_724E","R580",,,,,,"ATI AMD Stream Processor" ++"0x724F","R580_724F","R580",,,,,,"ATI Radeon X1900" ++"0x7280","RV570_7280","RV570",,,,,,"ATI Radeon X1950" ++"0x7281","RV560_7281","RV560",,,,,,"ATI RV560" ++"0x7283","RV560_7283","RV560",,,,,,"ATI RV560" ++"0x7284","R580_7284","R580",1,,,,,"ATI Mobility Radeon X1900" ++"0x7287","RV560_7287","RV560",,,,,,"ATI RV560" ++"0x7288","RV570_7288","RV570",,,,,,"ATI Radeon X1950 GT" ++"0x7289","RV570_7289","RV570",,,,,,"ATI RV570" ++"0x728B","RV570_728B","RV570",,,,,,"ATI RV570" ++"0x728C","RV570_728C","RV570",,,,,,"ATI ATI FireGL V7400" ++"0x7290","RV560_7290","RV560",,,,,,"ATI RV560" ++"0x7291","RV560_7291","RV560",,,,,,"ATI Radeon X1650" ++"0x7293","RV560_7293","RV560",,,,,,"ATI Radeon X1650" ++"0x7297","RV560_7297","RV560",,,,,,"ATI RV560" + "0x7834","RS350_7834","RS300",,1,,,,"ATI Radeon 9100 PRO IGP 7834" + "0x7835","RS350_7835","RS300",1,1,,,,"ATI Radeon Mobility 9200 IGP 7835" ++"0x791E","RS690_791E","RS690",,1,,,,"ATI Radeon X1200" ++"0x791F","RS690_791F","RS690",,1,,,,"ATI Radeon X1200" ++"0x796C","RS740_796C","RS740",,1,,,,"ATI RS740" ++"0x796D","RS740_796D","RS740",,1,,,,"ATI RS740M" ++"0x796E","RS740_796E","RS740",,1,,,,"ATI RS740" ++"0x796F","RS740_796F","RS740",,1,,,,"ATI RS740M" ++"0x9400","R600_9400","R600",,,,,,"ATI Radeon HD 2900 XT" ++"0x9401","R600_9401","R600",,,,,,"ATI Radeon HD 2900 XT" ++"0x9402","R600_9402","R600",,,,,,"ATI Radeon HD 2900 XT" ++"0x9403","R600_9403","R600",,,,,,"ATI Radeon HD 2900 Pro" ++"0x9405","R600_9405","R600",,,,,,"ATI Radeon HD 2900 GT" ++"0x940A","R600_940A","R600",,,,,,"ATI FireGL V8650" ++"0x940B","R600_940B","R600",,,,,,"ATI FireGL V8600" ++"0x940F","R600_940F","R600",,,,,,"ATI FireGL V7600" ++"0x94C0","RV610_94C0","RV610",,,,,,"ATI RV610" ++"0x94C1","RV610_94C1","RV610",,,,,,"ATI Radeon HD 2400 XT" ++"0x94C3","RV610_94C3","RV610",,,,,,"ATI Radeon HD 2400 Pro" ++"0x94C4","RV610_94C4","RV610",,,,,,"ATI ATI Radeon HD 2400 PRO AGP" ++"0x94C5","RV610_94C5","RV610",,,,,,"ATI FireGL V4000" ++"0x94C6","RV610_94C6","RV610",,,,,,"ATI RV610" ++"0x94C7","RV610_94C7","RV610",,,,,,"ATI ATI Radeon HD 2350" ++"0x94C8","RV610_94C8","RV610",1,,,,,"ATI Mobility Radeon HD 2400 XT" ++"0x94C9","RV610_94C9","RV610",1,,,,,"ATI Mobility Radeon HD 2400" ++"0x94CB","RV610_94CB","RV610",1,,,,,"ATI ATI RADEON E2400" ++"0x94CC","RV610_94CC","RV610",,,,,,"ATI RV610" ++"0x9580","RV630_9580","RV630",,,,,,"ATI RV630" ++"0x9581","RV630_9581","RV630",1,,,,,"ATI Mobility Radeon HD 2600" ++"0x9583","RV630_9583","RV630",1,,,,,"ATI Mobility Radeon HD 2600 XT" ++"0x9586","RV630_9586","RV630",,,,,,"ATI ATI Radeon HD 2600 XT AGP" ++"0x9587","RV630_9587","RV630",,,,,,"ATI ATI Radeon HD 2600 Pro AGP" ++"0x9588","RV630_9588","RV630",,,,,,"ATI Radeon HD 2600 XT" ++"0x9589","RV630_9589","RV630",,,,,,"ATI Radeon HD 2600 Pro" ++"0x958A","RV630_958A","RV630",,,,,,"ATI Gemini RV630" ++"0x958B","RV630_958B","RV630",1,,,,,"ATI Gemini ATI Mobility Radeon HD 2600 XT" ++"0x958C","RV630_958C","RV630",,,,,,"ATI FireGL V5600" ++"0x958D","RV630_958D","RV630",,,,,,"ATI FireGL V3600" ++"0x958E","RV630_958E","RV630",,,,,,"ATI ATI Radeon HD 2600 LE" +diff --git a/src/radeon.h b/src/radeon.h +index 03db360..7d57ca5 100644 +--- a/src/radeon.h ++++ b/src/radeon.h +@@ -200,189 +200,26 @@ typedef struct { + CARD16 rr4_offset; + } RADEONBIOSInitTable; + +-typedef struct { +- /* Common registers */ +- CARD32 ovr_clr; +- CARD32 ovr_wid_left_right; +- CARD32 ovr_wid_top_bottom; +- CARD32 ov0_scale_cntl; +- CARD32 mpp_tb_config; +- CARD32 mpp_gp_config; +- CARD32 subpic_cntl; +- CARD32 viph_control; +- CARD32 i2c_cntl_1; +- CARD32 gen_int_cntl; +- CARD32 cap0_trig_cntl; +- CARD32 cap1_trig_cntl; +- CARD32 bus_cntl; +- CARD32 bios_4_scratch; +- CARD32 bios_5_scratch; +- CARD32 bios_6_scratch; +- CARD32 surface_cntl; +- CARD32 surfaces[8][3]; +- CARD32 mc_agp_location; +- CARD32 mc_fb_location; +- CARD32 display_base_addr; +- CARD32 display2_base_addr; +- CARD32 ov0_base_addr; +- +- /* Other registers to save for VT switches */ +- CARD32 dp_datatype; +- CARD32 rbbm_soft_reset; +- CARD32 clock_cntl_index; +- CARD32 amcgpio_en_reg; +- CARD32 amcgpio_mask; +- +- /* CRTC registers */ +- CARD32 crtc_gen_cntl; +- CARD32 crtc_ext_cntl; +- CARD32 dac_cntl; +- CARD32 crtc_h_total_disp; +- CARD32 crtc_h_sync_strt_wid; +- CARD32 crtc_v_total_disp; +- CARD32 crtc_v_sync_strt_wid; +- CARD32 crtc_offset; +- CARD32 crtc_offset_cntl; +- CARD32 crtc_pitch; +- CARD32 disp_merge_cntl; +- CARD32 grph_buffer_cntl; +- CARD32 crtc_more_cntl; +- CARD32 crtc_tile_x0_y0; +- +- /* CRTC2 registers */ +- CARD32 crtc2_gen_cntl; +- CARD32 dac_macro_cntl; +- CARD32 dac2_cntl; +- CARD32 disp_output_cntl; +- CARD32 disp_tv_out_cntl; +- CARD32 disp_hw_debug; +- CARD32 disp2_merge_cntl; +- CARD32 grph2_buffer_cntl; +- CARD32 crtc2_h_total_disp; +- CARD32 crtc2_h_sync_strt_wid; +- CARD32 crtc2_v_total_disp; +- CARD32 crtc2_v_sync_strt_wid; +- CARD32 crtc2_offset; +- CARD32 crtc2_offset_cntl; +- CARD32 crtc2_pitch; +- CARD32 crtc2_tile_x0_y0; +- +- /* Flat panel registers */ +- CARD32 fp_crtc_h_total_disp; +- CARD32 fp_crtc_v_total_disp; +- CARD32 fp_gen_cntl; +- CARD32 fp2_gen_cntl; +- CARD32 fp_h_sync_strt_wid; +- CARD32 fp_h2_sync_strt_wid; +- CARD32 fp_horz_stretch; +- CARD32 fp_panel_cntl; +- CARD32 fp_v_sync_strt_wid; +- CARD32 fp_v2_sync_strt_wid; +- CARD32 fp_vert_stretch; +- CARD32 lvds_gen_cntl; +- CARD32 lvds_pll_cntl; +- CARD32 tmds_pll_cntl; +- CARD32 tmds_transmitter_cntl; +- +- /* Computed values for PLL */ +- CARD32 dot_clock_freq; +- CARD32 pll_output_freq; +- int feedback_div; +- int reference_div; +- int post_div; +- +- /* PLL registers */ +- unsigned ppll_ref_div; +- unsigned ppll_div_3; +- CARD32 htotal_cntl; +- CARD32 vclk_ecp_cntl; +- +- /* Computed values for PLL2 */ +- CARD32 dot_clock_freq_2; +- CARD32 pll_output_freq_2; +- int feedback_div_2; +- int reference_div_2; +- int post_div_2; +- +- /* PLL2 registers */ +- CARD32 p2pll_ref_div; +- CARD32 p2pll_div_0; +- CARD32 htotal_cntl2; +- CARD32 pixclks_cntl; +- +- /* Pallet */ +- Bool palette_valid; +- CARD32 palette[256]; +- CARD32 palette2[256]; +- +- CARD32 rs480_unk_e30; +- CARD32 rs480_unk_e34; +- CARD32 rs480_unk_e38; +- CARD32 rs480_unk_e3c; +- +- /* TV out registers */ +- CARD32 tv_master_cntl; +- CARD32 tv_htotal; +- CARD32 tv_hsize; +- CARD32 tv_hdisp; +- CARD32 tv_hstart; +- CARD32 tv_vtotal; +- CARD32 tv_vdisp; +- CARD32 tv_timing_cntl; +- CARD32 tv_vscaler_cntl1; +- CARD32 tv_vscaler_cntl2; +- CARD32 tv_sync_size; +- CARD32 tv_vrestart; +- CARD32 tv_hrestart; +- CARD32 tv_frestart; +- CARD32 tv_ftotal; +- CARD32 tv_clock_sel_cntl; +- CARD32 tv_clkout_cntl; +- CARD32 tv_data_delay_a; +- CARD32 tv_data_delay_b; +- CARD32 tv_dac_cntl; +- CARD32 tv_pll_cntl; +- CARD32 tv_pll_cntl1; +- CARD32 tv_pll_fine_cntl; +- CARD32 tv_modulator_cntl1; +- CARD32 tv_modulator_cntl2; +- CARD32 tv_frame_lock_cntl; +- CARD32 tv_pre_dac_mux_cntl; +- CARD32 tv_rgb_cntl; +- CARD32 tv_y_saw_tooth_cntl; +- CARD32 tv_y_rise_cntl; +- CARD32 tv_y_fall_cntl; +- CARD32 tv_uv_adr; +- CARD32 tv_upsamp_and_gain_cntl; +- CARD32 tv_gain_limit_settings; +- CARD32 tv_linear_gain_settings; +- CARD32 tv_crc_cntl; +- CARD32 tv_sync_cntl; +- CARD32 gpiopad_a; +- CARD32 pll_test_cntl; +- +- CARD16 h_code_timing[MAX_H_CODE_TIMING_LEN]; +- CARD16 v_code_timing[MAX_V_CODE_TIMING_LEN]; +- +-} RADEONSaveRec, *RADEONSavePtr; +- + #define RADEON_PLL_USE_BIOS_DIVS (1 << 0) + #define RADEON_PLL_NO_ODD_POST_DIV (1 << 1) + #define RADEON_PLL_USE_REF_DIV (1 << 2) ++#define RADEON_PLL_LEGACY (1 << 3) + + typedef struct { + CARD16 reference_freq; + CARD16 reference_div; +- CARD32 min_pll_freq; +- CARD32 max_pll_freq; ++ CARD32 pll_in_min; ++ CARD32 pll_in_max; ++ CARD32 pll_out_min; ++ CARD32 pll_out_max; + CARD16 xclk; + + CARD32 min_ref_div; + CARD32 max_ref_div; ++ CARD32 min_post_div; ++ CARD32 max_post_div; + CARD32 min_feedback_div; + CARD32 max_feedback_div; +- CARD32 pll_in_min; +- CARD32 pll_in_max; + CARD32 best_vco; + } RADEONPLLRec, *RADEONPLLPtr; + +@@ -415,6 +252,18 @@ typedef enum { + CHIP_FAMILY_R420, /* R420/R423/M18 */ + CHIP_FAMILY_RV410, /* RV410, M26 */ + CHIP_FAMILY_RS400, /* xpress 200, 200m (RS400/410/480) */ ++ CHIP_FAMILY_RV515, /* rv515 */ ++ CHIP_FAMILY_R520, /* r520 */ ++ CHIP_FAMILY_RV530, /* rv530 */ ++ CHIP_FAMILY_R580, /* r580 */ ++ CHIP_FAMILY_RV560, /* rv560 */ ++ CHIP_FAMILY_RV570, /* rv570 */ ++ CHIP_FAMILY_RS690, ++ CHIP_FAMILY_R600, /* r60 */ ++ CHIP_FAMILY_R630, ++ CHIP_FAMILY_RV610, ++ CHIP_FAMILY_RV630, ++ CHIP_FAMILY_RS740, + CHIP_FAMILY_LAST + } RADEONChipFamily; + +@@ -435,6 +284,8 @@ typedef enum { + (info->ChipFamily == CHIP_FAMILY_RV410) || \ + (info->ChipFamily == CHIP_FAMILY_RS400)) + ++#define IS_AVIVO_VARIANT ((info->ChipFamily >= CHIP_FAMILY_RV515)) ++ + /* + * Errata workarounds + */ +@@ -469,6 +320,8 @@ typedef enum { + CARD_PCIE + } RADEONCardType; + ++typedef struct _atomBiosHandle *atomBiosHandlePtr; ++ + typedef struct { + CARD32 pci_device_id; + RADEONChipFamily chip_family; +@@ -494,6 +347,7 @@ typedef struct { + CARD32 gartLocation; + CARD32 mc_fb_location; + CARD32 mc_agp_location; ++ CARD32 mc_agp_location_hi; + + void *MMIO; /* Map of MMIO region */ + void *FB; /* Map of frame buffer */ +@@ -536,8 +390,8 @@ typedef struct { + Bool IsDDR; + int DispPriority; + +- RADEONSaveRec SavedReg; /* Original (text) mode */ +- RADEONSaveRec ModeReg; /* Current mode */ ++ RADEONSavePtr SavedReg; /* Original (text) mode */ ++ RADEONSavePtr ModeReg; /* Current mode */ + Bool (*CloseScreen)(int, ScreenPtr); + + void (*BlockHandler)(int, pointer, pointer, pointer); +@@ -850,6 +704,10 @@ typedef struct { + #endif + RADEONExtTMDSChip ext_tmds_chip; + ++ atomBiosHandlePtr atomBIOS; ++ unsigned long FbFreeStart, FbFreeSize; ++ unsigned char* BIOSCopy; ++ + /* output enable masks for outputs shared across connectors */ + int output_crt1; + int output_crt2; +@@ -861,6 +719,13 @@ typedef struct { + Rotation rotation; + void (*PointerMoved)(int, int, int); + CreateScreenResourcesProcPtr CreateScreenResources; ++ ++ ++ Bool IsSecondary; ++ Bool IsPrimary; ++ ++ Bool r600_shadow_fb; ++ void *fb_shadow; + } RADEONInfoRec, *RADEONInfoPtr; + + #define RADEONWaitForFifo(pScrn, entries) \ +@@ -888,6 +753,9 @@ extern void RADEONEngineRestore(ScrnInfoPtr pScrn); + extern unsigned RADEONINPLL(ScrnInfoPtr pScrn, int addr); + extern void RADEONOUTPLL(ScrnInfoPtr pScrn, int addr, CARD32 data); + ++extern unsigned RADEONINMC(ScrnInfoPtr pScrn, int addr); ++extern void RADEONOUTMC(ScrnInfoPtr pScrn, int addr, CARD32 data); ++ + extern void RADEONWaitForVerticalSync(ScrnInfoPtr pScrn); + extern void RADEONWaitForVerticalSync2(ScrnInfoPtr pScrn); + +@@ -981,7 +849,7 @@ extern void RADEONBlank(ScrnInfoPtr pScrn); + extern void RADEONDisplayPowerManagementSet(ScrnInfoPtr pScrn, + int PowerManagementMode, + int flags); +-extern Bool RADEONAllocateControllers(ScrnInfoPtr pScrn); ++extern Bool RADEONAllocateControllers(ScrnInfoPtr pScrn, int mask); + extern Bool RADEONAllocateConnectors(ScrnInfoPtr pScrn); + extern int RADEONValidateMergeModes(ScrnInfoPtr pScrn); + extern int RADEONValidateDDCModes(ScrnInfoPtr pScrn1, char **ppModeName, +diff --git a/src/radeon_accel.c b/src/radeon_accel.c +index ed7d1e9..5bf03f5 100644 +--- a/src/radeon_accel.c ++++ b/src/radeon_accel.c +@@ -250,7 +250,7 @@ void RADEONEngineReset(ScrnInfoPtr pScrn) + host_path_cntl = INREG(RADEON_HOST_PATH_CNTL); + rbbm_soft_reset = INREG(RADEON_RBBM_SOFT_RESET); + +- if (IS_R300_VARIANT) { ++ if (IS_R300_VARIANT || IS_AVIVO_VARIANT) { + CARD32 tmp; + + OUTREG(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset | +@@ -284,7 +284,7 @@ void RADEONEngineReset(ScrnInfoPtr pScrn) + INREG(RADEON_HOST_PATH_CNTL); + OUTREG(RADEON_HOST_PATH_CNTL, host_path_cntl); + +- if (!IS_R300_VARIANT) ++ if (!IS_R300_VARIANT && !IS_AVIVO_VARIANT) + OUTREG(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset); + + OUTREG(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index); +@@ -322,7 +322,7 @@ void RADEONEngineRestore(ScrnInfoPtr pScrn) + #endif + + /* Restore SURFACE_CNTL */ +- OUTREG(RADEON_SURFACE_CNTL, info->ModeReg.surface_cntl); ++ OUTREG(RADEON_SURFACE_CNTL, info->ModeReg->surface_cntl); + + RADEONWaitForFifo(pScrn, 1); + OUTREG(RADEON_DEFAULT_SC_BOTTOM_RIGHT, (RADEON_DEFAULT_SC_RIGHT_MAX +@@ -853,6 +853,9 @@ Bool RADEONAccelInit(ScreenPtr pScreen) + ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; + RADEONInfoPtr info = RADEONPTR(pScrn); + ++ if (info->ChipFamily >= CHIP_FAMILY_R600) ++ return FALSE; ++ + #ifdef USE_EXA + if (info->useEXA) { + # ifdef XF86DRI +diff --git a/src/radeon_accelfuncs.c b/src/radeon_accelfuncs.c +index 212131f..6fbbc13 100644 +--- a/src/radeon_accelfuncs.c ++++ b/src/radeon_accelfuncs.c +@@ -1309,7 +1309,7 @@ FUNC_NAME(RADEONAccelInit)(ScreenPtr pScreen, XAAInfoRecPtr a) + a->CPUToScreenTextureFormats = RADEONTextureFormats; + a->CPUToScreenTextureDstFormats = RADEONDstFormats; + +- if (IS_R300_VARIANT) { ++ if (IS_R300_VARIANT || IS_AVIVO_VARIANT) { + xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Render acceleration " + "unsupported on Radeon 9500/9700 and newer.\n"); + } else if ((info->ChipFamily == CHIP_FAMILY_RV250) || +diff --git a/src/radeon_atombios.c b/src/radeon_atombios.c +new file mode 100644 +index 0000000..a04598d +--- /dev/null ++++ b/src/radeon_atombios.c +@@ -0,0 +1,2625 @@ ++/* ++ * Copyright 2007 Egbert Eich ++ * Copyright 2007 Luc Verhaegen ++ * Copyright 2007 Matthias Hopf ++ * Copyright 2007 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in ++ * all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++#ifdef HAVE_CONFIG_H ++# include "config.h" ++#endif ++#include "xf86.h" ++#include "xf86_OSproc.h" ++ ++#include "radeon.h" ++#include "radeon_atombios.h" ++#include "radeon_atomwrapper.h" ++#include "radeon_probe.h" ++#include "radeon_macros.h" ++ ++#include "xorg-server.h" ++#if XSERVER_LIBPCIACCESS ++#warning pciaccess defined ++#endif ++ ++/* only for testing now */ ++#include "xf86DDC.h" ++ ++typedef AtomBiosResult (*AtomBiosRequestFunc)(atomBiosHandlePtr handle, ++ AtomBiosRequestID unused, AtomBiosArgPtr data); ++typedef struct rhdConnectorInfo *rhdConnectorInfoPtr; ++ ++static AtomBiosResult rhdAtomInit(atomBiosHandlePtr unused1, ++ AtomBiosRequestID unused2, AtomBiosArgPtr data); ++static AtomBiosResult rhdAtomTearDown(atomBiosHandlePtr handle, ++ AtomBiosRequestID unused1, AtomBiosArgPtr unused2); ++static AtomBiosResult rhdAtomVramInfoQuery(atomBiosHandlePtr handle, ++ AtomBiosRequestID func, AtomBiosArgPtr data); ++static AtomBiosResult rhdAtomTmdsInfoQuery(atomBiosHandlePtr handle, ++ AtomBiosRequestID func, AtomBiosArgPtr data); ++static AtomBiosResult rhdAtomAllocateFbScratch(atomBiosHandlePtr handle, ++ AtomBiosRequestID func, AtomBiosArgPtr data); ++static AtomBiosResult rhdAtomLvdsGetTimings(atomBiosHandlePtr handle, ++ AtomBiosRequestID unused, AtomBiosArgPtr data); ++static AtomBiosResult rhdAtomLvdsInfoQuery(atomBiosHandlePtr handle, ++ AtomBiosRequestID func, AtomBiosArgPtr data); ++static AtomBiosResult rhdAtomGPIOI2CInfoQuery(atomBiosHandlePtr handle, ++ AtomBiosRequestID func, AtomBiosArgPtr data); ++static AtomBiosResult rhdAtomFirmwareInfoQuery(atomBiosHandlePtr handle, ++ AtomBiosRequestID func, AtomBiosArgPtr data); ++/*static AtomBiosResult rhdAtomConnectorInfo(atomBiosHandlePtr handle, ++ AtomBiosRequestID unused, AtomBiosArgPtr data);*/ ++# ifdef ATOM_BIOS_PARSER ++static AtomBiosResult rhdAtomExec(atomBiosHandlePtr handle, ++ AtomBiosRequestID unused, AtomBiosArgPtr data); ++# endif ++static AtomBiosResult ++rhdAtomCompassionateDataQuery(atomBiosHandlePtr handle, ++ AtomBiosRequestID func, AtomBiosArgPtr data); ++ ++ ++enum msgDataFormat { ++ MSG_FORMAT_NONE, ++ MSG_FORMAT_HEX, ++ MSG_FORMAT_DEC ++}; ++ ++struct atomBIOSRequests { ++ AtomBiosRequestID id; ++ AtomBiosRequestFunc request; ++ char *message; ++ enum msgDataFormat message_format; ++} AtomBiosRequestList [] = { ++ {ATOMBIOS_INIT, rhdAtomInit, ++ "AtomBIOS Init", MSG_FORMAT_NONE}, ++ {ATOMBIOS_TEARDOWN, rhdAtomTearDown, ++ "AtomBIOS Teardown", MSG_FORMAT_NONE}, ++# ifdef ATOM_BIOS_PARSER ++ {ATOMBIOS_EXEC, rhdAtomExec, ++ "AtomBIOS Exec", MSG_FORMAT_NONE}, ++#endif ++ {ATOMBIOS_ALLOCATE_FB_SCRATCH, rhdAtomAllocateFbScratch, ++ "AtomBIOS Set FB Space", MSG_FORMAT_NONE}, ++ /*{ATOMBIOS_GET_CONNECTORS, rhdAtomConnectorInfo, ++ "AtomBIOS Get Connectors", MSG_FORMAT_NONE},*/ ++ {ATOMBIOS_GET_PANEL_MODE, rhdAtomLvdsGetTimings, ++ "AtomBIOS Get Panel Mode", MSG_FORMAT_NONE}, ++ {ATOMBIOS_GET_PANEL_EDID, rhdAtomLvdsGetTimings, ++ "AtomBIOS Get Panel EDID", MSG_FORMAT_NONE}, ++ {GET_DEFAULT_ENGINE_CLOCK, rhdAtomFirmwareInfoQuery, ++ "Default Engine Clock", MSG_FORMAT_DEC}, ++ {GET_DEFAULT_MEMORY_CLOCK, rhdAtomFirmwareInfoQuery, ++ "Default Memory Clock", MSG_FORMAT_DEC}, ++ {GET_MAX_PIXEL_CLOCK_PLL_OUTPUT, rhdAtomFirmwareInfoQuery, ++ "Maximum Pixel ClockPLL Frequency Output", MSG_FORMAT_DEC}, ++ {GET_MIN_PIXEL_CLOCK_PLL_OUTPUT, rhdAtomFirmwareInfoQuery, ++ "Minimum Pixel ClockPLL Frequency Output", MSG_FORMAT_DEC}, ++ {GET_MAX_PIXEL_CLOCK_PLL_INPUT, rhdAtomFirmwareInfoQuery, ++ "Maximum Pixel ClockPLL Frequency Input", MSG_FORMAT_DEC}, ++ {GET_MIN_PIXEL_CLOCK_PLL_INPUT, rhdAtomFirmwareInfoQuery, ++ "Minimum Pixel ClockPLL Frequency Input", MSG_FORMAT_DEC}, ++ {GET_MAX_PIXEL_CLK, rhdAtomFirmwareInfoQuery, ++ "Maximum Pixel Clock", MSG_FORMAT_DEC}, ++ {GET_REF_CLOCK, rhdAtomFirmwareInfoQuery, ++ "Reference Clock", MSG_FORMAT_DEC}, ++ {GET_FW_FB_START, rhdAtomVramInfoQuery, ++ "Start of VRAM area used by Firmware", MSG_FORMAT_HEX}, ++ {GET_FW_FB_SIZE, rhdAtomVramInfoQuery, ++ "Framebuffer space used by Firmware (kb)", MSG_FORMAT_DEC}, ++ {ATOM_TMDS_FREQUENCY, rhdAtomTmdsInfoQuery, ++ "TMDS Frequency", MSG_FORMAT_DEC}, ++ {ATOM_TMDS_PLL_CHARGE_PUMP, rhdAtomTmdsInfoQuery, ++ "TMDS PLL ChargePump", MSG_FORMAT_DEC}, ++ {ATOM_TMDS_PLL_DUTY_CYCLE, rhdAtomTmdsInfoQuery, ++ "TMDS PLL DutyCycle", MSG_FORMAT_DEC}, ++ {ATOM_TMDS_PLL_VCO_GAIN, rhdAtomTmdsInfoQuery, ++ "TMDS PLL VCO Gain", MSG_FORMAT_DEC}, ++ {ATOM_TMDS_PLL_VOLTAGE_SWING, rhdAtomTmdsInfoQuery, ++ "TMDS PLL VoltageSwing", MSG_FORMAT_DEC}, ++ {ATOM_LVDS_SUPPORTED_REFRESH_RATE, rhdAtomLvdsInfoQuery, ++ "LVDS Supported Refresh Rate", MSG_FORMAT_DEC}, ++ {ATOM_LVDS_OFF_DELAY, rhdAtomLvdsInfoQuery, ++ "LVDS Off Delay", MSG_FORMAT_DEC}, ++ {ATOM_LVDS_SEQ_DIG_ONTO_DE, rhdAtomLvdsInfoQuery, ++ "LVDS SEQ Dig onto DE", MSG_FORMAT_DEC}, ++ {ATOM_LVDS_SEQ_DE_TO_BL, rhdAtomLvdsInfoQuery, ++ "LVDS SEQ DE to BL", MSG_FORMAT_DEC}, ++ {ATOM_LVDS_DITHER, rhdAtomLvdsInfoQuery, ++ "LVDS Ditherc", MSG_FORMAT_HEX}, ++ {ATOM_LVDS_DUALLINK, rhdAtomLvdsInfoQuery, ++ "LVDS Duallink", MSG_FORMAT_HEX}, ++ {ATOM_LVDS_GREYLVL, rhdAtomLvdsInfoQuery, ++ "LVDS Grey Level", MSG_FORMAT_HEX}, ++ {ATOM_LVDS_FPDI, rhdAtomLvdsInfoQuery, ++ "LVDS FPDI", MSG_FORMAT_HEX}, ++ {ATOM_LVDS_24BIT, rhdAtomLvdsInfoQuery, ++ "LVDS 24Bit", MSG_FORMAT_HEX}, ++ {ATOM_GPIO_I2C_CLK_MASK, rhdAtomGPIOI2CInfoQuery, ++ "GPIO_I2C_Clk_Mask", MSG_FORMAT_HEX}, ++ {ATOM_DAC1_BG_ADJ, rhdAtomCompassionateDataQuery, ++ "DAC1 BG Adjustment", MSG_FORMAT_HEX}, ++ {ATOM_DAC1_DAC_ADJ, rhdAtomCompassionateDataQuery, ++ "DAC1 DAC Adjustment", MSG_FORMAT_HEX}, ++ {ATOM_DAC1_FORCE, rhdAtomCompassionateDataQuery, ++ "DAC1 Force Data", MSG_FORMAT_HEX}, ++ {ATOM_DAC2_CRTC2_BG_ADJ, rhdAtomCompassionateDataQuery, ++ "DAC2_CRTC2 BG Adjustment", MSG_FORMAT_HEX}, ++ {ATOM_DAC2_CRTC2_DAC_ADJ, rhdAtomCompassionateDataQuery, ++ "DAC2_CRTC2 DAC Adjustment", MSG_FORMAT_HEX}, ++ {ATOM_DAC2_CRTC2_FORCE, rhdAtomCompassionateDataQuery, ++ "DAC2_CRTC2 Force", MSG_FORMAT_HEX}, ++ {ATOM_DAC2_CRTC2_MUX_REG_IND,rhdAtomCompassionateDataQuery, ++ "DAC2_CRTC2 Mux Register Index", MSG_FORMAT_HEX}, ++ {ATOM_DAC2_CRTC2_MUX_REG_INFO,rhdAtomCompassionateDataQuery, ++ "DAC2_CRTC2 Mux Register Info", MSG_FORMAT_HEX}, ++ {FUNC_END, NULL, ++ NULL, MSG_FORMAT_NONE} ++}; ++ ++enum { ++ legacyBIOSLocation = 0xC0000, ++ legacyBIOSMax = 0x10000 ++}; ++ ++#define DEBUGP(x) {x;} ++#define LOG_DEBUG 7 ++ ++# ifdef ATOM_BIOS_PARSER ++ ++# define LOG_CAIL LOG_DEBUG + 1 ++ ++static void ++RHDDebug(int scrnIndex, const char *format, ...) ++{ ++ va_list ap; ++ ++ va_start(ap, format); ++ xf86VDrvMsgVerb(scrnIndex, X_INFO, LOG_DEBUG, format, ap); ++ va_end(ap); ++} ++ ++static void ++RHDDebugCont(const char *format, ...) ++{ ++ va_list ap; ++ ++ va_start(ap, format); ++ xf86VDrvMsgVerb(-1, X_NONE, LOG_DEBUG, format, ap); ++ va_end(ap); ++} ++ ++static void ++CailDebug(int scrnIndex, const char *format, ...) ++{ ++ va_list ap; ++ ++ va_start(ap, format); ++ xf86VDrvMsgVerb(scrnIndex, X_INFO, LOG_CAIL, format, ap); ++ va_end(ap); ++} ++# define CAILFUNC(ptr) \ ++ CailDebug(((atomBiosHandlePtr)(ptr))->scrnIndex, "CAIL: %s\n", __func__) ++ ++# endif ++ ++static int ++rhdAtomAnalyzeCommonHdr(ATOM_COMMON_TABLE_HEADER *hdr) ++{ ++ if (hdr->usStructureSize == 0xaa55) ++ return FALSE; ++ ++ return TRUE; ++} ++ ++static int ++rhdAtomAnalyzeRomHdr(unsigned char *rombase, ++ ATOM_ROM_HEADER *hdr, ++ unsigned int *data_offset, ++ unsigned int *command_offset) ++{ ++ if (!rhdAtomAnalyzeCommonHdr(&hdr->sHeader)) { ++ return FALSE; ++ } ++ xf86DrvMsg(-1,X_NONE,"\tSubsystemVendorID: 0x%4.4x SubsystemID: 0x%4.4x\n", ++ hdr->usSubsystemVendorID,hdr->usSubsystemID); ++ xf86DrvMsg(-1,X_NONE,"\tIOBaseAddress: 0x%4.4x\n",hdr->usIoBaseAddress); ++ xf86DrvMsgVerb(-1,X_NONE,3,"\tFilename: %s\n",rombase + hdr->usConfigFilenameOffset); ++ xf86DrvMsgVerb(-1,X_NONE,3,"\tBIOS Bootup Message: %s\n", ++ rombase + hdr->usBIOS_BootupMessageOffset); ++ ++ *data_offset = hdr->usMasterDataTableOffset; ++ *command_offset = hdr->usMasterCommandTableOffset; ++ ++ return TRUE; ++} ++ ++static int ++rhdAtomAnalyzeRomDataTable(unsigned char *base, int offset, ++ void *ptr,unsigned short *size) ++{ ++ ATOM_COMMON_TABLE_HEADER *table = (ATOM_COMMON_TABLE_HEADER *) ++ (base + offset); ++ ++ if (!*size || !rhdAtomAnalyzeCommonHdr(table)) { ++ if (*size) *size -= 2; ++ *(void **)ptr = NULL; ++ return FALSE; ++ } ++ *size -= 2; ++ *(void **)ptr = (void *)(table); ++ return TRUE; ++} ++ ++Bool ++rhdAtomGetTableRevisionAndSize(ATOM_COMMON_TABLE_HEADER *hdr, ++ CARD8 *contentRev, ++ CARD8 *formatRev, ++ unsigned short *size) ++{ ++ if (!hdr) ++ return FALSE; ++ ++ if (contentRev) *contentRev = hdr->ucTableContentRevision; ++ if (formatRev) *formatRev = hdr->ucTableFormatRevision; ++ if (size) *size = (short)hdr->usStructureSize ++ - sizeof(ATOM_COMMON_TABLE_HEADER); ++ return TRUE; ++} ++ ++static Bool ++rhdAtomAnalyzeMasterDataTable(unsigned char *base, ++ ATOM_MASTER_DATA_TABLE *table, ++ atomDataTablesPtr data) ++{ ++ ATOM_MASTER_LIST_OF_DATA_TABLES *data_table = ++ &table->ListOfDataTables; ++ unsigned short size; ++ ++ if (!rhdAtomAnalyzeCommonHdr(&table->sHeader)) ++ return FALSE; ++ if (!rhdAtomGetTableRevisionAndSize(&table->sHeader,NULL,NULL, ++ &size)) ++ return FALSE; ++# define SET_DATA_TABLE(x) {\ ++ rhdAtomAnalyzeRomDataTable(base,data_table->x,(void *)(&(data->x)),&size); \ ++ } ++ ++# define SET_DATA_TABLE_VERS(x) {\ ++ rhdAtomAnalyzeRomDataTable(base,data_table->x,&(data->x.base),&size); \ ++ } ++ ++ SET_DATA_TABLE(UtilityPipeLine); ++ SET_DATA_TABLE(MultimediaCapabilityInfo); ++ SET_DATA_TABLE(MultimediaConfigInfo); ++ SET_DATA_TABLE(StandardVESA_Timing); ++ SET_DATA_TABLE_VERS(FirmwareInfo); ++ SET_DATA_TABLE(DAC_Info); ++ SET_DATA_TABLE_VERS(LVDS_Info); ++ SET_DATA_TABLE(TMDS_Info); ++ SET_DATA_TABLE(AnalogTV_Info); ++ SET_DATA_TABLE_VERS(SupportedDevicesInfo); ++ SET_DATA_TABLE(GPIO_I2C_Info); ++ SET_DATA_TABLE(VRAM_UsageByFirmware); ++ SET_DATA_TABLE(GPIO_Pin_LUT); ++ SET_DATA_TABLE(VESA_ToInternalModeLUT); ++ SET_DATA_TABLE_VERS(ComponentVideoInfo); ++ SET_DATA_TABLE(PowerPlayInfo); ++ SET_DATA_TABLE(CompassionateData); ++ SET_DATA_TABLE(SaveRestoreInfo); ++ SET_DATA_TABLE(PPLL_SS_Info); ++ SET_DATA_TABLE(OemInfo); ++ SET_DATA_TABLE(XTMDS_Info); ++ SET_DATA_TABLE(MclkSS_Info); ++ SET_DATA_TABLE(Object_Header); ++ SET_DATA_TABLE(IndirectIOAccess); ++ SET_DATA_TABLE(MC_InitParameter); ++ SET_DATA_TABLE(ASIC_VDDC_Info); ++ SET_DATA_TABLE(ASIC_InternalSS_Info); ++ SET_DATA_TABLE(TV_VideoMode); ++ SET_DATA_TABLE_VERS(VRAM_Info); ++ SET_DATA_TABLE(MemoryTrainingInfo); ++ SET_DATA_TABLE_VERS(IntegratedSystemInfo); ++ SET_DATA_TABLE(ASIC_ProfilingInfo); ++ SET_DATA_TABLE(VoltageObjectInfo); ++ SET_DATA_TABLE(PowerSourceInfo); ++# undef SET_DATA_TABLE ++ ++ return TRUE; ++} ++ ++static Bool ++rhdAtomGetDataTable(int scrnIndex, ++ unsigned char *base, ++ atomDataTables *atomDataPtr, ++ unsigned int *cmd_offset, ++ unsigned int BIOSImageSize) ++{ ++ unsigned int data_offset; ++ unsigned int atom_romhdr_off = *(unsigned short*) ++ (base + OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER); ++ ATOM_ROM_HEADER *atom_rom_hdr = ++ (ATOM_ROM_HEADER *)(base + atom_romhdr_off); ++ ++ //RHDFUNCI(scrnIndex); ++ ++ if (atom_romhdr_off + sizeof(ATOM_ROM_HEADER) > BIOSImageSize) { ++ xf86DrvMsg(scrnIndex,X_ERROR, ++ "%s: AtomROM header extends beyond BIOS image\n",__func__); ++ return FALSE; ++ } ++ ++ if (memcmp("ATOM",&atom_rom_hdr->uaFirmWareSignature,4)) { ++ xf86DrvMsg(scrnIndex,X_ERROR,"%s: No AtomBios signature found\n", ++ __func__); ++ return FALSE; ++ } ++ xf86DrvMsg(scrnIndex, X_INFO, "ATOM BIOS Rom: \n"); ++ if (!rhdAtomAnalyzeRomHdr(base, atom_rom_hdr, &data_offset, cmd_offset)) { ++ xf86DrvMsg(scrnIndex, X_ERROR, "RomHeader invalid\n"); ++ return FALSE; ++ } ++ ++ if (data_offset + sizeof (ATOM_MASTER_DATA_TABLE) > BIOSImageSize) { ++ xf86DrvMsg(scrnIndex,X_ERROR,"%s: Atom data table outside of BIOS\n", ++ __func__); ++ } ++ ++ if (*cmd_offset + sizeof (ATOM_MASTER_COMMAND_TABLE) > BIOSImageSize) { ++ xf86DrvMsg(scrnIndex,X_ERROR,"%s: Atom command table outside of BIOS\n", ++ __func__); ++ } ++ ++ if (!rhdAtomAnalyzeMasterDataTable(base, (ATOM_MASTER_DATA_TABLE *) ++ (base + data_offset), ++ atomDataPtr)) { ++ xf86DrvMsg(scrnIndex, X_ERROR, "%s: ROM Master Table invalid\n", ++ __func__); ++ return FALSE; ++ } ++ return TRUE; ++} ++ ++static Bool ++rhdAtomGetFbBaseAndSize(atomBiosHandlePtr handle, unsigned int *base, ++ unsigned int *size) ++{ ++ AtomBiosArgRec data; ++ if (RHDAtomBiosFunc(handle->scrnIndex, handle, GET_FW_FB_SIZE, &data) ++ == ATOM_SUCCESS) { ++ if (data.val == 0) { ++ xf86DrvMsg(handle->scrnIndex, X_WARNING, "%s: AtomBIOS specified VRAM " ++ "scratch space size invalid\n", __func__); ++ return FALSE; ++ } ++ if (size) ++ *size = (int)data.val; ++ } else ++ return FALSE; ++ if (RHDAtomBiosFunc(handle->scrnIndex, handle, GET_FW_FB_START, &data) ++ == ATOM_SUCCESS) { ++ if (data.val == 0) ++ return FALSE; ++ if (base) ++ *base = (int)data.val; ++ } ++ return TRUE; ++} ++ ++/* ++ * Uses videoRam form ScrnInfoRec. ++ */ ++static AtomBiosResult ++rhdAtomAllocateFbScratch(atomBiosHandlePtr handle, ++ AtomBiosRequestID func, AtomBiosArgPtr data) ++{ ++ unsigned int fb_base = 0; ++ unsigned int fb_size = 0; ++ unsigned int start = data->fb.start; ++ unsigned int size = data->fb.size; ++ handle->scratchBase = NULL; ++ handle->fbBase = 0; ++ ++ if (rhdAtomGetFbBaseAndSize(handle, &fb_base, &fb_size)) { ++ xf86DrvMsg(handle->scrnIndex, X_INFO, "AtomBIOS requests %ikB" ++ " of VRAM scratch space\n",fb_size); ++ fb_size *= 1024; /* convert to bytes */ ++ xf86DrvMsg(handle->scrnIndex, X_INFO, "AtomBIOS VRAM scratch base: 0x%x\n", ++ fb_base); ++ } else { ++ fb_size = 20 * 1024; ++ xf86DrvMsg(handle->scrnIndex, X_INFO, " default to: %i\n",fb_size); ++ } ++ if (fb_base && fb_size && size) { ++ /* 4k align */ ++ fb_size = (fb_size & ~(CARD32)0xfff) + ((fb_size & 0xfff) ? 1 : 0); ++ if ((fb_base + fb_size) > (start + size)) { ++ xf86DrvMsg(handle->scrnIndex, X_WARNING, ++ "%s: FW FB scratch area %i (size: %i)" ++ " extends beyond available framebuffer size %i\n", ++ __func__, fb_base, fb_size, size); ++ } else if ((fb_base + fb_size) < (start + size)) { ++ xf86DrvMsg(handle->scrnIndex, X_WARNING, ++ "%s: FW FB scratch area not located " ++ "at the end of VRAM. Scratch End: " ++ "0x%x VRAM End: 0x%x\n", __func__, ++ (unsigned int)(fb_base + fb_size), ++ size); ++ } else if (fb_base < start) { ++ xf86DrvMsg(handle->scrnIndex, X_WARNING, ++ "%s: FW FB scratch area extends below " ++ "the base of the free VRAM: 0x%x Base: 0x%x\n", ++ __func__, (unsigned int)(fb_base), start); ++ } else { ++ size -= fb_size; ++ handle->fbBase = fb_base; ++ return ATOM_SUCCESS; ++ } ++ } ++ ++ if (!handle->fbBase) { ++ xf86DrvMsg(handle->scrnIndex, X_INFO, ++ "Cannot get VRAM scratch space. " ++ "Allocating in main memory instead\n"); ++ handle->scratchBase = xcalloc(fb_size,1); ++ return ATOM_SUCCESS; ++ } ++ return ATOM_FAILED; ++} ++ ++# ifdef ATOM_BIOS_PARSER ++static Bool ++rhdAtomASICInit(atomBiosHandlePtr handle) ++{ ++ ASIC_INIT_PS_ALLOCATION asicInit; ++ AtomBiosArgRec data; ++ ++ RHDAtomBiosFunc(handle->scrnIndex, handle, ++ GET_DEFAULT_ENGINE_CLOCK, ++ &data); ++ asicInit.sASICInitClocks.ulDefaultEngineClock = data.val / 10;/*in 10 Khz*/ ++ RHDAtomBiosFunc(handle->scrnIndex, handle, ++ GET_DEFAULT_MEMORY_CLOCK, ++ &data); ++ asicInit.sASICInitClocks.ulDefaultMemoryClock = data.val / 10;/*in 10 Khz*/ ++ data.exec.dataSpace = NULL; ++ data.exec.index = 0x0; ++ data.exec.pspace = &asicInit; ++ xf86DrvMsg(handle->scrnIndex, X_INFO, "Calling ASIC Init\n"); ++ if (RHDAtomBiosFunc(handle->scrnIndex, handle, ++ ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) { ++ xf86DrvMsg(handle->scrnIndex, X_INFO, "ASIC_INIT Successful\n"); ++ return TRUE; ++ } ++ xf86DrvMsg(handle->scrnIndex, X_INFO, "ASIC_INIT Failed\n"); ++ return FALSE; ++} ++ ++Bool ++rhdAtomSetScaler(atomBiosHandlePtr handle, unsigned char scalerID, int setting) ++{ ++ ENABLE_SCALER_PARAMETERS scaler; ++ AtomBiosArgRec data; ++ ++ scaler.ucScaler = scalerID; ++ scaler.ucEnable = setting; ++ data.exec.dataSpace = NULL; ++ data.exec.index = 0x21; ++ data.exec.pspace = &scaler; ++ xf86DrvMsg(handle->scrnIndex, X_INFO, "Calling EnableScaler\n"); ++ if (RHDAtomBiosFunc(handle->scrnIndex, handle, ++ ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) { ++ xf86DrvMsg(handle->scrnIndex, X_INFO, "EnableScaler Successful\n"); ++ return TRUE; ++ } ++ xf86DrvMsg(handle->scrnIndex, X_INFO, "EableScaler Failed\n"); ++ return FALSE; ++} ++ ++# endif ++ ++static AtomBiosResult ++rhdAtomInit(atomBiosHandlePtr unused1, AtomBiosRequestID unused2, ++ AtomBiosArgPtr data) ++{ ++ int scrnIndex = data->val; ++ RADEONInfoPtr info = RADEONPTR(xf86Screens[scrnIndex]); ++ unsigned char *ptr; ++ atomDataTablesPtr atomDataPtr; ++ unsigned int cmd_offset; ++ atomBiosHandlePtr handle = NULL; ++ unsigned int BIOSImageSize = 0; ++ data->atomhandle = NULL; ++ ++ //RHDFUNCI(scrnIndex); ++ ++ /*if (info->BIOSCopy) { ++ xf86DrvMsg(scrnIndex,X_INFO,"Getting BIOS copy from INT10\n"); ++ ptr = info->BIOSCopy; ++ info->BIOSCopy = NULL; ++ ++ BIOSImageSize = ptr[2] * 512; ++ if (BIOSImageSize > legacyBIOSMax) { ++ xf86DrvMsg(scrnIndex,X_ERROR,"Invalid BIOS length field\n"); ++ return ATOM_FAILED; ++ } ++ } else*/ { ++ /*if (!xf86IsEntityPrimary(info->entityIndex)) { ++ if (!(BIOSImageSize = RHDReadPCIBios(info, &ptr))) ++ return ATOM_FAILED; ++ } else*/ { ++ int read_len; ++ unsigned char tmp[32]; ++ xf86DrvMsg(scrnIndex,X_INFO,"Getting BIOS copy from legacy VBIOS location\n"); ++ if (xf86ReadBIOS(legacyBIOSLocation, 0, tmp, 32) < 0) { ++ xf86DrvMsg(scrnIndex,X_ERROR, ++ "Cannot obtain POSTed BIOS header\n"); ++ return ATOM_FAILED; ++ } ++ BIOSImageSize = tmp[2] * 512; ++ if (BIOSImageSize > legacyBIOSMax) { ++ xf86DrvMsg(scrnIndex,X_ERROR,"Invalid BIOS length field\n"); ++ return ATOM_FAILED; ++ } ++ if (!(ptr = xcalloc(1,BIOSImageSize))) { ++ xf86DrvMsg(scrnIndex,X_ERROR, ++ "Cannot allocate %i bytes of memory " ++ "for BIOS image\n",BIOSImageSize); ++ return ATOM_FAILED; ++ } ++ if ((read_len = xf86ReadBIOS(legacyBIOSLocation, 0, ptr, BIOSImageSize) ++ < 0)) { ++ xf86DrvMsg(scrnIndex,X_ERROR,"Cannot read POSTed BIOS\n"); ++ goto error; ++ } ++ } ++ } ++ ++ if (!(atomDataPtr = xcalloc(1, sizeof(atomDataTables)))) { ++ xf86DrvMsg(scrnIndex,X_ERROR,"Cannot allocate memory for " ++ "ATOM BIOS data tabes\n"); ++ goto error; ++ } ++ if (!rhdAtomGetDataTable(scrnIndex, ptr, atomDataPtr, &cmd_offset, BIOSImageSize)) ++ goto error1; ++ if (!(handle = xcalloc(1, sizeof(atomBiosHandleRec)))) { ++ xf86DrvMsg(scrnIndex,X_ERROR,"Cannot allocate memory\n"); ++ goto error1; ++ } ++ handle->BIOSBase = ptr; ++ handle->atomDataPtr = atomDataPtr; ++ handle->cmd_offset = cmd_offset; ++ handle->scrnIndex = scrnIndex; ++#if XSERVER_LIBPCIACCESS ++ handle->device = info->PciInfo; ++#else ++ handle->PciTag = info->PciTag; ++#endif ++ handle->BIOSImageSize = BIOSImageSize; ++ ++# if ATOM_BIOS_PARSER ++ /* Try to find out if BIOS has been posted (either by system or int10 */ ++ if (!rhdAtomGetFbBaseAndSize(handle, NULL, NULL)) { ++ /* run AsicInit */ ++ if (!rhdAtomASICInit(handle)) ++ xf86DrvMsg(scrnIndex, X_WARNING, ++ "%s: AsicInit failed. Won't be able to obtain in VRAM " ++ "FB scratch space\n",__func__); ++ } ++# endif ++ ++ data->atomhandle = handle; ++ return ATOM_SUCCESS; ++ ++ error1: ++ xfree(atomDataPtr); ++ error: ++ xfree(ptr); ++ return ATOM_FAILED; ++} ++ ++static AtomBiosResult ++rhdAtomTearDown(atomBiosHandlePtr handle, ++ AtomBiosRequestID unused1, AtomBiosArgPtr unused2) ++{ ++ //RHDFUNC(handle); ++ ++ xfree(handle->BIOSBase); ++ xfree(handle->atomDataPtr); ++ if (handle->scratchBase) xfree(handle->scratchBase); ++ xfree(handle); ++ return ATOM_SUCCESS; ++} ++ ++static AtomBiosResult ++rhdAtomVramInfoQuery(atomBiosHandlePtr handle, AtomBiosRequestID func, ++ AtomBiosArgPtr data) ++{ ++ atomDataTablesPtr atomDataPtr; ++ CARD32 *val = &data->val; ++ //RHDFUNC(handle); ++ ++ atomDataPtr = handle->atomDataPtr; ++ ++ switch (func) { ++ case GET_FW_FB_START: ++ *val = atomDataPtr->VRAM_UsageByFirmware ++ ->asFirmwareVramReserveInfo[0].ulStartAddrUsedByFirmware; ++ break; ++ case GET_FW_FB_SIZE: ++ *val = atomDataPtr->VRAM_UsageByFirmware ++ ->asFirmwareVramReserveInfo[0].usFirmwareUseInKb; ++ break; ++ default: ++ return ATOM_NOT_IMPLEMENTED; ++ } ++ return ATOM_SUCCESS; ++} ++ ++static AtomBiosResult ++rhdAtomTmdsInfoQuery(atomBiosHandlePtr handle, ++ AtomBiosRequestID func, AtomBiosArgPtr data) ++{ ++ atomDataTablesPtr atomDataPtr; ++ CARD32 *val = &data->val; ++ int idx = *val; ++ ++ atomDataPtr = handle->atomDataPtr; ++ if (!rhdAtomGetTableRevisionAndSize( ++ (ATOM_COMMON_TABLE_HEADER *)(atomDataPtr->TMDS_Info), ++ NULL,NULL,NULL)) { ++ return ATOM_FAILED; ++ } ++ ++ //RHDFUNC(handle); ++ ++ switch (func) { ++ case ATOM_TMDS_FREQUENCY: ++ *val = atomDataPtr->TMDS_Info->asMiscInfo[idx].usFrequency; ++ break; ++ case ATOM_TMDS_PLL_CHARGE_PUMP: ++ *val = atomDataPtr->TMDS_Info->asMiscInfo[idx].ucPLL_ChargePump; ++ break; ++ case ATOM_TMDS_PLL_DUTY_CYCLE: ++ *val = atomDataPtr->TMDS_Info->asMiscInfo[idx].ucPLL_DutyCycle; ++ break; ++ case ATOM_TMDS_PLL_VCO_GAIN: ++ *val = atomDataPtr->TMDS_Info->asMiscInfo[idx].ucPLL_VCO_Gain; ++ break; ++ case ATOM_TMDS_PLL_VOLTAGE_SWING: ++ *val = atomDataPtr->TMDS_Info->asMiscInfo[idx].ucPLL_VoltageSwing; ++ break; ++ default: ++ return ATOM_NOT_IMPLEMENTED; ++ } ++ return ATOM_SUCCESS; ++} ++ ++static DisplayModePtr ++rhdAtomLvdsTimings(atomBiosHandlePtr handle, ATOM_DTD_FORMAT *dtd) ++{ ++ DisplayModePtr mode; ++#define NAME_LEN 16 ++ char name[NAME_LEN]; ++ ++ //RHDFUNC(handle); ++ ++ if (!(mode = (DisplayModePtr)xcalloc(1,sizeof(DisplayModeRec)))) ++ return NULL; ++ ++ mode->CrtcHDisplay = mode->HDisplay = dtd->usHActive; ++ mode->CrtcVDisplay = mode->VDisplay = dtd->usVActive; ++ mode->CrtcHBlankStart = dtd->usHActive + dtd->ucHBorder; ++ mode->CrtcHBlankEnd = mode->CrtcHBlankStart + dtd->usHBlanking_Time; ++ mode->CrtcHTotal = mode->HTotal = mode->CrtcHBlankEnd + dtd->ucHBorder; ++ mode->CrtcVBlankStart = dtd->usVActive + dtd->ucVBorder; ++ mode->CrtcVBlankEnd = mode->CrtcVBlankStart + dtd->usVBlanking_Time; ++ mode->CrtcVTotal = mode->VTotal = mode->CrtcVBlankEnd + dtd->ucVBorder; ++ mode->CrtcHSyncStart = mode->HSyncStart = dtd->usHActive + dtd->usHSyncOffset; ++ mode->CrtcHSyncEnd = mode->HSyncEnd = mode->HSyncStart + dtd->usHSyncWidth; ++ mode->CrtcVSyncStart = mode->VSyncStart = dtd->usVActive + dtd->usVSyncOffset; ++ mode->CrtcVSyncEnd = mode->VSyncEnd = mode->VSyncStart + dtd->usVSyncWidth; ++ ++ mode->SynthClock = mode->Clock = dtd->usPixClk * 10; ++ ++ mode->HSync = ((float) mode->Clock) / ((float)mode->HTotal); ++ mode->VRefresh = (1000.0 * ((float) mode->Clock)) ++ / ((float)(((float)mode->HTotal) * ((float)mode->VTotal))); ++ ++ snprintf(name, NAME_LEN, "%dx%d", ++ mode->HDisplay, mode->VDisplay); ++ mode->name = xstrdup(name); ++ ++ RHDDebug(handle->scrnIndex,"%s: LVDS Modeline: %s " ++ "%2.d %i (%i) %i %i (%i) %i %i (%i) %i %i (%i) %i\n", ++ __func__, mode->name, mode->Clock, ++ mode->HDisplay, mode->CrtcHBlankStart, mode->HSyncStart, mode->CrtcHSyncEnd, ++ mode->CrtcHBlankEnd, mode->HTotal, ++ mode->VDisplay, mode->CrtcVBlankStart, mode->VSyncStart, mode->VSyncEnd, ++ mode->CrtcVBlankEnd, mode->VTotal); ++ ++ return mode; ++} ++ ++static unsigned char* ++rhdAtomLvdsDDC(atomBiosHandlePtr handle, CARD32 offset, unsigned char *record) ++{ ++ unsigned char *EDIDBlock; ++ ++ //RHDFUNC(handle); ++ ++ while (*record != ATOM_RECORD_END_TYPE) { ++ ++ switch (*record) { ++ case LCD_MODE_PATCH_RECORD_MODE_TYPE: ++ offset += sizeof(ATOM_PATCH_RECORD_MODE); ++ if (offset > handle->BIOSImageSize) break; ++ record += sizeof(ATOM_PATCH_RECORD_MODE); ++ break; ++ ++ case LCD_RTS_RECORD_TYPE: ++ offset += sizeof(ATOM_LCD_RTS_RECORD); ++ if (offset > handle->BIOSImageSize) break; ++ record += sizeof(ATOM_LCD_RTS_RECORD); ++ break; ++ ++ case LCD_CAP_RECORD_TYPE: ++ offset += sizeof(ATOM_LCD_MODE_CONTROL_CAP); ++ if (offset > handle->BIOSImageSize) break; ++ record += sizeof(ATOM_LCD_MODE_CONTROL_CAP); ++ break; ++ ++ case LCD_FAKE_EDID_PATCH_RECORD_TYPE: ++ offset += sizeof(ATOM_FAKE_EDID_PATCH_RECORD); ++ /* check if the structure still fully lives in the BIOS image */ ++ if (offset > handle->BIOSImageSize) break; ++ offset += ((ATOM_FAKE_EDID_PATCH_RECORD*)record)->ucFakeEDIDLength ++ - sizeof(UCHAR); ++ if (offset > handle->BIOSImageSize) break; ++ /* dup string as we free it later */ ++ if (!(EDIDBlock = (unsigned char *)xalloc( ++ ((ATOM_FAKE_EDID_PATCH_RECORD*)record)->ucFakeEDIDLength))) ++ return NULL; ++ memcpy(EDIDBlock,&((ATOM_FAKE_EDID_PATCH_RECORD*)record)->ucFakeEDIDString, ++ ((ATOM_FAKE_EDID_PATCH_RECORD*)record)->ucFakeEDIDLength); ++ ++ /* for testing */ ++ { ++ xf86MonPtr mon = xf86InterpretEDID(handle->scrnIndex,EDIDBlock); ++ xf86PrintEDID(mon); ++ xfree(mon); ++ } ++ return EDIDBlock; ++ ++ case LCD_PANEL_RESOLUTION_RECORD_TYPE: ++ offset += sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD); ++ if (offset > handle->BIOSImageSize) break; ++ record += sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD); ++ break; ++ ++ default: ++ xf86DrvMsg(handle->scrnIndex, X_ERROR, ++ "%s: unknown record type: %x\n",__func__,*record); ++ return NULL; ++ } ++ } ++ ++ return NULL; ++} ++ ++static AtomBiosResult ++rhdAtomLvdsGetTimings(atomBiosHandlePtr handle, AtomBiosRequestID func, ++ AtomBiosArgPtr data) ++{ ++ atomDataTablesPtr atomDataPtr; ++ CARD8 crev, frev; ++ unsigned long offset; ++ ++ //RHDFUNC(handle); ++ ++ atomDataPtr = handle->atomDataPtr; ++ ++ if (!rhdAtomGetTableRevisionAndSize( ++ (ATOM_COMMON_TABLE_HEADER *)(atomDataPtr->LVDS_Info.base), ++ &frev,&crev,NULL)) { ++ return ATOM_FAILED; ++ } ++ ++ switch (crev) { ++ ++ case 1: ++ switch (func) { ++ case ATOMBIOS_GET_PANEL_MODE: ++ data->mode = rhdAtomLvdsTimings(handle, ++ &atomDataPtr->LVDS_Info ++ .LVDS_Info->sLCDTiming); ++ if (data->mode) ++ return ATOM_SUCCESS; ++ default: ++ return ATOM_FAILED; ++ } ++ case 2: ++ switch (func) { ++ case ATOMBIOS_GET_PANEL_MODE: ++ data->mode = rhdAtomLvdsTimings(handle, ++ &atomDataPtr->LVDS_Info ++ .LVDS_Info_v12->sLCDTiming); ++ if (data->mode) ++ return ATOM_SUCCESS; ++ return ATOM_FAILED; ++ ++ case ATOMBIOS_GET_PANEL_EDID: ++ offset = (unsigned long)&atomDataPtr->LVDS_Info.base ++ - (unsigned long)handle->BIOSBase ++ + atomDataPtr->LVDS_Info ++ .LVDS_Info_v12->usExtInfoTableOffset; ++ ++ data->EDIDBlock ++ = rhdAtomLvdsDDC(handle, offset, ++ (unsigned char *) ++ &atomDataPtr->LVDS_Info.base ++ + atomDataPtr->LVDS_Info ++ .LVDS_Info_v12->usExtInfoTableOffset); ++ if (data->EDIDBlock) ++ return ATOM_SUCCESS; ++ default: ++ return ATOM_FAILED; ++ } ++ default: ++ return ATOM_NOT_IMPLEMENTED; ++ } ++/*NOTREACHED*/ ++} ++ ++static AtomBiosResult ++rhdAtomLvdsInfoQuery(atomBiosHandlePtr handle, ++ AtomBiosRequestID func, AtomBiosArgPtr data) ++{ ++ atomDataTablesPtr atomDataPtr; ++ CARD8 crev, frev; ++ CARD32 *val = &data->val; ++ ++ //RHDFUNC(handle); ++ ++ atomDataPtr = handle->atomDataPtr; ++ ++ if (!rhdAtomGetTableRevisionAndSize( ++ (ATOM_COMMON_TABLE_HEADER *)(atomDataPtr->LVDS_Info.base), ++ &frev,&crev,NULL)) { ++ return ATOM_FAILED; ++ } ++ ++ switch (crev) { ++ case 1: ++ switch (func) { ++ case ATOM_LVDS_SUPPORTED_REFRESH_RATE: ++ *val = atomDataPtr->LVDS_Info ++ .LVDS_Info->usSupportedRefreshRate; ++ break; ++ case ATOM_LVDS_OFF_DELAY: ++ *val = atomDataPtr->LVDS_Info ++ .LVDS_Info->usOffDelayInMs; ++ break; ++ case ATOM_LVDS_SEQ_DIG_ONTO_DE: ++ *val = atomDataPtr->LVDS_Info ++ .LVDS_Info->ucPowerSequenceDigOntoDEin10Ms * 10; ++ break; ++ case ATOM_LVDS_SEQ_DE_TO_BL: ++ *val = atomDataPtr->LVDS_Info ++ .LVDS_Info->ucPowerSequenceDEtoBLOnin10Ms * 10; ++ break; ++ case ATOM_LVDS_DITHER: ++ *val = atomDataPtr->LVDS_Info ++ .LVDS_Info->ucLVDS_Misc & 0x40; ++ break; ++ case ATOM_LVDS_DUALLINK: ++ *val = atomDataPtr->LVDS_Info ++ .LVDS_Info->ucLVDS_Misc & 0x01; ++ break; ++ case ATOM_LVDS_24BIT: ++ *val = atomDataPtr->LVDS_Info ++ .LVDS_Info->ucLVDS_Misc & 0x02; ++ break; ++ case ATOM_LVDS_GREYLVL: ++ *val = atomDataPtr->LVDS_Info ++ .LVDS_Info->ucLVDS_Misc & 0x0C; ++ break; ++ case ATOM_LVDS_FPDI: ++ *val = atomDataPtr->LVDS_Info ++ .LVDS_Info->ucLVDS_Misc * 0x10; ++ break; ++ default: ++ return ATOM_NOT_IMPLEMENTED; ++ } ++ break; ++ case 2: ++ switch (func) { ++ case ATOM_LVDS_SUPPORTED_REFRESH_RATE: ++ *val = atomDataPtr->LVDS_Info ++ .LVDS_Info_v12->usSupportedRefreshRate; ++ break; ++ case ATOM_LVDS_OFF_DELAY: ++ *val = atomDataPtr->LVDS_Info ++ .LVDS_Info_v12->usOffDelayInMs; ++ break; ++ case ATOM_LVDS_SEQ_DIG_ONTO_DE: ++ *val = atomDataPtr->LVDS_Info ++ .LVDS_Info_v12->ucPowerSequenceDigOntoDEin10Ms * 10; ++ break; ++ case ATOM_LVDS_SEQ_DE_TO_BL: ++ *val = atomDataPtr->LVDS_Info ++ .LVDS_Info_v12->ucPowerSequenceDEtoBLOnin10Ms * 10; ++ break; ++ case ATOM_LVDS_DITHER: ++ *val = atomDataPtr->LVDS_Info ++ .LVDS_Info_v12->ucLVDS_Misc & 0x40; ++ break; ++ case ATOM_LVDS_DUALLINK: ++ *val = atomDataPtr->LVDS_Info ++ .LVDS_Info_v12->ucLVDS_Misc & 0x01; ++ break; ++ case ATOM_LVDS_24BIT: ++ *val = atomDataPtr->LVDS_Info ++ .LVDS_Info_v12->ucLVDS_Misc & 0x02; ++ break; ++ case ATOM_LVDS_GREYLVL: ++ *val = atomDataPtr->LVDS_Info ++ .LVDS_Info_v12->ucLVDS_Misc & 0x0C; ++ break; ++ case ATOM_LVDS_FPDI: ++ *val = atomDataPtr->LVDS_Info ++ .LVDS_Info_v12->ucLVDS_Misc * 0x10; ++ break; ++ default: ++ return ATOM_NOT_IMPLEMENTED; ++ } ++ break; ++ default: ++ return ATOM_NOT_IMPLEMENTED; ++ } ++ ++ return ATOM_SUCCESS; ++} ++ ++static AtomBiosResult ++rhdAtomCompassionateDataQuery(atomBiosHandlePtr handle, ++ AtomBiosRequestID func, AtomBiosArgPtr data) ++{ ++ atomDataTablesPtr atomDataPtr; ++ CARD8 crev, frev; ++ CARD32 *val = &data->val; ++ ++ //RHDFUNC(handle); ++ ++ atomDataPtr = handle->atomDataPtr; ++ ++ if (!rhdAtomGetTableRevisionAndSize( ++ (ATOM_COMMON_TABLE_HEADER *)(atomDataPtr->CompassionateData), ++ &frev,&crev,NULL)) { ++ return ATOM_FAILED; ++ } ++ ++ switch (func) { ++ case ATOM_DAC1_BG_ADJ: ++ *val = atomDataPtr->CompassionateData-> ++ ucDAC1_BG_Adjustment; ++ break; ++ case ATOM_DAC1_DAC_ADJ: ++ *val = atomDataPtr->CompassionateData-> ++ ucDAC1_DAC_Adjustment; ++ break; ++ case ATOM_DAC1_FORCE: ++ *val = atomDataPtr->CompassionateData-> ++ usDAC1_FORCE_Data; ++ break; ++ case ATOM_DAC2_CRTC2_BG_ADJ: ++ *val = atomDataPtr->CompassionateData-> ++ ucDAC2_CRT2_BG_Adjustment; ++ break; ++ case ATOM_DAC2_CRTC2_DAC_ADJ: ++ *val = atomDataPtr->CompassionateData-> ++ ucDAC2_CRT2_DAC_Adjustment; ++ break; ++ case ATOM_DAC2_CRTC2_FORCE: ++ *val = atomDataPtr->CompassionateData-> ++ usDAC2_CRT2_FORCE_Data; ++ break; ++ case ATOM_DAC2_CRTC2_MUX_REG_IND: ++ *val = atomDataPtr->CompassionateData-> ++ usDAC2_CRT2_MUX_RegisterIndex; ++ break; ++ case ATOM_DAC2_CRTC2_MUX_REG_INFO: ++ *val = atomDataPtr->CompassionateData-> ++ ucDAC2_CRT2_MUX_RegisterInfo; ++ break; ++ default: ++ return ATOM_NOT_IMPLEMENTED; ++ } ++ return ATOM_SUCCESS; ++} ++ ++static AtomBiosResult ++rhdAtomGPIOI2CInfoQuery(atomBiosHandlePtr handle, ++ AtomBiosRequestID func, AtomBiosArgPtr data) ++{ ++ atomDataTablesPtr atomDataPtr; ++ CARD8 crev, frev; ++ CARD32 *val = &data->val; ++ unsigned short size; ++ ++ //RHDFUNC(handle); ++ ++ atomDataPtr = handle->atomDataPtr; ++ ++ if (!rhdAtomGetTableRevisionAndSize( ++ (ATOM_COMMON_TABLE_HEADER *)(atomDataPtr->GPIO_I2C_Info), ++ &frev,&crev,&size)) { ++ return ATOM_FAILED; ++ } ++ ++ switch (func) { ++ case ATOM_GPIO_I2C_CLK_MASK: ++ if ((sizeof(ATOM_COMMON_TABLE_HEADER) ++ + (*val * sizeof(ATOM_GPIO_I2C_ASSIGMENT))) > size) { ++ xf86DrvMsg(handle->scrnIndex, X_ERROR, "%s: GPIO_I2C Device " ++ "num %lu exeeds table size %u\n",__func__, ++ (unsigned long)val, ++ size); ++ return ATOM_FAILED; ++ } ++ ++ *val = atomDataPtr->GPIO_I2C_Info->asGPIO_Info[*val] ++ .usClkMaskRegisterIndex; ++ break; ++ ++ default: ++ return ATOM_NOT_IMPLEMENTED; ++ } ++ return ATOM_SUCCESS; ++} ++ ++static AtomBiosResult ++rhdAtomFirmwareInfoQuery(atomBiosHandlePtr handle, ++ AtomBiosRequestID func, AtomBiosArgPtr data) ++{ ++ atomDataTablesPtr atomDataPtr; ++ CARD8 crev, frev; ++ CARD32 *val = &data->val; ++ ++ //RHDFUNC(handle); ++ ++ atomDataPtr = handle->atomDataPtr; ++ ++ if (!rhdAtomGetTableRevisionAndSize( ++ (ATOM_COMMON_TABLE_HEADER *)(atomDataPtr->FirmwareInfo.base), ++ &crev,&frev,NULL)) { ++ return ATOM_FAILED; ++ } ++ ++ switch (crev) { ++ case 1: ++ switch (func) { ++ case GET_DEFAULT_ENGINE_CLOCK: ++ *val = atomDataPtr->FirmwareInfo ++ .FirmwareInfo->ulDefaultEngineClock * 10; ++ break; ++ case GET_DEFAULT_MEMORY_CLOCK: ++ *val = atomDataPtr->FirmwareInfo ++ .FirmwareInfo->ulDefaultMemoryClock * 10; ++ break; ++ case GET_MAX_PIXEL_CLOCK_PLL_OUTPUT: ++ *val = atomDataPtr->FirmwareInfo ++ .FirmwareInfo->ulMaxPixelClockPLL_Output * 10; ++ break; ++ case GET_MIN_PIXEL_CLOCK_PLL_OUTPUT: ++ *val = atomDataPtr->FirmwareInfo ++ .FirmwareInfo->usMinPixelClockPLL_Output * 10; ++ case GET_MAX_PIXEL_CLOCK_PLL_INPUT: ++ *val = atomDataPtr->FirmwareInfo ++ .FirmwareInfo->usMaxPixelClockPLL_Input * 10; ++ break; ++ case GET_MIN_PIXEL_CLOCK_PLL_INPUT: ++ *val = atomDataPtr->FirmwareInfo ++ .FirmwareInfo->usMinPixelClockPLL_Input * 10; ++ break; ++ case GET_MAX_PIXEL_CLK: ++ *val = atomDataPtr->FirmwareInfo ++ .FirmwareInfo->usMaxPixelClock * 10; ++ break; ++ case GET_REF_CLOCK: ++ *val = atomDataPtr->FirmwareInfo ++ .FirmwareInfo->usReferenceClock * 10; ++ break; ++ default: ++ return ATOM_NOT_IMPLEMENTED; ++ } ++ case 2: ++ switch (func) { ++ case GET_DEFAULT_ENGINE_CLOCK: ++ *val = atomDataPtr->FirmwareInfo ++ .FirmwareInfo_V_1_2->ulDefaultEngineClock * 10; ++ break; ++ case GET_DEFAULT_MEMORY_CLOCK: ++ *val = atomDataPtr->FirmwareInfo ++ .FirmwareInfo_V_1_2->ulDefaultMemoryClock * 10; ++ break; ++ case GET_MAX_PIXEL_CLOCK_PLL_OUTPUT: ++ *val = atomDataPtr->FirmwareInfo ++ .FirmwareInfo_V_1_2->ulMaxPixelClockPLL_Output * 10; ++ break; ++ case GET_MIN_PIXEL_CLOCK_PLL_OUTPUT: ++ *val = atomDataPtr->FirmwareInfo ++ .FirmwareInfo_V_1_2->usMinPixelClockPLL_Output * 10; ++ break; ++ case GET_MAX_PIXEL_CLOCK_PLL_INPUT: ++ *val = atomDataPtr->FirmwareInfo ++ .FirmwareInfo_V_1_2->usMaxPixelClockPLL_Input * 10; ++ break; ++ case GET_MIN_PIXEL_CLOCK_PLL_INPUT: ++ *val = atomDataPtr->FirmwareInfo ++ .FirmwareInfo_V_1_2->usMinPixelClockPLL_Input * 10; ++ break; ++ case GET_MAX_PIXEL_CLK: ++ *val = atomDataPtr->FirmwareInfo ++ .FirmwareInfo_V_1_2->usMaxPixelClock * 10; ++ break; ++ case GET_REF_CLOCK: ++ *val = atomDataPtr->FirmwareInfo ++ .FirmwareInfo_V_1_2->usReferenceClock * 10; ++ break; ++ default: ++ return ATOM_NOT_IMPLEMENTED; ++ } ++ break; ++ case 3: ++ switch (func) { ++ case GET_DEFAULT_ENGINE_CLOCK: ++ *val = atomDataPtr->FirmwareInfo ++ .FirmwareInfo_V_1_3->ulDefaultEngineClock * 10; ++ break; ++ case GET_DEFAULT_MEMORY_CLOCK: ++ *val = atomDataPtr->FirmwareInfo ++ .FirmwareInfo_V_1_3->ulDefaultMemoryClock * 10; ++ break; ++ case GET_MAX_PIXEL_CLOCK_PLL_OUTPUT: ++ *val = atomDataPtr->FirmwareInfo ++ .FirmwareInfo_V_1_3->ulMaxPixelClockPLL_Output * 10; ++ break; ++ case GET_MIN_PIXEL_CLOCK_PLL_OUTPUT: ++ *val = atomDataPtr->FirmwareInfo ++ .FirmwareInfo_V_1_3->usMinPixelClockPLL_Output * 10; ++ break; ++ case GET_MAX_PIXEL_CLOCK_PLL_INPUT: ++ *val = atomDataPtr->FirmwareInfo ++ .FirmwareInfo_V_1_3->usMaxPixelClockPLL_Input * 10; ++ break; ++ case GET_MIN_PIXEL_CLOCK_PLL_INPUT: ++ *val = atomDataPtr->FirmwareInfo ++ .FirmwareInfo_V_1_3->usMinPixelClockPLL_Input * 10; ++ break; ++ case GET_MAX_PIXEL_CLK: ++ *val = atomDataPtr->FirmwareInfo ++ .FirmwareInfo_V_1_3->usMaxPixelClock * 10; ++ break; ++ case GET_REF_CLOCK: ++ *val = atomDataPtr->FirmwareInfo ++ .FirmwareInfo_V_1_3->usReferenceClock * 10; ++ break; ++ default: ++ return ATOM_NOT_IMPLEMENTED; ++ } ++ break; ++ case 4: ++ switch (func) { ++ case GET_DEFAULT_ENGINE_CLOCK: ++ *val = atomDataPtr->FirmwareInfo ++ .FirmwareInfo_V_1_4->ulDefaultEngineClock * 10; ++ break; ++ case GET_DEFAULT_MEMORY_CLOCK: ++ *val = atomDataPtr->FirmwareInfo ++ .FirmwareInfo_V_1_4->ulDefaultMemoryClock * 10; ++ break; ++ case GET_MAX_PIXEL_CLOCK_PLL_INPUT: ++ *val = atomDataPtr->FirmwareInfo ++ .FirmwareInfo_V_1_4->usMaxPixelClockPLL_Input * 10; ++ break; ++ case GET_MIN_PIXEL_CLOCK_PLL_INPUT: ++ *val = atomDataPtr->FirmwareInfo ++ .FirmwareInfo_V_1_4->usMinPixelClockPLL_Input * 10; ++ break; ++ case GET_MAX_PIXEL_CLOCK_PLL_OUTPUT: ++ *val = atomDataPtr->FirmwareInfo ++ .FirmwareInfo_V_1_4->ulMaxPixelClockPLL_Output * 10; ++ break; ++ case GET_MIN_PIXEL_CLOCK_PLL_OUTPUT: ++ *val = atomDataPtr->FirmwareInfo ++ .FirmwareInfo_V_1_4->usMinPixelClockPLL_Output * 10; ++ break; ++ case GET_MAX_PIXEL_CLK: ++ *val = atomDataPtr->FirmwareInfo ++ .FirmwareInfo_V_1_4->usMaxPixelClock * 10; ++ break; ++ case GET_REF_CLOCK: ++ *val = atomDataPtr->FirmwareInfo ++ .FirmwareInfo_V_1_4->usReferenceClock * 10; ++ break; ++ default: ++ return ATOM_NOT_IMPLEMENTED; ++ } ++ break; ++ default: ++ return ATOM_NOT_IMPLEMENTED; ++ } ++ return ATOM_SUCCESS; ++} ++ ++const int object_connector_convert[] = ++ { CONNECTOR_NONE, ++ CONNECTOR_DVI_I, ++ CONNECTOR_DVI_I, ++ CONNECTOR_DVI_D, ++ CONNECTOR_DVI_D, ++ CONNECTOR_VGA, ++ CONNECTOR_CTV, ++ CONNECTOR_STV, ++ CONNECTOR_NONE, ++ CONNECTOR_DIN, ++ CONNECTOR_SCART, ++ CONNECTOR_HDMI_TYPE_A, ++ CONNECTOR_HDMI_TYPE_B, ++ CONNECTOR_HDMI_TYPE_B, ++ CONNECTOR_LVDS, ++ CONNECTOR_DIN, ++ CONNECTOR_NONE, ++ CONNECTOR_NONE, ++ CONNECTOR_NONE, ++ CONNECTOR_NONE, ++ }; ++ ++static void ++rhdAtomParseI2CRecord(atomBiosHandlePtr handle, ++ ATOM_I2C_RECORD *Record, CARD32 *ddc_line) ++{ ++ ErrorF(" %s: I2C Record: %s[%x] EngineID: %x I2CAddr: %x\n", ++ __func__, ++ Record->sucI2cId.bfHW_Capable ? "HW_Line" : "GPIO_ID", ++ Record->sucI2cId.bfI2C_LineMux, ++ Record->sucI2cId.bfHW_EngineID, ++ Record->ucI2CAddr); ++ ++ if (!*(unsigned char *)&(Record->sucI2cId)) ++ *ddc_line = 0; ++ else { ++ ++ if (Record->ucI2CAddr != 0) ++ return; ++ ++ if (Record->sucI2cId.bfHW_Capable) { ++ switch(Record->sucI2cId.bfI2C_LineMux) { ++ case 0: *ddc_line = 0x7e40; break; ++ case 1: *ddc_line = 0x7e50; break; ++ case 2: *ddc_line = 0x7e30; break; ++ default: break; ++ } ++ return; ++ ++ } else { ++ /* add GPIO pin parsing */ ++ } ++ } ++} ++ ++static CARD32 ++RADEONLookupGPIOLineForDDC(ScrnInfoPtr pScrn, CARD8 id) ++{ ++ RADEONInfoPtr info = RADEONPTR (pScrn); ++ atomDataTablesPtr atomDataPtr; ++ ATOM_GPIO_I2C_ASSIGMENT gpio; ++ CARD32 ret = 0; ++ CARD8 crev, frev; ++ ++ atomDataPtr = info->atomBIOS->atomDataPtr; ++ ++ if (!rhdAtomGetTableRevisionAndSize( ++ &(atomDataPtr->GPIO_I2C_Info->sHeader), ++ &crev,&frev,NULL)) { ++ xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "No GPIO Info Table found!\n"); ++ return ret; ++ } ++ ++ /* note clk and data regs can be different! ++ * gpio.usClkMaskRegisterIndex and gpio.usDataMaskRegisterIndex ++ */ ++ ++ gpio = atomDataPtr->GPIO_I2C_Info->asGPIO_Info[id]; ++ ret = gpio.usClkMaskRegisterIndex * 4; ++ ++ return ret; ++} ++ ++Bool ++RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn) ++{ ++ RADEONInfoPtr info = RADEONPTR (pScrn); ++ CARD8 crev, frev; ++ unsigned short size; ++ atomDataTablesPtr atomDataPtr; ++ ATOM_CONNECTOR_OBJECT_TABLE *con_obj; ++ int i, j; ++ ++ atomDataPtr = info->atomBIOS->atomDataPtr; ++ if (!rhdAtomGetTableRevisionAndSize((ATOM_COMMON_TABLE_HEADER *)(atomDataPtr->Object_Header), &crev, &frev, &size)) ++ return FALSE; ++ ++ if (crev < 2) ++ return FALSE; ++ ++ con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *) ++ ((char *)&atomDataPtr->Object_Header->sHeader + ++ atomDataPtr->Object_Header->usConnectorObjectTableOffset); ++ ++ for (i = 0; i < con_obj->ucNumberOfObjects; i++) { ++ ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *SrcDstTable; ++ ATOM_COMMON_RECORD_HEADER *Record; ++ CARD8 obj_id, num, obj_type; ++ int record_base; ++ ++ obj_id = (con_obj->asObjects[i].usObjectID & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; ++ num = (con_obj->asObjects[i].usObjectID & ENUM_ID_MASK) >> ENUM_ID_SHIFT; ++ obj_type = (con_obj->asObjects[i].usObjectID & OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT; ++ if (obj_type != GRAPH_OBJECT_TYPE_CONNECTOR) ++ continue; ++ ++ SrcDstTable = (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *) ++ ((char *)&atomDataPtr->Object_Header->sHeader ++ + con_obj->asObjects[i].usSrcDstTableOffset); ++ ++ ErrorF("object id %04x %02x\n", obj_id, SrcDstTable->ucNumberOfSrc); ++ info->BiosConnector[i].ConnectorType = object_connector_convert[obj_id]; ++ info->BiosConnector[i].valid = TRUE; ++ info->BiosConnector[i].devices = 0; ++ ++ for (j = 0; j < SrcDstTable->ucNumberOfSrc; j++) { ++ CARD8 sobj_id; ++ ++ sobj_id = (SrcDstTable->usSrcObjectID[j] & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; ++ ErrorF("src object id %04x %d\n", SrcDstTable->usSrcObjectID[j], sobj_id); ++ ++ switch(sobj_id) { ++ case ENCODER_OBJECT_ID_INTERNAL_LVDS: ++ info->BiosConnector[i].devices |= (1 << ATOM_DEVICE_LCD1_INDEX); ++ break; ++ case ENCODER_OBJECT_ID_INTERNAL_TMDS1: ++ info->BiosConnector[i].devices |= (1 << ATOM_DEVICE_DFP1_INDEX); ++ info->BiosConnector[i].TMDSType = TMDS_INT; ++ break; ++ case ENCODER_OBJECT_ID_INTERNAL_TMDS2: ++ info->BiosConnector[i].devices |= (1 << ATOM_DEVICE_DFP2_INDEX); ++ info->BiosConnector[i].TMDSType = TMDS_EXT; ++ break; ++ case ENCODER_OBJECT_ID_INTERNAL_LVTM1: ++ info->BiosConnector[i].devices |= (1 << ATOM_DEVICE_DFP3_INDEX); ++ info->BiosConnector[i].TMDSType = TMDS_EXT; ++ break; ++ case ENCODER_OBJECT_ID_INTERNAL_DAC1: ++ case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: ++ info->BiosConnector[i].devices |= (1 << ATOM_DEVICE_CRT1_INDEX); ++ info->BiosConnector[i].DACType = DAC_PRIMARY; ++ break; ++ case ENCODER_OBJECT_ID_INTERNAL_DAC2: ++ case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: ++ info->BiosConnector[i].devices |= (1 << ATOM_DEVICE_CRT2_INDEX); ++ info->BiosConnector[i].DACType = DAC_TVDAC; ++ break; ++ } ++ } ++ ++ Record = (ATOM_COMMON_RECORD_HEADER *) ++ ((char *)&atomDataPtr->Object_Header->sHeader ++ + con_obj->asObjects[i].usRecordOffset); ++ ++ record_base = con_obj->asObjects[i].usRecordOffset; ++ ++ while (Record->ucRecordType > 0 ++ && Record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER ) { ++ ++ ErrorF("record type %d\n", Record->ucRecordType); ++ switch (Record->ucRecordType) { ++ case ATOM_I2C_RECORD_TYPE: ++ rhdAtomParseI2CRecord(info->atomBIOS, ++ (ATOM_I2C_RECORD *)Record, ++ &info->BiosConnector[i].ddc_line); ++ break; ++ case ATOM_HPD_INT_RECORD_TYPE: ++ break; ++ case ATOM_CONNECTOR_DEVICE_TAG_RECORD_TYPE: ++ break; ++ } ++ ++ Record = (ATOM_COMMON_RECORD_HEADER*) ++ ((char *)Record + Record->ucRecordSize); ++ } ++ } ++ return TRUE; ++} ++ ++ ++Bool ++RADEONGetATOMConnectorInfoFromBIOSConnectorTable (ScrnInfoPtr pScrn) ++{ ++ RADEONInfoPtr info = RADEONPTR (pScrn); ++ atomDataTablesPtr atomDataPtr; ++ CARD8 crev, frev; ++ int i, j; ++ ++ atomDataPtr = info->atomBIOS->atomDataPtr; ++ ++ if (!rhdAtomGetTableRevisionAndSize( ++ &(atomDataPtr->SupportedDevicesInfo.SupportedDevicesInfo->sHeader), ++ &crev,&frev,NULL)) { ++ xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "No Device Info Table found!\n"); ++ return FALSE; ++ } ++ ++ for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) { ++ ATOM_CONNECTOR_INFO_I2C ci ++ = atomDataPtr->SupportedDevicesInfo.SupportedDevicesInfo->asConnInfo[i]; ++ ++ if (!(atomDataPtr->SupportedDevicesInfo ++ .SupportedDevicesInfo->usDeviceSupport & (1 << i))) { ++ info->BiosConnector[i].valid = FALSE; ++ continue; ++ } ++ ++ if (i == ATOM_DEVICE_CV_INDEX) { ++ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Skipping Component Video\n"); ++ info->BiosConnector[i].valid = FALSE; ++ continue; ++ } ++ ++ info->BiosConnector[i].valid = TRUE; ++ info->BiosConnector[i].output_id = ci.sucI2cId.sbfAccess.bfI2C_LineMux; ++ info->BiosConnector[i].devices = (1 << i); ++ info->BiosConnector[i].ConnectorType = ci.sucConnectorInfo.sbfAccess.bfConnectorType; ++ info->BiosConnector[i].DACType = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC - 1; ++ ++ if (ci.sucI2cId.sbfAccess.bfHW_Capable) { ++ /* don't assign a gpio for tv */ ++ if ((i == ATOM_DEVICE_TV1_INDEX) || ++ (i == ATOM_DEVICE_TV2_INDEX) || ++ (i == ATOM_DEVICE_CV_INDEX)) ++ info->BiosConnector[i].ddc_line = 0; ++ else ++ info->BiosConnector[i].ddc_line = ++ RADEONLookupGPIOLineForDDC(pScrn, ci.sucI2cId.sbfAccess.bfI2C_LineMux); ++ } else if (ci.sucI2cId.sbfAccess.bfI2C_LineMux) { ++ /* add support for GPIO line */ ++ ErrorF("Unsupported SW GPIO - device %d: gpio line: 0x%x\n", ++ i, RADEONLookupGPIOLineForDDC(pScrn, ci.sucI2cId.sbfAccess.bfI2C_LineMux)); ++ info->BiosConnector[i].ddc_line = 0; ++ } else { ++ info->BiosConnector[i].ddc_line = 0; ++ } ++ ++ if (i == ATOM_DEVICE_DFP1_INDEX) ++ info->BiosConnector[i].TMDSType = TMDS_INT; ++ else if (i == ATOM_DEVICE_DFP2_INDEX) ++ info->BiosConnector[i].TMDSType = TMDS_EXT; ++ else if (i == ATOM_DEVICE_DFP3_INDEX) ++ info->BiosConnector[i].TMDSType = TMDS_EXT; ++ else ++ info->BiosConnector[i].TMDSType = TMDS_UNKNOWN; ++ ++ /* Always set the connector type to VGA for CRT1/CRT2. if they are ++ * shared with a DVI port, we'll pick up the DVI connector below when we ++ * merge the outputs ++ */ ++ if ((i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX) && ++ (info->BiosConnector[i].ConnectorType == CONNECTOR_DVI_I || ++ info->BiosConnector[i].ConnectorType == CONNECTOR_DVI_D || ++ info->BiosConnector[i].ConnectorType == CONNECTOR_DVI_A)) { ++ info->BiosConnector[i].ConnectorType = CONNECTOR_VGA; ++ } ++ ++ if (crev > 1) { ++ ATOM_CONNECTOR_INC_SRC_BITMAP isb ++ = atomDataPtr->SupportedDevicesInfo ++ .SupportedDevicesInfo_HD->asIntSrcInfo[i]; ++ ++ switch (isb.ucIntSrcBitmap) { ++ case 0x4: ++ info->BiosConnector[i].hpd_mask = 0x00000001; ++ break; ++ case 0xa: ++ info->BiosConnector[i].hpd_mask = 0x00000100; ++ break; ++ default: ++ info->BiosConnector[i].hpd_mask = 0; ++ break; ++ } ++ } else { ++ info->BiosConnector[i].hpd_mask = 0; ++ } ++ } ++ ++ /* CRTs/DFPs may share a port */ ++ for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) { ++ if (info->BiosConnector[i].valid) { ++ for (j = 0; j < ATOM_MAX_SUPPORTED_DEVICE; j++) { ++ if (info->BiosConnector[j].valid && (i != j) ) { ++ if (info->BiosConnector[i].output_id == info->BiosConnector[j].output_id) { ++ if (((i == ATOM_DEVICE_DFP1_INDEX) || ++ (i == ATOM_DEVICE_DFP2_INDEX) || ++ (i == ATOM_DEVICE_DFP3_INDEX)) && ++ ((j == ATOM_DEVICE_CRT1_INDEX) || (j == ATOM_DEVICE_CRT2_INDEX))) { ++ info->BiosConnector[i].DACType = info->BiosConnector[j].DACType; ++ info->BiosConnector[i].devices |= info->BiosConnector[j].devices; ++ info->BiosConnector[j].valid = FALSE; ++ } else if (((j == ATOM_DEVICE_DFP1_INDEX) || ++ (j == ATOM_DEVICE_DFP2_INDEX) || ++ (j == ATOM_DEVICE_DFP3_INDEX)) && ++ ((i == ATOM_DEVICE_CRT1_INDEX) || (i == ATOM_DEVICE_CRT2_INDEX))) { ++ info->BiosConnector[j].DACType = info->BiosConnector[i].DACType; ++ info->BiosConnector[j].devices |= info->BiosConnector[i].devices; ++ info->BiosConnector[i].valid = FALSE; ++ } ++ /* other possible combos? */ ++ } ++ } ++ } ++ } ++ } ++ ++ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Bios Connector table: \n"); ++ for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) { ++ if (info->BiosConnector[i].valid) { ++ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Port%d: DDCType-0x%x, DACType-%d, TMDSType-%d, ConnectorType-%d, hpd_mask-0x%x\n", ++ i, info->BiosConnector[i].ddc_line, info->BiosConnector[i].DACType, ++ info->BiosConnector[i].TMDSType, info->BiosConnector[i].ConnectorType, ++ info->BiosConnector[i].hpd_mask); ++ } ++ } ++ ++ return TRUE; ++} ++ ++#if 0 ++#define RHD_CONNECTORS_MAX 4 ++#define MAX_OUTPUTS_PER_CONNECTOR 2 ++ ++#define Limit(n,max,name) ((n >= max) ? ( \ ++ xf86DrvMsg(handle->scrnIndex,X_ERROR,"%s: %s %i exceeds maximum %i\n", \ ++ __func__,name,n,max), TRUE) : FALSE) ++ ++static const struct _rhd_connector_objs ++{ ++ char *name; ++ RADEONConnectorTypeATOM con; ++} rhd_connector_objs[] = { ++ { "NONE", CONNECTOR_NONE_ATOM }, ++ { "SINGLE_LINK_DVI_I", CONNECTOR_DVI_I_ATOM }, ++ { "DUAL_LINK_DVI_I", CONNECTOR_DVI_I_ATOM }, ++ { "SINGLE_LINK_DVI_D", CONNECTOR_DVI_D_ATOM }, ++ { "DUAL_LINK_DVI_D", CONNECTOR_DVI_D_ATOM }, ++ { "VGA", CONNECTOR_VGA_ATOM }, ++ { "COMPOSITE", CONNECTOR_CTV_ATOM }, ++ { "SVIDEO", CONNECTOR_STV_ATOM }, ++ { "D_CONNECTOR", CONNECTOR_NONE_ATOM }, ++ { "9PIN_DIN", CONNECTOR_NONE_ATOM }, ++ { "SCART", CONNECTOR_SCART_ATOM }, ++ { "HDMI_TYPE_A", CONNECTOR_HDMI_TYPE_A_ATOM }, ++ { "HDMI_TYPE_B", CONNECTOR_HDMI_TYPE_B_ATOM }, ++ { "HDMI_TYPE_B", CONNECTOR_HDMI_TYPE_B_ATOM }, ++ { "LVDS", CONNECTOR_LVDS_ATOM }, ++ { "7PIN_DIN", CONNECTOR_STV_ATOM }, ++ { "PCIE_CONNECTOR", CONNECTOR_NONE_ATOM }, ++ { "CROSSFIRE", CONNECTOR_NONE_ATOM }, ++ { "HARDCODE_DVI", CONNECTOR_NONE_ATOM }, ++ { "DISPLAYPORT", CONNECTOR_DISPLAY_PORT_ATOM } ++}; ++static const int n_rhd_connector_objs = sizeof (rhd_connector_objs) / sizeof(struct _rhd_connector_objs); ++ ++static const struct _rhd_encoders ++{ ++ char *name; ++ RADEONOutputTypeATOM ot; ++} rhd_encoders[] = { ++ { "NONE", OUTPUT_NONE_ATOM }, ++ { "INTERNAL_LVDS", OUTPUT_LVDS_ATOM }, ++ { "INTERNAL_TMDS1", OUTPUT_TMDSA_ATOM }, ++ { "INTERNAL_TMDS2", OUTPUT_TMDSB_ATOM }, ++ { "INTERNAL_DAC1", OUTPUT_DACA_ATOM }, ++ { "INTERNAL_DAC2", OUTPUT_DACB_ATOM }, ++ { "INTERNAL_SDVOA", OUTPUT_NONE_ATOM }, ++ { "INTERNAL_SDVOB", OUTPUT_NONE_ATOM }, ++ { "SI170B", OUTPUT_NONE_ATOM }, ++ { "CH7303", OUTPUT_NONE_ATOM }, ++ { "CH7301", OUTPUT_NONE_ATOM }, ++ { "INTERNAL_DVO1", OUTPUT_NONE_ATOM }, ++ { "EXTERNAL_SDVOA", OUTPUT_NONE_ATOM }, ++ { "EXTERNAL_SDVOB", OUTPUT_NONE_ATOM }, ++ { "TITFP513", OUTPUT_NONE_ATOM }, ++ { "INTERNAL_LVTM1", OUTPUT_LVTMA_ATOM }, ++ { "VT1623", OUTPUT_NONE_ATOM }, ++ { "HDMI_SI1930", OUTPUT_NONE_ATOM }, ++ { "HDMI_INTERNAL", OUTPUT_NONE_ATOM }, ++ { "INTERNAL_KLDSCP_TMDS1", OUTPUT_TMDSA_ATOM }, ++ { "INTERNAL_KLSCP_DVO1", OUTPUT_NONE_ATOM }, ++ { "INTERNAL_KLDSCP_DAC1", OUTPUT_DACA_ATOM }, ++ { "INTERNAL_KLDSCP_DAC2", OUTPUT_DACB_ATOM }, ++ { "SI178", OUTPUT_NONE_ATOM }, ++ { "MVPU_FPGA", OUTPUT_NONE_ATOM }, ++ { "INTERNAL_DDI", OUTPUT_NONE_ATOM }, ++ { "VT1625", OUTPUT_NONE_ATOM }, ++ { "HDMI_SI1932", OUTPUT_NONE_ATOM }, ++ { "AN9801", OUTPUT_NONE_ATOM }, ++ { "DP501", OUTPUT_NONE_ATOM }, ++}; ++static const int n_rhd_encoders = sizeof (rhd_encoders) / sizeof(struct _rhd_encoders); ++ ++static const struct _rhd_connectors ++{ ++ char *name; ++ RADEONConnectorTypeATOM con; ++ Bool dual; ++} rhd_connectors[] = { ++ {"NONE", CONNECTOR_NONE_ATOM, FALSE }, ++ {"VGA", CONNECTOR_VGA_ATOM, FALSE }, ++ {"DVI-I", CONNECTOR_DVI_I_ATOM, TRUE }, ++ {"DVI-D", CONNECTOR_DVI_D_ATOM, FALSE }, ++ {"DVI-A", CONNECTOR_DVI_A_ATOM, FALSE }, ++ {"SVIDEO", CONNECTOR_STV_ATOM, FALSE }, ++ {"COMPOSITE", CONNECTOR_CTV_ATOM, FALSE }, ++ {"PANEL", CONNECTOR_LVDS_ATOM, FALSE }, ++ {"DIGITAL_LINK", CONNECTOR_DIGITAL_ATOM, FALSE }, ++ {"SCART", CONNECTOR_SCART_ATOM, FALSE }, ++ {"HDMI Type A", CONNECTOR_HDMI_TYPE_A_ATOM, FALSE }, ++ {"HDMI Type B", CONNECTOR_HDMI_TYPE_B_ATOM, FALSE }, ++ {"UNKNOWN", CONNECTOR_NONE_ATOM, FALSE }, ++ {"UNKNOWN", CONNECTOR_NONE_ATOM, FALSE }, ++ {"DVI+DIN", CONNECTOR_NONE_ATOM, FALSE } ++}; ++static const int n_rhd_connectors = sizeof(rhd_connectors) / sizeof(struct _rhd_connectors); ++ ++static const struct _rhd_devices ++{ ++ char *name; ++ RADEONOutputTypeATOM ot; ++} rhd_devices[] = { ++ {" CRT1", OUTPUT_NONE_ATOM }, ++ {" LCD1", OUTPUT_LVTMA_ATOM }, ++ {" TV1", OUTPUT_NONE_ATOM }, ++ {" DFP1", OUTPUT_TMDSA_ATOM }, ++ {" CRT2", OUTPUT_NONE_ATOM }, ++ {" LCD2", OUTPUT_LVTMA_ATOM }, ++ {" TV2", OUTPUT_NONE_ATOM }, ++ {" DFP2", OUTPUT_LVTMA_ATOM }, ++ {" CV", OUTPUT_NONE_ATOM }, ++ {" DFP3", OUTPUT_LVTMA_ATOM } ++}; ++static const int n_rhd_devices = sizeof(rhd_devices) / sizeof(struct _rhd_devices); ++ ++static const rhdDDC hwddc[] = { RHD_DDC_0, RHD_DDC_1, RHD_DDC_2, RHD_DDC_3 }; ++static const int n_hwddc = sizeof(hwddc) / sizeof(rhdDDC); ++ ++static const rhdOutputType acc_dac[] = { OUTPUT_NONE_ATOM, ++ OUTPUT_DACA_ATOM, ++ OUTPUT_DACB_ATOM, ++ OUTPUT_DAC_EXTERNAL_ATOM }; ++static const int n_acc_dac = sizeof(acc_dac) / sizeof (rhdOutputType); ++ ++/* ++ * ++ */ ++static Bool ++rhdAtomInterpretObjectID(atomBiosHandlePtr handle, ++ CARD16 id, CARD8 *obj_type, CARD8 *obj_id, ++ CARD8 *num, char **name) ++{ ++ *obj_id = (id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; ++ *num = (id & ENUM_ID_MASK) >> ENUM_ID_SHIFT; ++ *obj_type = (id & OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT; ++ ++ *name = NULL; ++ ++ switch (*obj_type) { ++ case GRAPH_OBJECT_TYPE_CONNECTOR: ++ if (!Limit(*obj_id, n_rhd_connector_objs, "obj_id")) ++ *name = rhd_connector_objs[*obj_id].name; ++ break; ++ case GRAPH_OBJECT_TYPE_ENCODER: ++ if (!Limit(*obj_id, n_rhd_encoders, "obj_id")) ++ *name = rhd_encoders[*obj_id].name; ++ break; ++ default: ++ break; ++ } ++ return TRUE; ++} ++ ++/* ++ * ++ */ ++static void ++rhdAtomDDCFromI2CRecord(atomBiosHandlePtr handle, ++ ATOM_I2C_RECORD *Record, rhdDDC *DDC) ++{ ++ RHDDebug(handle->scrnIndex, ++ " %s: I2C Record: %s[%x] EngineID: %x I2CAddr: %x\n", ++ __func__, ++ Record->sucI2cId.bfHW_Capable ? "HW_Line" : "GPIO_ID", ++ Record->sucI2cId.bfI2C_LineMux, ++ Record->sucI2cId.bfHW_EngineID, ++ Record->ucI2CAddr); ++ ++ if (!*(unsigned char *)&(Record->sucI2cId)) ++ *DDC = RHD_DDC_NONE; ++ else { ++ ++ if (Record->ucI2CAddr != 0) ++ return; ++ ++ if (Record->sucI2cId.bfHW_Capable) { ++ ++ *DDC = (rhdDDC)Record->sucI2cId.bfI2C_LineMux; ++ if (*DDC >= RHD_DDC_MAX) ++ *DDC = RHD_DDC_NONE; ++ ++ } else { ++ *DDC = RHD_DDC_GPIO; ++ /* add GPIO pin parsing */ ++ } ++ } ++} ++ ++/* ++ * ++ */ ++static void ++rhdAtomParseGPIOLutForHPD(atomBiosHandlePtr handle, ++ CARD8 pinID, rhdHPD *HPD) ++{ ++ atomDataTablesPtr atomDataPtr; ++ ATOM_GPIO_PIN_LUT *gpio_pin_lut; ++ unsigned short size; ++ int i = 0; ++ ++ //RHDFUNC(handle); ++ ++ atomDataPtr = handle->atomDataPtr; ++ ++ *HPD = RHD_HPD_NONE; ++ ++ if (!rhdAtomGetTableRevisionAndSize( ++ &atomDataPtr->GPIO_Pin_LUT->sHeader, NULL, NULL, &size)) { ++ xf86DrvMsg(handle->scrnIndex, X_ERROR, ++ "%s: No valid GPIO pin LUT in AtomBIOS\n",__func__); ++ return; ++ } ++ gpio_pin_lut = atomDataPtr->GPIO_Pin_LUT; ++ ++ while (1) { ++ if (gpio_pin_lut->asGPIO_Pin[i].ucGPIO_ID == pinID) { ++ ++ if ((sizeof(ATOM_COMMON_TABLE_HEADER) ++ + (i * sizeof(ATOM_GPIO_PIN_ASSIGNMENT))) > size) ++ return; ++ ++ RHDDebug(handle->scrnIndex, ++ " %s: GPIO PinID: %i Index: %x Shift: %i\n", ++ __func__, ++ pinID, ++ gpio_pin_lut->asGPIO_Pin[i].usGpioPin_AIndex, ++ gpio_pin_lut->asGPIO_Pin[i].ucGpioPinBitShift); ++ ++ /* grr... map backwards: register indices -> line numbers */ ++ if (gpio_pin_lut->asGPIO_Pin[i].usGpioPin_AIndex ++ == (DC_GPIO_HPD_A >> 2)) { ++ switch (gpio_pin_lut->asGPIO_Pin[i].ucGpioPinBitShift) { ++ case 0: ++ *HPD = RHD_HPD_0; ++ return; ++ case 8: ++ *HPD = RHD_HPD_1; ++ return; ++ case 16: ++ *HPD = RHD_HPD_2; ++ return; ++ } ++ } ++ } ++ i++; ++ } ++} ++ ++/* ++ * ++ */ ++static void ++rhdAtomHPDFromRecord(atomBiosHandlePtr handle, ++ ATOM_HPD_INT_RECORD *Record, rhdHPD *HPD) ++{ ++ RHDDebug(handle->scrnIndex, ++ " %s: HPD Record: GPIO ID: %x Plugged_PinState: %x\n", ++ __func__, ++ Record->ucHPDIntGPIOID, ++ Record->ucPluggged_PinState); ++ rhdAtomParseGPIOLutForHPD(handle, Record->ucHPDIntGPIOID, HPD); ++} ++ ++/* ++ * ++ */ ++static char * ++rhdAtomDeviceTagsFromRecord(atomBiosHandlePtr handle, ++ ATOM_CONNECTOR_DEVICE_TAG_RECORD *Record) ++{ ++ int i, j, k; ++ char *devices; ++ ++ //RHDFUNC(handle); ++ ++ RHDDebug(handle->scrnIndex," NumberOfDevice: %i\n", ++ Record->ucNumberOfDevice); ++ ++ if (!Record->ucNumberOfDevice) return NULL; ++ ++ devices = (char *)xcalloc(Record->ucNumberOfDevice * 4 + 1,1); ++ ++ for (i = 0; i < Record->ucNumberOfDevice; i++) { ++ k = 0; ++ j = Record->asDeviceTag[i].usDeviceID; ++ ++ while (!(j & 0x1)) { j >>= 1; k++; }; ++ ++ if (!Limit(k,n_rhd_devices,"usDeviceID")) ++ strcat(devices, rhd_devices[k].name); ++ } ++ ++ RHDDebug(handle->scrnIndex," Devices:%s\n",devices); ++ ++ return devices; ++} ++ ++/* ++ * ++ */ ++static AtomBiosResult ++rhdAtomConnectorInfoFromObjectHeader(atomBiosHandlePtr handle, ++ rhdConnectorInfoPtr *ptr) ++{ ++ atomDataTablesPtr atomDataPtr; ++ CARD8 crev, frev; ++ ATOM_CONNECTOR_OBJECT_TABLE *con_obj; ++ rhdConnectorInfoPtr cp; ++ unsigned long object_header_end; ++ int ncon = 0; ++ int i,j; ++ unsigned short object_header_size; ++ ++ //RHDFUNC(handle); ++ ++ atomDataPtr = handle->atomDataPtr; ++ ++ if (!rhdAtomGetTableRevisionAndSize( ++ &atomDataPtr->Object_Header->sHeader, ++ &crev,&frev,&object_header_size)) { ++ return ATOM_NOT_IMPLEMENTED; ++ } ++ ++ if (crev < 2) /* don't bother with anything below rev 2 */ ++ return ATOM_NOT_IMPLEMENTED; ++ ++ if (!(cp = (rhdConnectorInfoPtr)xcalloc(sizeof(struct rhdConnectorInfo), ++ RHD_CONNECTORS_MAX))) ++ return ATOM_FAILED; ++ ++ object_header_end = ++ atomDataPtr->Object_Header->usConnectorObjectTableOffset ++ + object_header_size; ++ ++ RHDDebug(handle->scrnIndex,"ObjectTable - size: %u, BIOS - size: %u " ++ "TableOffset: %u object_header_end: %u\n", ++ object_header_size, handle->BIOSImageSize, ++ atomDataPtr->Object_Header->usConnectorObjectTableOffset, ++ object_header_end); ++ ++ if ((object_header_size > handle->BIOSImageSize) ++ || (atomDataPtr->Object_Header->usConnectorObjectTableOffset ++ > handle->BIOSImageSize) ++ || object_header_end > handle->BIOSImageSize) { ++ xf86DrvMsg(handle->scrnIndex, X_ERROR, ++ "%s: Object table information is bogus\n",__func__); ++ return ATOM_FAILED; ++ } ++ ++ if (((unsigned long)&atomDataPtr->Object_Header->sHeader ++ + object_header_end) > ((unsigned long)handle->BIOSBase ++ + handle->BIOSImageSize)) { ++ xf86DrvMsg(handle->scrnIndex, X_ERROR, ++ "%s: Object table extends beyond BIOS Image\n",__func__); ++ return ATOM_FAILED; ++ } ++ ++ con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *) ++ ((char *)&atomDataPtr->Object_Header->sHeader + ++ atomDataPtr->Object_Header->usConnectorObjectTableOffset); ++ ++ for (i = 0; i < con_obj->ucNumberOfObjects; i++) { ++ ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *SrcDstTable; ++ ATOM_COMMON_RECORD_HEADER *Record; ++ int record_base; ++ CARD8 obj_type, obj_id, num; ++ char *name; ++ int nout = 0; ++ ++ rhdAtomInterpretObjectID(handle, con_obj->asObjects[i].usObjectID, ++ &obj_type, &obj_id, &num, &name); ++ ++ RHDDebug(handle->scrnIndex, "Object: ID: %x name: %s type: %x id: %x\n", ++ con_obj->asObjects[i].usObjectID, name ? name : "", ++ obj_type, obj_id); ++ ++ ++ if (obj_type != GRAPH_OBJECT_TYPE_CONNECTOR) ++ continue; ++ ++ SrcDstTable = (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *) ++ ((char *)&atomDataPtr->Object_Header->sHeader ++ + con_obj->asObjects[i].usSrcDstTableOffset); ++ ++ if (con_obj->asObjects[i].usSrcDstTableOffset ++ + (SrcDstTable->ucNumberOfSrc ++ * sizeof(ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT)) ++ > handle->BIOSImageSize) { ++ xf86DrvMsg(handle->scrnIndex, X_ERROR, "%s: SrcDstTable[%i] extends " ++ "beyond Object_Header table\n",__func__,i); ++ continue; ++ } ++ ++ cp[ncon].Type = rhd_connector_objs[obj_id].con; ++ cp[ncon].Name = RhdAppendString(cp[ncon].Name,name); ++ ++ for (j = 0; j < SrcDstTable->ucNumberOfSrc; j++) { ++ CARD8 stype, sobj_id, snum; ++ char *sname; ++ ++ rhdAtomInterpretObjectID(handle, SrcDstTable->usSrcObjectID[j], ++ &stype, &sobj_id, &snum, &sname); ++ ++ RHDDebug(handle->scrnIndex, " * SrcObject: ID: %x name: %s\n", ++ SrcDstTable->usSrcObjectID[j], sname); ++ ++ cp[ncon].Output[nout] = rhd_encoders[sobj_id].ot; ++ if (++nout >= MAX_OUTPUTS_PER_CONNECTOR) ++ break; ++ } ++ ++ Record = (ATOM_COMMON_RECORD_HEADER *) ++ ((char *)&atomDataPtr->Object_Header->sHeader ++ + con_obj->asObjects[i].usRecordOffset); ++ ++ record_base = con_obj->asObjects[i].usRecordOffset; ++ ++ while (Record->ucRecordType > 0 ++ && Record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER ) { ++ char *taglist; ++ ++ if ((record_base += Record->ucRecordSize) ++ > object_header_size) { ++ xf86DrvMsg(handle->scrnIndex, X_ERROR, ++ "%s: Object Records extend beyond Object Table\n", ++ __func__); ++ break; ++ } ++ ++ RHDDebug(handle->scrnIndex, " - Record Type: %x\n", ++ Record->ucRecordType); ++ ++ switch (Record->ucRecordType) { ++ ++ case ATOM_I2C_RECORD_TYPE: ++ rhdAtomDDCFromI2CRecord(handle, ++ (ATOM_I2C_RECORD *)Record, ++ &cp[ncon].DDC); ++ break; ++ ++ case ATOM_HPD_INT_RECORD_TYPE: ++ rhdAtomHPDFromRecord(handle, ++ (ATOM_HPD_INT_RECORD *)Record, ++ &cp[ncon].HPD); ++ break; ++ ++ case ATOM_CONNECTOR_DEVICE_TAG_RECORD_TYPE: ++ taglist = rhdAtomDeviceTagsFromRecord(handle, ++ (ATOM_CONNECTOR_DEVICE_TAG_RECORD *)Record); ++ if (taglist) { ++ cp[ncon].Name = RhdAppendString(cp[ncon].Name,taglist); ++ xfree(taglist); ++ } ++ break; ++ ++ default: ++ break; ++ } ++ ++ Record = (ATOM_COMMON_RECORD_HEADER*) ++ ((char *)Record + Record->ucRecordSize); ++ ++ } ++ ++ if ((++ncon) == RHD_CONNECTORS_MAX) ++ break; ++ } ++ *ptr = cp; ++ ++ RhdPrintConnectorInfo(handle->scrnIndex, cp); ++ ++ return ATOM_SUCCESS; ++} ++ ++/* ++ * ++ */ ++static AtomBiosResult ++rhdAtomConnectorInfoFromSupportedDevices(atomBiosHandlePtr handle, ++ rhdConnectorInfoPtr *ptr) ++{ ++ atomDataTablesPtr atomDataPtr; ++ CARD8 crev, frev; ++ rhdConnectorInfoPtr cp; ++ struct { ++ rhdOutputType ot; ++ rhdConnectorType con; ++ rhdDDC ddc; ++ rhdHPD hpd; ++ Bool dual; ++ char *name; ++ char *outputName; ++ } devices[ATOM_MAX_SUPPORTED_DEVICE]; ++ int ncon = 0; ++ int n; ++ ++ //RHDFUNC(handle); ++ ++ atomDataPtr = handle->atomDataPtr; ++ ++ if (!rhdAtomGetTableRevisionAndSize( ++ &(atomDataPtr->SupportedDevicesInfo.SupportedDevicesInfo->sHeader), ++ &crev,&frev,NULL)) { ++ return ATOM_NOT_IMPLEMENTED; ++ } ++ ++ if (!(cp = (rhdConnectorInfoPtr)xcalloc(RHD_CONNECTORS_MAX, ++ sizeof(struct rhdConnectorInfo)))) ++ return ATOM_FAILED; ++ ++ for (n = 0; n < ATOM_MAX_SUPPORTED_DEVICE; n++) { ++ ATOM_CONNECTOR_INFO_I2C ci ++ = atomDataPtr->SupportedDevicesInfo.SupportedDevicesInfo->asConnInfo[n]; ++ ++ devices[n].ot = OUTPUT_NONE_ATOM; ++ ++ if (!(atomDataPtr->SupportedDevicesInfo ++ .SupportedDevicesInfo->usDeviceSupport & (1 << n))) ++ continue; ++ ++ if (Limit(ci.sucConnectorInfo.sbfAccess.bfConnectorType, ++ n_rhd_connectors, "bfConnectorType")) ++ continue; ++ ++ devices[n].con ++ = rhd_connectors[ci.sucConnectorInfo.sbfAccess.bfConnectorType].con; ++ if (devices[n].con == RHD_CONNECTOR_NONE) ++ continue; ++ ++ devices[n].dual ++ = rhd_connectors[ci.sucConnectorInfo.sbfAccess.bfConnectorType].dual; ++ devices[n].name ++ = rhd_connectors[ci.sucConnectorInfo.sbfAccess.bfConnectorType].name; ++ ++ RHDDebug(handle->scrnIndex,"AtomBIOS Connector[%i]: %s Device:%s ",n, ++ rhd_connectors[ci.sucConnectorInfo ++ .sbfAccess.bfConnectorType].name, ++ rhd_devices[n].name); ++ ++ devices[n].outputName = rhd_devices[n].name; ++ ++ if (!Limit(ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC, ++ n_acc_dac, "bfAssociatedDAC")) { ++ if ((devices[n].ot ++ = acc_dac[ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC]) ++ == OUTPUT_NONE_ATOM) { ++ devices[n].ot = rhd_devices[n].ot; ++ } ++ } else ++ devices[n].ot = OUTPUT_NONE_ATOM; ++ ++ RHDDebugCont("Output: %x ",devices[n].ot); ++ ++ if (ci.sucI2cId.sbfAccess.bfHW_Capable) { ++ ++ RHDDebugCont("HW DDC %i ", ++ ci.sucI2cId.sbfAccess.bfI2C_LineMux); ++ ++ if (Limit(ci.sucI2cId.sbfAccess.bfI2C_LineMux, ++ n_hwddc, "bfI2C_LineMux")) ++ devices[n].ddc = RHD_DDC_NONE; ++ else ++ devices[n].ddc = hwddc[ci.sucI2cId.sbfAccess.bfI2C_LineMux]; ++ ++ } else if (ci.sucI2cId.sbfAccess.bfI2C_LineMux) { ++ ++ RHDDebugCont("GPIO DDC "); ++ devices[n].ddc = RHD_DDC_GPIO; ++ ++ /* add support for GPIO line */ ++ } else { ++ ++ RHDDebugCont("NO DDC "); ++ devices[n].ddc = RHD_DDC_NONE; ++ ++ } ++ ++ if (crev > 1) { ++ ATOM_CONNECTOR_INC_SRC_BITMAP isb ++ = atomDataPtr->SupportedDevicesInfo ++ .SupportedDevicesInfo_HD->asIntSrcInfo[n]; ++ ++ switch (isb.ucIntSrcBitmap) { ++ case 0x4: ++ RHDDebugCont("HPD 0\n"); ++ devices[n].hpd = RHD_HPD_0; ++ break; ++ case 0xa: ++ RHDDebugCont("HPD 1\n"); ++ devices[n].hpd = RHD_HPD_1; ++ break; ++ default: ++ RHDDebugCont("NO HPD\n"); ++ devices[n].hpd = RHD_HPD_NONE; ++ break; ++ } ++ } else { ++ RHDDebugCont("NO HPD\n"); ++ devices[n].hpd = RHD_HPD_NONE; ++ } ++ } ++ /* sort devices for connectors */ ++ for (n = 0; n < ATOM_MAX_SUPPORTED_DEVICE; n++) { ++ int i; ++ ++ if (devices[n].ot == OUTPUT_NONE_ATOM) ++ continue; ++ if (devices[n].con == CONNECTOR_NONE_ATOM) ++ continue; ++ ++ cp[ncon].DDC = devices[n].ddc; ++ cp[ncon].HPD = devices[n].hpd; ++ cp[ncon].Output[0] = devices[n].ot; ++ cp[ncon].Output[1] = OUTPUT_NONE_ATOM; ++ cp[ncon].Type = devices[n].con; ++ cp[ncon].Name = xf86strdup(devices[n].name); ++ cp[ncon].Name = RhdAppendString(cp[ncon].Name, devices[n].outputName); ++ ++ if (devices[n].dual) { ++ if (devices[n].ddc == RHD_DDC_NONE) ++ xf86DrvMsg(handle->scrnIndex, X_ERROR, ++ "No DDC channel for device %s found." ++ " Cannot find matching device.\n",devices[n].name); ++ else { ++ for (i = n + 1; i < ATOM_MAX_SUPPORTED_DEVICE; i++) { ++ ++ if (!devices[i].dual) ++ continue; ++ ++ if (devices[n].ddc != devices[i].ddc) ++ continue; ++ ++ if (((devices[n].ot == OUTPUT_DACA_ATOM ++ || devices[n].ot == OUTPUT_DACB_ATOM) ++ && (devices[i].ot == OUTPUT_LVTMA_ATOM ++ || devices[i].ot == OUTPUT_TMDSA_ATOM)) ++ || ((devices[i].ot == OUTPUT_DACA_ATOM ++ || devices[i].ot == OUTPUT_DACB_ATOM) ++ && (devices[n].ot == OUTPUT_LVTMA_ATOM ++ || devices[n].ot == OUTPUT_TMDSA_ATOM))) { ++ ++ cp[ncon].Output[1] = devices[i].ot; ++ ++ if (cp[ncon].HPD == RHD_HPD_NONE) ++ cp[ncon].HPD = devices[i].hpd; ++ ++ cp[ncon].Name = RhdAppendString(cp[ncon].Name, ++ devices[i].outputName); ++ devices[i].ot = OUTPUT_NONE_ATOM; /* zero the device */ ++ } ++ } ++ } ++ } ++ ++ if ((++ncon) == RHD_CONNECTORS_MAX) ++ break; ++ } ++ *ptr = cp; ++ ++ RhdPrintConnectorInfo(handle->scrnIndex, cp); ++ ++ return ATOM_SUCCESS; ++} ++ ++/* ++ * ++ */ ++static AtomBiosResult ++rhdAtomConnectorInfo(atomBiosHandlePtr handle, ++ AtomBiosRequestID unused, AtomBiosArgPtr data) ++{ ++ data->connectorInfo = NULL; ++ ++ if (rhdAtomConnectorInfoFromObjectHeader(handle,&data->connectorInfo) ++ == ATOM_SUCCESS) ++ return ATOM_SUCCESS; ++ else ++ return rhdAtomConnectorInfoFromSupportedDevices(handle, ++ &data->connectorInfo); ++} ++#endif ++ ++# ifdef ATOM_BIOS_PARSER ++static AtomBiosResult ++rhdAtomExec (atomBiosHandlePtr handle, ++ AtomBiosRequestID unused, AtomBiosArgPtr data) ++{ ++ RADEONInfoPtr info = RADEONPTR (xf86Screens[handle->scrnIndex]); ++ Bool ret = FALSE; ++ char *msg; ++ int idx = data->exec.index; ++ void *pspace = data->exec.pspace; ++ pointer *dataSpace = data->exec.dataSpace; ++ ++ //RHDFUNCI(handle->scrnIndex); ++ ++ if (dataSpace) { ++ if (!handle->fbBase && !handle->scratchBase) ++ return ATOM_FAILED; ++ if (handle->fbBase) { ++ if (!info->FB) { ++ xf86DrvMsg(handle->scrnIndex, X_ERROR, "%s: " ++ "Cannot exec AtomBIOS: framebuffer not mapped\n", ++ __func__); ++ return ATOM_FAILED; ++ } ++ *dataSpace = (CARD8*)info->FB + handle->fbBase; ++ } else ++ *dataSpace = (CARD8*)handle->scratchBase; ++ } ++ ret = ParseTableWrapper(pspace, idx, handle, ++ handle->BIOSBase, ++ &msg); ++ if (!ret) ++ xf86DrvMsg(handle->scrnIndex, X_ERROR, "%s\n",msg); ++ else ++ xf86DrvMsgVerb(handle->scrnIndex, X_INFO, 5, "%s\n",msg); ++ ++ return (ret) ? ATOM_SUCCESS : ATOM_FAILED; ++} ++# endif ++ ++AtomBiosResult ++RHDAtomBiosFunc(int scrnIndex, atomBiosHandlePtr handle, ++ AtomBiosRequestID id, AtomBiosArgPtr data) ++{ ++ AtomBiosResult ret = ATOM_FAILED; ++ int i; ++ char *msg = NULL; ++ enum msgDataFormat msg_f = MSG_FORMAT_NONE; ++ AtomBiosRequestFunc req_func = NULL; ++ ++ //RHDFUNCI(scrnIndex); ++ ++ for (i = 0; AtomBiosRequestList[i].id != FUNC_END; i++) { ++ if (id == AtomBiosRequestList[i].id) { ++ req_func = AtomBiosRequestList[i].request; ++ msg = AtomBiosRequestList[i].message; ++ msg_f = AtomBiosRequestList[i].message_format; ++ break; ++ } ++ } ++ ++ if (req_func == NULL) { ++ xf86DrvMsg(scrnIndex, X_ERROR, "Unknown AtomBIOS request: %i\n",id); ++ return ATOM_NOT_IMPLEMENTED; ++ } ++ /* Hack for now */ ++ if (id == ATOMBIOS_INIT) ++ data->val = scrnIndex; ++ ++ if (id == ATOMBIOS_INIT || handle) ++ ret = req_func(handle, id, data); ++ ++ if (ret == ATOM_SUCCESS) { ++ ++ switch (msg_f) { ++ case MSG_FORMAT_DEC: ++ xf86DrvMsg(scrnIndex,X_INFO,"%s: %li\n", msg, ++ (unsigned long) data->val); ++ break; ++ case MSG_FORMAT_HEX: ++ xf86DrvMsg(scrnIndex,X_INFO,"%s: 0x%lx\n",msg , ++ (unsigned long) data->val); ++ break; ++ case MSG_FORMAT_NONE: ++ xf86DrvMsgVerb(scrnIndex, 7, X_INFO, ++ "Call to %s succeeded\n", msg); ++ break; ++ } ++ ++ } else { ++ ++ char *result = (ret == ATOM_FAILED) ? "failed" ++ : "not implemented"; ++ switch (msg_f) { ++ case MSG_FORMAT_DEC: ++ case MSG_FORMAT_HEX: ++ xf86DrvMsgVerb(scrnIndex, 1, X_WARNING, ++ "Call to %s %s\n", msg, result); ++ break; ++ case MSG_FORMAT_NONE: ++ xf86DrvMsg(scrnIndex,X_INFO,"Query for %s: %s\n", msg, result); ++ break; ++ } ++ } ++ return ret; ++} ++ ++# ifdef ATOM_BIOS_PARSER ++VOID* ++CailAllocateMemory(VOID *CAIL,UINT16 size) ++{ ++ CAILFUNC(CAIL); ++ ++ return malloc(size); ++} ++ ++VOID ++CailReleaseMemory(VOID *CAIL, VOID *addr) ++{ ++ CAILFUNC(CAIL); ++ ++ free(addr); ++} ++ ++VOID ++CailDelayMicroSeconds(VOID *CAIL, UINT32 delay) ++{ ++ CAILFUNC(CAIL); ++ ++ usleep(delay); ++ ++ DEBUGP(xf86DrvMsg(((atomBiosHandlePtr)CAIL)->scrnIndex,X_INFO,"Delay %i usec\n",delay)); ++} ++ ++UINT32 ++CailReadATIRegister(VOID* CAIL, UINT32 idx) ++{ ++ ScrnInfoPtr pScrn = xf86Screens[((atomBiosHandlePtr)CAIL)->scrnIndex]; ++ RADEONInfoPtr info = RADEONPTR(pScrn); ++ unsigned char *RADEONMMIO = info->MMIO; ++ UINT32 ret; ++ CAILFUNC(CAIL); ++ ++ ret = INREG(idx << 2); ++ DEBUGP(ErrorF("%s(%x) = %x\n",__func__,idx << 2,ret)); ++ return ret; ++} ++ ++VOID ++CailWriteATIRegister(VOID *CAIL, UINT32 idx, UINT32 data) ++{ ++ ScrnInfoPtr pScrn = xf86Screens[((atomBiosHandlePtr)CAIL)->scrnIndex]; ++ RADEONInfoPtr info = RADEONPTR(pScrn); ++ unsigned char *RADEONMMIO = info->MMIO; ++ CAILFUNC(CAIL); ++ ++ OUTREG(idx << 2,data); ++ DEBUGP(ErrorF("%s(%x,%x)\n",__func__,idx << 2,data)); ++} ++ ++UINT32 ++CailReadFBData(VOID* CAIL, UINT32 idx) ++{ ++ ScrnInfoPtr pScrn = xf86Screens[((atomBiosHandlePtr)CAIL)->scrnIndex]; ++ RADEONInfoPtr info = RADEONPTR(pScrn); ++ UINT32 ret; ++ ++ CAILFUNC(CAIL); ++ ++ if (((atomBiosHandlePtr)CAIL)->fbBase) { ++ CARD8 *FBBase = (CARD8*)info->FB; ++ ret = *((CARD32*)(FBBase + (((atomBiosHandlePtr)CAIL)->fbBase) + idx)); ++ DEBUGP(ErrorF("%s(%x) = %x\n",__func__,idx,ret)); ++ } else if (((atomBiosHandlePtr)CAIL)->scratchBase) { ++ ret = *(CARD32*)((CARD8*)(((atomBiosHandlePtr)CAIL)->scratchBase) + idx); ++ DEBUGP(ErrorF("%s(%x) = %x\n",__func__,idx,ret)); ++ } else { ++ xf86DrvMsg(((atomBiosHandlePtr)CAIL)->scrnIndex,X_ERROR, ++ "%s: no fbbase set\n",__func__); ++ return 0; ++ } ++ return ret; ++} ++ ++VOID ++CailWriteFBData(VOID *CAIL, UINT32 idx, UINT32 data) ++{ ++ CAILFUNC(CAIL); ++ ++ DEBUGP(ErrorF("%s(%x,%x)\n",__func__,idx,data)); ++ if (((atomBiosHandlePtr)CAIL)->fbBase) { ++ CARD8 *FBBase = (CARD8*) ++ RADEONPTR(xf86Screens[((atomBiosHandlePtr)CAIL)->scrnIndex])->FB; ++ *((CARD32*)(FBBase + (((atomBiosHandlePtr)CAIL)->fbBase) + idx)) = data; ++ } else if (((atomBiosHandlePtr)CAIL)->scratchBase) { ++ *(CARD32*)((CARD8*)(((atomBiosHandlePtr)CAIL)->scratchBase) + idx) = data; ++ } else ++ xf86DrvMsg(((atomBiosHandlePtr)CAIL)->scrnIndex,X_ERROR, ++ "%s: no fbbase set\n",__func__); ++} ++ ++ULONG ++CailReadMC(VOID *CAIL, ULONG Address) ++{ ++ ScrnInfoPtr pScrn = xf86Screens[((atomBiosHandlePtr)CAIL)->scrnIndex]; ++ ULONG ret; ++ ++ CAILFUNC(CAIL); ++ ++ ret = INMC(pScrn, Address); ++ DEBUGP(ErrorF("%s(%x) = %x\n",__func__,Address,ret)); ++ return ret; ++} ++ ++VOID ++CailWriteMC(VOID *CAIL, ULONG Address, ULONG data) ++{ ++ ScrnInfoPtr pScrn = xf86Screens[((atomBiosHandlePtr)CAIL)->scrnIndex]; ++ ++ CAILFUNC(CAIL); ++ DEBUGP(ErrorF("%s(%x,%x)\n",__func__,Address,data)); ++ OUTMC(pScrn, Address, data); ++} ++ ++#ifdef XSERVER_LIBPCIACCESS ++ ++VOID ++CailReadPCIConfigData(VOID*CAIL, VOID* ret, UINT32 idx,UINT16 size) ++{ ++ pci_device_cfg_read(RADEONPTR(xf86Screens[((atomBiosHandlePtr)CAIL)->scrnIndex])->PciInfo, ++ ret,idx << 2 , size >> 3, NULL); ++} ++ ++VOID ++CailWritePCIConfigData(VOID*CAIL,VOID*src,UINT32 idx,UINT16 size) ++{ ++ pci_device_cfg_write(RADEONPTR(xf86Screens[((atomBiosHandlePtr)CAIL)->scrnIndex])->PciInfo, ++ src, idx << 2, size >> 3, NULL); ++} ++ ++#else ++ ++VOID ++CailReadPCIConfigData(VOID*CAIL, VOID* ret, UINT32 idx,UINT16 size) ++{ ++ PCITAG tag = ((atomBiosHandlePtr)CAIL)->PciTag; ++ ++ CAILFUNC(CAIL); ++ ++ switch (size) { ++ case 8: ++ *(CARD8*)ret = pciReadByte(tag,idx << 2); ++ break; ++ case 16: ++ *(CARD16*)ret = pciReadWord(tag,idx << 2); ++ break; ++ case 32: ++ *(CARD32*)ret = pciReadLong(tag,idx << 2); ++ break; ++ default: ++ xf86DrvMsg(((atomBiosHandlePtr)CAIL)->scrnIndex, ++ X_ERROR,"%s: Unsupported size: %i\n", ++ __func__,(int)size); ++ return; ++ break; ++ } ++ DEBUGP(ErrorF("%s(%x) = %x\n",__func__,idx,*(unsigned int*)ret)); ++ ++} ++ ++VOID ++CailWritePCIConfigData(VOID*CAIL,VOID*src,UINT32 idx,UINT16 size) ++{ ++ PCITAG tag = ((atomBiosHandlePtr)CAIL)->PciTag; ++ ++ CAILFUNC(CAIL); ++ DEBUGP(ErrorF("%s(%x,%x)\n",__func__,idx,(*(unsigned int*)src))); ++ switch (size) { ++ case 8: ++ pciWriteByte(tag,idx << 2,*(CARD8*)src); ++ break; ++ case 16: ++ pciWriteWord(tag,idx << 2,*(CARD16*)src); ++ break; ++ case 32: ++ pciWriteLong(tag,idx << 2,*(CARD32*)src); ++ break; ++ default: ++ xf86DrvMsg(((atomBiosHandlePtr)CAIL)->scrnIndex,X_ERROR, ++ "%s: Unsupported size: %i\n",__func__,(int)size); ++ break; ++ } ++} ++#endif ++ ++ULONG ++CailReadPLL(VOID *CAIL, ULONG Address) ++{ ++ ScrnInfoPtr pScrn = xf86Screens[((atomBiosHandlePtr)CAIL)->scrnIndex]; ++ ULONG ret; ++ ++ CAILFUNC(CAIL); ++ ++ ret = RADEONINPLL(pScrn, Address); ++ DEBUGP(ErrorF("%s(%x) = %x\n",__func__,Address,ret)); ++ return ret; ++} ++ ++VOID ++CailWritePLL(VOID *CAIL, ULONG Address,ULONG Data) ++{ ++ ScrnInfoPtr pScrn = xf86Screens[((atomBiosHandlePtr)CAIL)->scrnIndex]; ++ CAILFUNC(CAIL); ++ ++ DEBUGP(ErrorF("%s(%x,%x)\n",__func__,Address,Data)); ++ RADEONOUTPLL(pScrn, Address, Data); ++} ++ ++void ++atombios_get_command_table_version(atomBiosHandlePtr atomBIOS, int index, int *major, int *minor) ++{ ++ ATOM_MASTER_COMMAND_TABLE *cmd_table = (void *)(atomBIOS->BIOSBase + atomBIOS->cmd_offset); ++ ATOM_MASTER_LIST_OF_COMMAND_TABLES *table_start; ++ ATOM_COMMON_ROM_COMMAND_TABLE_HEADER *table_hdr; ++ ++ //unsigned short *ptr; ++ unsigned short offset; ++ ++ table_start = &cmd_table->ListOfCommandTables; ++ ++ offset = *(((unsigned short *)table_start) + index); ++ ++ table_hdr = (ATOM_COMMON_ROM_COMMAND_TABLE_HEADER *)(atomBIOS->BIOSBase + offset); ++ ++ *major = table_hdr->CommonHeader.ucTableFormatRevision; ++ *minor = table_hdr->CommonHeader.ucTableContentRevision; ++} ++ ++ ++#endif /* ATOM_BIOS */ +diff --git a/src/radeon_atombios.h b/src/radeon_atombios.h +new file mode 100644 +index 0000000..33925a5 +--- /dev/null ++++ b/src/radeon_atombios.h +@@ -0,0 +1,235 @@ ++/* ++ * Copyright 2007 Egbert Eich ++ * Copyright 2007 Luc Verhaegen ++ * Copyright 2007 Matthias Hopf ++ * Copyright 2007 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in ++ * all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++ ++#ifndef RHD_ATOMBIOS_H_ ++# define RHD_ATOMBIOS_H_ ++ ++//#include "radeon.h" ++ ++# ifdef ATOM_BIOS ++ ++typedef enum _AtomBiosRequestID { ++ ATOMBIOS_INIT, ++ ATOMBIOS_TEARDOWN, ++# ifdef ATOM_BIOS_PARSER ++ ATOMBIOS_EXEC, ++#endif ++ ATOMBIOS_ALLOCATE_FB_SCRATCH, ++ ATOMBIOS_GET_CONNECTORS, ++ ATOMBIOS_GET_PANEL_MODE, ++ ATOMBIOS_GET_PANEL_EDID, ++ GET_DEFAULT_ENGINE_CLOCK, ++ GET_DEFAULT_MEMORY_CLOCK, ++ GET_MAX_PIXEL_CLOCK_PLL_OUTPUT, ++ GET_MIN_PIXEL_CLOCK_PLL_OUTPUT, ++ GET_MAX_PIXEL_CLOCK_PLL_INPUT, ++ GET_MIN_PIXEL_CLOCK_PLL_INPUT, ++ GET_MAX_PIXEL_CLK, ++ GET_REF_CLOCK, ++ GET_FW_FB_START, ++ GET_FW_FB_SIZE, ++ ATOM_TMDS_FREQUENCY, ++ ATOM_TMDS_PLL_CHARGE_PUMP, ++ ATOM_TMDS_PLL_DUTY_CYCLE, ++ ATOM_TMDS_PLL_VCO_GAIN, ++ ATOM_TMDS_PLL_VOLTAGE_SWING, ++ ATOM_LVDS_SUPPORTED_REFRESH_RATE, ++ ATOM_LVDS_OFF_DELAY, ++ ATOM_LVDS_SEQ_DIG_ONTO_DE, ++ ATOM_LVDS_SEQ_DE_TO_BL, ++ ATOM_LVDS_DITHER, ++ ATOM_LVDS_DUALLINK, ++ ATOM_LVDS_24BIT, ++ ATOM_LVDS_GREYLVL, ++ ATOM_LVDS_FPDI, ++ ATOM_GPIO_QUERIES, ++ ATOM_GPIO_I2C_CLK_MASK, ++ ATOM_DAC1_BG_ADJ, ++ ATOM_DAC1_DAC_ADJ, ++ ATOM_DAC1_FORCE, ++ ATOM_DAC2_CRTC2_BG_ADJ, ++ ATOM_DAC2_CRTC2_DAC_ADJ, ++ ATOM_DAC2_CRTC2_FORCE, ++ ATOM_DAC2_CRTC2_MUX_REG_IND, ++ ATOM_DAC2_CRTC2_MUX_REG_INFO, ++ FUNC_END ++} AtomBiosRequestID; ++ ++typedef enum _AtomBiosResult { ++ ATOM_SUCCESS, ++ ATOM_FAILED, ++ ATOM_NOT_IMPLEMENTED ++} AtomBiosResult; ++ ++typedef struct AtomExec { ++ int index; ++ pointer pspace; ++ pointer *dataSpace; ++} AtomExecRec, *AtomExecPtr; ++ ++typedef struct AtomFb { ++ unsigned int start; ++ unsigned int size; ++} AtomFbRec, *AtomFbPtr; ++ ++typedef union AtomBiosArg ++{ ++ CARD32 val; ++ struct rhdConnectorInfo *connectorInfo; ++ unsigned char* EDIDBlock; ++ atomBiosHandlePtr atomhandle; ++ DisplayModePtr mode; ++ AtomExecRec exec; ++ AtomFbRec fb; ++} AtomBiosArgRec, *AtomBiosArgPtr; ++ ++extern AtomBiosResult ++RHDAtomBiosFunc(int scrnIndex, atomBiosHandlePtr handle, ++ AtomBiosRequestID id, AtomBiosArgPtr data); ++ ++# include "xf86int10.h" ++# ifdef ATOM_BIOS_PARSER ++# define INT8 INT8 ++# define INT16 INT16 ++# define INT32 INT32 ++# include "CD_Common_Types.h" ++# else ++# ifndef ULONG ++typedef unsigned int ULONG; ++# define ULONG ULONG ++# endif ++# ifndef UCHAR ++typedef unsigned char UCHAR; ++# define UCHAR UCHAR ++# endif ++# ifndef USHORT ++typedef unsigned short USHORT; ++# define USHORT USHORT ++# endif ++# endif ++ ++# include "atombios.h" ++# include "ObjectID.h" ++ ++ ++/* ++ * This works around a bug in atombios.h where ++ * ATOM_MAX_SUPPORTED_DEVICE_INFO is specified incorrectly. ++ */ ++ ++#define ATOM_MAX_SUPPORTED_DEVICE_INFO_HD (ATOM_DEVICE_RESERVEDF_INDEX+1) ++typedef struct _ATOM_SUPPORTED_DEVICES_INFO_HD ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ USHORT usDeviceSupport; ++ ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_HD]; ++ ATOM_CONNECTOR_INC_SRC_BITMAP asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_HD]; ++} ATOM_SUPPORTED_DEVICES_INFO_HD; ++ ++typedef struct _atomDataTables ++{ ++ unsigned char *UtilityPipeLine; ++ ATOM_MULTIMEDIA_CAPABILITY_INFO *MultimediaCapabilityInfo; ++ ATOM_MULTIMEDIA_CONFIG_INFO *MultimediaConfigInfo; ++ ATOM_STANDARD_VESA_TIMING *StandardVESA_Timing; ++ union { ++ void *base; ++ ATOM_FIRMWARE_INFO *FirmwareInfo; ++ ATOM_FIRMWARE_INFO_V1_2 *FirmwareInfo_V_1_2; ++ ATOM_FIRMWARE_INFO_V1_3 *FirmwareInfo_V_1_3; ++ ATOM_FIRMWARE_INFO_V1_4 *FirmwareInfo_V_1_4; ++ } FirmwareInfo; ++ ATOM_DAC_INFO *DAC_Info; ++ union { ++ void *base; ++ ATOM_LVDS_INFO *LVDS_Info; ++ ATOM_LVDS_INFO_V12 *LVDS_Info_v12; ++ } LVDS_Info; ++ ATOM_TMDS_INFO *TMDS_Info; ++ ATOM_ANALOG_TV_INFO *AnalogTV_Info; ++ union { ++ void *base; ++ ATOM_SUPPORTED_DEVICES_INFO *SupportedDevicesInfo; ++ ATOM_SUPPORTED_DEVICES_INFO_2 *SupportedDevicesInfo_2; ++ ATOM_SUPPORTED_DEVICES_INFO_2d1 *SupportedDevicesInfo_2d1; ++ ATOM_SUPPORTED_DEVICES_INFO_HD *SupportedDevicesInfo_HD; ++ } SupportedDevicesInfo; ++ ATOM_GPIO_I2C_INFO *GPIO_I2C_Info; ++ ATOM_VRAM_USAGE_BY_FIRMWARE *VRAM_UsageByFirmware; ++ ATOM_GPIO_PIN_LUT *GPIO_Pin_LUT; ++ ATOM_VESA_TO_INTENAL_MODE_LUT *VESA_ToInternalModeLUT; ++ union { ++ void *base; ++ ATOM_COMPONENT_VIDEO_INFO *ComponentVideoInfo; ++ ATOM_COMPONENT_VIDEO_INFO_V21 *ComponentVideoInfo_v21; ++ } ComponentVideoInfo; ++/**/unsigned char *PowerPlayInfo; ++ COMPASSIONATE_DATA *CompassionateData; ++ ATOM_DISPLAY_DEVICE_PRIORITY_INFO *SaveRestoreInfo; ++/**/unsigned char *PPLL_SS_Info; ++ ATOM_OEM_INFO *OemInfo; ++ ATOM_XTMDS_INFO *XTMDS_Info; ++ ATOM_ASIC_MVDD_INFO *MclkSS_Info; ++ ATOM_OBJECT_HEADER *Object_Header; ++ INDIRECT_IO_ACCESS *IndirectIOAccess; ++ ATOM_MC_INIT_PARAM_TABLE *MC_InitParameter; ++/**/unsigned char *ASIC_VDDC_Info; ++ ATOM_ASIC_INTERNAL_SS_INFO *ASIC_InternalSS_Info; ++/**/unsigned char *TV_VideoMode; ++ union { ++ void *base; ++ ATOM_VRAM_INFO_V2 *VRAM_Info_v2; ++ ATOM_VRAM_INFO_V3 *VRAM_Info_v3; ++ } VRAM_Info; ++ ATOM_MEMORY_TRAINING_INFO *MemoryTrainingInfo; ++ union { ++ void *base; ++ ATOM_INTEGRATED_SYSTEM_INFO *IntegratedSystemInfo; ++ ATOM_INTEGRATED_SYSTEM_INFO_V2 *IntegratedSystemInfo_v2; ++ } IntegratedSystemInfo; ++ ATOM_ASIC_PROFILING_INFO *ASIC_ProfilingInfo; ++ ATOM_VOLTAGE_OBJECT_INFO *VoltageObjectInfo; ++ ATOM_POWER_SOURCE_INFO *PowerSourceInfo; ++} atomDataTables, *atomDataTablesPtr; ++ ++typedef struct _atomBiosHandle { ++ int scrnIndex; ++ unsigned char *BIOSBase; ++ atomDataTablesPtr atomDataPtr; ++ unsigned int cmd_offset; ++ pointer *scratchBase; ++ CARD32 fbBase; ++#if XSERVER_LIBPCIACCESS ++ struct pci_device *device; ++#else ++ PCITAG PciTag; ++#endif ++ unsigned int BIOSImageSize; ++} atomBiosHandleRec; ++ ++# endif ++ ++#endif /* RHD_ATOMBIOS_H_ */ +diff --git a/src/radeon_atomwrapper.c b/src/radeon_atomwrapper.c +new file mode 100644 +index 0000000..259366c +--- /dev/null ++++ b/src/radeon_atomwrapper.c +@@ -0,0 +1,101 @@ ++/* ++ * Copyright 2007 Luc Verhaegen ++ * Copyright 2007 Matthias Hopf ++ * Copyright 2007 Egbert Eich ++ * Copyright 2007 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in ++ * all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++#ifdef HAVE_CONFIG_H ++# include "config.h" ++#endif ++ ++//#include "radeon_atomwrapper.h" ++ ++#define INT32 INT32 ++#include "CD_Common_Types.h" ++#include "CD_Definitions.h" ++ ++ ++int ++ParseTableWrapper(void *pspace, int index, void *handle, void *BIOSBase, ++ char **msg_return) ++{ ++ DEVICE_DATA deviceData; ++ int ret = 0; ++ ++ /* FILL OUT PARAMETER SPACE */ ++ deviceData.pParameterSpace = (UINT32*) pspace; ++ deviceData.CAIL = handle; ++ deviceData.pBIOS_Image = BIOSBase; ++ deviceData.format = TABLE_FORMAT_BIOS; ++ ++ switch (ParseTable(&deviceData, index)) { /* IndexInMasterTable */ ++ case CD_SUCCESS: ++ ret = 1; ++ *msg_return = "ParseTable said: CD_SUCCESS"; ++ break; ++ case CD_CALL_TABLE: ++ ret = 1; ++ *msg_return = "ParseTable said: CD_CALL_TABLE"; ++ break; ++ case CD_COMPLETED: ++ ret = 1; ++ *msg_return = "ParseTable said: CD_COMPLETED"; ++ break; ++ case CD_GENERAL_ERROR: ++ ret = 0; ++ *msg_return = " ParseTable said: CD_GENERAL_ERROR"; ++ break; ++ case CD_INVALID_OPCODE: ++ ret = 0; ++ *msg_return = " ParseTable said: CD_INVALID_OPCODE"; ++ break; ++ case CD_NOT_IMPLEMENTED: ++ ret = 0; ++ *msg_return = " ParseTable said: CD_NOT_IMPLEMENTED"; ++ break; ++ case CD_EXEC_TABLE_NOT_FOUND: ++ ret = 0; ++ *msg_return = " ParseTable said: CD_EXEC_TABLE_NOT_FOUND"; ++ break; ++ case CD_EXEC_PARAMETER_ERROR: ++ ret = 0; ++ *msg_return = " ParseTable said: CD_EXEC_PARAMETER_ERROR"; ++ break; ++ case CD_EXEC_PARSER_ERROR: ++ ret = 0; ++ *msg_return = " ParseTable said: CD_EXEC_PARSER_ERROR"; ++ break; ++ case CD_INVALID_DESTINATION_TYPE: ++ ret = 0; ++ *msg_return = " ParseTable said: CD_INVALID_DESTINATION_TYPE"; ++ break; ++ case CD_UNEXPECTED_BEHAVIOR: ++ ret = 0; ++ *msg_return = " ParseTable said: CD_UNEXPECTED_BEHAVIOR"; ++ break; ++ case CD_INVALID_SWITCH_OPERAND_SIZE: ++ ret = 0; ++ *msg_return = " ParseTable said: CD_INVALID_SWITCH_OPERAND_SIZE\n"; ++ break; ++ } ++ return ret; ++} +diff --git a/src/radeon_atomwrapper.h b/src/radeon_atomwrapper.h +new file mode 100644 +index 0000000..1e7cc77 +--- /dev/null ++++ b/src/radeon_atomwrapper.h +@@ -0,0 +1,31 @@ ++/* ++ * Copyright 2007 Luc Verhaegen ++ * Copyright 2007 Matthias Hopf ++ * Copyright 2007 Egbert Eich ++ * Copyright 2007 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in ++ * all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++#ifndef RHD_ATOMWRAPPER_H_ ++# define RHD_ATOMWRAPPER_H_ ++ ++extern int ParseTableWrapper(void *pspace, int index, void *CAIL, ++ void *BIOSBase, char **msg_return); ++ ++#endif /* RHD_ATOMWRAPPER_H_ */ +diff --git a/src/radeon_bios.c b/src/radeon_bios.c +index d150c4b..46a58ca 100644 +--- a/src/radeon_bios.c ++++ b/src/radeon_bios.c +@@ -39,8 +39,32 @@ + #include "radeon_reg.h" + #include "radeon_macros.h" + #include "radeon_probe.h" ++#include "radeon_atombios.h" + #include "vbe.h" + ++typedef enum ++{ ++ DDC_NONE_DETECTED, ++ DDC_MONID, ++ DDC_DVI, ++ DDC_VGA, ++ DDC_CRT2, ++ DDC_LCD, ++ DDC_GPIO, ++} RADEONLegacyDDCType; ++ ++typedef enum ++{ ++ CONNECTOR_NONE_LEGACY, ++ CONNECTOR_PROPRIETARY_LEGACY, ++ CONNECTOR_CRT_LEGACY, ++ CONNECTOR_DVI_I_LEGACY, ++ CONNECTOR_DVI_D_LEGACY, ++ CONNECTOR_CTV_LEGACY, ++ CONNECTOR_STV_LEGACY, ++ CONNECTOR_UNSUPPORTED_LEGACY ++} RADEONLegacyConnectorType; ++ + /* Read the Video BIOS block and the FP registers (if applicable). */ + Bool RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10) + { +@@ -130,66 +154,115 @@ Bool RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10) + else + info->IsAtomBios = FALSE; + +- if (info->IsAtomBios) +- info->MasterDataStart = RADEON_BIOS16 (info->ROMHeaderStart + 32); +- + xf86DrvMsg(pScrn->scrnIndex, X_INFO, "%s BIOS detected\n", + info->IsAtomBios ? "ATOM":"Legacy"); + ++ if (info->IsAtomBios) { ++#if 1 ++ AtomBiosArgRec atomBiosArg; ++ ++ if (RHDAtomBiosFunc(pScrn->scrnIndex, NULL, ATOMBIOS_INIT, &atomBiosArg) ++ == ATOM_SUCCESS) { ++ info->atomBIOS = atomBiosArg.atomhandle; ++ } ++ ++ atomBiosArg.fb.start = info->FbFreeStart; ++ atomBiosArg.fb.size = info->FbFreeSize; ++ if (RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS, ATOMBIOS_ALLOCATE_FB_SCRATCH, ++ &atomBiosArg) == ATOM_SUCCESS) { ++ ++ info->FbFreeStart = atomBiosArg.fb.start; ++ info->FbFreeSize = atomBiosArg.fb.size; ++ } ++ ++ RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS, GET_DEFAULT_ENGINE_CLOCK, ++ &atomBiosArg); ++ RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS, GET_DEFAULT_MEMORY_CLOCK, ++ &atomBiosArg); ++ RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS, ++ GET_MAX_PIXEL_CLOCK_PLL_OUTPUT, &atomBiosArg); ++ RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS, ++ GET_MIN_PIXEL_CLOCK_PLL_OUTPUT, &atomBiosArg); ++ RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS, ++ GET_MAX_PIXEL_CLOCK_PLL_INPUT, &atomBiosArg); ++ RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS, ++ GET_MIN_PIXEL_CLOCK_PLL_INPUT, &atomBiosArg); ++ RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS, ++ GET_MAX_PIXEL_CLK, &atomBiosArg); ++ RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS, ++ GET_REF_CLOCK, &atomBiosArg); ++ ++#endif ++ info->MasterDataStart = RADEON_BIOS16 (info->ROMHeaderStart + 32); ++ } ++ + return TRUE; + } + + static Bool RADEONGetATOMConnectorInfoFromBIOS (ScrnInfoPtr pScrn) + { + RADEONInfoPtr info = RADEONPTR (pScrn); +- int offset, i, tmp, tmp0, crtc, portinfo, gpio; ++ int offset, i, j, tmp, tmp0, id, portinfo, gpio; + + if (!info->VBIOS) return FALSE; ++ ++ if (RADEONGetATOMConnectorInfoFromBIOSObject(pScrn)) ++ return TRUE; ++ ++ if (RADEONGetATOMConnectorInfoFromBIOSConnectorTable(pScrn)) ++ return TRUE; + + offset = RADEON_BIOS16(info->MasterDataStart + 22); + + if (offset) { + tmp = RADEON_BIOS16(offset + 4); +- for (i = 0; i < 8; i++) { ++ for (i = 0; i < RADEON_MAX_BIOS_CONNECTOR; i++) { + if (tmp & (1 << i)) { ++ ++ if (i == ATOM_DEVICE_CV_INDEX) { ++ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Skipping Component Video\n"); ++ info->BiosConnector[i].valid = FALSE; ++ continue; ++ } ++ + info->BiosConnector[i].valid = TRUE; + portinfo = RADEON_BIOS16(offset + 6 + i * 2); + info->BiosConnector[i].DACType = (portinfo & 0xf) - 1; + info->BiosConnector[i].ConnectorType = (portinfo >> 4) & 0xf; +- crtc = (portinfo >> 8) & 0xf; ++ id = (portinfo >> 8) & 0xf; + tmp0 = RADEON_BIOS16(info->MasterDataStart + 24); +- gpio = RADEON_BIOS16(tmp0 + 4 + 27 * crtc) * 4; +- switch(gpio) { +- case RADEON_GPIO_MONID: +- info->BiosConnector[i].DDCType = DDC_MONID; +- break; +- case RADEON_GPIO_DVI_DDC: +- info->BiosConnector[i].DDCType = DDC_DVI; +- break; +- case RADEON_GPIO_VGA_DDC: +- info->BiosConnector[i].DDCType = DDC_VGA; +- break; +- case RADEON_GPIO_CRT2_DDC: +- info->BiosConnector[i].DDCType = DDC_CRT2; +- break; +- case RADEON_LCD_GPIO_MASK: +- info->BiosConnector[i].DDCType = DDC_LCD; +- break; +- case RADEON_MDGPIO_EN_REG: +- info->BiosConnector[i].DDCType = DDC_GPIO; +- break; +- default: +- info->BiosConnector[i].DDCType = DDC_NONE_DETECTED; +- break; +- } ++ gpio = RADEON_BIOS16(tmp0 + 4 + 27 * id) * 4; ++ /* don't assign a gpio for tv */ ++ if ((i == ATOM_DEVICE_TV1_INDEX) || ++ (i == ATOM_DEVICE_TV2_INDEX) || ++ (i == ATOM_DEVICE_CV_INDEX)) ++ info->BiosConnector[i].ddc_line = 0; ++ else ++ info->BiosConnector[i].ddc_line = gpio; + +- if (i == 3) ++ info->BiosConnector[i].output_id = id; ++ info->BiosConnector[i].devices = (1 << i); ++ ++ if (i == ATOM_DEVICE_DFP1_INDEX) + info->BiosConnector[i].TMDSType = TMDS_INT; +- else if (i == 7) ++ else if (i == ATOM_DEVICE_DFP2_INDEX) ++ info->BiosConnector[i].TMDSType = TMDS_EXT; ++ else if (i == ATOM_DEVICE_DFP3_INDEX) + info->BiosConnector[i].TMDSType = TMDS_EXT; + else + info->BiosConnector[i].TMDSType = TMDS_UNKNOWN; + ++ /* Always set the connector type to VGA for CRT1/CRT2. if they are ++ * shared with a DVI port, we'll pick up the DVI connector below when we ++ * merge the outputs ++ */ ++ if ((i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX) && ++ (info->BiosConnector[i].ConnectorType == CONNECTOR_DVI_I || ++ info->BiosConnector[i].ConnectorType == CONNECTOR_DVI_D || ++ info->BiosConnector[i].ConnectorType == CONNECTOR_DVI_A)) { ++ info->BiosConnector[i].ConnectorType = CONNECTOR_VGA; ++ } ++ + } else { + info->BiosConnector[i].valid = FALSE; + } +@@ -199,23 +272,39 @@ static Bool RADEONGetATOMConnectorInfoFromBIOS (ScrnInfoPtr pScrn) + return FALSE; + } + +- /* DVI-I ports have 2 entries: one for analog, one for digital. combine them */ +- if (info->BiosConnector[0].valid && info->BiosConnector[7].valid) { +- info->BiosConnector[7].DACType = info->BiosConnector[0].DACType; +- info->BiosConnector[0].valid = FALSE; +- } +- +- if (info->BiosConnector[4].valid && info->BiosConnector[3].valid) { +- info->BiosConnector[3].DACType = info->BiosConnector[4].DACType; +- info->BiosConnector[4].valid = FALSE; ++ /* CRTs/DFPs may share a port */ ++ for (i = 0; i < RADEON_MAX_BIOS_CONNECTOR; i++) { ++ if (info->BiosConnector[i].valid) { ++ for (j = 0; j < RADEON_MAX_BIOS_CONNECTOR; j++) { ++ if (info->BiosConnector[j].valid && (i != j) ) { ++ if (info->BiosConnector[i].output_id == info->BiosConnector[j].output_id) { ++ if (((i == ATOM_DEVICE_DFP1_INDEX) || ++ (i == ATOM_DEVICE_DFP2_INDEX) || ++ (i == ATOM_DEVICE_DFP3_INDEX)) && ++ ((j == ATOM_DEVICE_CRT1_INDEX) || (j == ATOM_DEVICE_CRT2_INDEX))) { ++ info->BiosConnector[i].DACType = info->BiosConnector[j].DACType; ++ info->BiosConnector[i].devices |= info->BiosConnector[j].devices; ++ info->BiosConnector[j].valid = FALSE; ++ } else if (((j == ATOM_DEVICE_DFP1_INDEX) || ++ (j == ATOM_DEVICE_DFP2_INDEX) || ++ (j == ATOM_DEVICE_DFP3_INDEX)) && ++ ((i == ATOM_DEVICE_CRT1_INDEX) || (i == ATOM_DEVICE_CRT2_INDEX))) { ++ info->BiosConnector[j].DACType = info->BiosConnector[i].DACType; ++ info->BiosConnector[j].devices |= info->BiosConnector[i].devices; ++ info->BiosConnector[i].valid = FALSE; ++ } ++ /* other possible combos? */ ++ } ++ } ++ } ++ } + } + +- + xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Bios Connector table: \n"); + for (i = 0; i < RADEON_MAX_BIOS_CONNECTOR; i++) { + if (info->BiosConnector[i].valid) { +- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Port%d: DDCType-%d, DACType-%d, TMDSType-%d, ConnectorType-%d\n", +- i, info->BiosConnector[i].DDCType, info->BiosConnector[i].DACType, ++ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Port%d: DDCType-0x%x, DACType-%d, TMDSType-%d, ConnectorType-%d\n", ++ i, info->BiosConnector[i].ddc_line, info->BiosConnector[i].DACType, + info->BiosConnector[i].TMDSType, info->BiosConnector[i].ConnectorType); + } + } +@@ -227,6 +316,8 @@ static Bool RADEONGetLegacyConnectorInfoFromBIOS (ScrnInfoPtr pScrn) + { + RADEONInfoPtr info = RADEONPTR (pScrn); + int offset, i, entry, tmp, tmp0, tmp1; ++ RADEONLegacyDDCType DDCType; ++ RADEONLegacyConnectorType ConnectorType; + + if (!info->VBIOS) return FALSE; + +@@ -241,7 +332,55 @@ static Bool RADEONGetLegacyConnectorInfoFromBIOS (ScrnInfoPtr pScrn) + info->BiosConnector[i].valid = TRUE; + tmp = RADEON_BIOS16(entry); + info->BiosConnector[i].ConnectorType = (tmp >> 12) & 0xf; +- info->BiosConnector[i].DDCType = (tmp >> 8) & 0xf; ++ ConnectorType = (tmp >> 12) & 0xf; ++ switch (ConnectorType) { ++ case CONNECTOR_PROPRIETARY_LEGACY: ++ info->BiosConnector[i].ConnectorType = CONNECTOR_LVDS; ++ break; ++ case CONNECTOR_CRT_LEGACY: ++ info->BiosConnector[i].ConnectorType = CONNECTOR_VGA; ++ break; ++ case CONNECTOR_DVI_I_LEGACY: ++ info->BiosConnector[i].ConnectorType = CONNECTOR_DVI_I; ++ break; ++ case CONNECTOR_DVI_D_LEGACY: ++ info->BiosConnector[i].ConnectorType = CONNECTOR_DVI_D; ++ break; ++ case CONNECTOR_CTV_LEGACY: ++ info->BiosConnector[i].ConnectorType = CONNECTOR_CTV; ++ break; ++ case CONNECTOR_STV_LEGACY: ++ info->BiosConnector[i].ConnectorType = CONNECTOR_STV; ++ break; ++ default: ++ xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Unknown Connector Type: %d\n", ConnectorType); ++ info->BiosConnector[i].valid = FALSE; ++ break; ++ } ++ DDCType = (tmp >> 8) & 0xf; ++ switch (DDCType) { ++ case DDC_MONID: ++ info->BiosConnector[i].ddc_line = RADEON_GPIO_MONID; ++ break; ++ case DDC_DVI: ++ info->BiosConnector[i].ddc_line = RADEON_GPIO_DVI_DDC; ++ break; ++ case DDC_VGA: ++ info->BiosConnector[i].ddc_line = RADEON_GPIO_VGA_DDC; ++ break; ++ case DDC_CRT2: ++ info->BiosConnector[i].ddc_line = RADEON_GPIO_CRT2_DDC; ++ break; ++ case DDC_LCD: ++ info->BiosConnector[i].ddc_line = RADEON_LCD_GPIO_MASK; ++ break; ++ case DDC_GPIO: ++ info->BiosConnector[i].ddc_line = RADEON_MDGPIO_EN_REG; ++ break; ++ default: ++ xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Unknown DDC Type: %d\n", DDCType); ++ break; ++ } + info->BiosConnector[i].DACType = tmp & 0x1; + info->BiosConnector[i].TMDSType = (tmp >> 4) & 0x1; + +@@ -251,29 +390,22 @@ static Bool RADEONGetLegacyConnectorInfoFromBIOS (ScrnInfoPtr pScrn) + * lets see what happens with that. + */ + if (info->ChipFamily == CHIP_FAMILY_RS400 && +- info->BiosConnector[i].ConnectorType == CONNECTOR_CRT && +- info->BiosConnector[i].DDCType == DDC_CRT2) { +- info->BiosConnector[i].DDCType = DDC_MONID; ++ info->BiosConnector[i].ConnectorType == CONNECTOR_VGA && ++ info->BiosConnector[i].ddc_line == RADEON_GPIO_CRT2_DDC) { ++ info->BiosConnector[i].ddc_line = RADEON_GPIO_MONID; + } + + /* XPRESS desktop chips seem to have a proprietary connector listed for + * DVI-D, try and do the right thing here. + */ + if ((!info->IsMobility) && +- (info->BiosConnector[i].ConnectorType == CONNECTOR_PROPRIETARY)) { ++ (info->BiosConnector[i].ConnectorType == CONNECTOR_LVDS)) { + xf86DrvMsg(pScrn->scrnIndex, X_WARNING, + "Proprietary connector found, assuming DVI-D\n"); + info->BiosConnector[i].DACType = DAC_NONE; + info->BiosConnector[i].TMDSType = TMDS_EXT; + info->BiosConnector[i].ConnectorType = CONNECTOR_DVI_D; + } +- +- if (info->BiosConnector[i].ConnectorType >= CONNECTOR_UNSUPPORTED) { +- xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Unknown connector type: %d!\n", +- info->BiosConnector[i].ConnectorType); +- info->BiosConnector[i].valid = FALSE; +- } +- + } + } else { + xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "No Connector Info Table found!\n"); +@@ -285,7 +417,7 @@ static Bool RADEONGetLegacyConnectorInfoFromBIOS (ScrnInfoPtr pScrn) + offset = RADEON_BIOS16(info->ROMHeaderStart + 0x40); + if (offset) { + info->BiosConnector[4].valid = TRUE; +- info->BiosConnector[4].ConnectorType = CONNECTOR_PROPRIETARY; ++ info->BiosConnector[4].ConnectorType = CONNECTOR_LVDS; + info->BiosConnector[4].DACType = DAC_NONE; + info->BiosConnector[4].TMDSType = TMDS_NONE; + +@@ -294,19 +426,36 @@ static Bool RADEONGetLegacyConnectorInfoFromBIOS (ScrnInfoPtr pScrn) + tmp0 = RADEON_BIOS16(tmp + 0x15); + if (tmp0) { + tmp1 = RADEON_BIOS8(tmp0+2) & 0x07; +- if (tmp1) { +- info->BiosConnector[4].DDCType = tmp1; +- if (info->BiosConnector[4].DDCType > DDC_GPIO) { +- xf86DrvMsg(pScrn->scrnIndex, X_WARNING, +- "Unknown DDCType %d found\n", +- info->BiosConnector[4].DDCType); +- info->BiosConnector[4].DDCType = DDC_NONE_DETECTED; ++ if (tmp1) { ++ DDCType = tmp1; ++ switch (DDCType) { ++ case DDC_MONID: ++ info->BiosConnector[4].ddc_line = RADEON_GPIO_MONID; ++ break; ++ case DDC_DVI: ++ info->BiosConnector[4].ddc_line = RADEON_GPIO_DVI_DDC; ++ break; ++ case DDC_VGA: ++ info->BiosConnector[4].ddc_line = RADEON_GPIO_VGA_DDC; ++ break; ++ case DDC_CRT2: ++ info->BiosConnector[4].ddc_line = RADEON_GPIO_CRT2_DDC; ++ break; ++ case DDC_LCD: ++ info->BiosConnector[4].ddc_line = RADEON_LCD_GPIO_MASK; ++ break; ++ case DDC_GPIO: ++ info->BiosConnector[4].ddc_line = RADEON_MDGPIO_EN_REG; ++ break; ++ default: ++ xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Unknown DDC Type: %d\n", DDCType); ++ break; + } + xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "LCD DDC Info Table found!\n"); + } + } + } else { +- info->BiosConnector[4].DDCType = DDC_NONE_DETECTED; ++ info->BiosConnector[4].ddc_line = 0; + } + } + } +@@ -321,7 +470,7 @@ static Bool RADEONGetLegacyConnectorInfoFromBIOS (ScrnInfoPtr pScrn) + info->BiosConnector[5].ConnectorType = CONNECTOR_STV; + info->BiosConnector[5].DACType = DAC_TVDAC; + info->BiosConnector[5].TMDSType = TMDS_NONE; +- info->BiosConnector[5].DDCType = DDC_NONE_DETECTED; ++ info->BiosConnector[5].ddc_line = 0; + } + } + } +@@ -329,8 +478,8 @@ static Bool RADEONGetLegacyConnectorInfoFromBIOS (ScrnInfoPtr pScrn) + xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Bios Connector table: \n"); + for (i = 0; i < RADEON_MAX_BIOS_CONNECTOR; i++) { + if (info->BiosConnector[i].valid) { +- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Port%d: DDCType-%d, DACType-%d, TMDSType-%d, ConnectorType-%d\n", +- i, info->BiosConnector[i].DDCType, info->BiosConnector[i].DACType, ++ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Port%d: DDCType-0x%x, DACType-%d, TMDSType-%d, ConnectorType-%d\n", ++ i, info->BiosConnector[i].ddc_line, info->BiosConnector[i].DACType, + info->BiosConnector[i].TMDSType, info->BiosConnector[i].ConnectorType); + } + } +@@ -462,8 +611,19 @@ Bool RADEONGetClockInfoFromBIOS (ScrnInfoPtr pScrn) + or use a new algorithm to calculate + from min_input and max_input + */ +- pll->min_pll_freq = RADEON_BIOS16 (pll_info_block + 78); +- pll->max_pll_freq = RADEON_BIOS32 (pll_info_block + 32); ++ pll->pll_out_min = RADEON_BIOS16 (pll_info_block + 78); ++ pll->pll_out_max = RADEON_BIOS32 (pll_info_block + 32); ++ ++ if (pll->pll_out_min == 0) { ++ if (IS_AVIVO_VARIANT) ++ pll->pll_out_min = 64800; ++ else ++ pll->pll_out_min = 20000; ++ } ++ ++ pll->pll_in_min = RADEON_BIOS16 (pll_info_block + 74); ++ pll->pll_in_max = RADEON_BIOS16 (pll_info_block + 76); ++ + pll->xclk = RADEON_BIOS16 (pll_info_block + 72); + + info->sclk = RADEON_BIOS32(pll_info_block + 8) / 100.0; +@@ -473,8 +633,13 @@ Bool RADEONGetClockInfoFromBIOS (ScrnInfoPtr pScrn) + + pll->reference_freq = RADEON_BIOS16 (pll_info_block + 0x0e); + pll->reference_div = RADEON_BIOS16 (pll_info_block + 0x10); +- pll->min_pll_freq = RADEON_BIOS32 (pll_info_block + 0x12); +- pll->max_pll_freq = RADEON_BIOS32 (pll_info_block + 0x16); ++ pll->pll_out_min = RADEON_BIOS32 (pll_info_block + 0x12); ++ pll->pll_out_max = RADEON_BIOS32 (pll_info_block + 0x16); ++ ++ /* not available in the bios */ ++ pll->pll_in_min = 40; ++ pll->pll_in_max = 500; ++ + pll->xclk = RADEON_BIOS16 (pll_info_block + 0x08); + + info->sclk = RADEON_BIOS16(pll_info_block + 8) / 100.0; +@@ -487,8 +652,8 @@ Bool RADEONGetClockInfoFromBIOS (ScrnInfoPtr pScrn) + + xf86DrvMsg(pScrn->scrnIndex, X_INFO, "ref_freq: %d, min_pll: %u, " + "max_pll: %u, xclk: %d, sclk: %f, mclk: %f\n", +- pll->reference_freq, (unsigned)pll->min_pll_freq, +- (unsigned)pll->max_pll_freq, pll->xclk, info->sclk, ++ pll->reference_freq, (unsigned)pll->pll_out_min, ++ (unsigned)pll->pll_out_max, pll->xclk, info->sclk, + info->mclk); + + return TRUE; +diff --git a/src/radeon_chipinfo_gen.h b/src/radeon_chipinfo_gen.h +index a12b225..cf70557 100644 +--- a/src/radeon_chipinfo_gen.h ++++ b/src/radeon_chipinfo_gen.h +@@ -135,6 +135,138 @@ RADEONCardInfo RADEONCards[] = { + { 0x5E4C, CHIP_FAMILY_RV410, 0, 0, 0, 0, 0 }, + { 0x5E4D, CHIP_FAMILY_RV410, 0, 0, 0, 0, 0 }, + { 0x5E4F, CHIP_FAMILY_RV410, 0, 0, 0, 0, 0 }, ++ { 0x7100, CHIP_FAMILY_R520, 0, 0, 0, 0, 0 }, ++ { 0x7101, CHIP_FAMILY_R520, 1, 0, 0, 0, 0 }, ++ { 0x7102, CHIP_FAMILY_R520, 1, 0, 0, 0, 0 }, ++ { 0x7103, CHIP_FAMILY_R520, 1, 0, 0, 0, 0 }, ++ { 0x7104, CHIP_FAMILY_R520, 0, 0, 0, 0, 0 }, ++ { 0x7105, CHIP_FAMILY_R520, 0, 0, 0, 0, 0 }, ++ { 0x7106, CHIP_FAMILY_R520, 1, 0, 0, 0, 0 }, ++ { 0x7108, CHIP_FAMILY_R520, 0, 0, 0, 0, 0 }, ++ { 0x7109, CHIP_FAMILY_R520, 0, 0, 0, 0, 0 }, ++ { 0x710A, CHIP_FAMILY_R520, 0, 0, 0, 0, 0 }, ++ { 0x710B, CHIP_FAMILY_R520, 0, 0, 0, 0, 0 }, ++ { 0x710C, CHIP_FAMILY_R520, 0, 0, 0, 0, 0 }, ++ { 0x710E, CHIP_FAMILY_R520, 0, 0, 0, 0, 0 }, ++ { 0x710F, CHIP_FAMILY_R520, 0, 0, 0, 0, 0 }, ++ { 0x7140, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, ++ { 0x7141, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, ++ { 0x7142, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, ++ { 0x7143, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, ++ { 0x7144, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 }, ++ { 0x7145, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 }, ++ { 0x7146, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, ++ { 0x7147, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, ++ { 0x7149, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 }, ++ { 0x714A, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 }, ++ { 0x714B, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 }, ++ { 0x714C, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 }, ++ { 0x714D, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, ++ { 0x714E, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, ++ { 0x714F, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, ++ { 0x7151, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, ++ { 0x7152, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, ++ { 0x7153, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, ++ { 0x715E, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, ++ { 0x715F, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, ++ { 0x7180, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, ++ { 0x7181, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, ++ { 0x7183, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, ++ { 0x7186, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 }, ++ { 0x7187, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, ++ { 0x7188, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 }, ++ { 0x718A, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 }, ++ { 0x718B, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 }, ++ { 0x718C, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 }, ++ { 0x718D, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 }, ++ { 0x718F, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, ++ { 0x7193, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, ++ { 0x7196, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 }, ++ { 0x719B, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, ++ { 0x719F, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, ++ { 0x71C0, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 }, ++ { 0x71C1, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 }, ++ { 0x71C2, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 }, ++ { 0x71C3, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 }, ++ { 0x71C4, CHIP_FAMILY_RV530, 1, 0, 0, 0, 0 }, ++ { 0x71C5, CHIP_FAMILY_RV530, 1, 0, 0, 0, 0 }, ++ { 0x71C6, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 }, ++ { 0x71C7, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 }, ++ { 0x71CD, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 }, ++ { 0x71CE, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 }, ++ { 0x71D2, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 }, ++ { 0x71D4, CHIP_FAMILY_RV530, 1, 0, 0, 0, 0 }, ++ { 0x71D5, CHIP_FAMILY_RV530, 1, 0, 0, 0, 0 }, ++ { 0x71D6, CHIP_FAMILY_RV530, 1, 0, 0, 0, 0 }, ++ { 0x71DA, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 }, ++ { 0x71DE, CHIP_FAMILY_RV530, 1, 0, 0, 0, 0 }, ++ { 0x7200, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 }, ++ { 0x7210, CHIP_FAMILY_RV530, 1, 0, 0, 0, 0 }, ++ { 0x7211, CHIP_FAMILY_RV530, 1, 0, 0, 0, 0 }, ++ { 0x7240, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 }, ++ { 0x7243, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 }, ++ { 0x7244, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 }, ++ { 0x7245, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 }, ++ { 0x7246, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 }, ++ { 0x7247, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 }, ++ { 0x7248, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 }, ++ { 0x7249, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 }, ++ { 0x724A, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 }, ++ { 0x724B, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 }, ++ { 0x724C, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 }, ++ { 0x724D, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 }, ++ { 0x724E, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 }, ++ { 0x724F, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 }, ++ { 0x7280, CHIP_FAMILY_RV570, 0, 0, 0, 0, 0 }, ++ { 0x7281, CHIP_FAMILY_RV560, 0, 0, 0, 0, 0 }, ++ { 0x7283, CHIP_FAMILY_RV560, 0, 0, 0, 0, 0 }, ++ { 0x7284, CHIP_FAMILY_R580, 1, 0, 0, 0, 0 }, ++ { 0x7287, CHIP_FAMILY_RV560, 0, 0, 0, 0, 0 }, ++ { 0x7288, CHIP_FAMILY_RV570, 0, 0, 0, 0, 0 }, ++ { 0x7289, CHIP_FAMILY_RV570, 0, 0, 0, 0, 0 }, ++ { 0x728B, CHIP_FAMILY_RV570, 0, 0, 0, 0, 0 }, ++ { 0x728C, CHIP_FAMILY_RV570, 0, 0, 0, 0, 0 }, ++ { 0x7290, CHIP_FAMILY_RV560, 0, 0, 0, 0, 0 }, ++ { 0x7291, CHIP_FAMILY_RV560, 0, 0, 0, 0, 0 }, ++ { 0x7293, CHIP_FAMILY_RV560, 0, 0, 0, 0, 0 }, ++ { 0x7297, CHIP_FAMILY_RV560, 0, 0, 0, 0, 0 }, + { 0x7834, CHIP_FAMILY_RS300, 0, 1, 0, 0, 0 }, + { 0x7835, CHIP_FAMILY_RS300, 1, 1, 0, 0, 0 }, ++ { 0x791E, CHIP_FAMILY_RS690, 0, 1, 0, 0, 0 }, ++ { 0x791F, CHIP_FAMILY_RS690, 0, 1, 0, 0, 0 }, ++ { 0x796C, CHIP_FAMILY_RS740, 0, 1, 0, 0, 0 }, ++ { 0x796D, CHIP_FAMILY_RS740, 0, 1, 0, 0, 0 }, ++ { 0x796E, CHIP_FAMILY_RS740, 0, 1, 0, 0, 0 }, ++ { 0x796F, CHIP_FAMILY_RS740, 0, 1, 0, 0, 0 }, ++ { 0x9400, CHIP_FAMILY_R600, 0, 0, 0, 0, 0 }, ++ { 0x9401, CHIP_FAMILY_R600, 0, 0, 0, 0, 0 }, ++ { 0x9402, CHIP_FAMILY_R600, 0, 0, 0, 0, 0 }, ++ { 0x9403, CHIP_FAMILY_R600, 0, 0, 0, 0, 0 }, ++ { 0x9405, CHIP_FAMILY_R600, 0, 0, 0, 0, 0 }, ++ { 0x940A, CHIP_FAMILY_R600, 0, 0, 0, 0, 0 }, ++ { 0x940B, CHIP_FAMILY_R600, 0, 0, 0, 0, 0 }, ++ { 0x940F, CHIP_FAMILY_R600, 0, 0, 0, 0, 0 }, ++ { 0x94C0, CHIP_FAMILY_RV610, 0, 0, 0, 0, 0 }, ++ { 0x94C1, CHIP_FAMILY_RV610, 0, 0, 0, 0, 0 }, ++ { 0x94C3, CHIP_FAMILY_RV610, 0, 0, 0, 0, 0 }, ++ { 0x94C4, CHIP_FAMILY_RV610, 0, 0, 0, 0, 0 }, ++ { 0x94C5, CHIP_FAMILY_RV610, 0, 0, 0, 0, 0 }, ++ { 0x94C6, CHIP_FAMILY_RV610, 0, 0, 0, 0, 0 }, ++ { 0x94C7, CHIP_FAMILY_RV610, 0, 0, 0, 0, 0 }, ++ { 0x94C8, CHIP_FAMILY_RV610, 1, 0, 0, 0, 0 }, ++ { 0x94C9, CHIP_FAMILY_RV610, 1, 0, 0, 0, 0 }, ++ { 0x94CB, CHIP_FAMILY_RV610, 1, 0, 0, 0, 0 }, ++ { 0x94CC, CHIP_FAMILY_RV610, 0, 0, 0, 0, 0 }, ++ { 0x9580, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 }, ++ { 0x9581, CHIP_FAMILY_RV630, 1, 0, 0, 0, 0 }, ++ { 0x9583, CHIP_FAMILY_RV630, 1, 0, 0, 0, 0 }, ++ { 0x9586, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 }, ++ { 0x9587, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 }, ++ { 0x9588, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 }, ++ { 0x9589, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 }, ++ { 0x958A, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 }, ++ { 0x958B, CHIP_FAMILY_RV630, 1, 0, 0, 0, 0 }, ++ { 0x958C, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 }, ++ { 0x958D, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 }, ++ { 0x958E, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 }, + }; +diff --git a/src/radeon_chipset_gen.h b/src/radeon_chipset_gen.h +index 0a7a9c1..9f15b3d 100644 +--- a/src/radeon_chipset_gen.h ++++ b/src/radeon_chipset_gen.h +@@ -135,7 +135,139 @@ static SymTabRec RADEONChipsets[] = { + { PCI_CHIP_RV410_5E4C, "ATI Radeon X700 SE (RV410) (PCIE)" }, + { PCI_CHIP_RV410_5E4D, "ATI Radeon X700 (RV410) (PCIE)" }, + { PCI_CHIP_RV410_5E4F, "ATI Radeon X700 SE (RV410) (PCIE)" }, ++ { PCI_CHIP_R520_7100, "ATI Radeon X1800" }, ++ { PCI_CHIP_R520_7101, "ATI Mobility Radeon X1800 XT" }, ++ { PCI_CHIP_R520_7102, "ATI Mobility Radeon X1800" }, ++ { PCI_CHIP_R520_7103, "ATI Mobility FireGL V7200" }, ++ { PCI_CHIP_R520_7104, "ATI FireGL V7200" }, ++ { PCI_CHIP_R520_7105, "ATI FireGL V5300" }, ++ { PCI_CHIP_R520_7106, "ATI Mobility FireGL V7100" }, ++ { PCI_CHIP_R520_7108, "ATI Radeon X1800" }, ++ { PCI_CHIP_R520_7109, "ATI Radeon X1800" }, ++ { PCI_CHIP_R520_710A, "ATI Radeon X1800" }, ++ { PCI_CHIP_R520_710B, "ATI Radeon X1800" }, ++ { PCI_CHIP_R520_710C, "ATI Radeon X1800" }, ++ { PCI_CHIP_R520_710E, "ATI FireGL V7300" }, ++ { PCI_CHIP_R520_710F, "ATI FireGL V7350" }, ++ { PCI_CHIP_RV515_7140, "ATI Radeon X1600" }, ++ { PCI_CHIP_RV515_7141, "ATI RV505" }, ++ { PCI_CHIP_RV515_7142, "ATI Radeon X1300/X1550" }, ++ { PCI_CHIP_RV515_7143, "ATI Radeon X1550" }, ++ { PCI_CHIP_RV515_7144, "ATI M54-GL" }, ++ { PCI_CHIP_RV515_7145, "ATI Mobility Radeon X1400" }, ++ { PCI_CHIP_RV515_7146, "ATI Radeon X1300/X1550" }, ++ { PCI_CHIP_RV515_7147, "ATI Radeon X1550 64-bit" }, ++ { PCI_CHIP_RV515_7149, "ATI Mobility Radeon X1300" }, ++ { PCI_CHIP_RV515_714A, "ATI Mobility Radeon X1300" }, ++ { PCI_CHIP_RV515_714B, "ATI Mobility Radeon X1300" }, ++ { PCI_CHIP_RV515_714C, "ATI Mobility Radeon X1300" }, ++ { PCI_CHIP_RV515_714D, "ATI Radeon X1300" }, ++ { PCI_CHIP_RV515_714E, "ATI Radeon X1300" }, ++ { PCI_CHIP_RV515_714F, "ATI RV505" }, ++ { PCI_CHIP_RV515_7151, "ATI RV505" }, ++ { PCI_CHIP_RV515_7152, "ATI FireGL V3300" }, ++ { PCI_CHIP_RV515_7153, "ATI FireGL V3350" }, ++ { PCI_CHIP_RV515_715E, "ATI Radeon X1300" }, ++ { PCI_CHIP_RV515_715F, "ATI Radeon X1550 64-bit" }, ++ { PCI_CHIP_RV515_7180, "ATI Radeon X1300/X1550" }, ++ { PCI_CHIP_RV515_7181, "ATI Radeon X1600" }, ++ { PCI_CHIP_RV515_7183, "ATI Radeon X1300/X1550" }, ++ { PCI_CHIP_RV515_7186, "ATI Mobility Radeon X1450" }, ++ { PCI_CHIP_RV515_7187, "ATI Radeon X1300/X1550" }, ++ { PCI_CHIP_RV515_7188, "ATI Mobility Radeon X2300" }, ++ { PCI_CHIP_RV515_718A, "ATI Mobility Radeon X2300" }, ++ { PCI_CHIP_RV515_718B, "ATI Mobility Radeon X1350" }, ++ { PCI_CHIP_RV515_718C, "ATI Mobility Radeon X1350" }, ++ { PCI_CHIP_RV515_718D, "ATI Mobility Radeon X1450" }, ++ { PCI_CHIP_RV515_718F, "ATI Radeon X1300" }, ++ { PCI_CHIP_RV515_7193, "ATI Radeon X1550" }, ++ { PCI_CHIP_RV515_7196, "ATI Mobility Radeon X1350" }, ++ { PCI_CHIP_RV515_719B, "ATI FireMV 2250" }, ++ { PCI_CHIP_RV515_719F, "ATI Radeon X1550 64-bit" }, ++ { PCI_CHIP_RV530_71C0, "ATI Radeon X1600" }, ++ { PCI_CHIP_RV530_71C1, "ATI Radeon X1650" }, ++ { PCI_CHIP_RV530_71C2, "ATI Radeon X1600" }, ++ { PCI_CHIP_RV530_71C3, "ATI Radeon X1600" }, ++ { PCI_CHIP_RV530_71C4, "ATI Mobility FireGL V5200" }, ++ { PCI_CHIP_RV530_71C5, "ATI Mobility Radeon X1600" }, ++ { PCI_CHIP_RV530_71C6, "ATI Radeon X1650" }, ++ { PCI_CHIP_RV530_71C7, "ATI Radeon X1650" }, ++ { PCI_CHIP_RV530_71CD, "ATI Radeon X1600" }, ++ { PCI_CHIP_RV530_71CE, "ATI Radeon X1300 XT/X1600 Pro" }, ++ { PCI_CHIP_RV530_71D2, "ATI FireGL V3400" }, ++ { PCI_CHIP_RV530_71D4, "ATI Mobility FireGL V5250" }, ++ { PCI_CHIP_RV530_71D5, "ATI Mobility Radeon X1700" }, ++ { PCI_CHIP_RV530_71D6, "ATI Mobility Radeon X1700 XT" }, ++ { PCI_CHIP_RV530_71DA, "ATI FireGL V5200" }, ++ { PCI_CHIP_RV530_71DE, "ATI Mobility Radeon X1700" }, ++ { PCI_CHIP_RV530_7200, "ATI Radeon X2300HD" }, ++ { PCI_CHIP_RV530_7210, "ATI Mobility Radeon HD 2300" }, ++ { PCI_CHIP_RV530_7211, "ATI Mobility Radeon HD 2300" }, ++ { PCI_CHIP_R580_7240, "ATI Radeon X1950" }, ++ { PCI_CHIP_R580_7243, "ATI Radeon X1900" }, ++ { PCI_CHIP_R580_7244, "ATI Radeon X1950" }, ++ { PCI_CHIP_R580_7245, "ATI Radeon X1900" }, ++ { PCI_CHIP_R580_7246, "ATI Radeon X1900" }, ++ { PCI_CHIP_R580_7247, "ATI Radeon X1900" }, ++ { PCI_CHIP_R580_7248, "ATI Radeon X1900" }, ++ { PCI_CHIP_R580_7249, "ATI Radeon X1900" }, ++ { PCI_CHIP_R580_724A, "ATI Radeon X1900" }, ++ { PCI_CHIP_R580_724B, "ATI Radeon X1900" }, ++ { PCI_CHIP_R580_724C, "ATI Radeon X1900" }, ++ { PCI_CHIP_R580_724D, "ATI Radeon X1900" }, ++ { PCI_CHIP_R580_724E, "ATI AMD Stream Processor" }, ++ { PCI_CHIP_R580_724F, "ATI Radeon X1900" }, ++ { PCI_CHIP_RV570_7280, "ATI Radeon X1950" }, ++ { PCI_CHIP_RV560_7281, "ATI RV560" }, ++ { PCI_CHIP_RV560_7283, "ATI RV560" }, ++ { PCI_CHIP_R580_7284, "ATI Mobility Radeon X1900" }, ++ { PCI_CHIP_RV560_7287, "ATI RV560" }, ++ { PCI_CHIP_RV570_7288, "ATI Radeon X1950 GT" }, ++ { PCI_CHIP_RV570_7289, "ATI RV570" }, ++ { PCI_CHIP_RV570_728B, "ATI RV570" }, ++ { PCI_CHIP_RV570_728C, "ATI ATI FireGL V7400" }, ++ { PCI_CHIP_RV560_7290, "ATI RV560" }, ++ { PCI_CHIP_RV560_7291, "ATI Radeon X1650" }, ++ { PCI_CHIP_RV560_7293, "ATI Radeon X1650" }, ++ { PCI_CHIP_RV560_7297, "ATI RV560" }, + { PCI_CHIP_RS350_7834, "ATI Radeon 9100 PRO IGP 7834" }, + { PCI_CHIP_RS350_7835, "ATI Radeon Mobility 9200 IGP 7835" }, ++ { PCI_CHIP_RS690_791E, "ATI Radeon X1200" }, ++ { PCI_CHIP_RS690_791F, "ATI Radeon X1200" }, ++ { PCI_CHIP_RS740_796C, "ATI RS740" }, ++ { PCI_CHIP_RS740_796D, "ATI RS740M" }, ++ { PCI_CHIP_RS740_796E, "ATI RS740" }, ++ { PCI_CHIP_RS740_796F, "ATI RS740M" }, ++ { PCI_CHIP_R600_9400, "ATI Radeon HD 2900 XT" }, ++ { PCI_CHIP_R600_9401, "ATI Radeon HD 2900 XT" }, ++ { PCI_CHIP_R600_9402, "ATI Radeon HD 2900 XT" }, ++ { PCI_CHIP_R600_9403, "ATI Radeon HD 2900 Pro" }, ++ { PCI_CHIP_R600_9405, "ATI Radeon HD 2900 GT" }, ++ { PCI_CHIP_R600_940A, "ATI FireGL V8650" }, ++ { PCI_CHIP_R600_940B, "ATI FireGL V8600" }, ++ { PCI_CHIP_R600_940F, "ATI FireGL V7600" }, ++ { PCI_CHIP_RV610_94C0, "ATI RV610" }, ++ { PCI_CHIP_RV610_94C1, "ATI Radeon HD 2400 XT" }, ++ { PCI_CHIP_RV610_94C3, "ATI Radeon HD 2400 Pro" }, ++ { PCI_CHIP_RV610_94C4, "ATI ATI Radeon HD 2400 PRO AGP" }, ++ { PCI_CHIP_RV610_94C5, "ATI FireGL V4000" }, ++ { PCI_CHIP_RV610_94C6, "ATI RV610" }, ++ { PCI_CHIP_RV610_94C7, "ATI ATI Radeon HD 2350" }, ++ { PCI_CHIP_RV610_94C8, "ATI Mobility Radeon HD 2400 XT" }, ++ { PCI_CHIP_RV610_94C9, "ATI Mobility Radeon HD 2400" }, ++ { PCI_CHIP_RV610_94CB, "ATI ATI RADEON E2400" }, ++ { PCI_CHIP_RV610_94CC, "ATI RV610" }, ++ { PCI_CHIP_RV630_9580, "ATI RV630" }, ++ { PCI_CHIP_RV630_9581, "ATI Mobility Radeon HD 2600" }, ++ { PCI_CHIP_RV630_9583, "ATI Mobility Radeon HD 2600 XT" }, ++ { PCI_CHIP_RV630_9586, "ATI ATI Radeon HD 2600 XT AGP" }, ++ { PCI_CHIP_RV630_9587, "ATI ATI Radeon HD 2600 Pro AGP" }, ++ { PCI_CHIP_RV630_9588, "ATI Radeon HD 2600 XT" }, ++ { PCI_CHIP_RV630_9589, "ATI Radeon HD 2600 Pro" }, ++ { PCI_CHIP_RV630_958A, "ATI Gemini RV630" }, ++ { PCI_CHIP_RV630_958B, "ATI Gemini ATI Mobility Radeon HD 2600 XT" }, ++ { PCI_CHIP_RV630_958C, "ATI FireGL V5600" }, ++ { PCI_CHIP_RV630_958D, "ATI FireGL V3600" }, ++ { PCI_CHIP_RV630_958E, "ATI ATI Radeon HD 2600 LE" }, + { -1, NULL } + }; +diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c +index 07857dd..8e66518 100644 +--- a/src/radeon_crtc.c ++++ b/src/radeon_crtc.c +@@ -55,6 +55,12 @@ + + void radeon_crtc_load_lut(xf86CrtcPtr crtc); + ++extern void atombios_crtc_mode_set(xf86CrtcPtr crtc, ++ DisplayModePtr mode, ++ DisplayModePtr adjusted_mode, ++ int x, int y); ++extern void atombios_crtc_dpms(xf86CrtcPtr crtc, int mode); ++ + static void + radeon_crtc_dpms(xf86CrtcPtr crtc, int mode) + { +@@ -63,7 +69,12 @@ radeon_crtc_dpms(xf86CrtcPtr crtc, int mode) + RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; + RADEONInfoPtr info = RADEONPTR(pScrn); + unsigned char *RADEONMMIO = info->MMIO; +- ++ ++ if (IS_AVIVO_VARIANT) { ++ atombios_crtc_dpms(crtc, mode); ++ return; ++ } ++ + mask = radeon_crtc->crtc_id ? (RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_VSYNC_DIS | RADEON_CRTC2_HSYNC_DIS | RADEON_CRTC2_DISP_REQ_EN_B) : (RADEON_CRTC_DISPLAY_DIS | RADEON_CRTC_HSYNC_DIS | RADEON_CRTC_VSYNC_DIS); + + +@@ -116,6 +127,9 @@ radeon_crtc_mode_fixup(xf86CrtcPtr crtc, DisplayModePtr mode, + static void + radeon_crtc_mode_prepare(xf86CrtcPtr crtc) + { ++ ScrnInfoPtr pScrn = crtc->scrn; ++ RADEONInfoPtr info = RADEONPTR(pScrn); ++ + radeon_crtc_dpms(crtc, DPMSModeOff); + } + +@@ -166,7 +180,7 @@ RADEONInitSurfaceCntl(xf86CrtcPtr crtc, RADEONSavePtr save) + + } + +-static Bool ++Bool + RADEONInitCrtcBase(xf86CrtcPtr crtc, RADEONSavePtr save, + int x, int y) + { +@@ -284,7 +298,7 @@ RADEONInitCrtcBase(xf86CrtcPtr crtc, RADEONSavePtr save, + } + + /* Define CRTC registers for requested video mode */ +-static Bool ++Bool + RADEONInitCrtcRegisters(xf86CrtcPtr crtc, RADEONSavePtr save, + DisplayModePtr mode) + { +@@ -309,7 +323,7 @@ RADEONInitCrtcRegisters(xf86CrtcPtr crtc, RADEONSavePtr save, + return FALSE; + } + +- /*save->bios_4_scratch = info->SavedReg.bios_4_scratch;*/ ++ /*save->bios_4_scratch = info->SavedReg->bios_4_scratch;*/ + save->crtc_gen_cntl = (RADEON_CRTC_EXT_DISP_EN + | RADEON_CRTC_EN + | (format << 8) +@@ -328,7 +342,7 @@ RADEONInitCrtcRegisters(xf86CrtcPtr crtc, RADEONSavePtr save, + RADEON_CRTC_HSYNC_DIS | + RADEON_CRTC_DISPLAY_DIS); + +- save->disp_merge_cntl = info->SavedReg.disp_merge_cntl; ++ save->disp_merge_cntl = info->SavedReg->disp_merge_cntl; + save->disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN; + + save->crtc_more_cntl = 0; +@@ -378,10 +392,10 @@ RADEONInitCrtcRegisters(xf86CrtcPtr crtc, RADEONSavePtr save, + save->fp_crtc_v_total_disp = save->crtc_v_total_disp; + + if (info->IsDellServer) { +- save->dac2_cntl = info->SavedReg.dac2_cntl; +- save->tv_dac_cntl = info->SavedReg.tv_dac_cntl; +- save->crtc2_gen_cntl = info->SavedReg.crtc2_gen_cntl; +- save->disp_hw_debug = info->SavedReg.disp_hw_debug; ++ save->dac2_cntl = info->SavedReg->dac2_cntl; ++ save->tv_dac_cntl = info->SavedReg->tv_dac_cntl; ++ save->crtc2_gen_cntl = info->SavedReg->crtc2_gen_cntl; ++ save->disp_hw_debug = info->SavedReg->disp_hw_debug; + + save->dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL; + save->dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL; +@@ -397,7 +411,7 @@ RADEONInitCrtcRegisters(xf86CrtcPtr crtc, RADEONSavePtr save, + return TRUE; + } + +-static Bool ++Bool + RADEONInitCrtc2Base(xf86CrtcPtr crtc, RADEONSavePtr save, + int x, int y) + { +@@ -510,7 +524,7 @@ RADEONInitCrtc2Base(xf86CrtcPtr crtc, RADEONSavePtr save, + } + + /* Define CRTC2 registers for requested video mode */ +-static Bool ++Bool + RADEONInitCrtc2Registers(xf86CrtcPtr crtc, RADEONSavePtr save, + DisplayModePtr mode) + { +@@ -587,7 +601,7 @@ RADEONInitCrtc2Registers(xf86CrtcPtr crtc, RADEONSavePtr save, + ? RADEON_CRTC2_INTERLACE_EN + : 0)); + +- save->disp2_merge_cntl = info->SavedReg.disp2_merge_cntl; ++ save->disp2_merge_cntl = info->SavedReg->disp2_merge_cntl; + save->disp2_merge_cntl &= ~(RADEON_DISP2_RGB_OFFSET_EN); + + save->fp_h2_sync_strt_wid = save->crtc2_h_sync_strt_wid; +@@ -604,12 +618,12 @@ RADEONInitCrtc2Registers(xf86CrtcPtr crtc, RADEONSavePtr save, + } + + +-static int RADEONDiv(int n, int d) ++static CARD32 RADEONDiv(CARD64 n, CARD32 d) + { + return (n + (d / 2)) / d; + } + +-static void ++void + RADEONComputePLL(RADEONPLLPtr pll, + unsigned long freq, + CARD32 *chosen_dot_clock_freq, +@@ -618,10 +632,6 @@ RADEONComputePLL(RADEONPLLPtr pll, + CARD32 *chosen_post_div, + int flags) + { +- int post_divs[] = {1, 2, 4, 8, 3, 6, 12, 0}; +- +- int i; +- + CARD32 min_ref_div = pll->min_ref_div; + CARD32 max_ref_div = pll->max_ref_div; + CARD32 best_vco = pll->best_vco; +@@ -631,23 +641,33 @@ RADEONComputePLL(RADEONPLLPtr pll, + CARD32 best_freq = 1; + CARD32 best_error = 0xffffffff; + CARD32 best_vco_diff = 1; ++ CARD32 post_div; + +- freq = freq / 10; ++ freq = freq * 1000; + + ErrorF("freq: %lu\n", freq); + + if (flags & RADEON_PLL_USE_REF_DIV) + min_ref_div = max_ref_div = pll->reference_div; + +- for (i = 0; post_divs[i]; i++) { +- int post_div = post_divs[i]; ++ for (post_div = pll->min_post_div; post_div <= pll->max_post_div; ++post_div) { + CARD32 ref_div; +- CARD32 vco = freq * post_div; ++ CARD32 vco = (freq / 10000) * post_div; + + if ((flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1)) + continue; + +- if (vco < pll->min_pll_freq || vco > pll->max_pll_freq) ++ /* legacy radeons only have a few post_divs */ ++ if (flags & RADEON_PLL_LEGACY) { ++ if ((post_div == 5) || ++ (post_div == 7) || ++ (post_div == 9) || ++ (post_div == 10) || ++ (post_div == 11)) ++ continue; ++ } ++ ++ if (vco < pll->pll_out_min || vco > pll->pll_out_max) + continue; + + for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) { +@@ -657,21 +677,22 @@ RADEONComputePLL(RADEONPLLPtr pll, + if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max) + continue; + +- feedback_div = RADEONDiv(freq * ref_div * post_div, +- pll->reference_freq); ++ feedback_div = RADEONDiv((CARD64)freq * ref_div * post_div, ++ pll->reference_freq * 10000); + + if (feedback_div < pll->min_feedback_div || feedback_div > pll->max_feedback_div) + continue; + +- current_freq = RADEONDiv(pll->reference_freq * feedback_div, ++ current_freq = RADEONDiv((CARD64)pll->reference_freq * 10000 * feedback_div, + ref_div * post_div); + + error = abs(current_freq - freq); + vco_diff = abs(vco - best_vco); + + if ((best_vco == 0 && error < best_error) || ++ (ref_div == pll->reference_div) || + (best_vco != 0 && +- (error < best_error - 1000 || ++ (error < best_error - 100 || + (abs(error - best_error) < 100 && vco_diff < best_vco_diff )))) { + best_post_div = post_div; + best_ref_div = ref_div; +@@ -683,12 +704,12 @@ RADEONComputePLL(RADEONPLLPtr pll, + } + } + +- ErrorF("best_freq: %u\n", (unsigned)best_freq); +- ErrorF("best_feedback_div: %u\n", (unsigned)best_feedback_div); +- ErrorF("best_ref_div: %u\n", (unsigned)best_ref_div); +- ErrorF("best_post_div: %u\n", (unsigned)best_post_div); ++ ErrorF("best_freq: %u\n", best_freq); ++ ErrorF("best_feedback_div: %u\n", best_feedback_div); ++ ErrorF("best_ref_div: %u\n", best_ref_div); ++ ErrorF("best_post_div: %u\n", best_post_div); + +- *chosen_dot_clock_freq = best_freq; ++ *chosen_dot_clock_freq = best_freq / 10000; + *chosen_feedback_div = best_feedback_div; + *chosen_reference_div = best_ref_div; + *chosen_post_div = best_post_div; +@@ -772,9 +793,8 @@ RADEONInitPLLRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save, + + save->htotal_cntl = mode->HTotal & 0x7; + +- save->vclk_ecp_cntl = (info->SavedReg.vclk_ecp_cntl & +- ~RADEON_VCLK_SRC_SEL_MASK) | RADEON_VCLK_SRC_SEL_PPLLCLK; +- ++ save->vclk_ecp_cntl = (info->SavedReg->vclk_ecp_cntl & ++ ~RADEON_VCLK_SRC_SEL_MASK) | RADEON_VCLK_SRC_SEL_PPLLCLK; + } + + /* Define PLL2 registers for requested video mode */ +@@ -847,10 +867,9 @@ RADEONInitPLL2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save, + + save->htotal_cntl2 = mode->HTotal & 0x7; + +- save->pixclks_cntl = ((info->SavedReg.pixclks_cntl & ++ save->pixclks_cntl = ((info->SavedReg->pixclks_cntl & + ~(RADEON_PIX2CLK_SRC_SEL_MASK)) | + RADEON_PIX2CLK_SRC_SEL_P2PLLCLK); +- + } + + static void +@@ -860,8 +879,8 @@ RADEONInitBIOSRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save) + + /* tell the bios not to muck with the hardware on events */ + save->bios_4_scratch = 0x4; /* 0x4 needed for backlight */ +- save->bios_5_scratch = (info->SavedReg.bios_5_scratch & 0xff) | 0xff00; /* bits 0-3 keep backlight level */ +- save->bios_6_scratch = info->SavedReg.bios_6_scratch | 0x40000000; ++ save->bios_5_scratch = (info->SavedReg->bios_5_scratch & 0xff) | 0xff00; /* bits 0-3 keep backlight level */ ++ save->bios_6_scratch = info->SavedReg->bios_6_scratch | 0x40000000; + + } + +@@ -873,7 +892,7 @@ radeon_update_tv_routing(ScrnInfoPtr pScrn, RADEONSavePtr restore) + } + + static void +-radeon_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode, ++legacy_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode, + DisplayModePtr adjusted_mode, int x, int y) + { + ScrnInfoPtr pScrn = crtc->scrn; +@@ -883,7 +902,7 @@ radeon_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode, + Bool tilingOld = info->tilingEnabled; + int i = 0; + double dot_clock = 0; +- int pll_flags = 0; ++ int pll_flags = RADEON_PLL_LEGACY; + Bool update_tv_routing = FALSE; + + +@@ -915,38 +934,38 @@ radeon_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode, + } + + if (info->IsMobility) +- RADEONInitBIOSRegisters(pScrn, &info->ModeReg); ++ RADEONInitBIOSRegisters(pScrn, info->ModeReg); + + ErrorF("init memmap\n"); +- RADEONInitMemMapRegisters(pScrn, &info->ModeReg, info); ++ RADEONInitMemMapRegisters(pScrn, info->ModeReg, info); + ErrorF("init common\n"); +- RADEONInitCommonRegisters(&info->ModeReg, info); ++ RADEONInitCommonRegisters(info->ModeReg, info); + +- RADEONInitSurfaceCntl(crtc, &info->ModeReg); ++ RADEONInitSurfaceCntl(crtc, info->ModeReg); + + switch (radeon_crtc->crtc_id) { + case 0: + ErrorF("init crtc1\n"); +- RADEONInitCrtcRegisters(crtc, &info->ModeReg, adjusted_mode); +- RADEONInitCrtcBase(crtc, &info->ModeReg, x, y); ++ RADEONInitCrtcRegisters(crtc, info->ModeReg, adjusted_mode); ++ RADEONInitCrtcBase(crtc, info->ModeReg, x, y); + dot_clock = adjusted_mode->Clock / 1000.0; + if (dot_clock) { + ErrorF("init pll1\n"); +- RADEONInitPLLRegisters(pScrn, &info->ModeReg, &info->pll, adjusted_mode, pll_flags); ++ RADEONInitPLLRegisters(pScrn, info->ModeReg, &info->pll, adjusted_mode, pll_flags); + } else { +- info->ModeReg.ppll_ref_div = info->SavedReg.ppll_ref_div; +- info->ModeReg.ppll_div_3 = info->SavedReg.ppll_div_3; +- info->ModeReg.htotal_cntl = info->SavedReg.htotal_cntl; ++ info->ModeReg->ppll_ref_div = info->SavedReg->ppll_ref_div; ++ info->ModeReg->ppll_div_3 = info->SavedReg->ppll_div_3; ++ info->ModeReg->htotal_cntl = info->SavedReg->htotal_cntl; + } + break; + case 1: + ErrorF("init crtc2\n"); +- RADEONInitCrtc2Registers(crtc, &info->ModeReg, adjusted_mode); +- RADEONInitCrtc2Base(crtc, &info->ModeReg, x, y); ++ RADEONInitCrtc2Registers(crtc, info->ModeReg, adjusted_mode); ++ RADEONInitCrtc2Base(crtc, info->ModeReg, x, y); + dot_clock = adjusted_mode->Clock / 1000.0; + if (dot_clock) { + ErrorF("init pll2\n"); +- RADEONInitPLL2Registers(pScrn, &info->ModeReg, &info->pll, adjusted_mode, pll_flags); ++ RADEONInitPLL2Registers(pScrn, info->ModeReg, &info->pll, adjusted_mode, pll_flags); + } + break; + } +@@ -959,13 +978,13 @@ radeon_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode, + if (radeon_output->MonType == MT_STV || radeon_output->MonType == MT_CTV) { + switch (radeon_crtc->crtc_id) { + case 0: +- RADEONAdjustCrtcRegistersForTV(pScrn, &info->ModeReg, adjusted_mode, output); +- RADEONAdjustPLLRegistersForTV(pScrn, &info->ModeReg, adjusted_mode, output); ++ RADEONAdjustCrtcRegistersForTV(pScrn, info->ModeReg, adjusted_mode, output); ++ RADEONAdjustPLLRegistersForTV(pScrn, info->ModeReg, adjusted_mode, output); + update_tv_routing = TRUE; + break; + case 1: +- RADEONAdjustCrtc2RegistersForTV(pScrn, &info->ModeReg, adjusted_mode, output); +- RADEONAdjustPLL2RegistersForTV(pScrn, &info->ModeReg, adjusted_mode, output); ++ RADEONAdjustCrtc2RegistersForTV(pScrn, info->ModeReg, adjusted_mode, output); ++ RADEONAdjustPLL2RegistersForTV(pScrn, info->ModeReg, adjusted_mode, output); + break; + } + } +@@ -973,31 +992,37 @@ radeon_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode, + } + + if (info->IsMobility) +- RADEONRestoreBIOSRegisters(pScrn, &info->ModeReg); ++ RADEONRestoreBIOSRegisters(pScrn, info->ModeReg); + + ErrorF("restore memmap\n"); +- RADEONRestoreMemMapRegisters(pScrn, &info->ModeReg); ++ RADEONRestoreMemMapRegisters(pScrn, info->ModeReg); + ErrorF("restore common\n"); +- RADEONRestoreCommonRegisters(pScrn, &info->ModeReg); ++ RADEONRestoreCommonRegisters(pScrn, info->ModeReg); + + switch (radeon_crtc->crtc_id) { + case 0: + ErrorF("restore crtc1\n"); +- RADEONRestoreCrtcRegisters(pScrn, &info->ModeReg); ++ RADEONRestoreCrtcRegisters(pScrn, info->ModeReg); + ErrorF("restore pll1\n"); +- RADEONRestorePLLRegisters(pScrn, &info->ModeReg); ++ /*if (info->IsAtomBios) ++ atombios_crtc_set_pll(crtc, adjusted_mode); ++ else*/ ++ RADEONRestorePLLRegisters(pScrn, info->ModeReg); + break; + case 1: + ErrorF("restore crtc2\n"); +- RADEONRestoreCrtc2Registers(pScrn, &info->ModeReg); ++ RADEONRestoreCrtc2Registers(pScrn, info->ModeReg); + ErrorF("restore pll2\n"); +- RADEONRestorePLL2Registers(pScrn, &info->ModeReg); ++ /*if (info->IsAtomBios) ++ atombios_crtc_set_pll(crtc, adjusted_mode); ++ else*/ ++ RADEONRestorePLL2Registers(pScrn, info->ModeReg); + break; + } + + /* pixclks_cntl handles tv-out clock routing */ + if (update_tv_routing) +- radeon_update_tv_routing(pScrn, &info->ModeReg); ++ radeon_update_tv_routing(pScrn, info->ModeReg); + + if (info->DispPriority) + RADEONInitDispBandwidth(pScrn); +@@ -1019,8 +1044,25 @@ radeon_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode, + } + + static void ++radeon_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode, ++ DisplayModePtr adjusted_mode, int x, int y) ++{ ++ ScrnInfoPtr pScrn = crtc->scrn; ++ RADEONInfoPtr info = RADEONPTR(pScrn); ++ ++ if (IS_AVIVO_VARIANT) { ++ atombios_crtc_mode_set(crtc, mode, adjusted_mode, x, y); ++ } else { ++ legacy_crtc_mode_set(crtc, mode, adjusted_mode, x, y); ++ } ++} ++ ++static void + radeon_crtc_mode_commit(xf86CrtcPtr crtc) + { ++ ScrnInfoPtr pScrn = crtc->scrn; ++ RADEONInfoPtr info = RADEONPTR(pScrn); ++ + radeon_crtc_dpms(crtc, DPMSModeOn); + } + +@@ -1035,8 +1077,25 @@ void radeon_crtc_load_lut(xf86CrtcPtr crtc) + if (!crtc->enabled) + return; + ++ if (IS_AVIVO_VARIANT) { ++ OUTREG(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0); ++ ++ OUTREG(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); ++ OUTREG(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); ++ OUTREG(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); ++ ++ OUTREG(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0x0000ffff); ++ OUTREG(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0x0000ffff); ++ OUTREG(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0x0000ffff); ++ } ++ + PAL_SELECT(radeon_crtc->crtc_id); + ++ if (IS_AVIVO_VARIANT) { ++ OUTREG(AVIVO_DC_LUT_RW_MODE, 0); ++ OUTREG(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f); ++ } ++ + for (i = 0; i < 256; i++) { + OUTPAL(i, radeon_crtc->lut_r[i], radeon_crtc->lut_g[i], radeon_crtc->lut_b[i]); + } +@@ -1229,7 +1288,7 @@ radeon_crtc_shadow_create(xf86CrtcPtr crtc, void *data, int width, int height) + + if (!data) + data = radeon_crtc_shadow_allocate(crtc, width, height); +- ++ + rotate_pitch = pScrn->displayWidth * cpp; + + rotate_pixmap = GetScratchPixmapHeader(pScrn->pScreen, +@@ -1295,40 +1354,47 @@ static const xf86CrtcFuncsRec radeon_crtc_funcs = { + .destroy = NULL, /* XXX */ + }; + +-Bool RADEONAllocateControllers(ScrnInfoPtr pScrn) ++Bool RADEONAllocateControllers(ScrnInfoPtr pScrn, int mask) + { + RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); + +- if (pRADEONEnt->Controller[0]) +- return TRUE; +- +- pRADEONEnt->pCrtc[0] = xf86CrtcCreate(pScrn, &radeon_crtc_funcs); +- if (!pRADEONEnt->pCrtc[0]) +- return FALSE; +- +- pRADEONEnt->Controller[0] = xnfcalloc(sizeof(RADEONCrtcPrivateRec), 1); +- if (!pRADEONEnt->Controller[0]) +- return FALSE; +- +- pRADEONEnt->pCrtc[0]->driver_private = pRADEONEnt->Controller[0]; +- pRADEONEnt->Controller[0]->crtc_id = 0; +- +- if (!pRADEONEnt->HasCRTC2) +- return TRUE; ++ if (mask & 1) { ++ if (pRADEONEnt->Controller[0]) ++ return TRUE; ++ ++ pRADEONEnt->pCrtc[0] = xf86CrtcCreate(pScrn, &radeon_crtc_funcs); ++ if (!pRADEONEnt->pCrtc[0]) ++ return FALSE; ++ ++ pRADEONEnt->Controller[0] = xnfcalloc(sizeof(RADEONCrtcPrivateRec), 1); ++ if (!pRADEONEnt->Controller[0]) ++ return FALSE; ++ ++ pRADEONEnt->pCrtc[0]->driver_private = pRADEONEnt->Controller[0]; ++ pRADEONEnt->Controller[0]->crtc_id = 0; ++ pRADEONEnt->Controller[0]->crtc_offset = 0; ++ } + +- pRADEONEnt->pCrtc[1] = xf86CrtcCreate(pScrn, &radeon_crtc_funcs); +- if (!pRADEONEnt->pCrtc[1]) +- return FALSE; ++ if (mask & 2) { ++ if (!pRADEONEnt->HasCRTC2) ++ return TRUE; ++ ++ pRADEONEnt->pCrtc[1] = xf86CrtcCreate(pScrn, &radeon_crtc_funcs); ++ if (!pRADEONEnt->pCrtc[1]) ++ return FALSE; ++ ++ pRADEONEnt->Controller[1] = xnfcalloc(sizeof(RADEONCrtcPrivateRec), 1); ++ if (!pRADEONEnt->Controller[1]) ++ { ++ xfree(pRADEONEnt->Controller[0]); ++ return FALSE; ++ } + +- pRADEONEnt->Controller[1] = xnfcalloc(sizeof(RADEONCrtcPrivateRec), 1); +- if (!pRADEONEnt->Controller[1]) +- { +- xfree(pRADEONEnt->Controller[0]); +- return FALSE; ++ pRADEONEnt->pCrtc[1]->driver_private = pRADEONEnt->Controller[1]; ++ pRADEONEnt->Controller[1]->crtc_id = 1; ++ pRADEONEnt->Controller[1]->crtc_offset = AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL; + } + +- pRADEONEnt->pCrtc[1]->driver_private = pRADEONEnt->Controller[1]; +- pRADEONEnt->Controller[1]->crtc_id = 1; + return TRUE; + } + +diff --git a/src/radeon_cursor.c b/src/radeon_cursor.c +index ba1159c..0f7e668 100644 +--- a/src/radeon_cursor.c ++++ b/src/radeon_cursor.c +@@ -74,12 +74,12 @@ + #define CURSOR_SWAPPING_START() \ + do { \ + OUTREG(RADEON_SURFACE_CNTL, \ +- (info->ModeReg.surface_cntl | \ ++ (info->ModeReg->surface_cntl | \ + RADEON_NONSURF_AP0_SWP_32BPP | RADEON_NONSURF_AP1_SWP_32BPP) & \ + ~(RADEON_NONSURF_AP0_SWP_16BPP | RADEON_NONSURF_AP1_SWP_16BPP)); \ + } while (0) + #define CURSOR_SWAPPING_END() (OUTREG(RADEON_SURFACE_CNTL, \ +- info->ModeReg.surface_cntl)) ++ info->ModeReg->surface_cntl)) + + #else + +@@ -89,6 +89,25 @@ + + #endif + ++static void ++avivo_setup_cursor(xf86CrtcPtr crtc, Bool enable) ++{ ++ RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; ++ RADEONInfoPtr info = RADEONPTR(crtc->scrn); ++ unsigned char *RADEONMMIO = info->MMIO; ++ ++ OUTREG(AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset, 0); ++ ++ if (enable) { ++ OUTREG(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, ++ info->fbLocation + radeon_crtc->cursor_offset); ++ OUTREG(AVIVO_D1CUR_SIZE + radeon_crtc->crtc_offset, ++ ((CURSOR_WIDTH - 1) << 16) | (CURSOR_HEIGHT - 1)); ++ OUTREG(AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset, ++ AVIVO_D1CURSOR_EN | (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT)); ++ } ++} ++ + void + radeon_crtc_show_cursor (xf86CrtcPtr crtc) + { +@@ -98,19 +117,26 @@ radeon_crtc_show_cursor (xf86CrtcPtr crtc) + RADEONInfoPtr info = RADEONPTR(pScrn); + unsigned char *RADEONMMIO = info->MMIO; + +- switch (crtc_id) { +- case 0: +- OUTREG(RADEON_MM_INDEX, RADEON_CRTC_GEN_CNTL); +- break; +- case 1: +- OUTREG(RADEON_MM_INDEX, RADEON_CRTC2_GEN_CNTL); +- break; +- default: +- return; ++ if (IS_AVIVO_VARIANT) { ++ OUTREG(AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset, ++ INREG(AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset) ++ | AVIVO_D1CURSOR_EN); ++ avivo_setup_cursor(crtc, TRUE); ++ } else { ++ switch (crtc_id) { ++ case 0: ++ OUTREG(RADEON_MM_INDEX, RADEON_CRTC_GEN_CNTL); ++ break; ++ case 1: ++ OUTREG(RADEON_MM_INDEX, RADEON_CRTC2_GEN_CNTL); ++ break; ++ default: ++ return; ++ } ++ ++ OUTREGP(RADEON_MM_DATA, RADEON_CRTC_CUR_EN | 2 << 20, ++ ~(RADEON_CRTC_CUR_EN | RADEON_CRTC_CUR_MODE_MASK)); + } +- +- OUTREGP(RADEON_MM_DATA, RADEON_CRTC_CUR_EN | 2 << 20, +- ~(RADEON_CRTC_CUR_EN | RADEON_CRTC_CUR_MODE_MASK)); + } + + void +@@ -122,18 +148,25 @@ radeon_crtc_hide_cursor (xf86CrtcPtr crtc) + RADEONInfoPtr info = RADEONPTR(pScrn); + unsigned char *RADEONMMIO = info->MMIO; + +- switch (crtc_id) { +- case 0: +- OUTREG(RADEON_MM_INDEX, RADEON_CRTC_GEN_CNTL); +- break; +- case 1: +- OUTREG(RADEON_MM_INDEX, RADEON_CRTC2_GEN_CNTL); +- break; +- default: +- return; +- } +- +- OUTREGP(RADEON_MM_DATA, 0, ~RADEON_CRTC_CUR_EN); ++ if (IS_AVIVO_VARIANT) { ++ OUTREG(AVIVO_D1CUR_CONTROL+ radeon_crtc->crtc_offset, ++ INREG(AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset) ++ & ~(AVIVO_D1CURSOR_EN)); ++ avivo_setup_cursor(crtc, FALSE); ++ } else { ++ switch(crtc_id) { ++ case 0: ++ OUTREG(RADEON_MM_INDEX, RADEON_CRTC_GEN_CNTL); ++ break; ++ case 1: ++ OUTREG(RADEON_MM_INDEX, RADEON_CRTC2_GEN_CNTL); ++ break; ++ default: ++ return; ++ } ++ ++ OUTREGP(RADEON_MM_DATA, 0, ~RADEON_CRTC_CUR_EN); ++ } + } + + void +@@ -158,30 +191,38 @@ radeon_crtc_set_cursor_position (xf86CrtcPtr crtc, int x, int y) + else if (mode->Flags & V_DBLSCAN) + y *= 2; + +- if (crtc_id == 0) { +- OUTREG(RADEON_CUR_HORZ_VERT_OFF, (RADEON_CUR_LOCK +- | (xorigin << 16) +- | yorigin)); +- OUTREG(RADEON_CUR_HORZ_VERT_POSN, (RADEON_CUR_LOCK +- | ((xorigin ? 0 : x) << 16) +- | (yorigin ? 0 : y))); +- RADEONCTRACE(("cursor_offset: 0x%x, yorigin: %d, stride: %d, temp %08X\n", +- radeon_crtc->cursor_offset + pScrn->fbOffset, yorigin, stride, temp)); +- OUTREG(RADEON_CUR_OFFSET, +- radeon_crtc->cursor_offset + pScrn->fbOffset + yorigin * stride); +- } else if (crtc_id == 1) { +- OUTREG(RADEON_CUR2_HORZ_VERT_OFF, (RADEON_CUR2_LOCK +- | (xorigin << 16) +- | yorigin)); +- OUTREG(RADEON_CUR2_HORZ_VERT_POSN, (RADEON_CUR2_LOCK +- | ((xorigin ? 0 : x) << 16) +- | (yorigin ? 0 : y))); +- RADEONCTRACE(("cursor_offset2: 0x%x, yorigin: %d, stride: %d, temp %08X\n", +- radeon_crtc->cursor_offset + pScrn->fbOffset, yorigin, stride, temp)); +- OUTREG(RADEON_CUR2_OFFSET, +- radeon_crtc->cursor_offset + pScrn->fbOffset + yorigin * stride); ++ if (IS_AVIVO_VARIANT) { ++ /* avivo cursor spans the full fb width */ ++ x += crtc->x; ++ y += crtc->y; ++ OUTREG(AVIVO_D1CUR_POSITION + radeon_crtc->crtc_offset, ((xorigin ? 0 : x) << 16) ++ | (yorigin ? 0 : y)); ++ OUTREG(AVIVO_D1CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin); ++ } else { ++ if (crtc_id == 0) { ++ OUTREG(RADEON_CUR_HORZ_VERT_OFF, (RADEON_CUR_LOCK ++ | (xorigin << 16) ++ | yorigin)); ++ OUTREG(RADEON_CUR_HORZ_VERT_POSN, (RADEON_CUR_LOCK ++ | ((xorigin ? 0 : x) << 16) ++ | (yorigin ? 0 : y))); ++ RADEONCTRACE(("cursor_offset: 0x%x, yorigin: %d, stride: %d, temp %08X\n", ++ radeon_crtc->cursor_offset + pScrn->fbOffset, yorigin, stride, temp)); ++ OUTREG(RADEON_CUR_OFFSET, ++ radeon_crtc->cursor_offset + pScrn->fbOffset + yorigin * stride); ++ } else if (crtc_id == 1) { ++ OUTREG(RADEON_CUR2_HORZ_VERT_OFF, (RADEON_CUR2_LOCK ++ | (xorigin << 16) ++ | yorigin)); ++ OUTREG(RADEON_CUR2_HORZ_VERT_POSN, (RADEON_CUR2_LOCK ++ | ((xorigin ? 0 : x) << 16) ++ | (yorigin ? 0 : y))); ++ RADEONCTRACE(("cursor_offset2: 0x%x, yorigin: %d, stride: %d, temp %08X\n", ++ radeon_crtc->cursor_offset + pScrn->fbOffset, yorigin, stride, temp)); ++ OUTREG(RADEON_CUR2_OFFSET, ++ radeon_crtc->cursor_offset + pScrn->fbOffset + yorigin * stride); ++ } + } +- + } + + void +@@ -269,10 +310,11 @@ Bool RADEONCursorInit(ScreenPtr pScreen) + + #ifdef USE_XAA + if (!info->useEXA) { ++ int align = IS_AVIVO_VARIANT ? 4096 : 256; + FBAreaPtr fbarea; + + fbarea = xf86AllocateOffscreenArea(pScreen, width, height, +- 256, NULL, NULL, NULL); ++ align, NULL, NULL, NULL); + + if (!fbarea) { + cursor_offset = 0; +@@ -284,7 +326,7 @@ Bool RADEONCursorInit(ScreenPtr pScreen) + cursor_offset = RADEON_ALIGN((fbarea->box.x1 + + fbarea->box.y1 * width) * + info->CurrentLayout.pixel_bytes, +- 256); ++ align); + + for (c = 0; c < xf86_config->num_crtc; c++) { + xf86CrtcPtr crtc = xf86_config->crtc[c]; +diff --git a/src/radeon_display.c b/src/radeon_display.c +index ea31a82..2043f24 100644 +--- a/src/radeon_display.c ++++ b/src/radeon_display.c +@@ -318,7 +318,7 @@ void RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable) + { + ScrnInfoPtr pScrn = output->scrn; + RADEONInfoPtr info = RADEONPTR(pScrn); +- RADEONSavePtr save = &info->ModeReg; ++ RADEONSavePtr save = info->ModeReg; + unsigned char * RADEONMMIO = info->MMIO; + unsigned long tmp; + RADEONOutputPrivatePtr radeon_output; +@@ -720,7 +720,7 @@ void RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_b + critical_point = 0x10; + } + +- temp = info->SavedReg.grph_buffer_cntl; ++ temp = info->SavedReg->grph_buffer_cntl; + temp &= ~(RADEON_GRPH_STOP_REQ_MASK); + temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT); + temp &= ~(RADEON_GRPH_START_REQ_MASK); +@@ -742,7 +742,7 @@ void RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_b + + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "GRPH_BUFFER_CNTL from %x to %x\n", +- (unsigned int)info->SavedReg.grph_buffer_cntl, ++ (unsigned int)info->SavedReg->grph_buffer_cntl, + (unsigned int)INREG(RADEON_GRPH_BUFFER_CNTL)); + + if (mode2) { +@@ -750,7 +750,7 @@ void RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_b + + if (stop_req > max_stop_req) stop_req = max_stop_req; + +- temp = info->SavedReg.grph2_buffer_cntl; ++ temp = info->SavedReg->grph2_buffer_cntl; + temp &= ~(RADEON_GRPH_STOP_REQ_MASK); + temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT); + temp &= ~(RADEON_GRPH_START_REQ_MASK); +@@ -792,7 +792,7 @@ void RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_b + + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "GRPH2_BUFFER_CNTL from %x to %x\n", +- (unsigned int)info->SavedReg.grph2_buffer_cntl, ++ (unsigned int)info->SavedReg->grph2_buffer_cntl, + (unsigned int)INREG(RADEON_GRPH2_BUFFER_CNTL)); + } + } +@@ -804,7 +804,10 @@ void RADEONInitDispBandwidth(ScrnInfoPtr pScrn) + DisplayModePtr mode1, mode2; + int pixel_bytes2 = 0; + +- mode1 = info->CurrentLayout.mode; ++ if (info->IsPrimary || info->IsSecondary) ++ mode1 = &xf86_config->crtc[0]->mode; ++ else ++ mode1 = info->CurrentLayout.mode; + mode2 = NULL; + pixel_bytes2 = info->CurrentLayout.pixel_bytes; + +diff --git a/src/radeon_dri.c b/src/radeon_dri.c +index 3190451..f1003d7 100644 +--- a/src/radeon_dri.c ++++ b/src/radeon_dri.c +@@ -1188,7 +1188,7 @@ static void RADEONDRIIrqInit(RADEONInfoPtr info, ScreenPtr pScreen) + info->irq = 0; + } else { + unsigned char *RADEONMMIO = info->MMIO; +- info->ModeReg.gen_int_cntl = INREG( RADEON_GEN_INT_CNTL ); ++ info->ModeReg->gen_int_cntl = INREG( RADEON_GEN_INT_CNTL ); + } + } + +@@ -1768,7 +1768,7 @@ void RADEONDRICloseScreen(ScreenPtr pScreen) + RADEONDRISetVBlankInterrupt (pScrn, FALSE); + drmCtlUninstHandler(info->drmFD); + info->irq = 0; +- info->ModeReg.gen_int_cntl = 0; ++ info->ModeReg->gen_int_cntl = 0; + } + + /* De-allocate vertex buffers */ +diff --git a/src/radeon_driver.c b/src/radeon_driver.c +index 25b2119..2002dd3 100644 +--- a/src/radeon_driver.c ++++ b/src/radeon_driver.c +@@ -97,6 +97,7 @@ + #include "xf86cmap.h" + #include "vbe.h" + ++#include "shadow.h" + /* vgaHW definitions */ + #ifdef WITH_VGAHW + #include "vgaHW.h" +@@ -347,6 +348,15 @@ static const char *i2cSymbols[] = { + NULL + }; + ++static const char *shadowSymbols[] = { ++ "shadowAdd", ++ "shadowInit", ++ "shadowSetup", ++ "shadowUpdatePacked", ++ "shadowUpdatePackedWeak", ++ NULL ++}; ++ + void RADEONLoaderRefSymLists(void) + { + /* +@@ -405,23 +415,41 @@ struct RADEONInt10Save { + static Bool RADEONMapMMIO(ScrnInfoPtr pScrn); + static Bool RADEONUnmapMMIO(ScrnInfoPtr pScrn); + +-#if 0 ++static void * ++radeonShadowWindow(ScreenPtr screen, CARD32 row, CARD32 offset, int mode, ++ CARD32 *size, void *closure) ++{ ++ ScrnInfoPtr pScrn = xf86Screens[screen->myNum]; ++ RADEONInfoPtr info = RADEONPTR(pScrn); ++ int stride; ++ ++ stride = (pScrn->displayWidth * pScrn->bitsPerPixel) / 8; ++ *size = stride; ++ ++ return ((CARD8 *)info->FB + pScrn->fbOffset + ++ row * stride + offset); ++} + static Bool + RADEONCreateScreenResources (ScreenPtr pScreen) + { + ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; + RADEONInfoPtr info = RADEONPTR(pScrn); ++ PixmapPtr pixmap; + + pScreen->CreateScreenResources = info->CreateScreenResources; + if (!(*pScreen->CreateScreenResources)(pScreen)) + return FALSE; ++ pScreen->CreateScreenResources = RADEONCreateScreenResources; + +- if (!xf86RandR12CreateScreenResources(pScreen)) +- return FALSE; ++ if (info->r600_shadow_fb) { ++ pixmap = pScreen->GetScreenPixmap(pScreen); + +- return TRUE; ++ if (!shadowAdd(pScreen, pixmap, shadowUpdatePackedWeak(), ++ radeonShadowWindow, 0, NULL)) ++ return FALSE; ++ } ++ return TRUE; + } +-#endif + + RADEONEntPtr RADEONEntPriv(ScrnInfoPtr pScrn) + { +@@ -440,18 +468,20 @@ RADEONPreInt10Save(ScrnInfoPtr pScrn, void **pPtr) + CARD32 CardTmp; + static struct RADEONInt10Save SaveStruct = { 0, 0, 0 }; + +- /* Save the values and zap MEM_CNTL */ +- SaveStruct.MEM_CNTL = INREG(RADEON_MEM_CNTL); +- SaveStruct.MEMSIZE = INREG(RADEON_CONFIG_MEMSIZE); +- SaveStruct.MPP_TB_CONFIG = INREG(RADEON_MPP_TB_CONFIG); ++ if (!IS_AVIVO_VARIANT) { ++ /* Save the values and zap MEM_CNTL */ ++ SaveStruct.MEM_CNTL = INREG(RADEON_MEM_CNTL); ++ SaveStruct.MEMSIZE = INREG(RADEON_CONFIG_MEMSIZE); ++ SaveStruct.MPP_TB_CONFIG = INREG(RADEON_MPP_TB_CONFIG); + +- /* +- * Zap MEM_CNTL and set MPP_TB_CONFIG<31:24> to 4 +- */ +- OUTREG(RADEON_MEM_CNTL, 0); +- CardTmp = SaveStruct.MPP_TB_CONFIG & 0x00ffffffu; +- CardTmp |= 0x04 << 24; +- OUTREG(RADEON_MPP_TB_CONFIG, CardTmp); ++ /* ++ * Zap MEM_CNTL and set MPP_TB_CONFIG<31:24> to 4 ++ */ ++ OUTREG(RADEON_MEM_CNTL, 0); ++ CardTmp = SaveStruct.MPP_TB_CONFIG & 0x00ffffffu; ++ CardTmp |= 0x04 << 24; ++ OUTREG(RADEON_MPP_TB_CONFIG, CardTmp); ++ } + + *pPtr = (void *)&SaveStruct; + } +@@ -468,6 +498,9 @@ RADEONPostInt10Check(ScrnInfoPtr pScrn, void *ptr) + if (!pSave || !pSave->MEM_CNTL) + return; + ++ if (IS_AVIVO_VARIANT) ++ return; ++ + /* + * If either MEM_CNTL is currently zero or inconistent (configured for + * two channels with the two channels configured differently), restore +@@ -718,6 +751,141 @@ void RADEONOUTPLL(ScrnInfoPtr pScrn, int addr, CARD32 data) + RADEONPllErrataAfterData(info); + } + ++/* Read MC register */ ++unsigned RADEONINMC(ScrnInfoPtr pScrn, int addr) ++{ ++ RADEONInfoPtr info = RADEONPTR(pScrn); ++ unsigned char *RADEONMMIO = info->MMIO; ++ CARD32 data; ++ ++ if (IS_AVIVO_VARIANT) { ++ OUTREG(AVIVO_MC_INDEX, (addr & 0xff) | 0x7f0000); ++ (void)INREG(AVIVO_MC_INDEX); ++ data = INREG(AVIVO_MC_DATA); ++ ++ OUTREG(AVIVO_MC_INDEX, 0); ++ (void)INREG(AVIVO_MC_INDEX); ++ } else { ++ OUTREG(R300_MC_IND_INDEX, addr & 0x3f); ++ (void)INREG(R300_MC_IND_INDEX); ++ data = INREG(R300_MC_IND_DATA); ++ ++ OUTREG(R300_MC_IND_INDEX, 0); ++ (void)INREG(R300_MC_IND_INDEX); ++ } ++ ++ return data; ++} ++ ++/* Write MC information */ ++void RADEONOUTMC(ScrnInfoPtr pScrn, int addr, CARD32 data) ++{ ++ RADEONInfoPtr info = RADEONPTR(pScrn); ++ unsigned char *RADEONMMIO = info->MMIO; ++ ++ if (IS_AVIVO_VARIANT) { ++ OUTREG(AVIVO_MC_INDEX, (addr & 0xff) | 0xff0000); ++ (void)INREG(AVIVO_MC_INDEX); ++ OUTREG(AVIVO_MC_DATA, data); ++ OUTREG(AVIVO_MC_INDEX, 0); ++ (void)INREG(AVIVO_MC_INDEX); ++ } else { ++ OUTREG(R300_MC_IND_INDEX, (((addr) & 0x3f) | ++ R300_MC_IND_WR_EN)); ++ (void)INREG(R300_MC_IND_INDEX); ++ OUTREG(R300_MC_IND_DATA, data); ++ OUTREG(R300_MC_IND_INDEX, 0); ++ (void)INREG(R300_MC_IND_INDEX); ++ } ++} ++ ++Bool avivo_get_mc_idle(ScrnInfoPtr pScrn) ++{ ++ RADEONInfoPtr info = RADEONPTR(pScrn); ++ ++ if (info->ChipFamily >= CHIP_FAMILY_R600) { ++ /* no idea where this is on r600 yet */ ++ return TRUE; ++ } else if (info->ChipFamily == CHIP_FAMILY_RV515) { ++ if (INMC(pScrn, RV515_MC_STATUS) & RV515_MC_STATUS_IDLE) ++ return TRUE; ++ else ++ return FALSE; ++ } else { ++ if (INMC(pScrn, R520_MC_STATUS) & R520_MC_STATUS_IDLE) ++ return TRUE; ++ else ++ return FALSE; ++ } ++} ++ ++#define LOC_FB 0x1 ++#define LOC_AGP 0x2 ++void radeon_write_mc_fb_agp_location(ScrnInfoPtr pScrn, int mask, CARD32 fb_loc, CARD32 agp_loc, CARD32 agp_loc_hi) ++{ ++ RADEONInfoPtr info = RADEONPTR(pScrn); ++ unsigned char *RADEONMMIO = info->MMIO; ++ ++ if (info->ChipFamily >= CHIP_FAMILY_R600) { ++ if (mask & LOC_FB) ++ OUTREG(R600_MC_VM_FB_LOCATION, fb_loc); ++ if (mask & LOC_AGP) { ++ OUTREG(R600_MC_VM_AGP_BOT, agp_loc); ++ OUTREG(R600_MC_VM_AGP_TOP, agp_loc_hi); ++ } ++ } else if (info->ChipFamily == CHIP_FAMILY_RV515) { ++ if (mask & LOC_FB) ++ OUTMC(pScrn, RV515_MC_FB_LOCATION, fb_loc); ++ if (mask & LOC_AGP) ++ OUTMC(pScrn, RV515_MC_AGP_LOCATION, agp_loc); ++ (void)INMC(pScrn, RV515_MC_AGP_LOCATION); ++ } else if (info->ChipFamily >= CHIP_FAMILY_R520) { ++ if (mask & LOC_FB) ++ OUTMC(pScrn, R520_MC_FB_LOCATION, fb_loc); ++ if (mask & LOC_AGP) ++ OUTMC(pScrn, R520_MC_AGP_LOCATION, agp_loc); ++ (void)INMC(pScrn, R520_MC_FB_LOCATION); ++ } else { ++ if (mask & LOC_FB) ++ OUTREG(RADEON_MC_FB_LOCATION, fb_loc); ++ if (mask & LOC_AGP) ++ OUTREG(RADEON_MC_AGP_LOCATION, agp_loc); ++ } ++} ++ ++void radeon_read_mc_fb_agp_location(ScrnInfoPtr pScrn, int mask, CARD32 *fb_loc, CARD32 *agp_loc, CARD32 *agp_loc_hi) ++{ ++ RADEONInfoPtr info = RADEONPTR(pScrn); ++ unsigned char *RADEONMMIO = info->MMIO; ++ ++ if (info->ChipFamily >= CHIP_FAMILY_R600) { ++ if (mask & LOC_FB) ++ *fb_loc = INREG(R600_MC_VM_FB_LOCATION); ++ if (mask & LOC_AGP) { ++ *agp_loc = INREG(R600_MC_VM_AGP_BOT); ++ *agp_loc_hi = INREG(R600_MC_VM_AGP_TOP); ++ } ++ } else if (info->ChipFamily == CHIP_FAMILY_RV515) { ++ if (mask & LOC_FB) ++ *fb_loc = INMC(pScrn, RV515_MC_FB_LOCATION); ++ if (mask & LOC_AGP) { ++ *agp_loc = INMC(pScrn, RV515_MC_AGP_LOCATION); ++ *agp_loc_hi = 0; ++ } ++ } else if (info->ChipFamily >= CHIP_FAMILY_R520) { ++ if (mask & LOC_FB) ++ *fb_loc = INMC(pScrn, R520_MC_FB_LOCATION); ++ if (mask & LOC_AGP) { ++ *agp_loc = INMC(pScrn, R520_MC_AGP_LOCATION); ++ *agp_loc_hi = 0; ++ } ++ } else { ++ if (mask & LOC_FB) ++ *fb_loc = INREG(RADEON_MC_FB_LOCATION); ++ if (mask & LOC_AGP) ++ *agp_loc = INREG(RADEON_MC_AGP_LOCATION); ++ } ++} + + #if 0 + /* Read PAL information (only used for debugging) */ +@@ -1022,22 +1190,25 @@ static void RADEONGetClockInfo(ScrnInfoPtr pScrn) + + if (pll->reference_div < 2) pll->reference_div = 12; + } +- + } else { + xf86DrvMsg (pScrn->scrnIndex, X_WARNING, + "Video BIOS not detected, using default clock settings!\n"); + + /* Default min/max PLL values */ + if (info->ChipFamily == CHIP_FAMILY_R420 || info->ChipFamily == CHIP_FAMILY_RV410) { +- pll->min_pll_freq = 20000; +- pll->max_pll_freq = 50000; ++ pll->pll_in_min = 100; ++ pll->pll_in_max = 1350; ++ pll->pll_out_min = 20000; ++ pll->pll_out_max = 50000; + } else { +- pll->min_pll_freq = 12500; +- pll->max_pll_freq = 35000; ++ pll->pll_in_min = 40; ++ pll->pll_in_max = 500; ++ pll->pll_out_min = 12500; ++ pll->pll_out_max = 35000; + } + + if (RADEONProbePLLParameters(pScrn)) +- return; ++ return; + + if (info->IsIGP) + pll->reference_freq = 1432; +@@ -1058,25 +1229,30 @@ static void RADEONGetClockInfo(ScrnInfoPtr pScrn) + * Empirical value changed to 24 to raise pixel clock limit and + * allow higher resolution modes on capable monitors + */ +- pll->max_pll_freq = min(pll->max_pll_freq, ++ pll->pll_out_max = min(pll->pll_out_max, + 24 * info->mclk * 100 / pScrn->bitsPerPixel * + info->RamWidth / 16); + } + + /* card limits for computing PLLs */ ++ if (IS_AVIVO_VARIANT) { ++ pll->min_post_div = 2; ++ pll->max_post_div = 0x7f; ++ } else { ++ pll->min_post_div = 1; ++ pll->max_post_div = 12; //16 on crtc0 ++ } + pll->min_ref_div = 2; + pll->max_ref_div = 0x3ff; + pll->min_feedback_div = 4; + pll->max_feedback_div = 0x7ff; +- pll->pll_in_min = 40; +- pll->pll_in_max = 500; + pll->best_vco = 0; + + xf86DrvMsg (pScrn->scrnIndex, X_INFO, + "PLL parameters: rf=%u rd=%u min=%u max=%u; xclk=%u\n", + pll->reference_freq, + pll->reference_div, +- (unsigned)pll->min_pll_freq, (unsigned)pll->max_pll_freq, ++ (unsigned)pll->pll_out_min, (unsigned)pll->pll_out_max, + pll->xclk); + + /* (Some?) Radeon BIOSes seem too lie about their minimum dot +@@ -1085,7 +1261,7 @@ static void RADEONGetClockInfo(ScrnInfoPtr pScrn) + */ + if (xf86GetOptValFreq(info->Options, OPTION_MIN_DOTCLOCK, + OPTUNITS_MHZ, &min_dotclock)) { +- if (min_dotclock < 12 || min_dotclock*100 >= pll->max_pll_freq) { ++ if (min_dotclock < 12 || min_dotclock*100 >= pll->pll_out_max) { + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + "Illegal minimum dotclock specified %.2f MHz " + "(option ignored)\n", +@@ -1094,8 +1270,8 @@ static void RADEONGetClockInfo(ScrnInfoPtr pScrn) + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + "Forced minimum dotclock to %.2f MHz " + "(instead of detected %.2f MHz)\n", +- min_dotclock, ((double)pll->min_pll_freq/1000)); +- pll->min_pll_freq = min_dotclock * 1000; ++ min_dotclock, ((double)pll->pll_out_min/1000)); ++ pll->pll_out_min = min_dotclock * 1000; + } + } + } +@@ -1196,9 +1372,14 @@ void RADEONInitMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save, + { + save->mc_fb_location = info->mc_fb_location; + save->mc_agp_location = info->mc_agp_location; +- save->display_base_addr = info->fbLocation; +- save->display2_base_addr = info->fbLocation; +- save->ov0_base_addr = info->fbLocation; ++ ++ if (IS_AVIVO_VARIANT) { ++ save->mc_agp_location_hi = info->mc_agp_location_hi; ++ } else { ++ save->display_base_addr = info->fbLocation; ++ save->display2_base_addr = info->fbLocation; ++ save->ov0_base_addr = info->fbLocation; ++ } + } + + static void RADEONInitMemoryMap(ScrnInfoPtr pScrn) +@@ -1208,15 +1389,20 @@ static void RADEONInitMemoryMap(ScrnInfoPtr pScrn) + CARD32 mem_size; + CARD32 aper_size; + +- /* Default to existing values */ +- info->mc_fb_location = INREG(RADEON_MC_FB_LOCATION); +- info->mc_agp_location = INREG(RADEON_MC_AGP_LOCATION); ++ radeon_read_mc_fb_agp_location(pScrn, LOC_FB | LOC_AGP, &info->mc_fb_location, ++ &info->mc_agp_location, &info->mc_agp_location_hi); + + /* We shouldn't use info->videoRam here which might have been clipped + * but the real video RAM instead + */ +- mem_size = INREG(RADEON_CONFIG_MEMSIZE); +- aper_size = INREG(RADEON_CONFIG_APER_SIZE); ++ if (info->ChipFamily >= CHIP_FAMILY_R600) { ++ mem_size = INREG(R600_CONFIG_MEMSIZE); ++ aper_size = INREG(R600_CONFIG_APER_SIZE); ++ } else { ++ mem_size = INREG(RADEON_CONFIG_MEMSIZE); ++ aper_size = INREG(RADEON_CONFIG_APER_SIZE); ++ } ++ + if (mem_size == 0) + mem_size = 0x800000; + +@@ -1245,7 +1431,13 @@ static void RADEONInitMemoryMap(ScrnInfoPtr pScrn) + else + #endif + { +- CARD32 aper0_base = INREG(RADEON_CONFIG_APER_0_BASE); ++ CARD32 aper0_base; ++ ++ if (info->ChipFamily >= CHIP_FAMILY_R600) { ++ aper0_base = INREG(R600_CONFIG_F0_BASE); ++ } else { ++ aper0_base = INREG(RADEON_CONFIG_APER_0_BASE); ++ } + + /* Recent chips have an "issue" with the memory controller, the + * location must be aligned to the size. We just align it down, +@@ -1262,17 +1454,30 @@ static void RADEONInitMemoryMap(ScrnInfoPtr pScrn) + info->ChipFamily == CHIP_FAMILY_RV410) + aper0_base &= ~(mem_size - 1); + +- info->mc_fb_location = (aper0_base >> 16) | ++ if (info->ChipFamily >= CHIP_FAMILY_R600) { ++ info->mc_fb_location = (aper0_base >> 24) | ++ (((aper0_base + mem_size - 1) & 0xff000000U) >> 8); ++ ErrorF("mc fb loc is %08x\n", info->mc_fb_location); ++ } else { ++ info->mc_fb_location = (aper0_base >> 16) | + ((aper0_base + mem_size - 1) & 0xffff0000U); ++ } + } + } +- info->fbLocation = (info->mc_fb_location & 0xffff) << 16; +- ++ if (info->ChipFamily >= CHIP_FAMILY_R600) { ++ info->fbLocation = (info->mc_fb_location & 0xffff) << 24; ++ } else { ++ info->fbLocation = (info->mc_fb_location & 0xffff) << 16; ++ } + /* Just disable the damn AGP apertures for now, it may be + * re-enabled later by the DRM + */ +- info->mc_agp_location = 0xffffffc0; + ++ if (IS_AVIVO_VARIANT) { ++ OUTREG(AVIVO_HDP_FB_LOCATION, info->mc_fb_location); ++ info->mc_agp_location = 0x003f0000; ++ } else ++ info->mc_agp_location = 0xffffffc0; + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + "RADEONInitMemoryMap() : \n"); + xf86DrvMsg(pScrn->scrnIndex, X_INFO, +@@ -1334,9 +1539,14 @@ static CARD32 RADEONGetAccessibleVRAM(ScrnInfoPtr pScrn) + { + RADEONInfoPtr info = RADEONPTR(pScrn); + unsigned char *RADEONMMIO = info->MMIO; +- CARD32 aper_size = INREG(RADEON_CONFIG_APER_SIZE) / 1024; ++ CARD32 aper_size; + unsigned char byte; + ++ if (info->ChipFamily >= CHIP_FAMILY_R600) ++ aper_size = INREG(R600_CONFIG_APER_SIZE) / 1024; ++ else ++ aper_size = INREG(RADEON_CONFIG_APER_SIZE) / 1024; ++ + #ifdef XF86DRI + /* If we use the DRI, we need to check if it's a version that has the + * bug of always cropping MC_FB_LOCATION to one aperture, in which case +@@ -1364,7 +1574,8 @@ static CARD32 RADEONGetAccessibleVRAM(ScrnInfoPtr pScrn) + info->ChipFamily == CHIP_FAMILY_RV350 || + info->ChipFamily == CHIP_FAMILY_RV380 || + info->ChipFamily == CHIP_FAMILY_R420 || +- info->ChipFamily == CHIP_FAMILY_RV410) { ++ info->ChipFamily == CHIP_FAMILY_RV410 || ++ IS_AVIVO_VARIANT) { + OUTREGP (RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL, + ~RADEON_HDP_APER_CNTL); + xf86DrvMsg(pScrn->scrnIndex, X_INFO, +@@ -1411,13 +1622,18 @@ static Bool RADEONPreInitVRAM(ScrnInfoPtr pScrn) + + OUTREG(RADEON_CONFIG_MEMSIZE, pScrn->videoRam * 1024); + } else { +- /* Read VRAM size from card */ +- pScrn->videoRam = INREG(RADEON_CONFIG_MEMSIZE) / 1024; +- +- /* Some production boards of m6 will return 0 if it's 8 MB */ +- if (pScrn->videoRam == 0) { +- pScrn->videoRam = 8192; +- OUTREG(RADEON_CONFIG_MEMSIZE, 0x800000); ++ ++ if (info->ChipFamily >= CHIP_FAMILY_R600) ++ pScrn->videoRam = INREG(R600_CONFIG_MEMSIZE) / 1024; ++ else { ++ /* Read VRAM size from card */ ++ pScrn->videoRam = INREG(RADEON_CONFIG_MEMSIZE) / 1024; ++ ++ /* Some production boards of m6 will return 0 if it's 8 MB */ ++ if (pScrn->videoRam == 0) { ++ pScrn->videoRam = 8192; ++ OUTREG(RADEON_CONFIG_MEMSIZE, 0x800000); ++ } + } + } + +@@ -1437,7 +1653,8 @@ static Bool RADEONPreInitVRAM(ScrnInfoPtr pScrn) + if (pScrn->videoRam > accessible) + pScrn->videoRam = accessible; + +- info->MemCntl = INREG(RADEON_SDRAM_MODE_REG); ++ if (!IS_AVIVO_VARIANT) ++ info->MemCntl = INREG(RADEON_SDRAM_MODE_REG); + info->BusCntl = INREG(RADEON_BUS_CNTL); + + RADEONGetVRamType(pScrn); +@@ -1454,6 +1671,21 @@ static Bool RADEONPreInitVRAM(ScrnInfoPtr pScrn) + xf86DrvMsg(pScrn->scrnIndex, from, + "Mapped VideoRAM: %d kByte (%d bit %s SDRAM)\n", pScrn->videoRam, info->RamWidth, info->IsDDR?"DDR":"SDR"); + ++ if (info->IsPrimary) { ++ pScrn->videoRam /= 2; ++ xf86DrvMsg(pScrn->scrnIndex, X_INFO, ++ "Using %dk of videoram for primary head\n", ++ pScrn->videoRam); ++ } ++ ++ if (info->IsSecondary) { ++ pScrn->videoRam /= 2; ++ info->LinearAddr += pScrn->videoRam * 1024; ++ xf86DrvMsg(pScrn->scrnIndex, X_INFO, ++ "Using %dk of videoram for secondary head\n", ++ pScrn->videoRam); ++ } ++ + pScrn->videoRam &= ~1023; + info->FbMapSize = pScrn->videoRam * 1024; + +@@ -1562,6 +1794,15 @@ static Bool RADEONPreInitChipType(ScrnInfoPtr pScrn) + break; + } + ++ if (info->ChipFamily >= CHIP_FAMILY_R600) { ++ xf86DrvMsg(pScrn->scrnIndex, X_WARNING, ++ "R600 support is mostly incomplete and very experimental\n"); ++ } ++ ++ if ((info->ChipFamily >= CHIP_FAMILY_RV515) && (info->ChipFamily < CHIP_FAMILY_R600)) { ++ xf86DrvMsg(pScrn->scrnIndex, X_WARNING, ++ "R500 support is under development. Please report any issues to xorg-driver-ati@lists.x.org\n"); ++ } + + from = X_PROBED; + info->LinearAddr = PCI_REGION_BASE(info->PciInfo, 0, REGION_MEM) & ~0x1ffffffUL; +@@ -1717,6 +1958,14 @@ static Bool RADEONPreInitChipType(ScrnInfoPtr pScrn) + info->Chipset != PCI_CHIP_RN50_5969); + #endif + ++ if (info->ChipFamily >= CHIP_FAMILY_R600) { ++ info->r600_shadow_fb = TRUE; ++ xf86DrvMsg(pScrn->scrnIndex, X_INFO, ++ "using shadow framebuffer\n"); ++ if (!xf86LoadSubModule(pScrn, "shadow")) ++ return FALSE; ++ xf86LoaderReqSymLists(shadowSymbols, NULL); ++ } + return TRUE; + } + +@@ -1777,6 +2026,12 @@ static Bool RADEONPreInitAccel(ScrnInfoPtr pScrn) + + info->useEXA = FALSE; + ++ if (info->ChipFamily >= CHIP_FAMILY_R600) { ++ xf86DrvMsg(pScrn->scrnIndex, X_DEFAULT, ++ "No acceleration support available on R600 yet.\n"); ++ return TRUE; ++ } ++ + if (!xf86ReturnOptValBool(info->Options, OPTION_NOACCEL, FALSE)) { + int errmaj = 0, errmin = 0; + +@@ -1889,19 +2144,32 @@ static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn) + info->pLibDRMVersion = NULL; + info->pKernelDRMVersion = NULL; + ++ if (xf86IsEntityShared(info->pEnt->index)) { ++ xf86DrvMsg(pScrn->scrnIndex, X_WARNING, ++ "Direct Rendering Disabled -- " ++ "Dual-head configuration is not working with " ++ "DRI at present.\n" ++ "Please use the radeon MergedFB option if you " ++ "want Dual-head with DRI.\n"); ++ return FALSE; ++ } ++ if (info->IsSecondary) ++ return FALSE; ++ + if (info->Chipset == PCI_CHIP_RN50_515E || + info->Chipset == PCI_CHIP_RN50_5969 || + info->Chipset == PCI_CHIP_RC410_5A61 || + info->Chipset == PCI_CHIP_RC410_5A62 || +- info->Chipset == PCI_CHIP_RS485_5975) { ++ info->Chipset == PCI_CHIP_RS485_5975 || ++ info->ChipFamily >= CHIP_FAMILY_R600) { + if (xf86ReturnOptValBool(info->Options, OPTION_DRI, FALSE)) { + xf86DrvMsg(pScrn->scrnIndex, X_WARNING, +- "Direct rendering for RN50/RC410/RS485 forced on -- " ++ "Direct rendering for RN50/RC410/RS485/R600 forced on -- " + "This is NOT officially supported at the hardware level " + "and may cause instability or lockups\n"); + } else { + xf86DrvMsg(pScrn->scrnIndex, X_INFO, +- "Direct rendering not officially supported on RN50/RC410\n"); ++ "Direct rendering not officially supported on RN50/RC410/R600\n"); + return FALSE; + } + } +@@ -2087,7 +2355,7 @@ static void RADEONPreInitColorTiling(ScrnInfoPtr pScrn) + + info->allowColorTiling = xf86ReturnOptValBool(info->Options, + OPTION_COLOR_TILING, TRUE); +- if (IS_R300_VARIANT) { ++ if (IS_R300_VARIANT || IS_AVIVO_VARIANT) { + /* this may be 4096 on r4xx -- need to double check */ + info->MaxSurfaceWidth = 3968; /* one would have thought 4096...*/ + info->MaxLines = 4096; +@@ -2099,6 +2367,13 @@ static void RADEONPreInitColorTiling(ScrnInfoPtr pScrn) + if (!info->allowColorTiling) + return; + ++ if (info->ChipFamily >= CHIP_FAMILY_R600) ++ info->allowColorTiling = FALSE; ++ ++ /* for zaphod disable tiling for now */ ++ if (info->IsPrimary || info->IsSecondary) ++ info->allowColorTiling = FALSE; ++ + #ifdef XF86DRI + if (info->directRenderingEnabled && + info->pKernelDRMVersion->version_minor < 14) { +@@ -2319,12 +2594,41 @@ static void RADEONPreInitBIOS(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10) + #endif + } + ++static void RADEONFixZaphodOutputs(ScrnInfoPtr pScrn) ++{ ++ RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); ++ RADEONInfoPtr info = RADEONPTR(pScrn); ++ xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(pScrn); ++ int i; ++ ++ if (info->IsPrimary) { ++ xf86OutputDestroy(config->output[0]); ++ while(config->num_output > 1) { ++ xf86OutputDestroy(config->output[1]); ++ } ++ } else { ++ while(config->num_output > 1) { ++ xf86OutputDestroy(config->output[1]); ++ } ++ } ++} ++ + static Bool RADEONPreInitControllers(ScrnInfoPtr pScrn) + { + xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(pScrn); ++ RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); ++ RADEONInfoPtr info = RADEONPTR(pScrn); + int i; ++ int mask; + +- if (!RADEONAllocateControllers(pScrn)) ++ if (!info->IsPrimary && !info->IsSecondary) ++ mask = 3; ++ else if (info->IsPrimary) ++ mask = 1; ++ else ++ mask = 2; ++ ++ if (!RADEONAllocateControllers(pScrn, mask)) + return FALSE; + + RADEONGetClockInfo(pScrn); +@@ -2332,6 +2636,11 @@ static Bool RADEONPreInitControllers(ScrnInfoPtr pScrn) + if (!RADEONSetupConnectors(pScrn)) { + return FALSE; + } ++ ++ if (info->IsPrimary || info->IsSecondary) { ++ /* fixup outputs for zaphod */ ++ RADEONFixZaphodOutputs(pScrn); ++ } + + RADEONPrintPortMap(pScrn); + +@@ -2341,6 +2650,10 @@ static Bool RADEONPreInitControllers(ScrnInfoPtr pScrn) + + output->status = (*output->funcs->detect) (output); + ErrorF("finished output detect: %d\n", i); ++ if (info->IsPrimary || info->IsSecondary) { ++ if (output->status != XF86OutputStatusConnected) ++ return FALSE; ++ } + } + ErrorF("finished all detect\n"); + return TRUE; +@@ -2378,6 +2691,8 @@ _X_EXPORT Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) + void *int10_save = NULL; + const char *s; + int crtc_max_X, crtc_max_Y; ++ RADEONEntPtr pRADEONEnt; ++ DevUnion* pPriv; + + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "RADEONPreInit\n"); +@@ -2388,9 +2703,39 @@ _X_EXPORT Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) + info = RADEONPTR(pScrn); + info->MMIO = NULL; + ++ info->IsSecondary = FALSE; ++ info->IsPrimary = FALSE; ++ + info->pEnt = xf86GetEntityInfo(pScrn->entityList[pScrn->numEntities - 1]); + if (info->pEnt->location.type != BUS_PCI) goto fail; + ++ pPriv = xf86GetEntityPrivate(pScrn->entityList[0], ++ getRADEONEntityIndex()); ++ pRADEONEnt = pPriv->ptr; ++ ++ if(xf86IsEntityShared(pScrn->entityList[0])) ++ { ++ if(xf86IsPrimInitDone(pScrn->entityList[0])) ++ { ++ info->IsSecondary = TRUE; ++ pRADEONEnt->pSecondaryScrn = pScrn; ++ info->SavedReg = &pRADEONEnt->SavedReg; ++ info->ModeReg = &pRADEONEnt->ModeReg; ++ } ++ else ++ { ++ info->IsPrimary = TRUE; ++ xf86SetPrimInitDone(pScrn->entityList[0]); ++ pRADEONEnt->pPrimaryScrn = pScrn; ++ pRADEONEnt->HasSecondary = FALSE; ++ info->SavedReg = &pRADEONEnt->SavedReg; ++ info->ModeReg = &pRADEONEnt->ModeReg; ++ } ++ } else { ++ info->SavedReg = &pRADEONEnt->SavedReg; ++ info->ModeReg = &pRADEONEnt->ModeReg; ++ } ++ + info->PciInfo = xf86GetPciInfoForEntity(info->pEnt->index); + info->PciTag = pciTag(PCI_DEV_BUS(info->PciInfo), + PCI_DEV_DEV(info->PciInfo), +@@ -2557,7 +2902,7 @@ _X_EXPORT Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) + crtc_max_X = 1600; + crtc_max_Y = 1200; + } else { +- if (IS_R300_VARIANT) { ++ if (IS_R300_VARIANT || IS_AVIVO_VARIANT) { + crtc_max_X = 2560; + crtc_max_Y = 1200; + } else { +@@ -2738,10 +3083,11 @@ static void RADEONLoadPalette(ScrnInfoPtr pScrn, int numColors, + + /* Make the change through RandR */ + #ifdef RANDR_12_INTERFACE +- RRCrtcGammaSet(crtc->randr_crtc, lut_r, lut_g, lut_b); +-#else +- crtc->funcs->gamma_set(crtc, lut_r, lut_g, lut_b, 256); ++ if (crtc->randr_crtc) ++ RRCrtcGammaSet(crtc->randr_crtc, lut_r, lut_g, lut_b); ++ else + #endif ++ crtc->funcs->gamma_set(crtc, lut_r, lut_g, lut_b, 256); + } + } + +@@ -3152,15 +3498,6 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, + char* s; + #endif + +-#ifdef XF86DRI +- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, +- "RADEONScreenInit %lx %ld %d\n", +- pScrn->memPhysBase, pScrn->fbOffset, info->frontOffset); +-#else +- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, +- "RADEONScreenInit %lx %ld\n", +- pScrn->memPhysBase, pScrn->fbOffset); +-#endif + + info->accelOn = FALSE; + #ifdef USE_XAA +@@ -3170,6 +3507,16 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, + pScrn->fbOffset = info->frontOffset; + #endif + ++ if (info->IsSecondary) pScrn->fbOffset = pScrn->videoRam * 1024; ++#ifdef XF86DRI ++ xf86DrvMsg(pScrn->scrnIndex, X_INFO, ++ "RADEONScreenInit %lx %ld %d\n", ++ pScrn->memPhysBase, pScrn->fbOffset, info->frontOffset); ++#else ++ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, ++ "RADEONScreenInit %lx %ld\n", ++ pScrn->memPhysBase, pScrn->fbOffset); ++#endif + if (!RADEONMapMem(pScrn)) return FALSE; + + #ifdef XF86DRI +@@ -3184,9 +3531,10 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, + + RADEONSave(pScrn); + +- RADEONDisableDisplays(pScrn); ++ if (!IS_AVIVO_VARIANT) ++ RADEONDisableDisplays(pScrn); + +- if (info->IsMobility) { ++ if (info->IsMobility && !IS_AVIVO_VARIANT) { + if (xf86ReturnOptValBool(info->Options, OPTION_DYNAMIC_CLOCKS, FALSE)) { + RADEONSetDynamicClock(pScrn, 1); + } else { +@@ -3385,13 +3733,32 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, + #endif + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "Initializing fb layer\n"); ++ ++ if (info->r600_shadow_fb) { ++ info->fb_shadow = xcalloc(1, ++ pScrn->displayWidth * pScrn->virtualY * ++ ((pScrn->bitsPerPixel + 7) >> 3)); ++ if (info->fb_shadow == NULL) { ++ xf86DrvMsg(pScrn->scrnIndex, X_ERROR, ++ "Failed to allocate shadow framebuffer\n"); ++ info->r600_shadow_fb = FALSE; ++ } else { ++ if (!fbScreenInit(pScreen, info->fb_shadow, ++ pScrn->virtualX, pScrn->virtualY, ++ pScrn->xDpi, pScrn->yDpi, pScrn->displayWidth, ++ pScrn->bitsPerPixel)) ++ return FALSE; ++ } ++ } + +- /* Init fb layer */ +- if (!fbScreenInit(pScreen, info->FB + pScrn->fbOffset, +- pScrn->virtualX, pScrn->virtualY, +- pScrn->xDpi, pScrn->yDpi, pScrn->displayWidth, +- pScrn->bitsPerPixel)) +- return FALSE; ++ if (info->r600_shadow_fb == FALSE) { ++ /* Init fb layer */ ++ if (!fbScreenInit(pScreen, info->FB, ++ pScrn->virtualX, pScrn->virtualY, ++ pScrn->xDpi, pScrn->yDpi, pScrn->displayWidth, ++ pScrn->bitsPerPixel)) ++ return FALSE; ++ } + + xf86SetBlackWhitePixels(pScreen); + +@@ -3477,7 +3844,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, + * our local image to make sure we restore them properly on mode + * changes or VT switches + */ +- RADEONAdjustMemMapRegisters(pScrn, &info->ModeReg); ++ RADEONAdjustMemMapRegisters(pScrn, info->ModeReg); + + if ((info->DispPriority == 1) && (info->cardType==CARD_AGP)) { + /* we need to re-calculate bandwidth because of AGPMode difference. */ +@@ -3503,6 +3870,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, + + RADEONChangeSurfaces(pScrn); + ++ + /* Enable aceleration */ + if (!xf86ReturnOptValBool(info->Options, OPTION_NOACCEL, FALSE)) { + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, +@@ -3565,9 +3933,17 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, + RADEONDGAInit(pScreen); + + /* Init Xv */ +- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, +- "Initializing Xv\n"); +- RADEONInitVideo(pScreen); ++ if (!IS_AVIVO_VARIANT) { ++ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, ++ "Initializing Xv\n"); ++ RADEONInitVideo(pScreen); ++ } ++ ++ if (info->r600_shadow_fb == TRUE) { ++ if (!shadowSetup(pScreen)) { ++ return FALSE; ++ } ++ } + + /* Provide SaveScreen & wrap BlockHandler and CloseScreen */ + /* Wrap CloseScreen */ +@@ -3576,6 +3952,8 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, + pScreen->SaveScreen = RADEONSaveScreen; + info->BlockHandler = pScreen->BlockHandler; + pScreen->BlockHandler = RADEONBlockHandler; ++ info->CreateScreenResources = pScreen->CreateScreenResources; ++ pScreen->CreateScreenResources = RADEONCreateScreenResources; + + if (!xf86CrtcScreenInit (pScreen)) + return FALSE; +@@ -3614,184 +3992,252 @@ void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn, + RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); + unsigned char *RADEONMMIO = info->MMIO; + int timeout; ++ CARD32 mc_fb_loc, mc_agp_loc, mc_agp_loc_hi; + ++ radeon_read_mc_fb_agp_location(pScrn, LOC_FB | LOC_AGP, &mc_fb_loc, ++ &mc_agp_loc, &mc_agp_loc_hi); ++ ++ if (info->IsSecondary) ++ return; + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + "RADEONRestoreMemMapRegisters() : \n"); + xf86DrvMsg(pScrn->scrnIndex, X_INFO, +- " MC_FB_LOCATION : 0x%08x\n", +- (unsigned)restore->mc_fb_location); ++ " MC_FB_LOCATION : 0x%08x 0x%08x\n", ++ (unsigned)restore->mc_fb_location, mc_fb_loc); + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + " MC_AGP_LOCATION : 0x%08x\n", + (unsigned)restore->mc_agp_location); + +- /* Write memory mapping registers only if their value change +- * since we must ensure no access is done while they are +- * reprogrammed +- */ +- if (INREG(RADEON_MC_FB_LOCATION) != restore->mc_fb_location || +- INREG(RADEON_MC_AGP_LOCATION) != restore->mc_agp_location) { +- CARD32 crtc_ext_cntl, crtc_gen_cntl, crtc2_gen_cntl=0, ov0_scale_cntl; +- CARD32 old_mc_status, status_idle; ++ if (IS_AVIVO_VARIANT) { + +- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, +- " Map Changed ! Applying ...\n"); ++ if (mc_fb_loc != restore->mc_fb_location || ++ mc_agp_loc != restore->mc_agp_location) { ++ CARD32 tmp; + +- /* Make sure engine is idle. We assume the CCE is stopped +- * at this point +- */ +- RADEONWaitForIdleMMIO(pScrn); ++ RADEONWaitForIdleMMIO(pScrn); + +- if (info->IsIGP) +- goto igp_no_mcfb; ++ OUTREG(AVIVO_D1VGA_CONTROL, INREG(AVIVO_D1VGA_CONTROL) & ~AVIVO_DVGA_CONTROL_MODE_ENABLE); ++ OUTREG(AVIVO_D2VGA_CONTROL, INREG(AVIVO_D2VGA_CONTROL) & ~AVIVO_DVGA_CONTROL_MODE_ENABLE); + +- /* Capture MC_STATUS in case things go wrong ... */ +- old_mc_status = INREG(RADEON_MC_STATUS); +- +- /* Stop display & memory access */ +- ov0_scale_cntl = INREG(RADEON_OV0_SCALE_CNTL); +- OUTREG(RADEON_OV0_SCALE_CNTL, ov0_scale_cntl & ~RADEON_SCALER_ENABLE); +- crtc_ext_cntl = INREG(RADEON_CRTC_EXT_CNTL); +- OUTREG(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl | RADEON_CRTC_DISPLAY_DIS); +- crtc_gen_cntl = INREG(RADEON_CRTC_GEN_CNTL); +- RADEONWaitForVerticalSync(pScrn); +- OUTREG(RADEON_CRTC_GEN_CNTL, +- (crtc_gen_cntl +- & ~(RADEON_CRTC_CUR_EN | RADEON_CRTC_ICON_EN)) +- | RADEON_CRTC_DISP_REQ_EN_B | RADEON_CRTC_EXT_DISP_EN); +- +- if (pRADEONEnt->HasCRTC2) { +- crtc2_gen_cntl = INREG(RADEON_CRTC2_GEN_CNTL); +- RADEONWaitForVerticalSync2(pScrn); +- OUTREG(RADEON_CRTC2_GEN_CNTL, +- (crtc2_gen_cntl +- & ~(RADEON_CRTC2_CUR_EN | RADEON_CRTC2_ICON_EN)) +- | RADEON_CRTC2_DISP_REQ_EN_B); +- } ++ /* Stop display & memory access */ ++ tmp = INREG(AVIVO_D1CRTC_CONTROL); ++ OUTREG(AVIVO_D1CRTC_CONTROL, tmp & ~AVIVO_CRTC_EN); + +- /* Make sure the chip settles down (paranoid !) */ +- usleep(100000); ++ tmp = INREG(AVIVO_D2CRTC_CONTROL); ++ OUTREG(AVIVO_D2CRTC_CONTROL, tmp & ~AVIVO_CRTC_EN); + +- /* Wait for MC idle */ +- if (IS_R300_VARIANT) +- status_idle = R300_MC_IDLE; +- else +- status_idle = RADEON_MC_IDLE; ++ tmp = INREG(AVIVO_D2CRTC_CONTROL); + +- timeout = 0; +- while (!(INREG(RADEON_MC_STATUS) & status_idle)) { +- if (++timeout > 1000000) { +- xf86DrvMsg(pScrn->scrnIndex, X_ERROR, +- "Timeout trying to update memory controller settings !\n"); +- xf86DrvMsg(pScrn->scrnIndex, X_ERROR, +- "MC_STATUS = 0x%08x (on entry = 0x%08x)\n", +- INREG(RADEON_MC_STATUS), (unsigned int)old_mc_status); +- xf86DrvMsg(pScrn->scrnIndex, X_ERROR, +- "You will probably crash now ... \n"); +- /* Nothing we can do except maybe try to kill the server, +- * let's wait 2 seconds to leave the above message a chance +- * to maybe hit the disk and continue trying to setup despite +- * the MC being non-idle +- */ +- usleep(2000000); ++ usleep(10000); ++ timeout = 0; ++ while (!(avivo_get_mc_idle(pScrn))) { ++ if (++timeout > 1000000) { ++ xf86DrvMsg(pScrn->scrnIndex, X_ERROR, ++ "Timeout trying to update memory controller settings !\n"); ++ xf86DrvMsg(pScrn->scrnIndex, X_ERROR, ++ "You will probably crash now ... \n"); ++ /* Nothing we can do except maybe try to kill the server, ++ * let's wait 2 seconds to leave the above message a chance ++ * to maybe hit the disk and continue trying to setup despite ++ * the MC being non-idle ++ */ ++ usleep(2000000); ++ } ++ usleep(10); ++ } ++ ++ radeon_write_mc_fb_agp_location(pScrn, LOC_FB | LOC_AGP, ++ restore->mc_fb_location, ++ restore->mc_agp_location, ++ restore->mc_agp_location_hi); ++ ++ if (info->ChipFamily < CHIP_FAMILY_R600) { ++ OUTREG(AVIVO_HDP_FB_LOCATION, restore->mc_fb_location); + } +- usleep(10); ++ ++ /* Reset the engine and HDP */ ++ RADEONEngineReset(pScrn); + } ++ } else { + +- /* Update maps, first clearing out AGP to make sure we don't get +- * a temporary overlap ++ /* Write memory mapping registers only if their value change ++ * since we must ensure no access is done while they are ++ * reprogrammed + */ +- OUTREG(RADEON_MC_AGP_LOCATION, 0xfffffffc); +- OUTREG(RADEON_MC_FB_LOCATION, restore->mc_fb_location); +- igp_no_mcfb: +- OUTREG(RADEON_MC_AGP_LOCATION, restore->mc_agp_location); +- /* Make sure map fully reached the chip */ +- (void)INREG(RADEON_MC_FB_LOCATION); ++ if (mc_fb_loc != restore->mc_fb_location || ++ mc_agp_loc != restore->mc_agp_location) { ++ CARD32 crtc_ext_cntl, crtc_gen_cntl, crtc2_gen_cntl=0, ov0_scale_cntl; ++ CARD32 old_mc_status, status_idle; + +- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, +- " Map applied, resetting engine ...\n"); ++ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, ++ " Map Changed ! Applying ...\n"); + +- /* Reset the engine and HDP */ +- RADEONEngineReset(pScrn); ++ /* Make sure engine is idle. We assume the CCE is stopped ++ * at this point ++ */ ++ RADEONWaitForIdleMMIO(pScrn); + +- /* Make sure we have sane offsets before re-enabling the CRTCs, disable +- * stereo, clear offsets, and wait for offsets to catch up with hw +- */ ++ if (info->IsIGP) ++ goto igp_no_mcfb; + +- OUTREG(RADEON_CRTC_OFFSET_CNTL, RADEON_CRTC_OFFSET_FLIP_CNTL); +- OUTREG(RADEON_CRTC_OFFSET, 0); +- OUTREG(RADEON_CUR_OFFSET, 0); +- timeout = 0; +- while(INREG(RADEON_CRTC_OFFSET) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET) { +- if (timeout++ > 1000000) { +- xf86DrvMsg(pScrn->scrnIndex, X_ERROR, +- "Timeout waiting for CRTC offset to update !\n"); +- break; ++ /* Capture MC_STATUS in case things go wrong ... */ ++ old_mc_status = INREG(RADEON_MC_STATUS); ++ ++ /* Stop display & memory access */ ++ ov0_scale_cntl = INREG(RADEON_OV0_SCALE_CNTL); ++ OUTREG(RADEON_OV0_SCALE_CNTL, ov0_scale_cntl & ~RADEON_SCALER_ENABLE); ++ crtc_ext_cntl = INREG(RADEON_CRTC_EXT_CNTL); ++ OUTREG(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl | RADEON_CRTC_DISPLAY_DIS); ++ crtc_gen_cntl = INREG(RADEON_CRTC_GEN_CNTL); ++ RADEONWaitForVerticalSync(pScrn); ++ OUTREG(RADEON_CRTC_GEN_CNTL, ++ (crtc_gen_cntl ++ & ~(RADEON_CRTC_CUR_EN | RADEON_CRTC_ICON_EN)) ++ | RADEON_CRTC_DISP_REQ_EN_B | RADEON_CRTC_EXT_DISP_EN); ++ ++ if (pRADEONEnt->HasCRTC2) { ++ crtc2_gen_cntl = INREG(RADEON_CRTC2_GEN_CNTL); ++ RADEONWaitForVerticalSync2(pScrn); ++ OUTREG(RADEON_CRTC2_GEN_CNTL, ++ (crtc2_gen_cntl ++ & ~(RADEON_CRTC2_CUR_EN | RADEON_CRTC2_ICON_EN)) ++ | RADEON_CRTC2_DISP_REQ_EN_B); + } +- usleep(1000); +- } +- if (pRADEONEnt->HasCRTC2) { +- OUTREG(RADEON_CRTC2_OFFSET_CNTL, RADEON_CRTC2_OFFSET_FLIP_CNTL); +- OUTREG(RADEON_CRTC2_OFFSET, 0); +- OUTREG(RADEON_CUR2_OFFSET, 0); ++ ++ /* Make sure the chip settles down (paranoid !) */ ++ usleep(100000); ++ ++ /* Wait for MC idle */ ++ if (IS_R300_VARIANT) ++ status_idle = R300_MC_IDLE; ++ else ++ status_idle = RADEON_MC_IDLE; ++ ++ timeout = 0; ++ while (!(INREG(RADEON_MC_STATUS) & status_idle)) { ++ if (++timeout > 1000000) { ++ xf86DrvMsg(pScrn->scrnIndex, X_ERROR, ++ "Timeout trying to update memory controller settings !\n"); ++ xf86DrvMsg(pScrn->scrnIndex, X_ERROR, ++ "MC_STATUS = 0x%08x (on entry = 0x%08x)\n", ++ INREG(RADEON_MC_STATUS), (unsigned int)old_mc_status); ++ xf86DrvMsg(pScrn->scrnIndex, X_ERROR, ++ "You will probably crash now ... \n"); ++ /* Nothing we can do except maybe try to kill the server, ++ * let's wait 2 seconds to leave the above message a chance ++ * to maybe hit the disk and continue trying to setup despite ++ * the MC being non-idle ++ */ ++ usleep(2000000); ++ } ++ usleep(10); ++ } ++ ++ /* Update maps, first clearing out AGP to make sure we don't get ++ * a temporary overlap ++ */ ++ OUTREG(RADEON_MC_AGP_LOCATION, 0xfffffffc); ++ OUTREG(RADEON_MC_FB_LOCATION, restore->mc_fb_location); ++ radeon_write_mc_fb_agp_location(pScrn, LOC_FB | LOC_AGP, restore->mc_fb_location, ++ 0xfffffffc, 0); ++ igp_no_mcfb: ++ radeon_write_mc_fb_agp_location(pScrn, LOC_AGP, 0, ++ restore->mc_agp_location, 0); ++ /* Make sure map fully reached the chip */ ++ (void)INREG(RADEON_MC_FB_LOCATION); ++ ++ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, ++ " Map applied, resetting engine ...\n"); ++ ++ /* Reset the engine and HDP */ ++ RADEONEngineReset(pScrn); ++ ++ /* Make sure we have sane offsets before re-enabling the CRTCs, disable ++ * stereo, clear offsets, and wait for offsets to catch up with hw ++ */ ++ ++ OUTREG(RADEON_CRTC_OFFSET_CNTL, RADEON_CRTC_OFFSET_FLIP_CNTL); ++ OUTREG(RADEON_CRTC_OFFSET, 0); ++ OUTREG(RADEON_CUR_OFFSET, 0); + timeout = 0; +- while(INREG(RADEON_CRTC2_OFFSET) & RADEON_CRTC2_OFFSET__GUI_TRIG_OFFSET) { ++ while(INREG(RADEON_CRTC_OFFSET) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET) { + if (timeout++ > 1000000) { + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, +- "Timeout waiting for CRTC2 offset to update !\n"); ++ "Timeout waiting for CRTC offset to update !\n"); + break; + } + usleep(1000); + } ++ if (pRADEONEnt->HasCRTC2) { ++ OUTREG(RADEON_CRTC2_OFFSET_CNTL, RADEON_CRTC2_OFFSET_FLIP_CNTL); ++ OUTREG(RADEON_CRTC2_OFFSET, 0); ++ OUTREG(RADEON_CUR2_OFFSET, 0); ++ timeout = 0; ++ while(INREG(RADEON_CRTC2_OFFSET) & RADEON_CRTC2_OFFSET__GUI_TRIG_OFFSET) { ++ if (timeout++ > 1000000) { ++ xf86DrvMsg(pScrn->scrnIndex, X_ERROR, ++ "Timeout waiting for CRTC2 offset to update !\n"); ++ break; ++ } ++ usleep(1000); ++ } ++ } + } +- } + +- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, +- "Updating display base addresses...\n"); ++ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, ++ "Updating display base addresses...\n"); + +- OUTREG(RADEON_DISPLAY_BASE_ADDR, restore->display_base_addr); +- if (pRADEONEnt->HasCRTC2) +- OUTREG(RADEON_DISPLAY2_BASE_ADDR, restore->display2_base_addr); +- OUTREG(RADEON_OV0_BASE_ADDR, restore->ov0_base_addr); +- (void)INREG(RADEON_OV0_BASE_ADDR); ++ OUTREG(RADEON_DISPLAY_BASE_ADDR, restore->display_base_addr); ++ if (pRADEONEnt->HasCRTC2) ++ OUTREG(RADEON_DISPLAY2_BASE_ADDR, restore->display2_base_addr); ++ OUTREG(RADEON_OV0_BASE_ADDR, restore->ov0_base_addr); ++ (void)INREG(RADEON_OV0_BASE_ADDR); + +- /* More paranoia delays, wait 100ms */ +- usleep(100000); ++ /* More paranoia delays, wait 100ms */ ++ usleep(100000); + +- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, +- "Memory map updated.\n"); +- } ++ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, ++ "Memory map updated.\n"); ++ } ++} + + #ifdef XF86DRI + static void RADEONAdjustMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save) + { + RADEONInfoPtr info = RADEONPTR(pScrn); +- unsigned char *RADEONMMIO = info->MMIO; +- CARD32 fb, agp; +- +- fb = INREG(RADEON_MC_FB_LOCATION); +- agp = INREG(RADEON_MC_AGP_LOCATION); ++ CARD32 fb, agp, agp_hi; ++ int changed; + +- if (fb != info->mc_fb_location || agp != info->mc_agp_location) { +- xf86DrvMsg(pScrn->scrnIndex, X_WARNING, +- "DRI init changed memory map, adjusting ...\n"); +- xf86DrvMsg(pScrn->scrnIndex, X_WARNING, +- " MC_FB_LOCATION was: 0x%08x is: 0x%08x\n", +- (unsigned)info->mc_fb_location, (unsigned)fb); +- xf86DrvMsg(pScrn->scrnIndex, X_WARNING, +- " MC_AGP_LOCATION was: 0x%08x is: 0x%08x\n", +- (unsigned)info->mc_agp_location, (unsigned)agp); +- info->mc_fb_location = fb; +- info->mc_agp_location = agp; +- info->fbLocation = (save->mc_fb_location & 0xffff) << 16; +- info->dst_pitch_offset = +- (((pScrn->displayWidth * info->CurrentLayout.pixel_bytes / 64) +- << 22) | ((info->fbLocation + pScrn->fbOffset) >> 10)); ++ if (info->IsSecondary) ++ return; + ++ radeon_read_mc_fb_agp_location(pScrn, LOC_FB | LOC_AGP, &fb, &agp, &agp_hi); ++ ++ if (fb != info->mc_fb_location || agp != info->mc_agp_location || ++ agp_hi || info->mc_agp_location_hi) ++ changed = 1; + +- RADEONInitMemMapRegisters(pScrn, save, info); ++ if (changed) { ++ xf86DrvMsg(pScrn->scrnIndex, X_WARNING, ++ "DRI init changed memory map, adjusting ...\n"); ++ xf86DrvMsg(pScrn->scrnIndex, X_WARNING, ++ " MC_FB_LOCATION was: 0x%08lx is: 0x%08lx\n", ++ info->mc_fb_location, fb); ++ xf86DrvMsg(pScrn->scrnIndex, X_WARNING, ++ " MC_AGP_LOCATION was: 0x%08lx is: 0x%08lx\n", ++ info->mc_agp_location, agp); ++ info->mc_fb_location = fb; ++ info->mc_agp_location = agp; ++ if (info->ChipFamily >= CHIP_FAMILY_R600) ++ info->fbLocation = (info->mc_fb_location & 0xffff) << 24; ++ else ++ info->fbLocation = (info->mc_fb_location & 0xffff) << 16; + +- /* Adjust the various offsets */ +- RADEONRestoreMemMapRegisters(pScrn, save); ++ info->dst_pitch_offset = ++ (((pScrn->displayWidth * info->CurrentLayout.pixel_bytes / 64) ++ << 22) | ((info->fbLocation + pScrn->fbOffset) >> 10)); ++ RADEONInitMemMapRegisters(pScrn, save, info); ++ RADEONRestoreMemMapRegisters(pScrn, save); + } + + #ifdef USE_EXA +@@ -3826,6 +4272,9 @@ void RADEONRestoreCommonRegisters(ScrnInfoPtr pScrn, + RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); + unsigned char *RADEONMMIO = info->MMIO; + ++ if (info->IsSecondary) ++ return; ++ + OUTREG(RADEON_OVR_CLR, restore->ovr_clr); + OUTREG(RADEON_OVR_WID_LEFT_RIGHT, restore->ovr_wid_left_right); + OUTREG(RADEON_OVR_WID_TOP_BOTTOM, restore->ovr_wid_top_bottom); +@@ -4692,7 +5141,7 @@ void RADEONChangeSurfaces(ScrnInfoPtr pScrn) + #endif + if (info->ChipFamily < CHIP_FAMILY_R200) { + color_pattern = RADEON_SURF_TILE_COLOR_MACRO; +- } else if (IS_R300_VARIANT) { ++ } else if (IS_R300_VARIANT || IS_AVIVO_VARIANT) { + color_pattern = R300_SURF_TILE_COLOR_MACRO; + } else { + color_pattern = R200_SURF_TILE_COLOR_MACRO; +@@ -4731,7 +5180,7 @@ void RADEONChangeSurfaces(ScrnInfoPtr pScrn) + drmsurfalloc.flags = swap_pattern; + + if (info->tilingEnabled) { +- if (IS_R300_VARIANT) ++ if (IS_R300_VARIANT || IS_AVIVO_VARIANT) + drmsurfalloc.flags |= (width_bytes / 8) | color_pattern; + else + drmsurfalloc.flags |= (width_bytes / 16) | color_pattern; +@@ -4756,7 +5205,7 @@ void RADEONChangeSurfaces(ScrnInfoPtr pScrn) + depth_pattern = RADEON_SURF_TILE_DEPTH_16BPP; + else + depth_pattern = RADEON_SURF_TILE_DEPTH_32BPP; +- } else if (IS_R300_VARIANT) { ++ } else if (IS_R300_VARIANT || IS_AVIVO_VARIANT) { + if (depthCpp == 2) + depth_pattern = R300_SURF_TILE_COLOR_MACRO; + else +@@ -4776,7 +5225,7 @@ void RADEONChangeSurfaces(ScrnInfoPtr pScrn) + drmRadeonSurfaceAlloc drmsurfalloc; + drmsurfalloc.size = depthBufferSize; + drmsurfalloc.address = info->depthOffset; +- if (IS_R300_VARIANT) ++ if (IS_R300_VARIANT || IS_AVIVO_VARIANT) + drmsurfalloc.flags = swap_pattern | (depth_width_bytes / 8) | depth_pattern; + else + drmsurfalloc.flags = swap_pattern | (depth_width_bytes / 16) | depth_pattern; +@@ -4794,7 +5243,7 @@ void RADEONChangeSurfaces(ScrnInfoPtr pScrn) + unsigned char *RADEONMMIO = info->MMIO; + /* we don't need anything like WaitForFifo, no? */ + if (info->tilingEnabled) { +- if (IS_R300_VARIANT) ++ if (IS_R300_VARIANT || IS_AVIVO_VARIANT) + surf_info |= (width_bytes / 8) | color_pattern; + else + surf_info |= (width_bytes / 16) | color_pattern; +@@ -4808,7 +5257,7 @@ void RADEONChangeSurfaces(ScrnInfoPtr pScrn) + } + + /* Update surface images */ +- RADEONSaveSurfaces(pScrn, &info->ModeReg); ++ RADEONSaveSurfaces(pScrn, info->ModeReg); + } + + /* Read memory map */ +@@ -4817,11 +5266,14 @@ static void RADEONSaveMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save) + RADEONInfoPtr info = RADEONPTR(pScrn); + unsigned char *RADEONMMIO = info->MMIO; + +- save->mc_fb_location = INREG(RADEON_MC_FB_LOCATION); +- save->mc_agp_location = INREG(RADEON_MC_AGP_LOCATION); +- save->display_base_addr = INREG(RADEON_DISPLAY_BASE_ADDR); +- save->display2_base_addr = INREG(RADEON_DISPLAY2_BASE_ADDR); +- save->ov0_base_addr = INREG(RADEON_OV0_BASE_ADDR); ++ radeon_read_mc_fb_agp_location(pScrn, LOC_FB | LOC_AGP, &save->mc_fb_location, ++ &save->mc_agp_location, &save->mc_agp_location_hi); ++ ++ if (!IS_AVIVO_VARIANT) { ++ save->display_base_addr = INREG(RADEON_DISPLAY_BASE_ADDR); ++ save->display2_base_addr = INREG(RADEON_DISPLAY2_BASE_ADDR); ++ save->ov0_base_addr = INREG(RADEON_OV0_BASE_ADDR); ++ } + } + + /* Read common registers */ +@@ -5130,13 +5582,326 @@ static void RADEONSavePalette(ScrnInfoPtr pScrn, RADEONSavePtr save) + } + #endif + ++void avivo_save(ScrnInfoPtr pScrn, RADEONSavePtr save) ++{ ++ RADEONInfoPtr info = RADEONPTR(pScrn); ++ unsigned char *RADEONMMIO = info->MMIO; ++ struct avivo_state *state = &save->avivo; ++ ++ // state->vga_memory_base = INREG(AVIVO_VGA_MEMORY_BASE); ++ // state->vga_fb_start = INREG(AVIVO_VGA_FB_START); ++ state->vga1_cntl = INREG(AVIVO_D1VGA_CONTROL); ++ state->vga2_cntl = INREG(AVIVO_D2VGA_CONTROL); ++ ++ state->crtc_master_en = INREG(AVIVO_DC_CRTC_MASTER_EN); ++ state->crtc_tv_control = INREG(AVIVO_DC_CRTC_TV_CONTROL); ++ ++ state->pll1.ref_div_src = INREG(AVIVO_EXT1_PPLL_REF_DIV_SRC); ++ state->pll1.ref_div = INREG(AVIVO_EXT1_PPLL_REF_DIV); ++ state->pll1.fb_div = INREG(AVIVO_EXT1_PPLL_FB_DIV); ++ state->pll1.post_div_src = INREG(AVIVO_EXT1_PPLL_POST_DIV_SRC); ++ state->pll1.post_div = INREG(AVIVO_EXT1_PPLL_POST_DIV); ++ state->pll1.ext_ppll_cntl = INREG(AVIVO_EXT1_PPLL_CNTL); ++ state->pll1.pll_cntl = INREG(AVIVO_P1PLL_CNTL); ++ state->pll1.int_ss_cntl = INREG(AVIVO_P1PLL_INT_SS_CNTL); ++ ++ state->pll2.ref_div_src = INREG(AVIVO_EXT1_PPLL_REF_DIV_SRC); ++ state->pll2.ref_div = INREG(AVIVO_EXT2_PPLL_REF_DIV); ++ state->pll2.fb_div = INREG(AVIVO_EXT2_PPLL_FB_DIV); ++ state->pll2.post_div_src = INREG(AVIVO_EXT2_PPLL_POST_DIV_SRC); ++ state->pll2.post_div = INREG(AVIVO_EXT2_PPLL_POST_DIV); ++ state->pll2.ext_ppll_cntl = INREG(AVIVO_EXT2_PPLL_CNTL); ++ state->pll2.pll_cntl = INREG(AVIVO_P2PLL_CNTL); ++ state->pll2.int_ss_cntl = INREG(AVIVO_P2PLL_INT_SS_CNTL); ++ ++ state->crtc1.pll_source = INREG(AVIVO_PCLK_CRTC1_CNTL); ++ ++ state->crtc1.h_total = INREG(AVIVO_D1CRTC_H_TOTAL); ++ state->crtc1.h_blank_start_end = INREG(AVIVO_D1CRTC_H_BLANK_START_END); ++ state->crtc1.h_sync_a = INREG(AVIVO_D1CRTC_H_SYNC_A); ++ state->crtc1.h_sync_a_cntl = INREG(AVIVO_D1CRTC_H_SYNC_A_CNTL); ++ state->crtc1.h_sync_b = INREG(AVIVO_D1CRTC_H_SYNC_B); ++ state->crtc1.h_sync_b_cntl = INREG(AVIVO_D1CRTC_H_SYNC_B_CNTL); ++ ++ state->crtc1.v_total = INREG(AVIVO_D1CRTC_V_TOTAL); ++ state->crtc1.v_blank_start_end = INREG(AVIVO_D1CRTC_V_BLANK_START_END); ++ state->crtc1.v_sync_a = INREG(AVIVO_D1CRTC_V_SYNC_A); ++ state->crtc1.v_sync_a_cntl = INREG(AVIVO_D1CRTC_V_SYNC_A_CNTL); ++ state->crtc1.v_sync_b = INREG(AVIVO_D1CRTC_V_SYNC_B); ++ state->crtc1.v_sync_b_cntl = INREG(AVIVO_D1CRTC_V_SYNC_B_CNTL); ++ ++ state->crtc1.control = INREG(AVIVO_D1CRTC_CONTROL); ++ state->crtc1.blank_control = INREG(AVIVO_D1CRTC_BLANK_CONTROL); ++ state->crtc1.interlace_control = INREG(AVIVO_D1CRTC_INTERLACE_CONTROL); ++ state->crtc1.stereo_control = INREG(AVIVO_D1CRTC_STEREO_CONTROL); ++ ++ state->crtc1.cursor_control = INREG(AVIVO_D1CUR_CONTROL); ++ ++ state->grph1.enable = INREG(AVIVO_D1GRPH_ENABLE); ++ state->grph1.control = INREG(AVIVO_D1GRPH_CONTROL); ++ state->grph1.control = INREG(AVIVO_D1GRPH_CONTROL); ++ state->grph1.prim_surf_addr = INREG(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS); ++ state->grph1.sec_surf_addr = INREG(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS); ++ state->grph1.pitch = INREG(AVIVO_D1GRPH_PITCH); ++ state->grph1.x_offset = INREG(AVIVO_D1GRPH_SURFACE_OFFSET_X); ++ state->grph1.y_offset = INREG(AVIVO_D1GRPH_SURFACE_OFFSET_Y); ++ state->grph1.x_start = INREG(AVIVO_D1GRPH_X_START); ++ state->grph1.y_start = INREG(AVIVO_D1GRPH_Y_START); ++ state->grph1.x_end = INREG(AVIVO_D1GRPH_X_END); ++ state->grph1.y_end = INREG(AVIVO_D1GRPH_Y_END); ++ ++ state->grph1.viewport_start = INREG(AVIVO_D1MODE_VIEWPORT_START); ++ state->grph1.viewport_size = INREG(AVIVO_D1MODE_VIEWPORT_SIZE); ++ state->grph1.scl_enable = INREG(AVIVO_D1SCL_SCALER_ENABLE); ++ ++ state->crtc2.pll_source = INREG(AVIVO_PCLK_CRTC2_CNTL); ++ ++ state->crtc2.h_total = INREG(AVIVO_D2CRTC_H_TOTAL); ++ state->crtc2.h_blank_start_end = INREG(AVIVO_D2CRTC_H_BLANK_START_END); ++ state->crtc2.h_sync_a = INREG(AVIVO_D2CRTC_H_SYNC_A); ++ state->crtc2.h_sync_a_cntl = INREG(AVIVO_D2CRTC_H_SYNC_A_CNTL); ++ state->crtc2.h_sync_b = INREG(AVIVO_D2CRTC_H_SYNC_B); ++ state->crtc2.h_sync_b_cntl = INREG(AVIVO_D2CRTC_H_SYNC_B_CNTL); ++ ++ state->crtc2.v_total = INREG(AVIVO_D2CRTC_V_TOTAL); ++ state->crtc2.v_blank_start_end = INREG(AVIVO_D2CRTC_V_BLANK_START_END); ++ state->crtc2.v_sync_a = INREG(AVIVO_D2CRTC_V_SYNC_A); ++ state->crtc2.v_sync_a_cntl = INREG(AVIVO_D2CRTC_V_SYNC_A_CNTL); ++ state->crtc2.v_sync_b = INREG(AVIVO_D2CRTC_V_SYNC_B); ++ state->crtc2.v_sync_b_cntl = INREG(AVIVO_D2CRTC_V_SYNC_B_CNTL); ++ ++ state->crtc2.control = INREG(AVIVO_D2CRTC_CONTROL); ++ state->crtc2.blank_control = INREG(AVIVO_D2CRTC_BLANK_CONTROL); ++ state->crtc2.interlace_control = INREG(AVIVO_D2CRTC_INTERLACE_CONTROL); ++ state->crtc2.stereo_control = INREG(AVIVO_D2CRTC_STEREO_CONTROL); ++ ++ state->crtc2.cursor_control = INREG(AVIVO_D2CUR_CONTROL); ++ ++ state->grph2.enable = INREG(AVIVO_D2GRPH_ENABLE); ++ state->grph2.control = INREG(AVIVO_D2GRPH_CONTROL); ++ state->grph2.control = INREG(AVIVO_D2GRPH_CONTROL); ++ state->grph2.prim_surf_addr = INREG(AVIVO_D2GRPH_PRIMARY_SURFACE_ADDRESS); ++ state->grph2.sec_surf_addr = INREG(AVIVO_D2GRPH_SECONDARY_SURFACE_ADDRESS); ++ state->grph2.pitch = INREG(AVIVO_D2GRPH_PITCH); ++ state->grph2.x_offset = INREG(AVIVO_D2GRPH_SURFACE_OFFSET_X); ++ state->grph2.y_offset = INREG(AVIVO_D2GRPH_SURFACE_OFFSET_Y); ++ state->grph2.x_start = INREG(AVIVO_D2GRPH_X_START); ++ state->grph2.y_start = INREG(AVIVO_D2GRPH_Y_START); ++ state->grph2.x_end = INREG(AVIVO_D2GRPH_X_END); ++ state->grph2.y_end = INREG(AVIVO_D2GRPH_Y_END); ++ ++ state->grph2.viewport_start = INREG(AVIVO_D2MODE_VIEWPORT_START); ++ state->grph2.viewport_size = INREG(AVIVO_D2MODE_VIEWPORT_SIZE); ++ state->grph2.scl_enable = INREG(AVIVO_D2SCL_SCALER_ENABLE); ++ ++ state->daca.enable = INREG(AVIVO_DACA_ENABLE); ++ state->daca.source_select = INREG(AVIVO_DACA_SOURCE_SELECT); ++ state->daca.force_output_cntl = INREG(AVIVO_DACA_FORCE_OUTPUT_CNTL); ++ state->daca.powerdown = INREG(AVIVO_DACA_POWERDOWN); ++ ++ state->dacb.enable = INREG(AVIVO_DACB_ENABLE); ++ state->dacb.source_select = INREG(AVIVO_DACB_SOURCE_SELECT); ++ state->dacb.force_output_cntl = INREG(AVIVO_DACB_FORCE_OUTPUT_CNTL); ++ state->dacb.powerdown = INREG(AVIVO_DACB_POWERDOWN); ++ ++ state->tmds1.cntl = INREG(AVIVO_TMDSA_CNTL); ++ state->tmds1.source_select = INREG(AVIVO_TMDSA_SOURCE_SELECT); ++ state->tmds1.bit_depth_cntl = INREG(AVIVO_TMDSA_BIT_DEPTH_CONTROL); ++ state->tmds1.data_sync = INREG(AVIVO_TMDSA_DATA_SYNCHRONIZATION); ++ state->tmds1.transmitter_enable = INREG(AVIVO_TMDSA_TRANSMITTER_ENABLE); ++ state->tmds1.transmitter_cntl = INREG(AVIVO_TMDSA_TRANSMITTER_CONTROL); ++ ++ state->tmds2.cntl = INREG(AVIVO_LVTMA_CNTL); ++ state->tmds2.source_select = INREG(AVIVO_LVTMA_SOURCE_SELECT); ++ state->tmds2.bit_depth_cntl = INREG(AVIVO_LVTMA_BIT_DEPTH_CONTROL); ++ state->tmds2.data_sync = INREG(AVIVO_LVTMA_DATA_SYNCHRONIZATION); ++ ++ if (info->ChipFamily >= CHIP_FAMILY_R600) { ++ state->tmds2.transmitter_enable = INREG(R600_LVTMA_TRANSMITTER_ENABLE); ++ state->tmds2.transmitter_cntl = INREG(R600_LVTMA_TRANSMITTER_CONTROL); ++ state->lvtma_pwrseq_cntl = INREG(R600_LVTMA_PWRSEQ_CNTL); ++ state->lvtma_pwrseq_state = INREG(R600_LVTMA_PWRSEQ_STATE); ++ } else { ++ state->tmds2.transmitter_enable = INREG(R500_LVTMA_TRANSMITTER_ENABLE); ++ state->tmds2.transmitter_cntl = INREG(R500_LVTMA_TRANSMITTER_CONTROL); ++ state->lvtma_pwrseq_cntl = INREG(R500_LVTMA_PWRSEQ_CNTL); ++ state->lvtma_pwrseq_state = INREG(R500_LVTMA_PWRSEQ_STATE); ++ } ++ ++ if (state->crtc1.control & AVIVO_CRTC_EN) ++ info->crtc_on = TRUE; ++ ++ if (state->crtc2.control & AVIVO_CRTC_EN) ++ info->crtc2_on = TRUE; ++ ++} ++ ++void avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore) ++{ ++ RADEONInfoPtr info = RADEONPTR(pScrn); ++ unsigned char *RADEONMMIO = info->MMIO; ++ struct avivo_state *state = &restore->avivo; ++ ++ // OUTMC(pScrn, AVIVO_MC_MEMORY_MAP, state->mc_memory_map); ++ // OUTREG(AVIVO_VGA_MEMORY_BASE, state->vga_memory_base); ++ // OUTREG(AVIVO_VGA_FB_START, state->vga_fb_start); ++ ++ ++ OUTREG(AVIVO_DC_CRTC_MASTER_EN, state->crtc_master_en); ++ OUTREG(AVIVO_DC_CRTC_TV_CONTROL, state->crtc_tv_control); ++ ++ OUTREG(AVIVO_EXT1_PPLL_REF_DIV_SRC, state->pll1.ref_div_src); ++ OUTREG(AVIVO_EXT1_PPLL_REF_DIV, state->pll1.ref_div); ++ OUTREG(AVIVO_EXT1_PPLL_FB_DIV, state->pll1.fb_div); ++ OUTREG(AVIVO_EXT1_PPLL_POST_DIV_SRC, state->pll1.post_div_src); ++ OUTREG(AVIVO_EXT1_PPLL_POST_DIV, state->pll1.post_div); ++ OUTREG(AVIVO_EXT1_PPLL_CNTL, state->pll1.ext_ppll_cntl); ++ OUTREG(AVIVO_P1PLL_CNTL, state->pll1.pll_cntl); ++ OUTREG(AVIVO_P1PLL_INT_SS_CNTL, state->pll1.int_ss_cntl); ++ ++ OUTREG(AVIVO_EXT2_PPLL_REF_DIV_SRC, state->pll2.ref_div_src); ++ OUTREG(AVIVO_EXT2_PPLL_REF_DIV, state->pll2.ref_div); ++ OUTREG(AVIVO_EXT2_PPLL_FB_DIV, state->pll2.fb_div); ++ OUTREG(AVIVO_EXT2_PPLL_POST_DIV_SRC, state->pll2.post_div_src); ++ OUTREG(AVIVO_EXT2_PPLL_POST_DIV, state->pll2.post_div); ++ OUTREG(AVIVO_EXT2_PPLL_CNTL, state->pll2.ext_ppll_cntl); ++ OUTREG(AVIVO_P2PLL_CNTL, state->pll2.pll_cntl); ++ OUTREG(AVIVO_P2PLL_INT_SS_CNTL, state->pll2.int_ss_cntl); ++ ++ OUTREG(AVIVO_PCLK_CRTC1_CNTL, state->crtc1.pll_source); ++ ++ OUTREG(AVIVO_D1CRTC_H_TOTAL, state->crtc1.h_total); ++ OUTREG(AVIVO_D1CRTC_H_BLANK_START_END, state->crtc1.h_blank_start_end); ++ OUTREG(AVIVO_D1CRTC_H_SYNC_A, state->crtc1.h_sync_a); ++ OUTREG(AVIVO_D1CRTC_H_SYNC_A_CNTL, state->crtc1.h_sync_a_cntl); ++ OUTREG(AVIVO_D1CRTC_H_SYNC_B, state->crtc1.h_sync_b); ++ OUTREG(AVIVO_D1CRTC_H_SYNC_B_CNTL, state->crtc1.h_sync_b_cntl); ++ ++ OUTREG(AVIVO_D1CRTC_V_TOTAL, state->crtc1.v_total); ++ OUTREG(AVIVO_D1CRTC_V_BLANK_START_END, state->crtc1.v_blank_start_end); ++ OUTREG(AVIVO_D1CRTC_V_SYNC_A, state->crtc1.v_sync_a); ++ OUTREG(AVIVO_D1CRTC_V_SYNC_A_CNTL, state->crtc1.v_sync_a_cntl); ++ OUTREG(AVIVO_D1CRTC_V_SYNC_B, state->crtc1.v_sync_b); ++ OUTREG(AVIVO_D1CRTC_V_SYNC_B_CNTL, state->crtc1.v_sync_b_cntl); ++ ++ OUTREG(AVIVO_D1CRTC_CONTROL, state->crtc1.control); ++ OUTREG(AVIVO_D1CRTC_BLANK_CONTROL, state->crtc1.blank_control); ++ OUTREG(AVIVO_D1CRTC_INTERLACE_CONTROL, state->crtc1.interlace_control); ++ OUTREG(AVIVO_D1CRTC_STEREO_CONTROL, state->crtc1.stereo_control); ++ ++ OUTREG(AVIVO_D1CUR_CONTROL, state->crtc1.cursor_control); ++ ++ OUTREG(AVIVO_D1GRPH_ENABLE, state->grph1.enable); ++ OUTREG(AVIVO_D1GRPH_CONTROL, state->grph1.control); ++ OUTREG(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS, state->grph1.prim_surf_addr); ++ OUTREG(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS, state->grph1.sec_surf_addr); ++ OUTREG(AVIVO_D1GRPH_PITCH, state->grph1.pitch); ++ OUTREG(AVIVO_D1GRPH_SURFACE_OFFSET_X, state->grph1.x_offset); ++ OUTREG(AVIVO_D1GRPH_SURFACE_OFFSET_Y, state->grph1.y_offset); ++ OUTREG(AVIVO_D1GRPH_X_START, state->grph1.x_start); ++ OUTREG(AVIVO_D1GRPH_Y_START, state->grph1.y_start); ++ OUTREG(AVIVO_D1GRPH_X_END, state->grph1.x_end); ++ OUTREG(AVIVO_D1GRPH_Y_END, state->grph1.y_end); ++ ++ OUTREG(AVIVO_D1MODE_VIEWPORT_START, state->grph1.viewport_start); ++ OUTREG(AVIVO_D1MODE_VIEWPORT_SIZE, state->grph1.viewport_size); ++ OUTREG(AVIVO_D1SCL_SCALER_ENABLE, state->grph1.scl_enable); ++ ++ OUTREG(AVIVO_PCLK_CRTC2_CNTL, state->crtc2.pll_source); ++ ++ OUTREG(AVIVO_D2CRTC_H_TOTAL, state->crtc2.h_total); ++ OUTREG(AVIVO_D2CRTC_H_BLANK_START_END, state->crtc2.h_blank_start_end); ++ OUTREG(AVIVO_D2CRTC_H_SYNC_A, state->crtc2.h_sync_a); ++ OUTREG(AVIVO_D2CRTC_H_SYNC_A_CNTL, state->crtc2.h_sync_a_cntl); ++ OUTREG(AVIVO_D2CRTC_H_SYNC_B, state->crtc2.h_sync_b); ++ OUTREG(AVIVO_D2CRTC_H_SYNC_B_CNTL, state->crtc2.h_sync_b_cntl); ++ ++ OUTREG(AVIVO_D2CRTC_V_TOTAL, state->crtc2.v_total); ++ OUTREG(AVIVO_D2CRTC_V_BLANK_START_END, state->crtc2.v_blank_start_end); ++ OUTREG(AVIVO_D2CRTC_V_SYNC_A, state->crtc2.v_sync_a); ++ OUTREG(AVIVO_D2CRTC_V_SYNC_A_CNTL, state->crtc2.v_sync_a_cntl); ++ OUTREG(AVIVO_D2CRTC_V_SYNC_B, state->crtc2.v_sync_b); ++ OUTREG(AVIVO_D2CRTC_V_SYNC_B_CNTL, state->crtc2.v_sync_b_cntl); ++ ++ OUTREG(AVIVO_D2CRTC_CONTROL, state->crtc2.control); ++ OUTREG(AVIVO_D2CRTC_BLANK_CONTROL, state->crtc2.blank_control); ++ OUTREG(AVIVO_D2CRTC_INTERLACE_CONTROL, state->crtc2.interlace_control); ++ OUTREG(AVIVO_D2CRTC_STEREO_CONTROL, state->crtc2.stereo_control); ++ ++ OUTREG(AVIVO_D2CUR_CONTROL, state->crtc2.cursor_control); ++ ++ OUTREG(AVIVO_D2GRPH_ENABLE, state->grph2.enable); ++ OUTREG(AVIVO_D2GRPH_CONTROL, state->grph2.control); ++ OUTREG(AVIVO_D2GRPH_PRIMARY_SURFACE_ADDRESS, state->grph2.prim_surf_addr); ++ OUTREG(AVIVO_D2GRPH_SECONDARY_SURFACE_ADDRESS, state->grph2.sec_surf_addr); ++ OUTREG(AVIVO_D2GRPH_PITCH, state->grph2.pitch); ++ OUTREG(AVIVO_D2GRPH_SURFACE_OFFSET_X, state->grph2.x_offset); ++ OUTREG(AVIVO_D2GRPH_SURFACE_OFFSET_Y, state->grph2.y_offset); ++ OUTREG(AVIVO_D2GRPH_X_START, state->grph2.x_start); ++ OUTREG(AVIVO_D2GRPH_Y_START, state->grph2.y_start); ++ OUTREG(AVIVO_D2GRPH_X_END, state->grph2.x_end); ++ OUTREG(AVIVO_D2GRPH_Y_END, state->grph2.y_end); ++ ++ OUTREG(AVIVO_D2MODE_VIEWPORT_START, state->grph2.viewport_start); ++ OUTREG(AVIVO_D2MODE_VIEWPORT_SIZE, state->grph2.viewport_size); ++ OUTREG(AVIVO_D2SCL_SCALER_ENABLE, state->grph2.scl_enable); ++ ++ ++ OUTREG(AVIVO_DACA_ENABLE, state->daca.enable); ++ OUTREG(AVIVO_DACA_SOURCE_SELECT, state->daca.source_select); ++ OUTREG(AVIVO_DACA_FORCE_OUTPUT_CNTL, state->daca.force_output_cntl); ++ OUTREG(AVIVO_DACA_POWERDOWN, state->daca.powerdown); ++ ++ OUTREG(AVIVO_TMDSA_CNTL, state->tmds1.cntl); ++ OUTREG(AVIVO_TMDSA_BIT_DEPTH_CONTROL, state->tmds1.bit_depth_cntl); ++ OUTREG(AVIVO_TMDSA_DATA_SYNCHRONIZATION, state->tmds1.data_sync); ++ OUTREG(AVIVO_TMDSA_TRANSMITTER_ENABLE, state->tmds1.transmitter_enable); ++ OUTREG(AVIVO_TMDSA_TRANSMITTER_CONTROL, state->tmds1.transmitter_cntl); ++ OUTREG(AVIVO_TMDSA_SOURCE_SELECT, state->tmds1.source_select); ++ ++ OUTREG(AVIVO_DACB_ENABLE, state->dacb.enable); ++ OUTREG(AVIVO_DACB_SOURCE_SELECT, state->dacb.source_select); ++ OUTREG(AVIVO_DACB_FORCE_OUTPUT_CNTL, state->dacb.force_output_cntl); ++ OUTREG(AVIVO_DACB_POWERDOWN, state->dacb.powerdown); ++ ++ OUTREG(AVIVO_LVTMA_CNTL, state->tmds2.cntl); ++ OUTREG(AVIVO_LVTMA_BIT_DEPTH_CONTROL, state->tmds2.bit_depth_cntl); ++ OUTREG(AVIVO_LVTMA_DATA_SYNCHRONIZATION, state->tmds2.data_sync); ++ OUTREG(AVIVO_LVTMA_SOURCE_SELECT, state->tmds2.source_select); ++ ++ if (info->ChipFamily >= CHIP_FAMILY_R600) { ++ OUTREG(R600_LVTMA_TRANSMITTER_ENABLE, state->tmds2.transmitter_enable); ++ OUTREG(R600_LVTMA_TRANSMITTER_CONTROL, state->tmds2.transmitter_cntl); ++ OUTREG(R600_LVTMA_PWRSEQ_CNTL, state->lvtma_pwrseq_cntl); ++ OUTREG(R600_LVTMA_PWRSEQ_STATE, state->lvtma_pwrseq_state); ++ } else { ++ OUTREG(R500_LVTMA_TRANSMITTER_ENABLE, state->tmds2.transmitter_enable); ++ OUTREG(R500_LVTMA_TRANSMITTER_CONTROL, state->tmds2.transmitter_cntl); ++ OUTREG(R500_LVTMA_PWRSEQ_CNTL, state->lvtma_pwrseq_cntl); ++ OUTREG(R500_LVTMA_PWRSEQ_STATE, state->lvtma_pwrseq_state); ++ } ++ ++ OUTREG(AVIVO_D1VGA_CONTROL, state->vga1_cntl); ++ OUTREG(AVIVO_D2VGA_CONTROL, state->vga2_cntl); ++} ++ ++void avivo_restore_vga_regs(ScrnInfoPtr pScrn, RADEONSavePtr restore) ++{ ++ RADEONInfoPtr info = RADEONPTR(pScrn); ++ unsigned char *RADEONMMIO = info->MMIO; ++ struct avivo_state *state = &restore->avivo; ++ ++ OUTREG(AVIVO_D1VGA_CONTROL, state->vga1_cntl); ++ OUTREG(AVIVO_D2VGA_CONTROL, state->vga2_cntl); ++} ++ + /* Save everything needed to restore the original VC state */ + static void RADEONSave(ScrnInfoPtr pScrn) + { + RADEONInfoPtr info = RADEONPTR(pScrn); + RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); + unsigned char *RADEONMMIO = info->MMIO; +- RADEONSavePtr save = &info->SavedReg; ++ RADEONSavePtr save = info->SavedReg; + + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "RADEONSave\n"); +@@ -5160,26 +5925,33 @@ static void RADEONSave(ScrnInfoPtr pScrn) + vgaHWLock(hwp); + } + #endif +- save->dp_datatype = INREG(RADEON_DP_DATATYPE); +- save->rbbm_soft_reset = INREG(RADEON_RBBM_SOFT_RESET); +- save->clock_cntl_index = INREG(RADEON_CLOCK_CNTL_INDEX); +- RADEONPllErrataAfterIndex(info); + +- RADEONSaveMemMapRegisters(pScrn, save); +- RADEONSaveCommonRegisters(pScrn, save); +- RADEONSavePLLRegisters(pScrn, save); +- RADEONSaveCrtcRegisters(pScrn, save); +- RADEONSaveFPRegisters(pScrn, save); +- RADEONSaveBIOSRegisters(pScrn, save); +- RADEONSaveDACRegisters(pScrn, save); +- if (pRADEONEnt->HasCRTC2) { +- RADEONSaveCrtc2Registers(pScrn, save); +- RADEONSavePLL2Registers(pScrn, save); +- } +- if (info->InternalTVOut) +- RADEONSaveTVRegisters(pScrn, save); +- +- RADEONSaveSurfaces(pScrn, save); ++ if (IS_AVIVO_VARIANT) { ++ RADEONSaveMemMapRegisters(pScrn, save); ++ avivo_save(pScrn, save); ++ } else { ++ save->dp_datatype = INREG(RADEON_DP_DATATYPE); ++ save->rbbm_soft_reset = INREG(RADEON_RBBM_SOFT_RESET); ++ save->clock_cntl_index = INREG(RADEON_CLOCK_CNTL_INDEX); ++ RADEONPllErrataAfterIndex(info); ++ ++ RADEONSaveMemMapRegisters(pScrn, save); ++ RADEONSaveCommonRegisters(pScrn, save); ++ RADEONSavePLLRegisters(pScrn, save); ++ RADEONSaveCrtcRegisters(pScrn, save); ++ RADEONSaveFPRegisters(pScrn, save); ++ RADEONSaveBIOSRegisters(pScrn, save); ++ RADEONSaveDACRegisters(pScrn, save); ++ if (pRADEONEnt->HasCRTC2) { ++ RADEONSaveCrtc2Registers(pScrn, save); ++ RADEONSavePLL2Registers(pScrn, save); ++ } ++ if (info->InternalTVOut) ++ RADEONSaveTVRegisters(pScrn, save); ++ } ++ ++ RADEONSaveSurfaces(pScrn, save); ++ + } + + /* Restore the original (text) mode */ +@@ -5188,7 +5960,7 @@ void RADEONRestore(ScrnInfoPtr pScrn) + RADEONInfoPtr info = RADEONPTR(pScrn); + RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); + unsigned char *RADEONMMIO = info->MMIO; +- RADEONSavePtr restore = &info->SavedReg; ++ RADEONSavePtr restore = info->SavedReg; + xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); + xf86CrtcPtr crtc; + +@@ -5202,33 +5974,40 @@ void RADEONRestore(ScrnInfoPtr pScrn) + + RADEONBlank(pScrn); + +- OUTREG(RADEON_CLOCK_CNTL_INDEX, restore->clock_cntl_index); +- RADEONPllErrataAfterIndex(info); +- OUTREG(RADEON_RBBM_SOFT_RESET, restore->rbbm_soft_reset); +- OUTREG(RADEON_DP_DATATYPE, restore->dp_datatype); +- OUTREG(RADEON_GRPH_BUFFER_CNTL, restore->grph_buffer_cntl); +- OUTREG(RADEON_GRPH2_BUFFER_CNTL, restore->grph2_buffer_cntl); ++ if (IS_AVIVO_VARIANT) { ++ RADEONRestoreMemMapRegisters(pScrn, restore); ++ avivo_restore(pScrn, restore); ++ } else { ++ OUTREG(RADEON_CLOCK_CNTL_INDEX, restore->clock_cntl_index); ++ RADEONPllErrataAfterIndex(info); ++ OUTREG(RADEON_RBBM_SOFT_RESET, restore->rbbm_soft_reset); ++ OUTREG(RADEON_DP_DATATYPE, restore->dp_datatype); ++ OUTREG(RADEON_GRPH_BUFFER_CNTL, restore->grph_buffer_cntl); ++ OUTREG(RADEON_GRPH2_BUFFER_CNTL, restore->grph2_buffer_cntl); + +- RADEONRestoreMemMapRegisters(pScrn, restore); +- RADEONRestoreCommonRegisters(pScrn, restore); ++ if (!info->IsSecondary) { ++ RADEONRestoreMemMapRegisters(pScrn, restore); ++ RADEONRestoreCommonRegisters(pScrn, restore); + +- if (pRADEONEnt->HasCRTC2) { +- RADEONRestoreCrtc2Registers(pScrn, restore); +- RADEONRestorePLL2Registers(pScrn, restore); +- } ++ if (pRADEONEnt->HasCRTC2) { ++ RADEONRestoreCrtc2Registers(pScrn, restore); ++ RADEONRestorePLL2Registers(pScrn, restore); ++ } + +- RADEONRestoreBIOSRegisters(pScrn, restore); +- RADEONRestoreCrtcRegisters(pScrn, restore); +- RADEONRestorePLLRegisters(pScrn, restore); +- RADEONRestoreRMXRegisters(pScrn, restore); +- RADEONRestoreFPRegisters(pScrn, restore); +- RADEONRestoreFP2Registers(pScrn, restore); +- RADEONRestoreLVDSRegisters(pScrn, restore); ++ RADEONRestoreBIOSRegisters(pScrn, restore); ++ RADEONRestoreCrtcRegisters(pScrn, restore); ++ RADEONRestorePLLRegisters(pScrn, restore); ++ RADEONRestoreRMXRegisters(pScrn, restore); ++ RADEONRestoreFPRegisters(pScrn, restore); ++ RADEONRestoreFP2Registers(pScrn, restore); ++ RADEONRestoreLVDSRegisters(pScrn, restore); + +- if (info->InternalTVOut) +- RADEONRestoreTVRegisters(pScrn, restore); ++ if (info->InternalTVOut) ++ RADEONRestoreTVRegisters(pScrn, restore); ++ } + +- RADEONRestoreSurfaces(pScrn, restore); ++ RADEONRestoreSurfaces(pScrn, restore); ++ } + + #if 1 + /* Temp fix to "solve" VT switch problems. When switching VTs on +@@ -5256,8 +6035,8 @@ void RADEONRestore(ScrnInfoPtr pScrn) + #endif + + /* need to make sure we don't enable a crtc by accident or we may get a hang */ +- if (pRADEONEnt->HasCRTC2) { +- if (info->crtc2_on) { ++ if (pRADEONEnt->HasCRTC2 && !info->IsSecondary) { ++ if (info->crtc2_on && xf86_config->num_crtc > 1) { + crtc = xf86_config->crtc[1]; + crtc->funcs->dpms(crtc, DPMSModeOn); + } +@@ -5269,6 +6048,8 @@ void RADEONRestore(ScrnInfoPtr pScrn) + /* to restore console mode, DAC registers should be set after every other registers are set, + * otherwise,we may get blank screen + */ ++ if (IS_AVIVO_VARIANT) ++ avivo_restore_vga_regs(pScrn, restore); + RADEONRestoreDACRegisters(pScrn, restore); + + #if 0 +@@ -5448,7 +6229,7 @@ void RADEONDoAdjustFrame(ScrnInfoPtr pScrn, int x, int y, Bool crtc2) + crtcoffsetcntl &= ~RADEON_CRTC_OFFSET_FLIP_CNTL; + #endif + if (info->tilingEnabled) { +- if (IS_R300_VARIANT) { ++ if (IS_R300_VARIANT || IS_AVIVO_VARIANT) { + /* On r300/r400 when tiling is enabled crtc_offset is set to the address of + * the surface. the x/y offsets are handled by the X_Y tile reg for each crtc + * Makes tiling MUCH easier. +@@ -5505,7 +6286,7 @@ void RADEONDoAdjustFrame(ScrnInfoPtr pScrn, int x, int y, Bool crtc2) + } + #endif + +- if (IS_R300_VARIANT) { ++ if (IS_R300_VARIANT || IS_AVIVO_VARIANT) { + OUTREG(xytilereg, crtcxytile); + } else { + OUTREG(regcntl, crtcoffsetcntl); +@@ -5592,7 +6373,7 @@ Bool RADEONEnterVT(int scrnIndex, int flags) + + } + +- RADEONRestoreSurfaces(pScrn, &info->ModeReg); ++ RADEONRestoreSurfaces(pScrn, info->ModeReg); + #ifdef XF86DRI + if (info->directRenderingEnabled) { + if (info->cardType == CARD_PCIE && info->pKernelDRMVersion->version_minor >= 19 && info->FbSecureSize) +@@ -5604,7 +6385,7 @@ Bool RADEONEnterVT(int scrnIndex, int flags) + /* get the DRI back into shape after resume */ + RADEONDRISetVBlankInterrupt (pScrn, TRUE); + RADEONDRIResume(pScrn->pScreen); +- RADEONAdjustMemMapRegisters(pScrn, &info->ModeReg); ++ RADEONAdjustMemMapRegisters(pScrn, info->ModeReg); + + } + #endif +diff --git a/src/radeon_exa_funcs.c b/src/radeon_exa_funcs.c +index 2b7f0e8..278d5a7 100644 +--- a/src/radeon_exa_funcs.c ++++ b/src/radeon_exa_funcs.c +@@ -251,7 +251,7 @@ FUNC_NAME(RADEONUploadToScreen)(PixmapPtr pDst, int x, int y, int w, int h, + #endif + #if X_BYTE_ORDER == X_BIG_ENDIAN + unsigned char *RADEONMMIO = info->MMIO; +- unsigned int swapper = info->ModeReg.surface_cntl & ++ unsigned int swapper = info->ModeReg->surface_cntl & + ~(RADEON_NONSURF_AP0_SWP_32BPP | RADEON_NONSURF_AP1_SWP_32BPP | + RADEON_NONSURF_AP0_SWP_16BPP | RADEON_NONSURF_AP1_SWP_16BPP); + #endif +@@ -311,7 +311,7 @@ FUNC_NAME(RADEONUploadToScreen)(PixmapPtr pDst, int x, int y, int w, int h, + + #if X_BYTE_ORDER == X_BIG_ENDIAN + /* restore byte swapping */ +- OUTREG(RADEON_SURFACE_CNTL, info->ModeReg.surface_cntl); ++ OUTREG(RADEON_SURFACE_CNTL, info->ModeReg->surface_cntl); + #endif + + return TRUE; +@@ -354,7 +354,7 @@ FUNC_NAME(RADEONDownloadFromScreen)(PixmapPtr pSrc, int x, int y, int w, int h, + RINFO_FROM_SCREEN(pSrc->drawable.pScreen); + #if X_BYTE_ORDER == X_BIG_ENDIAN + unsigned char *RADEONMMIO = info->MMIO; +- unsigned int swapper = info->ModeReg.surface_cntl & ++ unsigned int swapper = info->ModeReg->surface_cntl & + ~(RADEON_NONSURF_AP0_SWP_32BPP | RADEON_NONSURF_AP1_SWP_32BPP | + RADEON_NONSURF_AP0_SWP_16BPP | RADEON_NONSURF_AP1_SWP_16BPP); + #endif +@@ -492,7 +492,7 @@ FUNC_NAME(RADEONDownloadFromScreen)(PixmapPtr pSrc, int x, int y, int w, int h, + + #if X_BYTE_ORDER == X_BIG_ENDIAN + /* restore byte swapping */ +- OUTREG(RADEON_SURFACE_CNTL, info->ModeReg.surface_cntl); ++ OUTREG(RADEON_SURFACE_CNTL, info->ModeReg->surface_cntl); + #endif + + return TRUE; +diff --git a/src/radeon_macros.h b/src/radeon_macros.h +index efc9e82..7f532a8 100644 +--- a/src/radeon_macros.h ++++ b/src/radeon_macros.h +@@ -92,12 +92,20 @@ do { \ + + #define OUTPAL_START(idx) \ + do { \ +- OUTREG8(RADEON_PALETTE_INDEX, (idx)); \ ++ if (IS_AVIVO_VARIANT) { \ ++ OUTREG8(AVIVO_DC_LUT_RW_INDEX, (idx)); \ ++ } else { \ ++ OUTREG8(RADEON_PALETTE_INDEX, (idx)); \ ++ } \ + } while (0) + + #define OUTPAL_NEXT(r, g, b) \ + do { \ +- OUTREG(RADEON_PALETTE_DATA, ((r) << 16) | ((g) << 8) | (b)); \ ++ if (IS_AVIVO_VARIANT) { \ ++ OUTREG(AVIVO_DC_LUT_30_COLOR, ((r) << 22) | ((g) << 12) | ((b) << 2)); \ ++ } else { \ ++ OUTREG(RADEON_PALETTE_DATA, ((r) << 16) | ((g) << 8) | (b)); \ ++ } \ + } while (0) + + #define OUTPAL_NEXT_CARD32(v) \ +@@ -113,20 +121,43 @@ do { \ + + #define INPAL_START(idx) \ + do { \ +- OUTREG(RADEON_PALETTE_INDEX, (idx) << 16); \ ++ if (IS_AVIVO_VARIANT) { \ ++ OUTREG8(AVIVO_DC_LUT_RW_INDEX, (idx)); \ ++ } else { \ ++ OUTREG(RADEON_PALETTE_INDEX, (idx) << 16); \ ++ } \ + } while (0) + +-#define INPAL_NEXT() INREG(RADEON_PALETTE_DATA) ++#define INPAL_NEXT() \ ++do { \ ++ if (IS_AVIVO_VARIANT) { \ ++ INREG(AVIVO_DC_LUT_30_COLOR); \ ++ } else { \ ++ INREG(RADEON_PALETTE_DATA); \ ++ } \ ++} while (0) + + #define PAL_SELECT(idx) \ + do { \ +- if (!idx) { \ +- OUTREG(RADEON_DAC_CNTL2, INREG(RADEON_DAC_CNTL2) & \ +- (CARD32)~RADEON_DAC2_PALETTE_ACC_CTL); \ +- } else { \ +- OUTREG(RADEON_DAC_CNTL2, INREG(RADEON_DAC_CNTL2) | \ +- RADEON_DAC2_PALETTE_ACC_CTL); \ +- } \ ++ if (IS_AVIVO_VARIANT) { \ ++ if (!idx) { \ ++ OUTREG(AVIVO_DC_LUT_RW_SELECT, 0); \ ++ } else { \ ++ OUTREG(AVIVO_DC_LUT_RW_SELECT, 1); \ ++ } \ ++ } else { \ ++ if (!idx) { \ ++ OUTREG(RADEON_DAC_CNTL2, INREG(RADEON_DAC_CNTL2) & \ ++ (CARD32)~RADEON_DAC2_PALETTE_ACC_CTL); \ ++ } else { \ ++ OUTREG(RADEON_DAC_CNTL2, INREG(RADEON_DAC_CNTL2) | \ ++ RADEON_DAC2_PALETTE_ACC_CTL); \ ++ } \ ++ } \ + } while (0) + ++#define INMC(pScrn, addr) RADEONINMC(pScrn, addr) ++ ++#define OUTMC(pScrn, addr, val) RADEONOUTMC(pScrn, addr, val) ++ + #endif +diff --git a/src/radeon_modes.c b/src/radeon_modes.c +index 3c4badd..c9e99b8 100644 +--- a/src/radeon_modes.c ++++ b/src/radeon_modes.c +@@ -59,20 +59,22 @@ void RADEONSetPitch (ScrnInfoPtr pScrn) + { + int dummy = pScrn->virtualX; + RADEONInfoPtr info = RADEONPTR(pScrn); ++ int pitch_mask = 0; ++ int align_large; ++ ++ align_large = info->allowColorTiling || IS_AVIVO_VARIANT; + + /* FIXME: May need to validate line pitch here */ + switch (pScrn->depth / 8) { +- case 1: if (info->allowColorTiling) dummy = (pScrn->virtualX + 255) & ~255; +- else dummy = (pScrn->virtualX + 127) & ~127; ++ case 1: pitch_mask = align_large ? 255 : 127; + break; +- case 2: if (info->allowColorTiling) dummy = (pScrn->virtualX + 127) & ~127; +- else dummy = (pScrn->virtualX + 31) & ~31; ++ case 2: pitch_mask = align_large ? 127 : 31; + break; + case 3: +- case 4: if (info->allowColorTiling) dummy = (pScrn->virtualX + 63) & ~63; +- else dummy = (pScrn->virtualX + 15) & ~15; ++ case 4: pitch_mask = align_large ? 63 : 15; + break; + } ++ dummy = (pScrn->virtualX + pitch_mask) & ~pitch_mask; + pScrn->displayWidth = dummy; + info->CurrentLayout.displayWidth = pScrn->displayWidth; + +@@ -214,7 +216,7 @@ RADEONProbeOutputModes(xf86OutputPtr output) + ErrorF("in RADEONProbeOutputModes\n"); + + if (output->status == XF86OutputStatusConnected) { +- if (radeon_output->type == OUTPUT_STV || radeon_output->type == OUTPUT_CTV) { ++ if (OUTPUT_IS_TV) { + modes = RADEONTVModes(output); + } else { + if (output->MonInfo) +diff --git a/src/radeon_output.c b/src/radeon_output.c +index 6454460..5a99094 100644 +--- a/src/radeon_output.c ++++ b/src/radeon_output.c +@@ -46,7 +46,7 @@ + #include "radeon_probe.h" + #include "radeon_version.h" + #include "radeon_tv.h" +- ++#include "radeon_atombios.h" + + const char *MonTypeName[7] = { + "AUTO", +@@ -75,16 +75,6 @@ const char *TMDSTypeName[4] = { + "None" + }; + +-const char *DDCTypeName[7] = { +- "None", +- "MONID", +- "DVI_DDC", +- "VGA_DDC", +- "CRT2_DDC", +- "LCD_DDC", +- "GPIO_DDC" +-}; +- + const char *DACTypeName[4] = { + "Unknown", + "Primary", +@@ -92,18 +82,7 @@ const char *DACTypeName[4] = { + "None" + }; + +-const char *ConnectorTypeName[8] = { +- "None", +- "Proprietary/LVDS", +- "VGA", +- "DVI-I", +- "DVI-D", +- "CTV", +- "STV", +- "Unsupported" +-}; +- +-const char *ConnectorTypeNameATOM[10] = { ++const char *ConnectorTypeName[15] = { + "None", + "VGA", + "DVI-I", +@@ -113,16 +92,26 @@ const char *ConnectorTypeNameATOM[10] = { + "CTV", + "LVDS", + "Digital", ++ "SCART", ++ "HDMI-A", ++ "HDMI-B", ++ "DIN", ++ "DisplayPort", + "Unsupported" + }; + +-const char *OutputType[10] = { ++const char *OutputType[11] = { + "None", + "VGA", + "DVI", ++ "DVI", ++ "DVI", + "LVDS", + "S-video", + "Composite", ++ "Component", ++ "HDMI", ++ "DisplayPort", + }; + + static const RADEONTMDSPll default_tmds_pll[CHIP_FAMILY_LAST][4] = +@@ -154,6 +143,16 @@ static RADEONMonitorType radeon_detect_primary_dac(ScrnInfoPtr pScrn, Bool color + static RADEONMonitorType radeon_detect_tv_dac(ScrnInfoPtr pScrn, Bool color); + static RADEONMonitorType radeon_detect_ext_dac(ScrnInfoPtr pScrn); + static void RADEONGetTMDSInfoFromTable(xf86OutputPtr output); ++#define AVIVO_I2C_DISABLE 0 ++#define AVIVO_I2C_ENABLE 1 ++static Bool AVIVOI2CDoLock(ScrnInfoPtr pScrn, int lock_state, int gpio); ++ ++extern void atombios_output_mode_set(xf86OutputPtr output, ++ DisplayModePtr mode, ++ DisplayModePtr adjusted_mode); ++extern void atombios_output_dpms(xf86OutputPtr output, int mode); ++extern RADEONMonitorType atombios_dac_detect(ScrnInfoPtr pScrn, xf86OutputPtr output); ++extern int atombios_external_tmds_setup(xf86OutputPtr output, DisplayModePtr mode); + + Bool + RADEONDVOReadByte(I2CDevPtr dvo, int addr, CARD8 *ch) +@@ -250,7 +249,6 @@ RADEONRestoreDVOChip(ScrnInfoPtr pScrn, xf86OutputPtr output) + + void RADEONPrintPortMap(ScrnInfoPtr pScrn) + { +- RADEONInfoPtr info = RADEONPTR(pScrn); + xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); + RADEONOutputPrivatePtr radeon_output; + xf86OutputPtr output; +@@ -261,32 +259,63 @@ void RADEONPrintPortMap(ScrnInfoPtr pScrn) + radeon_output = output->driver_private; + + xf86DrvMsg(pScrn->scrnIndex, X_INFO, +- "Port%d:\n Monitor -- %s\n Connector -- %s\n DAC Type -- %s\n TMDS Type -- %s\n DDC Type -- %s\n", ++ "Port%d:\n Monitor -- %s\n Connector -- %s\n DAC Type -- %s\n TMDS Type -- %s\n DDC Type -- 0x%x\n", + o, + MonTypeName[radeon_output->MonType+1], +- info->IsAtomBios ? +- ConnectorTypeNameATOM[radeon_output->ConnectorType]: + ConnectorTypeName[radeon_output->ConnectorType], + DACTypeName[radeon_output->DACType+1], + TMDSTypeName[radeon_output->TMDSType+1], +- DDCTypeName[radeon_output->DDCType]); ++ radeon_output->ddc_line); + } + + } + + static RADEONMonitorType ++avivo_display_ddc_connected(ScrnInfoPtr pScrn, xf86OutputPtr output) ++{ ++ RADEONInfoPtr info = RADEONPTR(pScrn); ++ RADEONMonitorType MonType = MT_NONE; ++ xf86MonPtr MonInfo = NULL; ++ RADEONOutputPrivatePtr radeon_output = output->driver_private; ++ ++ if (radeon_output->pI2CBus) { ++ AVIVOI2CDoLock(pScrn, AVIVO_I2C_ENABLE, radeon_output->ddc_line); ++ MonInfo = xf86OutputGetEDID(output, radeon_output->pI2CBus); ++ AVIVOI2CDoLock(pScrn, AVIVO_I2C_DISABLE, radeon_output->ddc_line); ++ } ++ if (MonInfo) { ++ if (!xf86ReturnOptValBool(info->Options, OPTION_IGNORE_EDID, FALSE)) ++ xf86OutputSetEDID(output, MonInfo); ++ if (radeon_output->type == OUTPUT_LVDS) ++ MonType = MT_LCD; ++ else if (radeon_output->type == OUTPUT_DVI_D) ++ MonType = MT_DFP; ++ else if (radeon_output->type == OUTPUT_HDMI) ++ MonType = MT_DFP; ++ else if (radeon_output->type == OUTPUT_DVI_I && (MonInfo->rawData[0x14] & 0x80)) /* if it's digital and DVI */ ++ MonType = MT_DFP; ++ else ++ MonType = MT_CRT; ++ } else MonType = MT_NONE; ++ ++ xf86DrvMsg(pScrn->scrnIndex, X_INFO, ++ "DDC Type: 0x%x, Detected Monitor Type: %d\n", radeon_output->ddc_line, MonType); ++ ++ return MonType; ++} ++ ++static RADEONMonitorType + RADEONDisplayDDCConnected(ScrnInfoPtr pScrn, xf86OutputPtr output) + { + RADEONInfoPtr info = RADEONPTR(pScrn); + unsigned char *RADEONMMIO = info->MMIO; +- unsigned long DDCReg; ++ CARD32 DDCReg; + RADEONMonitorType MonType = MT_NONE; + xf86MonPtr MonInfo = NULL; + RADEONOutputPrivatePtr radeon_output = output->driver_private; +- RADEONDDCType DDCType = radeon_output->DDCType; + int i, j; + +- DDCReg = radeon_output->DDCReg; ++ DDCReg = radeon_output->ddc_line; + + /* Read and output monitor info using DDC2 over I2C bus */ + if (radeon_output->pI2CBus && info->ddc2 && (DDCReg != RADEON_LCD_GPIO_MASK) && (DDCReg != RADEON_MDGPIO_EN_REG)) { +@@ -357,22 +386,20 @@ RADEONDisplayDDCConnected(ScrnInfoPtr pScrn, xf86OutputPtr output) + if (MonInfo) { + if (!xf86ReturnOptValBool(info->Options, OPTION_IGNORE_EDID, FALSE)) + xf86OutputSetEDID(output, MonInfo); +- if ((info->IsAtomBios && radeon_output->ConnectorType == CONNECTOR_LVDS_ATOM) || +- (!info->IsAtomBios && radeon_output->ConnectorType == CONNECTOR_PROPRIETARY)) { ++ if (radeon_output->type == OUTPUT_LVDS) + MonType = MT_LCD; +- } else if ((info->IsAtomBios && radeon_output->ConnectorType == CONNECTOR_DVI_D_ATOM) || +- (!info->IsAtomBios && radeon_output->ConnectorType == CONNECTOR_DVI_D)) { ++ else if (radeon_output->type == OUTPUT_DVI_D) + MonType = MT_DFP; +- } else if (radeon_output->type == OUTPUT_DVI && +- (MonInfo->rawData[0x14] & 0x80)) { /* if it's digital and DVI */ ++ else if (radeon_output->type == OUTPUT_HDMI) + MonType = MT_DFP; +- } else { ++ else if (radeon_output->type == OUTPUT_DVI_I && (MonInfo->rawData[0x14] & 0x80)) /* if it's digital and DVI */ ++ MonType = MT_DFP; ++ else + MonType = MT_CRT; +- } + } else MonType = MT_NONE; + + xf86DrvMsg(pScrn->scrnIndex, X_INFO, +- "DDC Type: %d, Detected Monitor Type: %d\n", DDCType, MonType); ++ "DDC Type: 0x%x, Detected Monitor Type: %d\n", radeon_output->ddc_line, MonType); + + return MonType; + } +@@ -624,6 +651,45 @@ RADEONCrtIsPhysicallyConnected(ScrnInfoPtr pScrn, int IsCrtDac) + } + #endif + ++static RADEONMonitorType ++legacy_dac_detect(ScrnInfoPtr pScrn, xf86OutputPtr output) ++{ ++ RADEONInfoPtr info = RADEONPTR(pScrn); ++ RADEONOutputPrivatePtr radeon_output = output->driver_private; ++ RADEONMonitorType found = MT_NONE; ++ ++ if (OUTPUT_IS_TV) { ++ if (xf86ReturnOptValBool(info->Options, OPTION_FORCE_TVOUT, FALSE)) { ++ if (radeon_output->type == OUTPUT_STV) ++ radeon_output->MonType = MT_STV; ++ else ++ radeon_output->MonType = MT_CTV; ++ } else { ++ if (info->InternalTVOut) { ++ if (radeon_output->load_detection) ++ radeon_output->MonType = radeon_detect_tv(pScrn); ++ else ++ radeon_output->MonType = MT_NONE; ++ } ++ } ++ } else { ++ if (radeon_output->DACType == DAC_PRIMARY) { ++ if (radeon_output->load_detection) ++ found = radeon_detect_primary_dac(pScrn, TRUE); ++ } else if (radeon_output->DACType == DAC_TVDAC) { ++ if (radeon_output->load_detection) { ++ if (info->ChipFamily == CHIP_FAMILY_R200) ++ found = radeon_detect_ext_dac(pScrn); ++ else ++ found = radeon_detect_tv_dac(pScrn, TRUE); ++ } else ++ found = MT_NONE; ++ } ++ } ++ ++ return found; ++} ++ + /* Primary Head (DVI or Laptop Int. panel)*/ + /* A ddc capable display connected on DVI port */ + /* Secondary Head (mostly VGA, can be DVI on some OEM boards)*/ +@@ -633,38 +699,32 @@ void RADEONConnectorFindMonitor(ScrnInfoPtr pScrn, xf86OutputPtr output) + RADEONOutputPrivatePtr radeon_output = output->driver_private; + + if (radeon_output->MonType == MT_UNKNOWN) { +- if (radeon_output->type == OUTPUT_STV || radeon_output->type == OUTPUT_CTV) { +- if (xf86ReturnOptValBool(info->Options, OPTION_FORCE_TVOUT, FALSE)) { +- if (radeon_output->type == OUTPUT_STV) +- radeon_output->MonType = MT_STV; +- else +- radeon_output->MonType = MT_CTV; +- } else { +- if (info->InternalTVOut) { +- if (radeon_output->load_detection) +- radeon_output->MonType = radeon_detect_tv(pScrn); +- else ++ if (IS_AVIVO_VARIANT) { ++ radeon_output->MonType = avivo_display_ddc_connected(pScrn, output); ++ if (!radeon_output->MonType) { ++ if (radeon_output->type == OUTPUT_LVDS) ++ radeon_output->MonType = MT_LCD; ++ else if (OUTPUT_IS_TV) { ++ if (xf86ReturnOptValBool(info->Options, OPTION_FORCE_TVOUT, FALSE)) { ++ if (radeon_output->type == OUTPUT_STV) ++ radeon_output->MonType = MT_STV; ++ else ++ radeon_output->MonType = MT_CTV; ++ } else + radeon_output->MonType = MT_NONE; +- } ++ } else ++ radeon_output->MonType = atombios_dac_detect(pScrn, output); + } + } else { + radeon_output->MonType = RADEONDisplayDDCConnected(pScrn, output); + if (!radeon_output->MonType) { +- if (radeon_output->type == OUTPUT_LVDS || radeon_output->type == OUTPUT_DVI) ++ if (radeon_output->type == OUTPUT_LVDS || OUTPUT_IS_DVI) + radeon_output->MonType = RADEONPortCheckNonDDC(pScrn, output); + if (!radeon_output->MonType) { +- if (radeon_output->DACType == DAC_PRIMARY) { +- if (radeon_output->load_detection) +- radeon_output->MonType = radeon_detect_primary_dac(pScrn, TRUE); +- } else if (radeon_output->DACType == DAC_TVDAC) { +- if (radeon_output->load_detection) { +- if (info->ChipFamily == CHIP_FAMILY_R200) +- radeon_output->MonType = radeon_detect_ext_dac(pScrn); +- else +- radeon_output->MonType = radeon_detect_tv_dac(pScrn, TRUE); +- } else +- radeon_output->MonType = MT_NONE; +- } ++ if (info->IsAtomBios) ++ radeon_output->MonType = atombios_dac_detect(pScrn, output); ++ else ++ radeon_output->MonType = legacy_dac_detect(pScrn, output); + } + } + } +@@ -676,10 +736,7 @@ void RADEONConnectorFindMonitor(ScrnInfoPtr pScrn, xf86OutputPtr output) + + if (output->MonInfo) { + xf86DrvMsg(pScrn->scrnIndex, X_INFO, "EDID data from the display on connector: %s ----------------------\n", +- info->IsAtomBios ? +- ConnectorTypeNameATOM[radeon_output->ConnectorType]: +- ConnectorTypeName[radeon_output->ConnectorType] +- ); ++ ConnectorTypeName[radeon_output->ConnectorType]); + xf86PrintEDID( output->MonInfo ); + } + } +@@ -752,7 +809,7 @@ static RADEONMonitorType RADEONPortCheckNonDDC(ScrnInfoPtr pScrn, xf86OutputPtr + }*/ + + xf86DrvMsg(pScrn->scrnIndex, X_INFO, +- "Detected Monitor Type: %d\n", MonType); ++ "Detected non-DDC Monitor Type: %d\n", MonType); + + return MonType; + +@@ -761,6 +818,14 @@ static RADEONMonitorType RADEONPortCheckNonDDC(ScrnInfoPtr pScrn, xf86OutputPtr + static void + radeon_dpms(xf86OutputPtr output, int mode) + { ++ ScrnInfoPtr pScrn = output->scrn; ++ RADEONInfoPtr info = RADEONPTR(pScrn); ++ ++ if (IS_AVIVO_VARIANT) { ++ atombios_output_dpms(output, mode); ++ return; ++ } ++ + switch(mode) { + case DPMSModeOn: + RADEONEnableDisplay(output, TRUE); +@@ -790,8 +855,7 @@ radeon_mode_valid(xf86OutputPtr output, DisplayModePtr pMode) + { + RADEONOutputPrivatePtr radeon_output = output->driver_private; + +- if (radeon_output->type == OUTPUT_STV || +- radeon_output->type == OUTPUT_CTV) { ++ if (OUTPUT_IS_TV) { + /* FIXME: Update when more modes are added */ + if (pMode->HDisplay == 800 && pMode->VDisplay == 600) + return MODE_OK; +@@ -872,7 +936,7 @@ static void RADEONInitFPRegisters(xf86OutputPtr output, RADEONSavePtr save, + RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); + RADEONOutputPrivatePtr radeon_output = output->driver_private; + int i; +- CARD32 tmp = info->SavedReg.tmds_pll_cntl & 0xfffff; ++ CARD32 tmp = info->SavedReg->tmds_pll_cntl & 0xfffff; + + for (i=0; i<4; i++) { + if (radeon_output->tmds_pll[i].freq == 0) break; +@@ -886,12 +950,12 @@ static void RADEONInitFPRegisters(xf86OutputPtr output, RADEONSavePtr save, + if (tmp & 0xfff00000) + save->tmds_pll_cntl = tmp; + else { +- save->tmds_pll_cntl = info->SavedReg.tmds_pll_cntl & 0xfff00000; ++ save->tmds_pll_cntl = info->SavedReg->tmds_pll_cntl & 0xfff00000; + save->tmds_pll_cntl |= tmp; + } + } else save->tmds_pll_cntl = tmp; + +- save->tmds_transmitter_cntl = info->SavedReg.tmds_transmitter_cntl & ++ save->tmds_transmitter_cntl = info->SavedReg->tmds_transmitter_cntl & + ~(RADEON_TMDS_TRANSMITTER_PLLRST); + + if (IS_R300_VARIANT || (info->ChipFamily == CHIP_FAMILY_R200) || !pRADEONEnt->HasCRTC2) +@@ -899,7 +963,7 @@ static void RADEONInitFPRegisters(xf86OutputPtr output, RADEONSavePtr save, + else /* weird, RV chips got this bit reversed? */ + save->tmds_transmitter_cntl |= (RADEON_TMDS_TRANSMITTER_PLLEN); + +- save->fp_gen_cntl = info->SavedReg.fp_gen_cntl | ++ save->fp_gen_cntl = info->SavedReg->fp_gen_cntl | + (RADEON_FP_CRTC_DONT_SHADOW_VPAR | + RADEON_FP_CRTC_DONT_SHADOW_HEND ); + +@@ -938,10 +1002,10 @@ static void RADEONInitFP2Registers(xf86OutputPtr output, RADEONSavePtr save, + + + if (pScrn->rgbBits == 8) +- save->fp2_gen_cntl = info->SavedReg.fp2_gen_cntl | ++ save->fp2_gen_cntl = info->SavedReg->fp2_gen_cntl | + RADEON_FP2_PANEL_FORMAT; /* 24 bit format, */ + else +- save->fp2_gen_cntl = info->SavedReg.fp2_gen_cntl & ++ save->fp2_gen_cntl = info->SavedReg->fp2_gen_cntl & + ~RADEON_FP2_PANEL_FORMAT;/* 18 bit format, */ + + save->fp2_gen_cntl &= ~(RADEON_FP2_ON | +@@ -983,12 +1047,12 @@ static void RADEONInitLVDSRegisters(xf86OutputPtr output, RADEONSavePtr save, + ScrnInfoPtr pScrn = output->scrn; + RADEONInfoPtr info = RADEONPTR(pScrn); + +- save->lvds_pll_cntl = (info->SavedReg.lvds_pll_cntl | ++ save->lvds_pll_cntl = (info->SavedReg->lvds_pll_cntl | + RADEON_LVDS_PLL_EN); + + save->lvds_pll_cntl &= ~RADEON_LVDS_PLL_RESET; + +- save->lvds_gen_cntl = info->SavedReg.lvds_gen_cntl; ++ save->lvds_gen_cntl = info->SavedReg->lvds_gen_cntl; + save->lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS; + save->lvds_gen_cntl &= ~(RADEON_LVDS_ON | + RADEON_LVDS_BLON | +@@ -1023,9 +1087,9 @@ static void RADEONInitRMXRegisters(xf86OutputPtr output, RADEONSavePtr save, + int yres = mode->VDisplay; + float Hratio, Vratio; + +- save->fp_vert_stretch = info->SavedReg.fp_vert_stretch & ++ save->fp_vert_stretch = info->SavedReg->fp_vert_stretch & + RADEON_VERT_STRETCH_RESERVED; +- save->fp_horz_stretch = info->SavedReg.fp_horz_stretch & ++ save->fp_horz_stretch = info->SavedReg->fp_horz_stretch & + (RADEON_HORZ_FP_LOOP_STRETCH | + RADEON_HORZ_AUTO_RATIO_INC); + +@@ -1074,25 +1138,25 @@ static void RADEONInitDACRegisters(xf86OutputPtr output, RADEONSavePtr save, + + if (IsPrimary) { + if ((info->ChipFamily == CHIP_FAMILY_R200) || IS_R300_VARIANT) { +- save->disp_output_cntl = info->SavedReg.disp_output_cntl & ++ save->disp_output_cntl = info->SavedReg->disp_output_cntl & + ~RADEON_DISP_DAC_SOURCE_MASK; + } else { +- save->dac2_cntl = info->SavedReg.dac2_cntl & ~(RADEON_DAC2_DAC_CLK_SEL); ++ save->dac2_cntl = info->SavedReg->dac2_cntl & ~(RADEON_DAC2_DAC_CLK_SEL); + } + } else { + if ((info->ChipFamily == CHIP_FAMILY_R200) || IS_R300_VARIANT) { +- save->disp_output_cntl = info->SavedReg.disp_output_cntl & ++ save->disp_output_cntl = info->SavedReg->disp_output_cntl & + ~RADEON_DISP_DAC_SOURCE_MASK; + save->disp_output_cntl |= RADEON_DISP_DAC_SOURCE_CRTC2; + } else { +- save->dac2_cntl = info->SavedReg.dac2_cntl | RADEON_DAC2_DAC_CLK_SEL; ++ save->dac2_cntl = info->SavedReg->dac2_cntl | RADEON_DAC2_DAC_CLK_SEL; + } + } + save->dac_cntl = (RADEON_DAC_MASK_ALL + | RADEON_DAC_VGA_ADR_EN + | (info->dac6bits ? 0 : RADEON_DAC_8BIT_EN)); + +- save->dac_macro_cntl = info->SavedReg.dac_macro_cntl; ++ save->dac_macro_cntl = info->SavedReg->dac_macro_cntl; + } + + static void +@@ -1104,7 +1168,7 @@ RADEONInitTvDacCntl(xf86OutputPtr output, RADEONSavePtr save) + + if (info->ChipFamily == CHIP_FAMILY_R420 || + info->ChipFamily == CHIP_FAMILY_RV410) { +- save->tv_dac_cntl = info->SavedReg.tv_dac_cntl & ++ save->tv_dac_cntl = info->SavedReg->tv_dac_cntl & + ~(RADEON_TV_DAC_STD_MASK | + RADEON_TV_DAC_BGADJ_MASK | + R420_TV_DAC_DACADJ_MASK | +@@ -1113,7 +1177,7 @@ RADEONInitTvDacCntl(xf86OutputPtr output, RADEONSavePtr save) + R420_TV_DAC_GDACPD | + R420_TV_DAC_TVENABLE); + } else { +- save->tv_dac_cntl = info->SavedReg.tv_dac_cntl & ++ save->tv_dac_cntl = info->SavedReg->tv_dac_cntl & + ~(RADEON_TV_DAC_STD_MASK | + RADEON_TV_DAC_BGADJ_MASK | + RADEON_TV_DAC_DACADJ_MASK | +@@ -1139,34 +1203,34 @@ static void RADEONInitDAC2Registers(xf86OutputPtr output, RADEONSavePtr save, + RADEONInitTvDacCntl(output, save); + + if (IS_R300_VARIANT) +- save->gpiopad_a = info->SavedReg.gpiopad_a | 1; ++ save->gpiopad_a = info->SavedReg->gpiopad_a | 1; + +- save->dac2_cntl = info->SavedReg.dac2_cntl | RADEON_DAC2_DAC2_CLK_SEL; ++ save->dac2_cntl = info->SavedReg->dac2_cntl | RADEON_DAC2_DAC2_CLK_SEL; + + if (IsPrimary) { + if (IS_R300_VARIANT) { +- save->disp_output_cntl = info->SavedReg.disp_output_cntl & ++ save->disp_output_cntl = info->SavedReg->disp_output_cntl & + ~RADEON_DISP_TVDAC_SOURCE_MASK; + save->disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC; + } else if (info->ChipFamily == CHIP_FAMILY_R200) { +- save->fp2_gen_cntl = info->SavedReg.fp2_gen_cntl & ++ save->fp2_gen_cntl = info->SavedReg->fp2_gen_cntl & + ~(R200_FP2_SOURCE_SEL_MASK | + RADEON_FP2_DVO_RATE_SEL_SDR); + } else { +- save->disp_hw_debug = info->SavedReg.disp_hw_debug | RADEON_CRT2_DISP1_SEL; ++ save->disp_hw_debug = info->SavedReg->disp_hw_debug | RADEON_CRT2_DISP1_SEL; + } + } else { + if (IS_R300_VARIANT) { +- save->disp_output_cntl = info->SavedReg.disp_output_cntl & ++ save->disp_output_cntl = info->SavedReg->disp_output_cntl & + ~RADEON_DISP_TVDAC_SOURCE_MASK; + save->disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC2; + } else if (info->ChipFamily == CHIP_FAMILY_R200) { +- save->fp2_gen_cntl = info->SavedReg.fp2_gen_cntl & ++ save->fp2_gen_cntl = info->SavedReg->fp2_gen_cntl & + ~(R200_FP2_SOURCE_SEL_MASK | + RADEON_FP2_DVO_RATE_SEL_SDR); + save->fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2; + } else { +- save->disp_hw_debug = info->SavedReg.disp_hw_debug & ++ save->disp_hw_debug = info->SavedReg->disp_hw_debug & + ~RADEON_CRT2_DISP1_SEL; + } + } +@@ -1204,7 +1268,7 @@ RADEONInitOutputRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save, + } + + static void +-radeon_mode_set(xf86OutputPtr output, DisplayModePtr mode, ++legacy_mode_set(xf86OutputPtr output, DisplayModePtr mode, + DisplayModePtr adjusted_mode) + { + ScrnInfoPtr pScrn = output->scrn; +@@ -1213,43 +1277,60 @@ radeon_mode_set(xf86OutputPtr output, DisplayModePtr mode, + xf86CrtcPtr crtc = output->crtc; + RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; + +- RADEONInitOutputRegisters(pScrn, &info->ModeReg, adjusted_mode, output, radeon_crtc->crtc_id); ++ RADEONInitOutputRegisters(pScrn, info->ModeReg, adjusted_mode, output, radeon_crtc->crtc_id); + + if (radeon_crtc->crtc_id == 0) +- RADEONRestoreRMXRegisters(pScrn, &info->ModeReg); ++ RADEONRestoreRMXRegisters(pScrn, info->ModeReg); + + switch(radeon_output->MonType) { + case MT_LCD: + ErrorF("restore LVDS\n"); +- RADEONRestoreLVDSRegisters(pScrn, &info->ModeReg); ++ RADEONRestoreLVDSRegisters(pScrn, info->ModeReg); + break; + case MT_DFP: + if (radeon_output->TMDSType == TMDS_INT) { + ErrorF("restore FP\n"); +- RADEONRestoreFPRegisters(pScrn, &info->ModeReg); ++ RADEONRestoreFPRegisters(pScrn, info->ModeReg); + } else { + ErrorF("restore FP2\n"); +- RADEONRestoreDVOChip(pScrn, output); +- RADEONRestoreFP2Registers(pScrn, &info->ModeReg); ++ if (info->IsAtomBios) ++ atombios_external_tmds_setup(output, mode); ++ else ++ RADEONRestoreDVOChip(pScrn, output); ++ RADEONRestoreFP2Registers(pScrn, info->ModeReg); + } + break; + case MT_STV: + case MT_CTV: + ErrorF("restore tv\n"); +- RADEONRestoreDACRegisters(pScrn, &info->ModeReg); +- RADEONRestoreTVRegisters(pScrn, &info->ModeReg); ++ RADEONRestoreDACRegisters(pScrn, info->ModeReg); ++ RADEONRestoreTVRegisters(pScrn, info->ModeReg); + break; + default: + ErrorF("restore dac\n"); +- RADEONRestoreDACRegisters(pScrn, &info->ModeReg); ++ RADEONRestoreDACRegisters(pScrn, info->ModeReg); + } + + } + + static void ++radeon_mode_set(xf86OutputPtr output, DisplayModePtr mode, ++ DisplayModePtr adjusted_mode) ++{ ++ ScrnInfoPtr pScrn = output->scrn; ++ RADEONInfoPtr info = RADEONPTR(pScrn); ++ ++ if (IS_AVIVO_VARIANT) ++ atombios_output_mode_set(output, mode, adjusted_mode); ++ else ++ legacy_mode_set(output, mode, adjusted_mode); ++ ++} ++ ++static void + radeon_mode_commit(xf86OutputPtr output) + { +- RADEONEnableDisplay(output, TRUE); ++ radeon_dpms(output, DPMSModeOn); + } + + /* the following functions are based on the load detection code +@@ -1680,19 +1761,6 @@ radeon_detect(xf86OutputPtr output) + radeon_output->MonType = MT_UNKNOWN; + RADEONConnectorFindMonitor(pScrn, output); + +- /* force montype based on output property */ +- if (radeon_output->type == OUTPUT_DVI) { +- if (radeon_output->MonType == MT_NONE) +- connected = FALSE; +- if ((info->IsAtomBios && radeon_output->ConnectorType == CONNECTOR_DVI_I_ATOM) || +- (!info->IsAtomBios && radeon_output->ConnectorType == CONNECTOR_DVI_I)) { +- if (radeon_output->DVIType == DVI_ANALOG) +- radeon_output->MonType = MT_CRT; +- else if (radeon_output->DVIType == DVI_DIGITAL) +- radeon_output->MonType = MT_DFP; +- } +- } +- + /* set montype so users can force outputs on even if detection fails */ + if (radeon_output->MonType == MT_NONE) { + connected = FALSE; +@@ -1704,9 +1772,20 @@ radeon_detect(xf86OutputPtr output) + radeon_output->MonType = MT_STV; + else if (radeon_output->type == OUTPUT_CTV) + radeon_output->MonType = MT_CTV; +- else if ((info->IsAtomBios && radeon_output->ConnectorType == CONNECTOR_DVI_D_ATOM) || +- (!info->IsAtomBios && radeon_output->ConnectorType == CONNECTOR_DVI_D)) ++ else if (radeon_output->type == OUTPUT_CV) ++ radeon_output->MonType = MT_CV; ++ else if (radeon_output->type == OUTPUT_DVI_D) + radeon_output->MonType = MT_DFP; ++ else if (radeon_output->type == OUTPUT_HDMI) ++ radeon_output->MonType = MT_DFP; ++ else if (radeon_output->type == OUTPUT_DVI_A) ++ radeon_output->MonType = MT_CRT; ++ else if (radeon_output->type == OUTPUT_DVI_I) { ++ if (radeon_output->DVIType == DVI_ANALOG) ++ radeon_output->MonType = MT_CRT; ++ else if (radeon_output->DVIType == DVI_DIGITAL) ++ radeon_output->MonType = MT_DFP; ++ } + } + + if (radeon_output->MonType == MT_UNKNOWN) { +@@ -1728,13 +1807,13 @@ radeon_detect(xf86OutputPtr output) + /* default to unknown for flaky chips/connectors + * so we can get something on the screen + */ +- if ((radeon_output->type == OUTPUT_VGA || radeon_output->type == OUTPUT_DVI) && ++ if ((radeon_output->type == OUTPUT_VGA || radeon_output->type == OUTPUT_DVI_I) && + (radeon_output->DACType == DAC_TVDAC) && + (info->ChipFamily == CHIP_FAMILY_RS400)) { + radeon_output->MonType = MT_CRT; + return XF86OutputStatusUnknown; + } else if ((info->ChipFamily == CHIP_FAMILY_RS400) && +- radeon_output->type == OUTPUT_DVI) { ++ radeon_output->type == OUTPUT_DVI_D) { + radeon_output->MonType = MT_DFP; /* MT_LCD ??? */ + return XF86OutputStatusUnknown; + } +@@ -1819,7 +1898,7 @@ radeon_create_resources(xf86OutputPtr output) + "RRConfigureOutputProperty error, %d\n", err); + } + /* Set the current value of the backlight property */ +- //data = (info->SavedReg.lvds_gen_cntl & RADEON_LVDS_BL_MOD_LEVEL_MASK) >> RADEON_LVDS_BL_MOD_LEVEL_SHIFT; ++ //data = (info->SavedReg->lvds_gen_cntl & RADEON_LVDS_BL_MOD_LEVEL_MASK) >> RADEON_LVDS_BL_MOD_LEVEL_SHIFT; + data = RADEON_MAX_BACKLIGHT_LEVEL; + err = RRChangeOutputProperty(output->randr_output, backlight_atom, + XA_INTEGER, 32, PropModeReplace, 1, &data, +@@ -1862,8 +1941,7 @@ radeon_create_resources(xf86OutputPtr output) + } + } + +- if (radeon_output->type == OUTPUT_DVI && +- radeon_output->TMDSType == TMDS_INT) { ++ if (OUTPUT_IS_DVI && radeon_output->TMDSType == TMDS_INT) { + tmds_pll_atom = MAKE_ATOM("tmds_pll"); + + err = RRConfigureOutputProperty(output->randr_output, tmds_pll_atom, +@@ -1894,8 +1972,7 @@ radeon_create_resources(xf86OutputPtr output) + + /* RMX control - fullscreen, centered, keep ratio, off */ + /* actually more of a crtc property as only crtc1 has rmx */ +- if (radeon_output->type == OUTPUT_LVDS || +- radeon_output->type == OUTPUT_DVI) { ++ if (radeon_output->type == OUTPUT_LVDS || OUTPUT_IS_DVI) { + rmx_atom = MAKE_ATOM("scaler"); + + err = RRConfigureOutputProperty(output->randr_output, rmx_atom, +@@ -1919,31 +1996,27 @@ radeon_create_resources(xf86OutputPtr output) + } + + /* force auto/analog/digital for DVI-I ports */ +- if (radeon_output->type == OUTPUT_DVI) { +- if ((info->IsAtomBios && radeon_output->ConnectorType == CONNECTOR_DVI_I_ATOM) || +- (!info->IsAtomBios && radeon_output->ConnectorType == CONNECTOR_DVI_I)) { +- monitor_type_atom = MAKE_ATOM("dvi_monitor_type"); +- +- err = RRConfigureOutputProperty(output->randr_output, monitor_type_atom, +- FALSE, FALSE, FALSE, 0, NULL); +- if (err != 0) { +- xf86DrvMsg(pScrn->scrnIndex, X_ERROR, +- "RRConfigureOutputProperty error, %d\n", err); +- } +- /* Set the current value of the backlight property */ +- s = "auto"; +- err = RRChangeOutputProperty(output->randr_output, monitor_type_atom, +- XA_STRING, 8, PropModeReplace, strlen(s), (pointer)s, +- FALSE, FALSE); +- if (err != 0) { +- xf86DrvMsg(pScrn->scrnIndex, X_ERROR, +- "RRChangeOutputProperty error, %d\n", err); +- } ++ if (radeon_output->type == OUTPUT_DVI_I) { ++ monitor_type_atom = MAKE_ATOM("dvi_monitor_type"); ++ ++ err = RRConfigureOutputProperty(output->randr_output, monitor_type_atom, ++ FALSE, FALSE, FALSE, 0, NULL); ++ if (err != 0) { ++ xf86DrvMsg(pScrn->scrnIndex, X_ERROR, ++ "RRConfigureOutputProperty error, %d\n", err); ++ } ++ /* Set the current value of the backlight property */ ++ s = "auto"; ++ err = RRChangeOutputProperty(output->randr_output, monitor_type_atom, ++ XA_STRING, 8, PropModeReplace, strlen(s), (pointer)s, ++ FALSE, FALSE); ++ if (err != 0) { ++ xf86DrvMsg(pScrn->scrnIndex, X_ERROR, ++ "RRChangeOutputProperty error, %d\n", err); + } + } + +- if (radeon_output->type == OUTPUT_STV || +- radeon_output->type == OUTPUT_CTV) { ++ if (OUTPUT_IS_TV) { + tv_hsize_atom = MAKE_ATOM("tv_horizontal_size"); + + range[0] = -MAX_H_SIZE; +@@ -1962,10 +2035,7 @@ radeon_create_resources(xf86OutputPtr output) + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, + "RRChangeOutputProperty error, %d\n", err); + } +- } + +- if (radeon_output->type == OUTPUT_STV || +- radeon_output->type == OUTPUT_CTV) { + tv_hpos_atom = MAKE_ATOM("tv_horizontal_position"); + + range[0] = -MAX_H_POSITION; +@@ -1984,10 +2054,7 @@ radeon_create_resources(xf86OutputPtr output) + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, + "RRChangeOutputProperty error, %d\n", err); + } +- } + +- if (radeon_output->type == OUTPUT_STV || +- radeon_output->type == OUTPUT_CTV) { + tv_vpos_atom = MAKE_ATOM("tv_vertical_position"); + + range[0] = -MAX_V_POSITION; +@@ -2006,10 +2073,7 @@ radeon_create_resources(xf86OutputPtr output) + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, + "RRChangeOutputProperty error, %d\n", err); + } +- } + +- if (radeon_output->type == OUTPUT_STV || +- radeon_output->type == OUTPUT_CTV) { + tv_std_atom = MAKE_ATOM("tv_standard"); + + err = RRConfigureOutputProperty(output->randr_output, tv_std_atom, +@@ -2225,6 +2289,12 @@ radeon_set_property(xf86OutputPtr output, Atom property, + } else if (value->size == strlen("scart-pal") && !strncmp("scart-pal", s, strlen("scart-pal"))) { + radeon_output->tvStd = TV_STD_SCART_PAL; + return TRUE; ++ } else if (value->size == strlen("pal-cn") && !strncmp("pal-cn", s, strlen("pal-cn"))) { ++ radeon_output->tvStd = TV_STD_PAL_CN; ++ return TRUE; ++ } else if (value->size == strlen("secam") && !strncmp("secam", s, strlen("secam"))) { ++ radeon_output->tvStd = TV_STD_SECAM; ++ return TRUE; + } + return FALSE; + } +@@ -2250,52 +2320,136 @@ static const xf86OutputFuncsRec radeon_output_funcs = { + + void RADEONSetOutputType(ScrnInfoPtr pScrn, RADEONOutputPrivatePtr radeon_output) + { +- RADEONInfoPtr info = RADEONPTR (pScrn); + RADEONOutputType output; + +- if (info->IsAtomBios) { +- switch(radeon_output->ConnectorType) { +- case CONNECTOR_VGA_ATOM: +- output = OUTPUT_VGA; break; +- case CONNECTOR_DVI_I_ATOM: +- case CONNECTOR_DVI_D_ATOM: +- case CONNECTOR_DVI_A_ATOM: +- output = OUTPUT_DVI; break; +- case CONNECTOR_STV_ATOM: +- output = OUTPUT_STV; break; +- case CONNECTOR_CTV_ATOM: +- output = OUTPUT_CTV; break; +- case CONNECTOR_LVDS_ATOM: +- case CONNECTOR_DIGITAL_ATOM: +- output = OUTPUT_LVDS; break; +- case CONNECTOR_NONE_ATOM: +- case CONNECTOR_UNSUPPORTED_ATOM: +- default: +- output = OUTPUT_NONE; break; +- } +- } +- else { +- switch(radeon_output->ConnectorType) { +- case CONNECTOR_PROPRIETARY: +- output = OUTPUT_LVDS; break; +- case CONNECTOR_CRT: +- output = OUTPUT_VGA; break; +- case CONNECTOR_DVI_I: +- case CONNECTOR_DVI_D: +- output = OUTPUT_DVI; break; +- case CONNECTOR_CTV: +- output = OUTPUT_CTV; break; +- case CONNECTOR_STV: +- output = OUTPUT_STV; break; +- case CONNECTOR_NONE: +- case CONNECTOR_UNSUPPORTED: +- default: +- output = OUTPUT_NONE; break; +- } ++ switch(radeon_output->ConnectorType) { ++ case CONNECTOR_VGA: ++ output = OUTPUT_VGA; break; ++ case CONNECTOR_DVI_I: ++ output = OUTPUT_DVI_I; break; ++ case CONNECTOR_DVI_D: ++ output = OUTPUT_DVI_D; break; ++ case CONNECTOR_DVI_A: ++ output = OUTPUT_DVI_A; break; ++ case CONNECTOR_STV: ++ output = OUTPUT_STV; break; ++ case CONNECTOR_CTV: ++ output = OUTPUT_CTV; break; ++ case CONNECTOR_LVDS: ++ output = OUTPUT_LVDS; break; ++ case CONNECTOR_HDMI_TYPE_A: ++ case CONNECTOR_HDMI_TYPE_B: ++ output = OUTPUT_HDMI; break; ++ case CONNECTOR_DIGITAL: ++ case CONNECTOR_NONE: ++ case CONNECTOR_UNSUPPORTED: ++ default: ++ output = OUTPUT_NONE; break; + } + radeon_output->type = output; + } + ++static ++Bool AVIVOI2CReset(ScrnInfoPtr pScrn) ++{ ++ RADEONInfoPtr info = RADEONPTR(pScrn); ++ unsigned char *RADEONMMIO = info->MMIO; ++ ++ OUTREG(AVIVO_I2C_STOP, 1); ++ INREG(AVIVO_I2C_STOP); ++ OUTREG(AVIVO_I2C_STOP, 0x0); ++ return TRUE; ++} ++ ++static ++Bool AVIVOI2CDoLock(ScrnInfoPtr pScrn, int lock_state, int gpio_reg) ++{ ++ RADEONInfoPtr info = RADEONPTR(pScrn); ++ unsigned char *RADEONMMIO = info->MMIO; ++ CARD32 temp; ++ ++ temp = INREG(gpio_reg); ++ if (gpio_reg == AVIVO_GPIO_0) { ++ if (lock_state == AVIVO_I2C_ENABLE) ++ temp |= (1 << 19) | (1 << 18); ++ else ++ temp &= ~((1 << 19) | (1 << 18)); ++ } else { ++ if (lock_state == AVIVO_I2C_ENABLE) ++ temp |= (1 << 0) | (1 << 8); ++ else ++ temp &= ~((1 << 0) | (1 << 8)); ++ } ++ OUTREG(gpio_reg, temp); ++ temp = INREG(gpio_reg); ++ ++ return TRUE; ++} ++ ++void ++avivo_i2c_gpio_get_bits(I2CBusPtr b, int *Clock, int *data) ++{ ++ ScrnInfoPtr screen_info = xf86Screens[b->scrnIndex]; ++ RADEONInfoPtr info = RADEONPTR(screen_info); ++ unsigned char *RADEONMMIO = info->MMIO; ++ unsigned long val; ++ ++ /* Get the result */ ++ if (b->DriverPrivate.uval == AVIVO_GPIO_0) { ++ val = INREG(b->DriverPrivate.uval + 0xc); ++ *Clock = (val & (1<<19)) != 0; ++ *data = (val & (1<<18)) != 0; ++ } else { ++ val = INREG(b->DriverPrivate.uval + 0xc); ++ *Clock = (val & (1<<0)) != 0; ++ *data = (val & (1<<8)) != 0; ++ } ++} ++ ++static void ++avivo_i2c_gpio_put_bits(I2CBusPtr b, int Clock, int data) ++{ ++ ScrnInfoPtr screen_info = xf86Screens[b->scrnIndex]; ++ RADEONInfoPtr info = RADEONPTR(screen_info); ++ unsigned char *RADEONMMIO = info->MMIO; ++ unsigned long val; ++ ++ val = 0; ++ if (b->DriverPrivate.uval == AVIVO_GPIO_0) { ++ val |= (Clock ? 0:(1<<19)); ++ val |= (data ? 0:(1<<18)); ++ } else { ++ val |= (Clock ? 0:(1<<0)); ++ val |= (data ? 0:(1<<8)); ++ ++ } ++ ++ OUTREG(b->DriverPrivate.uval + 0x8, val); ++ /* read back to improve reliability on some cards. */ ++ val = INREG(b->DriverPrivate.uval + 0x8); ++} ++ ++static Bool ++avivo_i2c_init(ScrnInfoPtr pScrn, I2CBusPtr *bus_ptr, int i2c_reg, char *name) ++{ ++ I2CBusPtr pI2CBus; ++ ++ pI2CBus = xf86CreateI2CBusRec(); ++ if (!pI2CBus) return FALSE; ++ ++ pI2CBus->BusName = name; ++ pI2CBus->scrnIndex = pScrn->scrnIndex; ++ pI2CBus->I2CPutBits = avivo_i2c_gpio_put_bits; ++ pI2CBus->I2CGetBits = avivo_i2c_gpio_get_bits; ++ pI2CBus->AcknTimeout = 5; ++ pI2CBus->DriverPrivate.uval = i2c_reg; ++ ++ if (!xf86I2CBusInit(pI2CBus)) return FALSE; ++ ++ *bus_ptr = pI2CBus; ++ return TRUE; ++} ++ + static void RADEONI2CGetBits(I2CBusPtr b, int *Clock, int *data) + { + ScrnInfoPtr pScrn = xf86Screens[b->scrnIndex]; +@@ -2649,18 +2803,20 @@ RADEONGetTVInfo(xf86OutputPtr output) + void RADEONInitConnector(xf86OutputPtr output) + { + ScrnInfoPtr pScrn = output->scrn; ++ RADEONInfoPtr info = RADEONPTR(pScrn); + RADEONOutputPrivatePtr radeon_output = output->driver_private; +- int DDCReg = 0; +- char* name = (char*) DDCTypeName[radeon_output->DDCType]; +- +- switch(radeon_output->DDCType) { +- case DDC_MONID: DDCReg = RADEON_GPIO_MONID; break; +- case DDC_DVI : DDCReg = RADEON_GPIO_DVI_DDC; break; +- case DDC_VGA : DDCReg = RADEON_GPIO_VGA_DDC; break; +- case DDC_CRT2 : DDCReg = RADEON_GPIO_CRT2_DDC; break; +- case DDC_LCD : DDCReg = RADEON_LCD_GPIO_MASK; break; +- case DDC_GPIO : DDCReg = RADEON_MDGPIO_EN_REG; break; +- default: break; ++ char stmp[16]; ++ char *name; ++ sprintf(stmp, "DDC_0x%x", radeon_output->ddc_line); ++ name = xnfalloc(strlen(stmp) + 1); ++ strcpy(name, stmp); ++ ++ if (IS_AVIVO_VARIANT) { ++ if (radeon_output->ddc_line) ++ avivo_i2c_init(pScrn, &radeon_output->pI2CBus, radeon_output->ddc_line, name); ++ } else { ++ if (radeon_output->ddc_line) ++ RADEONI2CInit(pScrn, &radeon_output->pI2CBus, radeon_output->ddc_line, name); + } + + if (radeon_output->DACType == DAC_PRIMARY) +@@ -2671,17 +2827,12 @@ void RADEONInitConnector(xf86OutputPtr output) + else + radeon_output->load_detection = 0; /* shared tvdac between vga/dvi/tv */ + +- if (DDCReg) { +- radeon_output->DDCReg = DDCReg; +- RADEONI2CInit(pScrn, &radeon_output->pI2CBus, DDCReg, name); +- } +- + if (radeon_output->type == OUTPUT_LVDS) { + radeon_output->rmx_type = RMX_FULL; + RADEONGetLVDSInfo(output); + } + +- if (radeon_output->type == OUTPUT_DVI) { ++ if (OUTPUT_IS_DVI) { + I2CBusPtr pDVOBus; + radeon_output->rmx_type = RMX_OFF; + if (radeon_output->TMDSType == TMDS_EXT) { +@@ -2705,8 +2856,7 @@ void RADEONInitConnector(xf86OutputPtr output) + RADEONGetTMDSInfo(output); + } + +- if (radeon_output->type == OUTPUT_STV || +- radeon_output->type == OUTPUT_CTV) { ++ if (OUTPUT_IS_TV) { + RADEONGetTVInfo(output); + RADEONGetTVDacAdjInfo(output); + } +@@ -2726,32 +2876,32 @@ static Bool RADEONSetupAppleConnectors(ScrnInfoPtr pScrn) + + switch (info->MacModel) { + case RADEON_MAC_IBOOK: +- info->BiosConnector[0].DDCType = DDC_DVI; ++ info->BiosConnector[0].ddc_line = RADEON_GPIO_DVI_DDC; + info->BiosConnector[0].DACType = DAC_NONE; + info->BiosConnector[0].TMDSType = TMDS_NONE; +- info->BiosConnector[0].ConnectorType = CONNECTOR_PROPRIETARY; ++ info->BiosConnector[0].ConnectorType = CONNECTOR_LVDS; + info->BiosConnector[0].valid = TRUE; + +- info->BiosConnector[1].DDCType = DDC_VGA; ++ info->BiosConnector[1].ddc_line = RADEON_GPIO_VGA_DDC; + info->BiosConnector[1].DACType = DAC_TVDAC; + info->BiosConnector[1].TMDSType = TMDS_NONE; +- info->BiosConnector[1].ConnectorType = CONNECTOR_CRT; ++ info->BiosConnector[1].ConnectorType = CONNECTOR_VGA; + info->BiosConnector[1].valid = TRUE; + + info->BiosConnector[2].ConnectorType = CONNECTOR_STV; + info->BiosConnector[2].DACType = DAC_TVDAC; + info->BiosConnector[2].TMDSType = TMDS_NONE; +- info->BiosConnector[2].DDCType = DDC_NONE_DETECTED; ++ info->BiosConnector[2].ddc_line = 0; + info->BiosConnector[2].valid = TRUE; + return TRUE; + case RADEON_MAC_POWERBOOK_EXTERNAL: +- info->BiosConnector[0].DDCType = DDC_DVI; ++ info->BiosConnector[0].ddc_line = RADEON_GPIO_DVI_DDC; + info->BiosConnector[0].DACType = DAC_NONE; + info->BiosConnector[0].TMDSType = TMDS_NONE; +- info->BiosConnector[0].ConnectorType = CONNECTOR_PROPRIETARY; ++ info->BiosConnector[0].ConnectorType = CONNECTOR_LVDS; + info->BiosConnector[0].valid = TRUE; + +- info->BiosConnector[1].DDCType = DDC_VGA; ++ info->BiosConnector[1].ddc_line = RADEON_GPIO_VGA_DDC; + info->BiosConnector[1].DACType = DAC_PRIMARY; + info->BiosConnector[1].TMDSType = TMDS_EXT; + info->BiosConnector[1].ConnectorType = CONNECTOR_DVI_I; +@@ -2760,17 +2910,18 @@ static Bool RADEONSetupAppleConnectors(ScrnInfoPtr pScrn) + info->BiosConnector[2].ConnectorType = CONNECTOR_STV; + info->BiosConnector[2].DACType = DAC_TVDAC; + info->BiosConnector[2].TMDSType = TMDS_NONE; +- info->BiosConnector[2].DDCType = DDC_NONE_DETECTED; ++ info->BiosConnector[2].ddc_line = 0; + info->BiosConnector[2].valid = TRUE; + return TRUE; ++ + case RADEON_MAC_POWERBOOK_INTERNAL: +- info->BiosConnector[0].DDCType = DDC_DVI; ++ info->BiosConnector[0].ddc_line = RADEON_GPIO_DVI_DDC; + info->BiosConnector[0].DACType = DAC_NONE; + info->BiosConnector[0].TMDSType = TMDS_NONE; +- info->BiosConnector[0].ConnectorType = CONNECTOR_PROPRIETARY; ++ info->BiosConnector[0].ConnectorType = CONNECTOR_LVDS; + info->BiosConnector[0].valid = TRUE; + +- info->BiosConnector[1].DDCType = DDC_VGA; ++ info->BiosConnector[1].ddc_line = RADEON_GPIO_VGA_DDC; + info->BiosConnector[1].DACType = DAC_PRIMARY; + info->BiosConnector[1].TMDSType = TMDS_INT; + info->BiosConnector[1].ConnectorType = CONNECTOR_DVI_I; +@@ -2779,17 +2930,17 @@ static Bool RADEONSetupAppleConnectors(ScrnInfoPtr pScrn) + info->BiosConnector[2].ConnectorType = CONNECTOR_STV; + info->BiosConnector[2].DACType = DAC_TVDAC; + info->BiosConnector[2].TMDSType = TMDS_NONE; +- info->BiosConnector[2].DDCType = DDC_NONE_DETECTED; ++ info->BiosConnector[2].ddc_line = 0; + info->BiosConnector[2].valid = TRUE; + return TRUE; + case RADEON_MAC_POWERBOOK_VGA: +- info->BiosConnector[0].DDCType = DDC_DVI; ++ info->BiosConnector[0].ddc_line = RADEON_GPIO_DVI_DDC; + info->BiosConnector[0].DACType = DAC_NONE; + info->BiosConnector[0].TMDSType = TMDS_NONE; +- info->BiosConnector[0].ConnectorType = CONNECTOR_CRT; ++ info->BiosConnector[0].ConnectorType = CONNECTOR_VGA; + info->BiosConnector[0].valid = TRUE; + +- info->BiosConnector[1].DDCType = DDC_VGA; ++ info->BiosConnector[1].ddc_line = RADEON_GPIO_VGA_DDC; + info->BiosConnector[1].DACType = DAC_PRIMARY; + info->BiosConnector[1].TMDSType = TMDS_INT; + info->BiosConnector[1].ConnectorType = CONNECTOR_DVI_I; +@@ -2798,11 +2949,11 @@ static Bool RADEONSetupAppleConnectors(ScrnInfoPtr pScrn) + info->BiosConnector[2].ConnectorType = CONNECTOR_STV; + info->BiosConnector[2].DACType = DAC_TVDAC; + info->BiosConnector[2].TMDSType = TMDS_NONE; +- info->BiosConnector[2].DDCType = DDC_NONE_DETECTED; ++ info->BiosConnector[2].ddc_line = 0; + info->BiosConnector[2].valid = TRUE; + return TRUE; + case RADEON_MAC_MINI_EXTERNAL: +- info->BiosConnector[0].DDCType = DDC_CRT2; ++ info->BiosConnector[0].ddc_line = RADEON_GPIO_CRT2_DDC; + info->BiosConnector[0].DACType = DAC_TVDAC; + info->BiosConnector[0].TMDSType = TMDS_EXT; + info->BiosConnector[0].ConnectorType = CONNECTOR_DVI_I; +@@ -2811,11 +2962,11 @@ static Bool RADEONSetupAppleConnectors(ScrnInfoPtr pScrn) + info->BiosConnector[1].ConnectorType = CONNECTOR_STV; + info->BiosConnector[1].DACType = DAC_TVDAC; + info->BiosConnector[1].TMDSType = TMDS_NONE; +- info->BiosConnector[1].DDCType = DDC_NONE_DETECTED; ++ info->BiosConnector[1].ddc_line = 0; + info->BiosConnector[1].valid = TRUE; + return TRUE; + case RADEON_MAC_MINI_INTERNAL: +- info->BiosConnector[0].DDCType = DDC_CRT2; ++ info->BiosConnector[0].ddc_line = RADEON_GPIO_CRT2_DDC; + info->BiosConnector[0].DACType = DAC_TVDAC; + info->BiosConnector[0].TMDSType = TMDS_INT; + info->BiosConnector[0].ConnectorType = CONNECTOR_DVI_I; +@@ -2824,26 +2975,26 @@ static Bool RADEONSetupAppleConnectors(ScrnInfoPtr pScrn) + info->BiosConnector[1].ConnectorType = CONNECTOR_STV; + info->BiosConnector[1].DACType = DAC_TVDAC; + info->BiosConnector[1].TMDSType = TMDS_NONE; +- info->BiosConnector[1].DDCType = DDC_NONE_DETECTED; ++ info->BiosConnector[1].ddc_line = 0; + info->BiosConnector[1].valid = TRUE; + return TRUE; + case RADEON_MAC_IMAC_G5_ISIGHT: +- info->BiosConnector[0].DDCType = DDC_MONID; ++ info->BiosConnector[0].ddc_line = RADEON_GPIO_MONID; + info->BiosConnector[0].DACType = DAC_NONE; + info->BiosConnector[0].TMDSType = TMDS_INT; + info->BiosConnector[0].ConnectorType = CONNECTOR_DVI_D; + info->BiosConnector[0].valid = TRUE; + +- info->BiosConnector[1].DDCType = DDC_DVI; ++ info->BiosConnector[1].ddc_line = RADEON_GPIO_DVI_DDC; + info->BiosConnector[1].DACType = DAC_TVDAC; + info->BiosConnector[1].TMDSType = TMDS_NONE; +- info->BiosConnector[1].ConnectorType = CONNECTOR_CRT; ++ info->BiosConnector[1].ConnectorType = CONNECTOR_VGA; + info->BiosConnector[1].valid = TRUE; + + info->BiosConnector[2].ConnectorType = CONNECTOR_STV; + info->BiosConnector[2].DACType = DAC_TVDAC; + info->BiosConnector[2].TMDSType = TMDS_NONE; +- info->BiosConnector[2].DDCType = DDC_NONE_DETECTED; ++ info->BiosConnector[2].ddc_line = 0; + info->BiosConnector[2].valid = TRUE; + return TRUE; + default: +@@ -2860,108 +3011,146 @@ static void RADEONSetupGenericConnectors(ScrnInfoPtr pScrn) + RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); + + if (!pRADEONEnt->HasCRTC2) { +- info->BiosConnector[0].DDCType = DDC_VGA; ++ info->BiosConnector[0].ddc_line = RADEON_GPIO_VGA_DDC; + info->BiosConnector[0].DACType = DAC_PRIMARY; + info->BiosConnector[0].TMDSType = TMDS_NONE; +- info->BiosConnector[0].ConnectorType = CONNECTOR_CRT; ++ info->BiosConnector[0].ConnectorType = CONNECTOR_VGA; + info->BiosConnector[0].valid = TRUE; + return; + } + +- if (info->IsMobility) { +- /* Below is the most common setting, but may not be true */ +- if (info->IsIGP) { +- info->BiosConnector[0].DDCType = DDC_LCD; +- info->BiosConnector[0].DACType = DAC_UNKNOWN; +- info->BiosConnector[0].TMDSType = TMDS_UNKNOWN; +- info->BiosConnector[0].ConnectorType = CONNECTOR_PROPRIETARY; ++ if (IS_AVIVO_VARIANT) { ++ if (info->IsMobility) { ++ info->BiosConnector[0].ddc_line = 0x7e60; ++ info->BiosConnector[0].DACType = DAC_NONE; ++ info->BiosConnector[0].TMDSType = TMDS_NONE; ++ info->BiosConnector[0].ConnectorType = CONNECTOR_LVDS; ++ info->BiosConnector[0].devices = ATOM_DEVICE_LCD1_SUPPORT; + info->BiosConnector[0].valid = TRUE; + +- /* IGP only has TVDAC */ +- if (info->ChipFamily == CHIP_FAMILY_RS400) +- info->BiosConnector[1].DDCType = DDC_CRT2; +- else +- info->BiosConnector[1].DDCType = DDC_VGA; +- info->BiosConnector[1].DACType = DAC_TVDAC; +- info->BiosConnector[1].TMDSType = TMDS_UNKNOWN; +- info->BiosConnector[1].ConnectorType = CONNECTOR_CRT; +- info->BiosConnector[1].valid = TRUE; +- } else { +-#if defined(__powerpc__) +- info->BiosConnector[0].DDCType = DDC_DVI; +-#else +- info->BiosConnector[0].DDCType = DDC_LCD; +-#endif +- info->BiosConnector[0].DACType = DAC_UNKNOWN; +- info->BiosConnector[0].TMDSType = TMDS_UNKNOWN; +- info->BiosConnector[0].ConnectorType = CONNECTOR_PROPRIETARY; +- info->BiosConnector[0].valid = TRUE; +- +- info->BiosConnector[1].DDCType = DDC_VGA; ++ info->BiosConnector[1].ddc_line = 0x7e40; + info->BiosConnector[1].DACType = DAC_PRIMARY; +- info->BiosConnector[1].TMDSType = TMDS_UNKNOWN; +- info->BiosConnector[1].ConnectorType = CONNECTOR_CRT; +- info->BiosConnector[1].valid = TRUE; +- } +- } else { +- /* Below is the most common setting, but may not be true */ +- if (info->IsIGP) { +- if (info->ChipFamily == CHIP_FAMILY_RS400) +- info->BiosConnector[0].DDCType = DDC_CRT2; +- else +- info->BiosConnector[0].DDCType = DDC_VGA; +- info->BiosConnector[0].DACType = DAC_TVDAC; +- info->BiosConnector[0].TMDSType = TMDS_UNKNOWN; +- info->BiosConnector[0].ConnectorType = CONNECTOR_CRT; +- info->BiosConnector[0].valid = TRUE; +- +- /* not sure what a good default DDCType for DVI on +- * IGP desktop chips is +- */ +- info->BiosConnector[1].DDCType = DDC_MONID; /* DDC_DVI? */ +- info->BiosConnector[1].DACType = DAC_UNKNOWN; +- info->BiosConnector[1].TMDSType = TMDS_EXT; +- info->BiosConnector[1].ConnectorType = CONNECTOR_DVI_D; ++ info->BiosConnector[1].TMDSType = TMDS_NONE; ++ info->BiosConnector[1].ConnectorType = CONNECTOR_VGA; ++ info->BiosConnector[1].devices = ATOM_DEVICE_CRT1_SUPPORT; + info->BiosConnector[1].valid = TRUE; + } else { +- info->BiosConnector[0].DDCType = DDC_DVI; ++ info->BiosConnector[0].ddc_line = 0x7e50; + info->BiosConnector[0].DACType = DAC_TVDAC; + info->BiosConnector[0].TMDSType = TMDS_INT; + info->BiosConnector[0].ConnectorType = CONNECTOR_DVI_I; ++ info->BiosConnector[0].devices = ATOM_DEVICE_CRT2_SUPPORT | ATOM_DEVICE_DFP1_SUPPORT; + info->BiosConnector[0].valid = TRUE; + +-#if defined(__powerpc__) +- info->BiosConnector[1].DDCType = DDC_VGA; +- info->BiosConnector[1].DACType = DAC_PRIMARY; +- info->BiosConnector[1].TMDSType = TMDS_EXT; +- info->BiosConnector[1].ConnectorType = CONNECTOR_DVI_I; +- info->BiosConnector[1].valid = TRUE; +-#else +- info->BiosConnector[1].DDCType = DDC_VGA; ++ info->BiosConnector[1].ddc_line = 0x7e40; + info->BiosConnector[1].DACType = DAC_PRIMARY; + info->BiosConnector[1].TMDSType = TMDS_NONE; +- info->BiosConnector[1].ConnectorType = CONNECTOR_CRT; ++ info->BiosConnector[1].ConnectorType = CONNECTOR_VGA; ++ info->BiosConnector[1].devices = ATOM_DEVICE_CRT1_SUPPORT; + info->BiosConnector[1].valid = TRUE; +-#endif + } +- } + +- if (info->InternalTVOut) { + info->BiosConnector[2].ConnectorType = CONNECTOR_STV; + info->BiosConnector[2].DACType = DAC_TVDAC; + info->BiosConnector[2].TMDSType = TMDS_NONE; +- info->BiosConnector[2].DDCType = DDC_NONE_DETECTED; ++ info->BiosConnector[2].ddc_line = 0; ++ info->BiosConnector[2].devices = ATOM_DEVICE_TV1_SUPPORT; + info->BiosConnector[2].valid = TRUE; +- } ++ } else { ++ if (info->IsMobility) { ++ /* Below is the most common setting, but may not be true */ ++ if (info->IsIGP) { ++ info->BiosConnector[0].ddc_line = RADEON_LCD_GPIO_MASK; ++ info->BiosConnector[0].DACType = DAC_UNKNOWN; ++ info->BiosConnector[0].TMDSType = TMDS_UNKNOWN; ++ info->BiosConnector[0].ConnectorType = CONNECTOR_LVDS; ++ info->BiosConnector[0].valid = TRUE; ++ ++ /* IGP only has TVDAC */ ++ if (info->ChipFamily == CHIP_FAMILY_RS400) ++ info->BiosConnector[1].ddc_line = RADEON_GPIO_CRT2_DDC; ++ else ++ info->BiosConnector[1].ddc_line = RADEON_GPIO_VGA_DDC; ++ info->BiosConnector[1].DACType = DAC_TVDAC; ++ info->BiosConnector[1].TMDSType = TMDS_UNKNOWN; ++ info->BiosConnector[1].ConnectorType = CONNECTOR_VGA; ++ info->BiosConnector[1].valid = TRUE; ++ } else { ++#if defined(__powerpc__) ++ info->BiosConnector[0].ddc_line = RADEON_GPIO_DVI_DDC; ++#else ++ info->BiosConnector[0].ddc_line = RADEON_LCD_GPIO_MASK; ++#endif ++ info->BiosConnector[0].DACType = DAC_UNKNOWN; ++ info->BiosConnector[0].TMDSType = TMDS_UNKNOWN; ++ info->BiosConnector[0].ConnectorType = CONNECTOR_LVDS; ++ info->BiosConnector[0].valid = TRUE; ++ ++ info->BiosConnector[1].ddc_line = RADEON_GPIO_VGA_DDC; ++ info->BiosConnector[1].DACType = DAC_PRIMARY; ++ info->BiosConnector[1].TMDSType = TMDS_UNKNOWN; ++ info->BiosConnector[1].ConnectorType = CONNECTOR_VGA; ++ info->BiosConnector[1].valid = TRUE; ++ } ++ } else { ++ /* Below is the most common setting, but may not be true */ ++ if (info->IsIGP) { ++ if (info->ChipFamily == CHIP_FAMILY_RS400) ++ info->BiosConnector[0].ddc_line = RADEON_GPIO_CRT2_DDC; ++ else ++ info->BiosConnector[0].ddc_line = RADEON_GPIO_VGA_DDC; ++ info->BiosConnector[0].DACType = DAC_TVDAC; ++ info->BiosConnector[0].TMDSType = TMDS_UNKNOWN; ++ info->BiosConnector[0].ConnectorType = CONNECTOR_VGA; ++ info->BiosConnector[0].valid = TRUE; ++ ++ /* not sure what a good default DDCType for DVI on ++ * IGP desktop chips is ++ */ ++ info->BiosConnector[1].ddc_line = RADEON_GPIO_MONID; /* DDC_DVI? */ ++ info->BiosConnector[1].DACType = DAC_UNKNOWN; ++ info->BiosConnector[1].TMDSType = TMDS_EXT; ++ info->BiosConnector[1].ConnectorType = CONNECTOR_DVI_D; ++ info->BiosConnector[1].valid = TRUE; ++ } else { ++ info->BiosConnector[0].ddc_line = RADEON_GPIO_DVI_DDC; ++ info->BiosConnector[0].DACType = DAC_TVDAC; ++ info->BiosConnector[0].TMDSType = TMDS_INT; ++ info->BiosConnector[0].ConnectorType = CONNECTOR_DVI_I; ++ info->BiosConnector[0].valid = TRUE; + +- /* Some cards have the DDC lines swapped and we have no way to +- * detect it yet (Mac cards) +- */ +- if (xf86ReturnOptValBool(info->Options, OPTION_REVERSE_DDC, FALSE)) { +- info->BiosConnector[0].DDCType = DDC_VGA; +- info->BiosConnector[1].DDCType = DDC_DVI; +- } ++#if defined(__powerpc__) ++ info->BiosConnector[1].ddc_line = RADEON_GPIO_VGA_DDC; ++ info->BiosConnector[1].DACType = DAC_PRIMARY; ++ info->BiosConnector[1].TMDSType = TMDS_EXT; ++ info->BiosConnector[1].ConnectorType = CONNECTOR_DVI_I; ++ info->BiosConnector[1].valid = TRUE; ++#else ++ info->BiosConnector[1].ddc_line = RADEON_GPIO_VGA_DDC; ++ info->BiosConnector[1].DACType = DAC_PRIMARY; ++ info->BiosConnector[1].TMDSType = TMDS_EXT; ++ info->BiosConnector[1].ConnectorType = CONNECTOR_VGA; ++ info->BiosConnector[1].valid = TRUE; ++#endif ++ } ++ } + ++ if (info->InternalTVOut) { ++ info->BiosConnector[2].ConnectorType = CONNECTOR_STV; ++ info->BiosConnector[2].DACType = DAC_TVDAC; ++ info->BiosConnector[2].TMDSType = TMDS_NONE; ++ info->BiosConnector[2].ddc_line = 0; ++ info->BiosConnector[2].valid = TRUE; ++ } ++ ++ /* Some cards have the DDC lines swapped and we have no way to ++ * detect it yet (Mac cards) ++ */ ++ if (xf86ReturnOptValBool(info->Options, OPTION_REVERSE_DDC, FALSE)) { ++ info->BiosConnector[0].ddc_line = RADEON_GPIO_VGA_DDC; ++ info->BiosConnector[1].ddc_line = RADEON_GPIO_DVI_DDC; ++ } ++ } + } + + #if defined(__powerpc__) +@@ -3091,6 +3280,7 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn) + int i = 0; + int num_vga = 0; + int num_dvi = 0; ++ int num_hdmi = 0; + + /* We first get the information about all connectors from BIOS. + * This is how the card is phyiscally wired up. +@@ -3098,7 +3288,7 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn) + */ + for (i = 0; i < RADEON_MAX_BIOS_CONNECTOR; i++) { + info->BiosConnector[i].valid = FALSE; +- info->BiosConnector[i].DDCType = DDC_NONE_DETECTED; ++ info->BiosConnector[i].ddc_line = 0; + info->BiosConnector[i].DACType = DAC_UNKNOWN; + info->BiosConnector[i].TMDSType = TMDS_UNKNOWN; + info->BiosConnector[i].ConnectorType = CONNECTOR_NONE; +@@ -3152,12 +3342,12 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn) + if (info->HasSingleDAC) { + /* For RS300/RS350/RS400 chips, there is no primary DAC. Force VGA port to use TVDAC*/ + for (i = 0; i < RADEON_MAX_BIOS_CONNECTOR; i++) { +- if (info->BiosConnector[i].ConnectorType == CONNECTOR_CRT) ++ if (info->BiosConnector[i].ConnectorType == CONNECTOR_VGA) + info->BiosConnector[i].DACType = DAC_TVDAC; + } + } else if (!pRADEONEnt->HasCRTC2) { + for (i = 0; i < RADEON_MAX_BIOS_CONNECTOR; i++) { +- if (info->BiosConnector[i].ConnectorType == CONNECTOR_CRT) ++ if (info->BiosConnector[i].ConnectorType == CONNECTOR_VGA) + info->BiosConnector[i].DACType = DAC_PRIMARY; + } + } +@@ -3172,11 +3362,11 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn) + info->BiosConnector[0].valid = TRUE; + info->BiosConnector[1].valid = TRUE; + if (sscanf(optstr, "%u,%d,%d,%u,%u,%d,%d,%u", +- &info->BiosConnector[0].DDCType, ++ &info->BiosConnector[0].ddc_line, + &info->BiosConnector[0].DACType, + &info->BiosConnector[0].TMDSType, + &info->BiosConnector[0].ConnectorType, +- &info->BiosConnector[1].DDCType, ++ &info->BiosConnector[1].ddc_line, + &info->BiosConnector[1].DACType, + &info->BiosConnector[1].TMDSType, + &info->BiosConnector[1].ConnectorType) != 8) { +@@ -3191,21 +3381,15 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn) + if (info->BiosConnector[i].DACType == DAC_TVDAC) + info->tvdac_use_count++; + +- if (info->IsAtomBios) { +- if ((info->BiosConnector[i].ConnectorType == CONNECTOR_DVI_D_ATOM) || +- (info->BiosConnector[i].ConnectorType == CONNECTOR_DVI_I_ATOM) || +- (info->BiosConnector[i].ConnectorType == CONNECTOR_DVI_A_ATOM)) { +- num_dvi++; +- } else if (info->BiosConnector[i].ConnectorType == CONNECTOR_VGA_ATOM) { +- num_vga++; +- } +- } else { +- if ((info->BiosConnector[i].ConnectorType == CONNECTOR_DVI_D) || +- (info->BiosConnector[i].ConnectorType == CONNECTOR_DVI_I)) { +- num_dvi++; +- } else if (info->BiosConnector[i].ConnectorType == CONNECTOR_CRT) { +- num_vga++; +- } ++ if ((info->BiosConnector[i].ConnectorType == CONNECTOR_DVI_D) || ++ (info->BiosConnector[i].ConnectorType == CONNECTOR_DVI_I) || ++ (info->BiosConnector[i].ConnectorType == CONNECTOR_DVI_A)) { ++ num_dvi++; ++ } else if (info->BiosConnector[i].ConnectorType == CONNECTOR_VGA) { ++ num_vga++; ++ } else if ((info->BiosConnector[i].ConnectorType == CONNECTOR_HDMI_TYPE_A) || ++ (info->BiosConnector[i].ConnectorType == CONNECTOR_HDMI_TYPE_B)) { ++ num_hdmi++; + } + } + } +@@ -3226,67 +3410,47 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn) + } + radeon_output->MonType = MT_UNKNOWN; + radeon_output->ConnectorType = info->BiosConnector[i].ConnectorType; +- radeon_output->DDCType = info->BiosConnector[i].DDCType; +- if (info->IsAtomBios) { +- if (radeon_output->ConnectorType == CONNECTOR_DVI_D_ATOM) +- radeon_output->DACType = DAC_NONE; +- else +- radeon_output->DACType = info->BiosConnector[i].DACType; ++ radeon_output->ddc_line = info->BiosConnector[i].ddc_line; ++ radeon_output->devices = info->BiosConnector[i].devices; ++ radeon_output->output_id = info->BiosConnector[i].output_id; + +- if (radeon_output->ConnectorType == CONNECTOR_VGA_ATOM) +- radeon_output->TMDSType = TMDS_NONE; +- else +- radeon_output->TMDSType = info->BiosConnector[i].TMDSType; +- } else { +- if (radeon_output->ConnectorType == CONNECTOR_DVI_D) +- radeon_output->DACType = DAC_NONE; +- else +- radeon_output->DACType = info->BiosConnector[i].DACType; ++ if (radeon_output->ConnectorType == CONNECTOR_DVI_D) ++ radeon_output->DACType = DAC_NONE; ++ else ++ radeon_output->DACType = info->BiosConnector[i].DACType; ++ ++ if (radeon_output->ConnectorType == CONNECTOR_VGA) ++ radeon_output->TMDSType = TMDS_NONE; ++ else ++ radeon_output->TMDSType = info->BiosConnector[i].TMDSType; + +- if (radeon_output->ConnectorType == CONNECTOR_CRT) +- radeon_output->TMDSType = TMDS_NONE; +- else +- radeon_output->TMDSType = info->BiosConnector[i].TMDSType; +- } + RADEONSetOutputType(pScrn, radeon_output); +- if (info->IsAtomBios) { +- if ((info->BiosConnector[i].ConnectorType == CONNECTOR_DVI_D_ATOM) || +- (info->BiosConnector[i].ConnectorType == CONNECTOR_DVI_I_ATOM) || +- (info->BiosConnector[i].ConnectorType == CONNECTOR_DVI_A_ATOM)) { +- if (num_dvi > 1) { +- output = xf86OutputCreate(pScrn, &radeon_output_funcs, "DVI-1"); +- num_dvi--; +- } else { +- output = xf86OutputCreate(pScrn, &radeon_output_funcs, "DVI-0"); +- } +- } else if (info->BiosConnector[i].ConnectorType == CONNECTOR_VGA_ATOM) { +- if (num_vga > 1) { +- output = xf86OutputCreate(pScrn, &radeon_output_funcs, "VGA-1"); +- num_vga--; +- } else { +- output = xf86OutputCreate(pScrn, &radeon_output_funcs, "VGA-0"); +- } +- } else +- output = xf86OutputCreate(pScrn, &radeon_output_funcs, OutputType[radeon_output->type]); +- } else { +- if ((info->BiosConnector[i].ConnectorType == CONNECTOR_DVI_D) || +- (info->BiosConnector[i].ConnectorType == CONNECTOR_DVI_I)) { +- if (num_dvi > 1) { +- output = xf86OutputCreate(pScrn, &radeon_output_funcs, "DVI-1"); +- num_dvi--; +- } else { +- output = xf86OutputCreate(pScrn, &radeon_output_funcs, "DVI-0"); +- } +- } else if (info->BiosConnector[i].ConnectorType == CONNECTOR_CRT) { +- if (num_vga > 1) { +- output = xf86OutputCreate(pScrn, &radeon_output_funcs, "VGA-1"); +- num_vga--; +- } else { +- output = xf86OutputCreate(pScrn, &radeon_output_funcs, "VGA-0"); +- } +- } else +- output = xf86OutputCreate(pScrn, &radeon_output_funcs, OutputType[radeon_output->type]); +- } ++ if ((info->BiosConnector[i].ConnectorType == CONNECTOR_DVI_D) || ++ (info->BiosConnector[i].ConnectorType == CONNECTOR_DVI_I) || ++ (info->BiosConnector[i].ConnectorType == CONNECTOR_DVI_A)) { ++ if (num_dvi > 1) { ++ output = xf86OutputCreate(pScrn, &radeon_output_funcs, "DVI-1"); ++ num_dvi--; ++ } else { ++ output = xf86OutputCreate(pScrn, &radeon_output_funcs, "DVI-0"); ++ } ++ } else if (info->BiosConnector[i].ConnectorType == CONNECTOR_VGA) { ++ if (num_vga > 1) { ++ output = xf86OutputCreate(pScrn, &radeon_output_funcs, "VGA-1"); ++ num_vga--; ++ } else { ++ output = xf86OutputCreate(pScrn, &radeon_output_funcs, "VGA-0"); ++ } ++ } else if ((info->BiosConnector[i].ConnectorType == CONNECTOR_HDMI_TYPE_A) || ++ (info->BiosConnector[i].ConnectorType == CONNECTOR_HDMI_TYPE_B)) { ++ if (num_hdmi > 1) { ++ output = xf86OutputCreate(pScrn, &radeon_output_funcs, "HDMI-1"); ++ num_hdmi--; ++ } else { ++ output = xf86OutputCreate(pScrn, &radeon_output_funcs, "HDMI-0"); ++ } ++ } else ++ output = xf86OutputCreate(pScrn, &radeon_output_funcs, OutputType[radeon_output->type]); + + if (!output) { + return FALSE; +diff --git a/src/radeon_pci_chipset_gen.h b/src/radeon_pci_chipset_gen.h +index 7a36242..5847d5a 100644 +--- a/src/radeon_pci_chipset_gen.h ++++ b/src/radeon_pci_chipset_gen.h +@@ -135,7 +135,139 @@ PciChipsets RADEONPciChipsets[] = { + { PCI_CHIP_RV410_5E4C, PCI_CHIP_RV410_5E4C, RES_SHARED_VGA }, + { PCI_CHIP_RV410_5E4D, PCI_CHIP_RV410_5E4D, RES_SHARED_VGA }, + { PCI_CHIP_RV410_5E4F, PCI_CHIP_RV410_5E4F, RES_SHARED_VGA }, ++ { PCI_CHIP_R520_7100, PCI_CHIP_R520_7100, RES_SHARED_VGA }, ++ { PCI_CHIP_R520_7101, PCI_CHIP_R520_7101, RES_SHARED_VGA }, ++ { PCI_CHIP_R520_7102, PCI_CHIP_R520_7102, RES_SHARED_VGA }, ++ { PCI_CHIP_R520_7103, PCI_CHIP_R520_7103, RES_SHARED_VGA }, ++ { PCI_CHIP_R520_7104, PCI_CHIP_R520_7104, RES_SHARED_VGA }, ++ { PCI_CHIP_R520_7105, PCI_CHIP_R520_7105, RES_SHARED_VGA }, ++ { PCI_CHIP_R520_7106, PCI_CHIP_R520_7106, RES_SHARED_VGA }, ++ { PCI_CHIP_R520_7108, PCI_CHIP_R520_7108, RES_SHARED_VGA }, ++ { PCI_CHIP_R520_7109, PCI_CHIP_R520_7109, RES_SHARED_VGA }, ++ { PCI_CHIP_R520_710A, PCI_CHIP_R520_710A, RES_SHARED_VGA }, ++ { PCI_CHIP_R520_710B, PCI_CHIP_R520_710B, RES_SHARED_VGA }, ++ { PCI_CHIP_R520_710C, PCI_CHIP_R520_710C, RES_SHARED_VGA }, ++ { PCI_CHIP_R520_710E, PCI_CHIP_R520_710E, RES_SHARED_VGA }, ++ { PCI_CHIP_R520_710F, PCI_CHIP_R520_710F, RES_SHARED_VGA }, ++ { PCI_CHIP_RV515_7140, PCI_CHIP_RV515_7140, RES_SHARED_VGA }, ++ { PCI_CHIP_RV515_7141, PCI_CHIP_RV515_7141, RES_SHARED_VGA }, ++ { PCI_CHIP_RV515_7142, PCI_CHIP_RV515_7142, RES_SHARED_VGA }, ++ { PCI_CHIP_RV515_7143, PCI_CHIP_RV515_7143, RES_SHARED_VGA }, ++ { PCI_CHIP_RV515_7144, PCI_CHIP_RV515_7144, RES_SHARED_VGA }, ++ { PCI_CHIP_RV515_7145, PCI_CHIP_RV515_7145, RES_SHARED_VGA }, ++ { PCI_CHIP_RV515_7146, PCI_CHIP_RV515_7146, RES_SHARED_VGA }, ++ { PCI_CHIP_RV515_7147, PCI_CHIP_RV515_7147, RES_SHARED_VGA }, ++ { PCI_CHIP_RV515_7149, PCI_CHIP_RV515_7149, RES_SHARED_VGA }, ++ { PCI_CHIP_RV515_714A, PCI_CHIP_RV515_714A, RES_SHARED_VGA }, ++ { PCI_CHIP_RV515_714B, PCI_CHIP_RV515_714B, RES_SHARED_VGA }, ++ { PCI_CHIP_RV515_714C, PCI_CHIP_RV515_714C, RES_SHARED_VGA }, ++ { PCI_CHIP_RV515_714D, PCI_CHIP_RV515_714D, RES_SHARED_VGA }, ++ { PCI_CHIP_RV515_714E, PCI_CHIP_RV515_714E, RES_SHARED_VGA }, ++ { PCI_CHIP_RV515_714F, PCI_CHIP_RV515_714F, RES_SHARED_VGA }, ++ { PCI_CHIP_RV515_7151, PCI_CHIP_RV515_7151, RES_SHARED_VGA }, ++ { PCI_CHIP_RV515_7152, PCI_CHIP_RV515_7152, RES_SHARED_VGA }, ++ { PCI_CHIP_RV515_7153, PCI_CHIP_RV515_7153, RES_SHARED_VGA }, ++ { PCI_CHIP_RV515_715E, PCI_CHIP_RV515_715E, RES_SHARED_VGA }, ++ { PCI_CHIP_RV515_715F, PCI_CHIP_RV515_715F, RES_SHARED_VGA }, ++ { PCI_CHIP_RV515_7180, PCI_CHIP_RV515_7180, RES_SHARED_VGA }, ++ { PCI_CHIP_RV515_7181, PCI_CHIP_RV515_7181, RES_SHARED_VGA }, ++ { PCI_CHIP_RV515_7183, PCI_CHIP_RV515_7183, RES_SHARED_VGA }, ++ { PCI_CHIP_RV515_7186, PCI_CHIP_RV515_7186, RES_SHARED_VGA }, ++ { PCI_CHIP_RV515_7187, PCI_CHIP_RV515_7187, RES_SHARED_VGA }, ++ { PCI_CHIP_RV515_7188, PCI_CHIP_RV515_7188, RES_SHARED_VGA }, ++ { PCI_CHIP_RV515_718A, PCI_CHIP_RV515_718A, RES_SHARED_VGA }, ++ { PCI_CHIP_RV515_718B, PCI_CHIP_RV515_718B, RES_SHARED_VGA }, ++ { PCI_CHIP_RV515_718C, PCI_CHIP_RV515_718C, RES_SHARED_VGA }, ++ { PCI_CHIP_RV515_718D, PCI_CHIP_RV515_718D, RES_SHARED_VGA }, ++ { PCI_CHIP_RV515_718F, PCI_CHIP_RV515_718F, RES_SHARED_VGA }, ++ { PCI_CHIP_RV515_7193, PCI_CHIP_RV515_7193, RES_SHARED_VGA }, ++ { PCI_CHIP_RV515_7196, PCI_CHIP_RV515_7196, RES_SHARED_VGA }, ++ { PCI_CHIP_RV515_719B, PCI_CHIP_RV515_719B, RES_SHARED_VGA }, ++ { PCI_CHIP_RV515_719F, PCI_CHIP_RV515_719F, RES_SHARED_VGA }, ++ { PCI_CHIP_RV530_71C0, PCI_CHIP_RV530_71C0, RES_SHARED_VGA }, ++ { PCI_CHIP_RV530_71C1, PCI_CHIP_RV530_71C1, RES_SHARED_VGA }, ++ { PCI_CHIP_RV530_71C2, PCI_CHIP_RV530_71C2, RES_SHARED_VGA }, ++ { PCI_CHIP_RV530_71C3, PCI_CHIP_RV530_71C3, RES_SHARED_VGA }, ++ { PCI_CHIP_RV530_71C4, PCI_CHIP_RV530_71C4, RES_SHARED_VGA }, ++ { PCI_CHIP_RV530_71C5, PCI_CHIP_RV530_71C5, RES_SHARED_VGA }, ++ { PCI_CHIP_RV530_71C6, PCI_CHIP_RV530_71C6, RES_SHARED_VGA }, ++ { PCI_CHIP_RV530_71C7, PCI_CHIP_RV530_71C7, RES_SHARED_VGA }, ++ { PCI_CHIP_RV530_71CD, PCI_CHIP_RV530_71CD, RES_SHARED_VGA }, ++ { PCI_CHIP_RV530_71CE, PCI_CHIP_RV530_71CE, RES_SHARED_VGA }, ++ { PCI_CHIP_RV530_71D2, PCI_CHIP_RV530_71D2, RES_SHARED_VGA }, ++ { PCI_CHIP_RV530_71D4, PCI_CHIP_RV530_71D4, RES_SHARED_VGA }, ++ { PCI_CHIP_RV530_71D5, PCI_CHIP_RV530_71D5, RES_SHARED_VGA }, ++ { PCI_CHIP_RV530_71D6, PCI_CHIP_RV530_71D6, RES_SHARED_VGA }, ++ { PCI_CHIP_RV530_71DA, PCI_CHIP_RV530_71DA, RES_SHARED_VGA }, ++ { PCI_CHIP_RV530_71DE, PCI_CHIP_RV530_71DE, RES_SHARED_VGA }, ++ { PCI_CHIP_RV530_7200, PCI_CHIP_RV530_7200, RES_SHARED_VGA }, ++ { PCI_CHIP_RV530_7210, PCI_CHIP_RV530_7210, RES_SHARED_VGA }, ++ { PCI_CHIP_RV530_7211, PCI_CHIP_RV530_7211, RES_SHARED_VGA }, ++ { PCI_CHIP_R580_7240, PCI_CHIP_R580_7240, RES_SHARED_VGA }, ++ { PCI_CHIP_R580_7243, PCI_CHIP_R580_7243, RES_SHARED_VGA }, ++ { PCI_CHIP_R580_7244, PCI_CHIP_R580_7244, RES_SHARED_VGA }, ++ { PCI_CHIP_R580_7245, PCI_CHIP_R580_7245, RES_SHARED_VGA }, ++ { PCI_CHIP_R580_7246, PCI_CHIP_R580_7246, RES_SHARED_VGA }, ++ { PCI_CHIP_R580_7247, PCI_CHIP_R580_7247, RES_SHARED_VGA }, ++ { PCI_CHIP_R580_7248, PCI_CHIP_R580_7248, RES_SHARED_VGA }, ++ { PCI_CHIP_R580_7249, PCI_CHIP_R580_7249, RES_SHARED_VGA }, ++ { PCI_CHIP_R580_724A, PCI_CHIP_R580_724A, RES_SHARED_VGA }, ++ { PCI_CHIP_R580_724B, PCI_CHIP_R580_724B, RES_SHARED_VGA }, ++ { PCI_CHIP_R580_724C, PCI_CHIP_R580_724C, RES_SHARED_VGA }, ++ { PCI_CHIP_R580_724D, PCI_CHIP_R580_724D, RES_SHARED_VGA }, ++ { PCI_CHIP_R580_724E, PCI_CHIP_R580_724E, RES_SHARED_VGA }, ++ { PCI_CHIP_R580_724F, PCI_CHIP_R580_724F, RES_SHARED_VGA }, ++ { PCI_CHIP_RV570_7280, PCI_CHIP_RV570_7280, RES_SHARED_VGA }, ++ { PCI_CHIP_RV560_7281, PCI_CHIP_RV560_7281, RES_SHARED_VGA }, ++ { PCI_CHIP_RV560_7283, PCI_CHIP_RV560_7283, RES_SHARED_VGA }, ++ { PCI_CHIP_R580_7284, PCI_CHIP_R580_7284, RES_SHARED_VGA }, ++ { PCI_CHIP_RV560_7287, PCI_CHIP_RV560_7287, RES_SHARED_VGA }, ++ { PCI_CHIP_RV570_7288, PCI_CHIP_RV570_7288, RES_SHARED_VGA }, ++ { PCI_CHIP_RV570_7289, PCI_CHIP_RV570_7289, RES_SHARED_VGA }, ++ { PCI_CHIP_RV570_728B, PCI_CHIP_RV570_728B, RES_SHARED_VGA }, ++ { PCI_CHIP_RV570_728C, PCI_CHIP_RV570_728C, RES_SHARED_VGA }, ++ { PCI_CHIP_RV560_7290, PCI_CHIP_RV560_7290, RES_SHARED_VGA }, ++ { PCI_CHIP_RV560_7291, PCI_CHIP_RV560_7291, RES_SHARED_VGA }, ++ { PCI_CHIP_RV560_7293, PCI_CHIP_RV560_7293, RES_SHARED_VGA }, ++ { PCI_CHIP_RV560_7297, PCI_CHIP_RV560_7297, RES_SHARED_VGA }, + { PCI_CHIP_RS350_7834, PCI_CHIP_RS350_7834, RES_SHARED_VGA }, + { PCI_CHIP_RS350_7835, PCI_CHIP_RS350_7835, RES_SHARED_VGA }, ++ { PCI_CHIP_RS690_791E, PCI_CHIP_RS690_791E, RES_SHARED_VGA }, ++ { PCI_CHIP_RS690_791F, PCI_CHIP_RS690_791F, RES_SHARED_VGA }, ++ { PCI_CHIP_RS740_796C, PCI_CHIP_RS740_796C, RES_SHARED_VGA }, ++ { PCI_CHIP_RS740_796D, PCI_CHIP_RS740_796D, RES_SHARED_VGA }, ++ { PCI_CHIP_RS740_796E, PCI_CHIP_RS740_796E, RES_SHARED_VGA }, ++ { PCI_CHIP_RS740_796F, PCI_CHIP_RS740_796F, RES_SHARED_VGA }, ++ { PCI_CHIP_R600_9400, PCI_CHIP_R600_9400, RES_SHARED_VGA }, ++ { PCI_CHIP_R600_9401, PCI_CHIP_R600_9401, RES_SHARED_VGA }, ++ { PCI_CHIP_R600_9402, PCI_CHIP_R600_9402, RES_SHARED_VGA }, ++ { PCI_CHIP_R600_9403, PCI_CHIP_R600_9403, RES_SHARED_VGA }, ++ { PCI_CHIP_R600_9405, PCI_CHIP_R600_9405, RES_SHARED_VGA }, ++ { PCI_CHIP_R600_940A, PCI_CHIP_R600_940A, RES_SHARED_VGA }, ++ { PCI_CHIP_R600_940B, PCI_CHIP_R600_940B, RES_SHARED_VGA }, ++ { PCI_CHIP_R600_940F, PCI_CHIP_R600_940F, RES_SHARED_VGA }, ++ { PCI_CHIP_RV610_94C0, PCI_CHIP_RV610_94C0, RES_SHARED_VGA }, ++ { PCI_CHIP_RV610_94C1, PCI_CHIP_RV610_94C1, RES_SHARED_VGA }, ++ { PCI_CHIP_RV610_94C3, PCI_CHIP_RV610_94C3, RES_SHARED_VGA }, ++ { PCI_CHIP_RV610_94C4, PCI_CHIP_RV610_94C4, RES_SHARED_VGA }, ++ { PCI_CHIP_RV610_94C5, PCI_CHIP_RV610_94C5, RES_SHARED_VGA }, ++ { PCI_CHIP_RV610_94C6, PCI_CHIP_RV610_94C6, RES_SHARED_VGA }, ++ { PCI_CHIP_RV610_94C7, PCI_CHIP_RV610_94C7, RES_SHARED_VGA }, ++ { PCI_CHIP_RV610_94C8, PCI_CHIP_RV610_94C8, RES_SHARED_VGA }, ++ { PCI_CHIP_RV610_94C9, PCI_CHIP_RV610_94C9, RES_SHARED_VGA }, ++ { PCI_CHIP_RV610_94CB, PCI_CHIP_RV610_94CB, RES_SHARED_VGA }, ++ { PCI_CHIP_RV610_94CC, PCI_CHIP_RV610_94CC, RES_SHARED_VGA }, ++ { PCI_CHIP_RV630_9580, PCI_CHIP_RV630_9580, RES_SHARED_VGA }, ++ { PCI_CHIP_RV630_9581, PCI_CHIP_RV630_9581, RES_SHARED_VGA }, ++ { PCI_CHIP_RV630_9583, PCI_CHIP_RV630_9583, RES_SHARED_VGA }, ++ { PCI_CHIP_RV630_9586, PCI_CHIP_RV630_9586, RES_SHARED_VGA }, ++ { PCI_CHIP_RV630_9587, PCI_CHIP_RV630_9587, RES_SHARED_VGA }, ++ { PCI_CHIP_RV630_9588, PCI_CHIP_RV630_9588, RES_SHARED_VGA }, ++ { PCI_CHIP_RV630_9589, PCI_CHIP_RV630_9589, RES_SHARED_VGA }, ++ { PCI_CHIP_RV630_958A, PCI_CHIP_RV630_958A, RES_SHARED_VGA }, ++ { PCI_CHIP_RV630_958B, PCI_CHIP_RV630_958B, RES_SHARED_VGA }, ++ { PCI_CHIP_RV630_958C, PCI_CHIP_RV630_958C, RES_SHARED_VGA }, ++ { PCI_CHIP_RV630_958D, PCI_CHIP_RV630_958D, RES_SHARED_VGA }, ++ { PCI_CHIP_RV630_958E, PCI_CHIP_RV630_958E, RES_SHARED_VGA }, + { -1, -1, RES_UNDEFINED } + }; +diff --git a/src/radeon_probe.c b/src/radeon_probe.c +index baea47c..e0a77e6 100644 +--- a/src/radeon_probe.c ++++ b/src/radeon_probe.c +@@ -175,7 +175,7 @@ RADEONProbe(DriverPtr drv, int flags) + DevUnion *pPriv; + RADEONEntPtr pRADEONEnt; + +- /*xf86SetEntitySharable(usedChips[i]);*/ ++ xf86SetEntitySharable(usedChips[i]); + + if (gRADEONEntityIndex == -1) + gRADEONEntityIndex = xf86AllocateEntityPrivateIndex(); +diff --git a/src/radeon_probe.h b/src/radeon_probe.h +index 7f8ce45..a25d635 100644 +--- a/src/radeon_probe.h ++++ b/src/radeon_probe.h +@@ -36,6 +36,7 @@ + #ifndef _RADEON_PROBE_H_ + #define _RADEON_PROBE_H_ 1 + ++#include + #include "xf86str.h" + #include "xf86DDC.h" + #include "randrstr.h" +@@ -54,54 +55,39 @@ + + typedef enum + { +- DDC_NONE_DETECTED, +- DDC_MONID, +- DDC_DVI, +- DDC_VGA, +- DDC_CRT2, +- DDC_LCD, +- DDC_GPIO, +-} RADEONDDCType; +- +-typedef enum +-{ + MT_UNKNOWN = -1, + MT_NONE = 0, + MT_CRT = 1, + MT_LCD = 2, + MT_DFP = 3, + MT_CTV = 4, +- MT_STV = 5 ++ MT_STV = 5, ++ MT_CV = 6, ++ MT_HDMI = 7, // this should really just be MT_DFP ++ MT_DP = 8 + } RADEONMonitorType; + + typedef enum + { + CONNECTOR_NONE, +- CONNECTOR_PROPRIETARY, +- CONNECTOR_CRT, ++ CONNECTOR_VGA, + CONNECTOR_DVI_I, + CONNECTOR_DVI_D, +- CONNECTOR_CTV, ++ CONNECTOR_DVI_A, + CONNECTOR_STV, ++ CONNECTOR_CTV, ++ CONNECTOR_LVDS, ++ CONNECTOR_DIGITAL, ++ CONNECTOR_SCART, ++ CONNECTOR_HDMI_TYPE_A, ++ CONNECTOR_HDMI_TYPE_B, ++ CONNECTOR_DIN, ++ CONNECTOR_DISPLAY_PORT, + CONNECTOR_UNSUPPORTED + } RADEONConnectorType; + + typedef enum + { +- CONNECTOR_NONE_ATOM, +- CONNECTOR_VGA_ATOM, +- CONNECTOR_DVI_I_ATOM, +- CONNECTOR_DVI_D_ATOM, +- CONNECTOR_DVI_A_ATOM, +- CONNECTOR_STV_ATOM, +- CONNECTOR_CTV_ATOM, +- CONNECTOR_LVDS_ATOM, +- CONNECTOR_DIGITAL_ATOM, +- CONNECTOR_UNSUPPORTED_ATOM +-} RADEONConnectorTypeATOM; +- +-typedef enum +-{ + DAC_UNKNOWN = -1, + DAC_PRIMARY = 0, + DAC_TVDAC = 1, +@@ -140,12 +126,23 @@ typedef enum + { + OUTPUT_NONE, + OUTPUT_VGA, +- OUTPUT_DVI, ++ OUTPUT_DVI_I, ++ OUTPUT_DVI_D, ++ OUTPUT_DVI_A, + OUTPUT_LVDS, + OUTPUT_STV, + OUTPUT_CTV, ++ OUTPUT_CV, ++ OUTPUT_HDMI, ++ OUTPUT_DP + } RADEONOutputType; + ++#define OUTPUT_IS_DVI ((radeon_output->type == OUTPUT_DVI_D || \ ++ radeon_output->type == OUTPUT_DVI_I || \ ++ radeon_output->type == OUTPUT_DVI_A)) ++#define OUTPUT_IS_TV ((radeon_output->type == OUTPUT_STV || \ ++ radeon_output->type == OUTPUT_CTV)) ++ + /* standards */ + typedef enum + { +@@ -155,6 +152,8 @@ typedef enum + TV_STD_PAL_60 = 8, + TV_STD_NTSC_J = 16, + TV_STD_SCART_PAL = 32, ++ TV_STD_SECAM = 64, ++ TV_STD_PAL_CN = 128, + } TVStd; + + typedef struct _RADEONCrtcPrivateRec { +@@ -169,21 +168,32 @@ typedef struct _RADEONCrtcPrivateRec { + CARD32 cursor_offset; + /* Lookup table values to be set when the CRTC is enabled */ + CARD8 lut_r[256], lut_g[256], lut_b[256]; ++ ++ uint32_t crtc_offset; ++ int h_total, h_blank, h_sync_wid, h_sync_pol; ++ int v_total, v_blank, v_sync_wid, v_sync_pol; ++ int fb_format, fb_length; ++ int fb_pitch, fb_width, fb_height; ++ INT16 cursor_x; ++ INT16 cursor_y; + } RADEONCrtcPrivateRec, *RADEONCrtcPrivatePtr; + + typedef struct { +- RADEONDDCType DDCType; ++ CARD32 ddc_line; + RADEONDacType DACType; + RADEONTmdsType TMDSType; + RADEONConnectorType ConnectorType; + Bool valid; ++ int output_id; ++ int devices; ++ int hpd_mask; + } RADEONBIOSConnector; + + typedef struct _RADEONOutputPrivateRec { + int num; + RADEONOutputType type; + void *dev_priv; +- RADEONDDCType DDCType; ++ CARD32 ddc_line; + RADEONDacType DACType; + RADEONDviType DVIType; + RADEONTmdsType TMDSType; +@@ -222,10 +232,289 @@ typedef struct _RADEONOutputPrivateRec { + int SupportedTVStds; + Bool tv_on; + int load_detection; ++ ++ char *name; ++ int output_id; ++ int devices; + } RADEONOutputPrivateRec, *RADEONOutputPrivatePtr; + ++struct avivo_pll_state { ++ CARD32 ref_div_src; ++ CARD32 ref_div; ++ CARD32 fb_div; ++ CARD32 post_div_src; ++ CARD32 post_div; ++ CARD32 ext_ppll_cntl; ++ CARD32 pll_cntl; ++ CARD32 int_ss_cntl; ++}; ++ ++ ++struct avivo_crtc_state { ++ CARD32 pll_source; ++ CARD32 h_total; ++ CARD32 h_blank_start_end; ++ CARD32 h_sync_a; ++ CARD32 h_sync_a_cntl; ++ CARD32 h_sync_b; ++ CARD32 h_sync_b_cntl; ++ CARD32 v_total; ++ CARD32 v_blank_start_end; ++ CARD32 v_sync_a; ++ CARD32 v_sync_a_cntl; ++ CARD32 v_sync_b; ++ CARD32 v_sync_b_cntl; ++ CARD32 control; ++ CARD32 blank_control; ++ CARD32 interlace_control; ++ CARD32 stereo_control; ++ CARD32 cursor_control; ++}; ++ ++struct avivo_grph_state { ++ CARD32 enable; ++ CARD32 control; ++ CARD32 prim_surf_addr; ++ CARD32 sec_surf_addr; ++ CARD32 pitch; ++ CARD32 x_offset; ++ CARD32 y_offset; ++ CARD32 x_start; ++ CARD32 y_start; ++ CARD32 x_end; ++ CARD32 y_end; ++ ++ CARD32 viewport_start; ++ CARD32 viewport_size; ++ CARD32 scl_enable; ++}; ++ ++struct avivo_dac_state { ++ CARD32 enable; ++ CARD32 source_select; ++ CARD32 force_output_cntl; ++ CARD32 powerdown; ++}; ++ ++struct avivo_dig_state { ++ CARD32 cntl; ++ CARD32 bit_depth_cntl; ++ CARD32 data_sync; ++ CARD32 transmitter_enable; ++ CARD32 transmitter_cntl; ++ CARD32 source_select; ++}; ++ ++struct avivo_state ++{ ++ CARD32 hdp_fb_location; ++ CARD32 mc_memory_map; ++ CARD32 vga_memory_base; ++ CARD32 vga_fb_start; ++ ++ CARD32 vga1_cntl; ++ CARD32 vga2_cntl; ++ ++ CARD32 crtc_master_en; ++ CARD32 crtc_tv_control; ++ ++ CARD32 lvtma_pwrseq_cntl; ++ CARD32 lvtma_pwrseq_state; ++ ++ struct avivo_pll_state pll1; ++ struct avivo_pll_state pll2; ++ ++ struct avivo_crtc_state crtc1; ++ struct avivo_crtc_state crtc2; ++ ++ struct avivo_grph_state grph1; ++ struct avivo_grph_state grph2; ++ ++ struct avivo_dac_state daca; ++ struct avivo_dac_state dacb; ++ ++ struct avivo_dig_state tmds1; ++ struct avivo_dig_state tmds2; ++ ++}; ++ ++/* ++ * Maximum length of horizontal/vertical code timing tables for state storage ++ */ ++#define MAX_H_CODE_TIMING_LEN 32 ++#define MAX_V_CODE_TIMING_LEN 32 ++ ++typedef struct { ++ struct avivo_state avivo; ++ ++ /* Common registers */ ++ CARD32 ovr_clr; ++ CARD32 ovr_wid_left_right; ++ CARD32 ovr_wid_top_bottom; ++ CARD32 ov0_scale_cntl; ++ CARD32 mpp_tb_config; ++ CARD32 mpp_gp_config; ++ CARD32 subpic_cntl; ++ CARD32 viph_control; ++ CARD32 i2c_cntl_1; ++ CARD32 gen_int_cntl; ++ CARD32 cap0_trig_cntl; ++ CARD32 cap1_trig_cntl; ++ CARD32 bus_cntl; ++ CARD32 bios_4_scratch; ++ CARD32 bios_5_scratch; ++ CARD32 bios_6_scratch; ++ CARD32 surface_cntl; ++ CARD32 surfaces[8][3]; ++ CARD32 mc_agp_location; ++ CARD32 mc_agp_location_hi; ++ CARD32 mc_fb_location; ++ CARD32 display_base_addr; ++ CARD32 display2_base_addr; ++ CARD32 ov0_base_addr; ++ ++ /* Other registers to save for VT switches */ ++ CARD32 dp_datatype; ++ CARD32 rbbm_soft_reset; ++ CARD32 clock_cntl_index; ++ CARD32 amcgpio_en_reg; ++ CARD32 amcgpio_mask; ++ ++ /* CRTC registers */ ++ CARD32 crtc_gen_cntl; ++ CARD32 crtc_ext_cntl; ++ CARD32 dac_cntl; ++ CARD32 crtc_h_total_disp; ++ CARD32 crtc_h_sync_strt_wid; ++ CARD32 crtc_v_total_disp; ++ CARD32 crtc_v_sync_strt_wid; ++ CARD32 crtc_offset; ++ CARD32 crtc_offset_cntl; ++ CARD32 crtc_pitch; ++ CARD32 disp_merge_cntl; ++ CARD32 grph_buffer_cntl; ++ CARD32 crtc_more_cntl; ++ CARD32 crtc_tile_x0_y0; ++ ++ /* CRTC2 registers */ ++ CARD32 crtc2_gen_cntl; ++ CARD32 dac_macro_cntl; ++ CARD32 dac2_cntl; ++ CARD32 disp_output_cntl; ++ CARD32 disp_tv_out_cntl; ++ CARD32 disp_hw_debug; ++ CARD32 disp2_merge_cntl; ++ CARD32 grph2_buffer_cntl; ++ CARD32 crtc2_h_total_disp; ++ CARD32 crtc2_h_sync_strt_wid; ++ CARD32 crtc2_v_total_disp; ++ CARD32 crtc2_v_sync_strt_wid; ++ CARD32 crtc2_offset; ++ CARD32 crtc2_offset_cntl; ++ CARD32 crtc2_pitch; ++ CARD32 crtc2_tile_x0_y0; ++ ++ /* Flat panel registers */ ++ CARD32 fp_crtc_h_total_disp; ++ CARD32 fp_crtc_v_total_disp; ++ CARD32 fp_gen_cntl; ++ CARD32 fp2_gen_cntl; ++ CARD32 fp_h_sync_strt_wid; ++ CARD32 fp_h2_sync_strt_wid; ++ CARD32 fp_horz_stretch; ++ CARD32 fp_panel_cntl; ++ CARD32 fp_v_sync_strt_wid; ++ CARD32 fp_v2_sync_strt_wid; ++ CARD32 fp_vert_stretch; ++ CARD32 lvds_gen_cntl; ++ CARD32 lvds_pll_cntl; ++ CARD32 tmds_pll_cntl; ++ CARD32 tmds_transmitter_cntl; ++ ++ /* Computed values for PLL */ ++ CARD32 dot_clock_freq; ++ CARD32 pll_output_freq; ++ int feedback_div; ++ int reference_div; ++ int post_div; ++ ++ /* PLL registers */ ++ unsigned ppll_ref_div; ++ unsigned ppll_div_3; ++ CARD32 htotal_cntl; ++ CARD32 vclk_ecp_cntl; ++ ++ /* Computed values for PLL2 */ ++ CARD32 dot_clock_freq_2; ++ CARD32 pll_output_freq_2; ++ int feedback_div_2; ++ int reference_div_2; ++ int post_div_2; ++ ++ /* PLL2 registers */ ++ CARD32 p2pll_ref_div; ++ CARD32 p2pll_div_0; ++ CARD32 htotal_cntl2; ++ CARD32 pixclks_cntl; ++ ++ /* Pallet */ ++ Bool palette_valid; ++ CARD32 palette[256]; ++ CARD32 palette2[256]; ++ ++ CARD32 rs480_unk_e30; ++ CARD32 rs480_unk_e34; ++ CARD32 rs480_unk_e38; ++ CARD32 rs480_unk_e3c; ++ ++ /* TV out registers */ ++ CARD32 tv_master_cntl; ++ CARD32 tv_htotal; ++ CARD32 tv_hsize; ++ CARD32 tv_hdisp; ++ CARD32 tv_hstart; ++ CARD32 tv_vtotal; ++ CARD32 tv_vdisp; ++ CARD32 tv_timing_cntl; ++ CARD32 tv_vscaler_cntl1; ++ CARD32 tv_vscaler_cntl2; ++ CARD32 tv_sync_size; ++ CARD32 tv_vrestart; ++ CARD32 tv_hrestart; ++ CARD32 tv_frestart; ++ CARD32 tv_ftotal; ++ CARD32 tv_clock_sel_cntl; ++ CARD32 tv_clkout_cntl; ++ CARD32 tv_data_delay_a; ++ CARD32 tv_data_delay_b; ++ CARD32 tv_dac_cntl; ++ CARD32 tv_pll_cntl; ++ CARD32 tv_pll_cntl1; ++ CARD32 tv_pll_fine_cntl; ++ CARD32 tv_modulator_cntl1; ++ CARD32 tv_modulator_cntl2; ++ CARD32 tv_frame_lock_cntl; ++ CARD32 tv_pre_dac_mux_cntl; ++ CARD32 tv_rgb_cntl; ++ CARD32 tv_y_saw_tooth_cntl; ++ CARD32 tv_y_rise_cntl; ++ CARD32 tv_y_fall_cntl; ++ CARD32 tv_uv_adr; ++ CARD32 tv_upsamp_and_gain_cntl; ++ CARD32 tv_gain_limit_settings; ++ CARD32 tv_linear_gain_settings; ++ CARD32 tv_crc_cntl; ++ CARD32 tv_sync_cntl; ++ CARD32 gpiopad_a; ++ CARD32 pll_test_cntl; ++ ++ CARD16 h_code_timing[MAX_H_CODE_TIMING_LEN]; ++ CARD16 v_code_timing[MAX_V_CODE_TIMING_LEN]; ++ ++} RADEONSaveRec, *RADEONSavePtr; ++ + #define RADEON_MAX_CRTC 2 +-#define RADEON_MAX_BIOS_CONNECTOR 8 ++#define RADEON_MAX_BIOS_CONNECTOR 16 + + typedef struct + { +@@ -243,6 +532,12 @@ typedef struct + xf86CrtcPtr pCrtc[RADEON_MAX_CRTC]; + RADEONCrtcPrivatePtr Controller[RADEON_MAX_CRTC]; + ++ ScrnInfoPtr pSecondaryScrn; ++ ScrnInfoPtr pPrimaryScrn; ++ ++ RADEONSaveRec ModeReg; /* Current mode */ ++ RADEONSaveRec SavedReg; /* Original (text) mode */ ++ + } RADEONEntRec, *RADEONEntPtr; + + /* radeon_probe.c */ +diff --git a/src/radeon_reg.h b/src/radeon_reg.h +index 6e4e383..dce29e2 100644 +--- a/src/radeon_reg.h ++++ b/src/radeon_reg.h +@@ -997,6 +997,7 @@ + #define RADEON_MPP_GP_CONFIG 0x01c8 /* ? */ + #define R300_MC_IND_INDEX 0x01f8 + # define R300_MC_IND_ADDR_MASK 0x3f ++# define R300_MC_IND_WR_EN (1 << 8) + #define R300_MC_IND_DATA 0x01fc + #define R300_MC_READ_CNTL_AB 0x017c + # define R300_MEM_RBS_POSITION_A_MASK 0x03 +@@ -3271,4 +3272,464 @@ + #define RADEON_RS480_UNK_e38 0xe38 + #define RADEON_RS480_UNK_e3c 0xe3c + ++ ++#define AVIVO_MC_INDEX 0x0070 ++#define R520_MC_STATUS 0x00 ++#define R520_MC_STATUS_IDLE (1<<1) ++#define RV515_MC_STATUS 0x08 ++#define RV515_MC_STATUS_IDLE (1<<4) ++#define AVIVO_MC_DATA 0x0074 ++ ++#define RV515_MC_FB_LOCATION 0x1 ++#define RV515_MC_AGP_LOCATION 0x2 ++#define R520_MC_FB_LOCATION 0x4 ++#define R520_MC_AGP_LOCATION 0x5 ++ ++#define AVIVO_HDP_FB_LOCATION 0x134 ++ ++#define AVIVO_D1VGA_CONTROL 0x0330 ++# define AVIVO_DVGA_CONTROL_MODE_ENABLE (1<<0) ++# define AVIVO_DVGA_CONTROL_TIMING_SELECT (1<<8) ++# define AVIVO_DVGA_CONTROL_SYNC_POLARITY_SELECT (1<<9) ++# define AVIVO_DVGA_CONTROL_OVERSCAN_TIMING_SELECT (1<<10) ++# define AVIVO_DVGA_CONTROL_OVERSCAN_COLOR_EN (1<<16) ++# define AVIVO_DVGA_CONTROL_ROTATE (1<<24) ++#define AVIVO_D2VGA_CONTROL 0x0338 ++ ++#define AVIVO_EXT1_PPLL_REF_DIV_SRC 0x400 ++#define AVIVO_EXT1_PPLL_REF_DIV 0x404 ++#define AVIVO_EXT1_PPLL_UPDATE_LOCK 0x408 ++#define AVIVO_EXT1_PPLL_UPDATE_CNTL 0x40c ++ ++#define AVIVO_EXT2_PPLL_REF_DIV_SRC 0x410 ++#define AVIVO_EXT2_PPLL_REF_DIV 0x414 ++#define AVIVO_EXT2_PPLL_UPDATE_LOCK 0x418 ++#define AVIVO_EXT2_PPLL_UPDATE_CNTL 0x41c ++ ++#define AVIVO_EXT1_PPLL_FB_DIV 0x430 ++#define AVIVO_EXT2_PPLL_FB_DIV 0x434 ++ ++#define AVIVO_EXT1_PPLL_POST_DIV_SRC 0x438 ++#define AVIVO_EXT1_PPLL_POST_DIV 0x43c ++ ++#define AVIVO_EXT2_PPLL_POST_DIV_SRC 0x440 ++#define AVIVO_EXT2_PPLL_POST_DIV 0x444 ++ ++#define AVIVO_EXT1_PPLL_CNTL 0x448 ++#define AVIVO_EXT2_PPLL_CNTL 0x44c ++ ++#define AVIVO_P1PLL_CNTL 0x450 ++#define AVIVO_P2PLL_CNTL 0x454 ++#define AVIVO_P1PLL_INT_SS_CNTL 0x458 ++#define AVIVO_P2PLL_INT_SS_CNTL 0x45c ++#define AVIVO_P1PLL_TMDSA_CNTL 0x460 ++#define AVIVO_P2PLL_LVTMA_CNTL 0x464 ++ ++#define AVIVO_PCLK_CRTC1_CNTL 0x480 ++#define AVIVO_PCLK_CRTC2_CNTL 0x484 ++ ++#define AVIVO_D1CRTC_H_TOTAL 0x6000 ++#define AVIVO_D1CRTC_H_BLANK_START_END 0x6004 ++#define AVIVO_D1CRTC_H_SYNC_A 0x6008 ++#define AVIVO_D1CRTC_H_SYNC_A_CNTL 0x600c ++#define AVIVO_D1CRTC_H_SYNC_B 0x6010 ++#define AVIVO_D1CRTC_H_SYNC_B_CNTL 0x6014 ++ ++#define AVIVO_D1CRTC_V_TOTAL 0x6020 ++#define AVIVO_D1CRTC_V_BLANK_START_END 0x6024 ++#define AVIVO_D1CRTC_V_SYNC_A 0x6028 ++#define AVIVO_D1CRTC_V_SYNC_A_CNTL 0x602c ++#define AVIVO_D1CRTC_V_SYNC_B 0x6030 ++#define AVIVO_D1CRTC_V_SYNC_B_CNTL 0x6034 ++ ++#define AVIVO_D1CRTC_CONTROL 0x6080 ++# define AVIVO_CRTC_EN (1<<0) ++#define AVIVO_D1CRTC_BLANK_CONTROL 0x6084 ++#define AVIVO_D1CRTC_INTERLACE_CONTROL 0x6088 ++#define AVIVO_D1CRTC_INTERLACE_STATUS 0x608c ++#define AVIVO_D1CRTC_STEREO_CONTROL 0x60c4 ++ ++/* master controls */ ++#define AVIVO_DC_CRTC_MASTER_EN 0x60f8 ++#define AVIVO_DC_CRTC_TV_CONTROL 0x60fc ++ ++#define AVIVO_D1GRPH_ENABLE 0x6100 ++#define AVIVO_D1GRPH_CONTROL 0x6104 ++# define AVIVO_D1GRPH_CONTROL_DEPTH_8BPP (0<<0) ++# define AVIVO_D1GRPH_CONTROL_DEPTH_16BPP (1<<0) ++# define AVIVO_D1GRPH_CONTROL_DEPTH_32BPP (2<<0) ++# define AVIVO_D1GRPH_CONTROL_DEPTH_64BPP (3<<0) ++ ++# define AVIVO_D1GRPH_CONTROL_8BPP_INDEXED (0<<8) ++ ++# define AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555 (0<<8) ++# define AVIVO_D1GRPH_CONTROL_16BPP_RGB565 (1<<8) ++# define AVIVO_D1GRPH_CONTROL_16BPP_ARGB4444 (2<<8) ++# define AVIVO_D1GRPH_CONTROL_16BPP_AI88 (3<<8) ++# define AVIVO_D1GRPH_CONTROL_16BPP_MONO16 (4<<8) ++ ++# define AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888 (0<<8) ++# define AVIVO_D1GRPH_CONTROL_32BPP_ARGB2101010 (1<<8) ++# define AVIVO_D1GRPH_CONTROL_32BPP_DIGITAL (2<<8) ++# define AVIVO_D1GRPH_CONTROL_32BPP_8B_ARGB2101010 (3<<8) ++ ++ ++# define AVIVO_D1GRPH_CONTROL_64BPP_ARGB16161616 (0<<8) ++ ++# define AVIVO_D1GRPH_SWAP_RB (1<<16) ++# define AVIVO_D1GRPH_TILED (1<<20) ++# define AVIVO_D1GRPH_MACRO_ADDRESS_MODE (1<<21) ++ ++#define AVIVO_D1GRPH_LUT_SEL 0x6108 ++#define AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS 0x6110 ++#define AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS 0x6118 ++#define AVIVO_D1GRPH_PITCH 0x6120 ++#define AVIVO_D1GRPH_SURFACE_OFFSET_X 0x6124 ++#define AVIVO_D1GRPH_SURFACE_OFFSET_Y 0x6128 ++#define AVIVO_D1GRPH_X_START 0x612c ++#define AVIVO_D1GRPH_Y_START 0x6130 ++#define AVIVO_D1GRPH_X_END 0x6134 ++#define AVIVO_D1GRPH_Y_END 0x6138 ++#define AVIVO_D1GRPH_UPDATE 0x6144 ++# define AVIVO_D1GRPH_UPDATE_LOCK (1<<16) ++#define AVIVO_D1GRPH_FLIP_CONTROL 0x6148 ++ ++#define AVIVO_D1CUR_CONTROL 0x6400 ++# define AVIVO_D1CURSOR_EN (1<<0) ++# define AVIVO_D1CURSOR_MODE_SHIFT 8 ++# define AVIVO_D1CURSOR_MODE_MASK (0x3<<8) ++# define AVIVO_D1CURSOR_MODE_24BPP (0x2) ++#define AVIVO_D1CUR_SURFACE_ADDRESS 0x6408 ++#define AVIVO_D1CUR_SIZE 0x6410 ++#define AVIVO_D1CUR_POSITION 0x6414 ++#define AVIVO_D1CUR_HOT_SPOT 0x6418 ++ ++#define AVIVO_DC_LUT_RW_SELECT 0x6480 ++#define AVIVO_DC_LUT_RW_MODE 0x6484 ++#define AVIVO_DC_LUT_RW_INDEX 0x6488 ++#define AVIVO_DC_LUT_SEQ_COLOR 0x648c ++#define AVIVO_DC_LUT_PWL_DATA 0x6490 ++#define AVIVO_DC_LUT_30_COLOR 0x6494 ++#define AVIVO_DC_LUT_READ_PIPE_SELECT 0x6498 ++#define AVIVO_DC_LUT_WRITE_EN_MASK 0x649c ++#define AVIVO_DC_LUT_AUTOFILL 0x64a0 ++ ++#define AVIVO_DC_LUTA_CONTROL 0x64c0 ++#define AVIVO_DC_LUTA_BLACK_OFFSET_BLUE 0x64c4 ++#define AVIVO_DC_LUTA_BLACK_OFFSET_GREEN 0x64c8 ++#define AVIVO_DC_LUTA_BLACK_OFFSET_RED 0x64cc ++#define AVIVO_DC_LUTA_WHITE_OFFSET_BLUE 0x64d0 ++#define AVIVO_DC_LUTA_WHITE_OFFSET_GREEN 0x64d4 ++#define AVIVO_DC_LUTA_WHITE_OFFSET_RED 0x64d8 ++ ++ ++#define AVIVO_D1MODE_DESKTOP_HEIGHT 0x652C ++#define AVIVO_D1MODE_VIEWPORT_START 0x6580 ++#define AVIVO_D1MODE_VIEWPORT_SIZE 0x6584 ++#define AVIVO_D1MODE_EXT_OVERSCAN_LEFT_RIGHT 0x6588 ++#define AVIVO_D1MODE_EXT_OVERSCAN_TOP_BOTTOM 0x658c ++ ++#define AVIVO_D1SCL_SCALER_ENABLE 0x6590 ++#define AVIVO_D1SCL_UPDATE 0x65cc ++# define AVIVO_D1SCL_UPDATE_LOCK (1<<16) ++ ++/* second crtc */ ++#define AVIVO_D2CRTC_H_TOTAL 0x6800 ++#define AVIVO_D2CRTC_H_BLANK_START_END 0x6804 ++#define AVIVO_D2CRTC_H_SYNC_A 0x6808 ++#define AVIVO_D2CRTC_H_SYNC_A_CNTL 0x680c ++#define AVIVO_D2CRTC_H_SYNC_B 0x6810 ++#define AVIVO_D2CRTC_H_SYNC_B_CNTL 0x6814 ++ ++#define AVIVO_D2CRTC_V_TOTAL 0x6820 ++#define AVIVO_D2CRTC_V_BLANK_START_END 0x6824 ++#define AVIVO_D2CRTC_V_SYNC_A 0x6828 ++#define AVIVO_D2CRTC_V_SYNC_A_CNTL 0x682c ++#define AVIVO_D2CRTC_V_SYNC_B 0x6830 ++#define AVIVO_D2CRTC_V_SYNC_B_CNTL 0x6834 ++ ++#define AVIVO_D2CRTC_CONTROL 0x6880 ++#define AVIVO_D2CRTC_BLANK_CONTROL 0x6884 ++#define AVIVO_D2CRTC_INTERLACE_CONTROL 0x6888 ++#define AVIVO_D2CRTC_INTERLACE_STATUS 0x688c ++#define AVIVO_D2CRTC_STEREO_CONTROL 0x68c4 ++ ++#define AVIVO_D2GRPH_ENABLE 0x6900 ++#define AVIVO_D2GRPH_CONTROL 0x6904 ++#define AVIVO_D2GRPH_LUT_SEL 0x6908 ++#define AVIVO_D2GRPH_PRIMARY_SURFACE_ADDRESS 0x6910 ++#define AVIVO_D2GRPH_SECONDARY_SURFACE_ADDRESS 0x6918 ++#define AVIVO_D2GRPH_PITCH 0x6920 ++#define AVIVO_D2GRPH_SURFACE_OFFSET_X 0x6924 ++#define AVIVO_D2GRPH_SURFACE_OFFSET_Y 0x6928 ++#define AVIVO_D2GRPH_X_START 0x692c ++#define AVIVO_D2GRPH_Y_START 0x6930 ++#define AVIVO_D2GRPH_X_END 0x6934 ++#define AVIVO_D2GRPH_Y_END 0x6938 ++#define AVIVO_D2GRPH_UPDATE 0x6944 ++#define AVIVO_D2GRPH_FLIP_CONTROL 0x6948 ++ ++#define AVIVO_D2CUR_CONTROL 0x6c00 ++#define AVIVO_D2CUR_SURFACE_ADDRESS 0x6c08 ++#define AVIVO_D2CUR_SIZE 0x6c10 ++#define AVIVO_D2CUR_POSITION 0x6c14 ++ ++#define AVIVO_D2MODE_VIEWPORT_START 0x6d80 ++#define AVIVO_D2MODE_VIEWPORT_SIZE 0x6d84 ++#define AVIVO_D2MODE_EXT_OVERSCAN_LEFT_RIGHT 0x6d88 ++#define AVIVO_D2MODE_EXT_OVERSCAN_TOP_BOTTOM 0x6d8c ++ ++#define AVIVO_D2SCL_SCALER_ENABLE 0x6d90 ++ ++#define AVIVO_DACA_ENABLE 0x7800 ++# define AVIVO_DAC_ENABLE (1 << 0) ++#define AVIVO_DACA_SOURCE_SELECT 0x7804 ++# define AVIVO_DAC_SOURCE_CRTC1 (0 << 0) ++# define AVIVO_DAC_SOURCE_CRTC2 (1 << 0) ++# define AVIVO_DAC_SOURCE_TV (2 << 0) ++ ++#define AVIVO_DACA_FORCE_OUTPUT_CNTL 0x783c ++# define AVIVO_DACA_FORCE_OUTPUT_CNTL_FORCE_DATA_EN (1 << 0) ++# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_SHIFT (8) ++# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_BLUE (1 << 0) ++# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_GREEN (1 << 1) ++# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_RED (1 << 2) ++# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_ON_BLANKB_ONLY (1 << 24) ++#define AVIVO_DACA_POWERDOWN 0x7850 ++# define AVIVO_DACA_POWERDOWN_POWERDOWN (1 << 0) ++# define AVIVO_DACA_POWERDOWN_BLUE (1 << 8) ++# define AVIVO_DACA_POWERDOWN_GREEN (1 << 16) ++# define AVIVO_DACA_POWERDOWN_RED (1 << 24) ++ ++#define AVIVO_DACB_ENABLE 0x7a00 ++#define AVIVO_DACB_SOURCE_SELECT 0x7a04 ++#define AVIVO_DACB_FORCE_OUTPUT_CNTL 0x7a3c ++# define AVIVO_DACB_FORCE_OUTPUT_CNTL_FORCE_DATA_EN (1 << 0) ++# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_SHIFT (8) ++# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_BLUE (1 << 0) ++# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_GREEN (1 << 1) ++# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_RED (1 << 2) ++# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_ON_BLANKB_ONLY (1 << 24) ++#define AVIVO_DACB_POWERDOWN 0x7a50 ++# define AVIVO_DACB_POWERDOWN_POWERDOWN (1 << 0) ++# define AVIVO_DACB_POWERDOWN_BLUE (1 << 8) ++# define AVIVO_DACB_POWERDOWN_GREEN (1 << 16) ++# define AVIVO_DACB_POWERDOWN_RED ++ ++#define AVIVO_TMDSA_CNTL 0x7880 ++# define AVIVO_TMDSA_CNTL_ENABLE (1 << 0) ++# define AVIVO_TMDSA_CNTL_HPD_MASK (1 << 4) ++# define AVIVO_TMDSA_CNTL_HPD_SELECT (1 << 8) ++# define AVIVO_TMDSA_CNTL_SYNC_PHASE (1 << 12) ++# define AVIVO_TMDSA_CNTL_PIXEL_ENCODING (1 << 16) ++# define AVIVO_TMDSA_CNTL_DUAL_LINK_ENABLE (1 << 24) ++# define AVIVO_TMDSA_CNTL_SWAP (1 << 28) ++#define AVIVO_TMDSA_SOURCE_SELECT 0x7884 ++/* 78a8 appears to be some kind of (reasonably tolerant) clock? ++ * 78d0 definitely hits the transmitter, definitely clock. */ ++/* MYSTERY1 This appears to control dithering? */ ++#define AVIVO_TMDSA_BIT_DEPTH_CONTROL 0x7894 ++# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN (1 << 0) ++# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH (1 << 4) ++# define AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN (1 << 8) ++# define AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH (1 << 12) ++# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_EN (1 << 16) ++# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH (1 << 20) ++# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL (1 << 24) ++# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_RESET (1 << 26) ++#define AVIVO_TMDSA_DCBALANCER_CONTROL 0x78d0 ++# define AVIVO_TMDSA_DCBALANCER_CONTROL_EN (1 << 0) ++# define AVIVO_TMDSA_DCBALANCER_CONTROL_TEST_EN (1 << 8) ++# define AVIVO_TMDSA_DCBALANCER_CONTROL_TEST_IN_SHIFT (16) ++# define AVIVO_TMDSA_DCBALANCER_CONTROL_FORCE (1 << 24) ++#define AVIVO_TMDSA_DATA_SYNCHRONIZATION 0x78d8 ++# define AVIVO_TMDSA_DATA_SYNCHRONIZATION_DSYNSEL (1 << 0) ++# define AVIVO_TMDSA_DATA_SYNCHRONIZATION_PFREQCHG (1 << 8) ++#define AVIVO_TMDSA_CLOCK_ENABLE 0x7900 ++#define AVIVO_TMDSA_TRANSMITTER_ENABLE 0x7904 ++# define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX0_ENABLE (1 << 0) ++# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKC0EN (1 << 1) ++# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD00EN (1 << 2) ++# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD01EN (1 << 3) ++# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD02EN (1 << 4) ++# define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX1_ENABLE (1 << 8) ++# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD10EN (1 << 10) ++# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD11EN (1 << 11) ++# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD12EN (1 << 12) ++# define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX_ENABLE_HPD_MASK (1 << 16) ++# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK (1 << 17) ++# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK (1 << 18) ++ ++#define AVIVO_TMDSA_TRANSMITTER_CONTROL 0x7910 ++# define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_ENABLE (1 << 0) ++# define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_RESET (1 << 1) ++# define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_HPD_MASK_SHIFT (2) ++# define AVIVO_TMDSA_TRANSMITTER_CONTROL_IDSCKSEL (1 << 4) ++# define AVIVO_TMDSA_TRANSMITTER_CONTROL_BGSLEEP (1 << 5) ++# define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN (1 << 6) ++# define AVIVO_TMDSA_TRANSMITTER_CONTROL_TMCLK (1 << 8) ++# define AVIVO_TMDSA_TRANSMITTER_CONTROL_TMCLK_FROM_PADS (1 << 13) ++# define AVIVO_TMDSA_TRANSMITTER_CONTROL_TDCLK (1 << 14) ++# define AVIVO_TMDSA_TRANSMITTER_CONTROL_TDCLK_FROM_PADS (1 << 15) ++# define AVIVO_TMDSA_TRANSMITTER_CONTROL_CLK_PATTERN_SHIFT (16) ++# define AVIVO_TMDSA_TRANSMITTER_CONTROL_BYPASS_PLL (1 << 28) ++# define AVIVO_TMDSA_TRANSMITTER_CONTROL_USE_CLK_DATA (1 << 29) ++# define AVIVO_TMDSA_TRANSMITTER_CONTROL_INPUT_TEST_CLK_SEL (1 << 31) ++ ++#define AVIVO_LVTMA_CNTL 0x7a80 ++# define AVIVO_LVTMA_CNTL_ENABLE (1 << 0) ++# define AVIVO_LVTMA_CNTL_HPD_MASK (1 << 4) ++# define AVIVO_LVTMA_CNTL_HPD_SELECT (1 << 8) ++# define AVIVO_LVTMA_CNTL_SYNC_PHASE (1 << 12) ++# define AVIVO_LVTMA_CNTL_PIXEL_ENCODING (1 << 16) ++# define AVIVO_LVTMA_CNTL_DUAL_LINK_ENABLE (1 << 24) ++# define AVIVO_LVTMA_CNTL_SWAP (1 << 28) ++#define AVIVO_LVTMA_SOURCE_SELECT 0x7a84 ++#define AVIVO_LVTMA_COLOR_FORMAT 0x7a88 ++#define AVIVO_LVTMA_BIT_DEPTH_CONTROL 0x7a94 ++# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN (1 << 0) ++# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH (1 << 4) ++# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN (1 << 8) ++# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH (1 << 12) ++# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_EN (1 << 16) ++# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH (1 << 20) ++# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL (1 << 24) ++# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_RESET (1 << 26) ++ ++ ++ ++#define AVIVO_LVTMA_DCBALANCER_CONTROL 0x7ad0 ++# define AVIVO_LVTMA_DCBALANCER_CONTROL_EN (1 << 0) ++# define AVIVO_LVTMA_DCBALANCER_CONTROL_TEST_EN (1 << 8) ++# define AVIVO_LVTMA_DCBALANCER_CONTROL_TEST_IN_SHIFT (16) ++# define AVIVO_LVTMA_DCBALANCER_CONTROL_FORCE (1 << 24) ++ ++#define AVIVO_LVTMA_DATA_SYNCHRONIZATION 0x78d8 ++# define AVIVO_LVTMA_DATA_SYNCHRONIZATION_DSYNSEL (1 << 0) ++# define AVIVO_LVTMA_DATA_SYNCHRONIZATION_PFREQCHG (1 << 8) ++#define R500_LVTMA_CLOCK_ENABLE 0x7b00 ++#define R600_LVTMA_CLOCK_ENABLE 0x7b04 ++ ++#define R500_LVTMA_TRANSMITTER_ENABLE 0x7b04 ++#define R600_LVTMA_TRANSMITTER_ENABLE 0x7b08 ++# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKC0EN (1 << 1) ++# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD00EN (1 << 2) ++# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD01EN (1 << 3) ++# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD02EN (1 << 4) ++# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD03EN (1 << 5) ++# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKC1EN (1 << 9) ++# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD10EN (1 << 10) ++# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD11EN (1 << 11) ++# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD12EN (1 << 12) ++# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK (1 << 17) ++# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK (1 << 18) ++ ++#define R500_LVTMA_TRANSMITTER_CONTROL 0x7b10 ++#define R600_LVTMA_TRANSMITTER_CONTROL 0x7b14 ++# define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_ENABLE (1 << 0) ++# define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_RESET (1 << 1) ++# define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_HPD_MASK_SHIFT (2) ++# define AVIVO_LVTMA_TRANSMITTER_CONTROL_IDSCKSEL (1 << 4) ++# define AVIVO_LVTMA_TRANSMITTER_CONTROL_BGSLEEP (1 << 5) ++# define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN (1 << 6) ++# define AVIVO_LVTMA_TRANSMITTER_CONTROL_TMCLK (1 << 8) ++# define AVIVO_LVTMA_TRANSMITTER_CONTROL_TMCLK_FROM_PADS (1 << 13) ++# define AVIVO_LVTMA_TRANSMITTER_CONTROL_TDCLK (1 << 14) ++# define AVIVO_LVTMA_TRANSMITTER_CONTROL_TDCLK_FROM_PADS (1 << 15) ++# define AVIVO_LVTMA_TRANSMITTER_CONTROL_CLK_PATTERN_SHIFT (16) ++# define AVIVO_LVTMA_TRANSMITTER_CONTROL_BYPASS_PLL (1 << 28) ++# define AVIVO_LVTMA_TRANSMITTER_CONTROL_USE_CLK_DATA (1 << 29) ++# define AVIVO_LVTMA_TRANSMITTER_CONTROL_INPUT_TEST_CLK_SEL (1 << 31) ++ ++#define R500_LVTMA_PWRSEQ_CNTL 0x7af0 ++#define R600_LVTMA_PWRSEQ_CNTL 0x7af4 ++# define AVIVO_LVTMA_PWRSEQ_EN (1 << 0) ++# define AVIVO_LVTMA_PWRSEQ_PLL_ENABLE_MASK (1 << 2) ++# define AVIVO_LVTMA_PWRSEQ_PLL_RESET_MASK (1 << 3) ++# define AVIVO_LVTMA_PWRSEQ_TARGET_STATE (1 << 4) ++# define AVIVO_LVTMA_SYNCEN (1 << 8) ++# define AVIVO_LVTMA_SYNCEN_OVRD (1 << 9) ++# define AVIVO_LVTMA_SYNCEN_POL (1 << 10) ++# define AVIVO_LVTMA_DIGON (1 << 16) ++# define AVIVO_LVTMA_DIGON_OVRD (1 << 17) ++# define AVIVO_LVTMA_DIGON_POL (1 << 18) ++# define AVIVO_LVTMA_BLON (1 << 24) ++# define AVIVO_LVTMA_BLON_OVRD (1 << 25) ++# define AVIVO_LVTMA_BLON_POL (1 << 26) ++ ++#define R500_LVTMA_PWRSEQ_STATE 0x7af4 ++#define R600_LVTMA_PWRSEQ_STATE 0x7af8 ++# define AVIVO_LVTMA_PWRSEQ_STATE_TARGET_STATE_R (1 << 0) ++# define AVIVO_LVTMA_PWRSEQ_STATE_DIGON (1 << 1) ++# define AVIVO_LVTMA_PWRSEQ_STATE_SYNCEN (1 << 2) ++# define AVIVO_LVTMA_PWRSEQ_STATE_BLON (1 << 3) ++# define AVIVO_LVTMA_PWRSEQ_STATE_DONE (1 << 4) ++# define AVIVO_LVTMA_PWRSEQ_STATE_STATUS_SHIFT (8) ++ ++#define AVIVO_LVDS_BACKLIGHT_CNTL 0x7af8 ++# define AVIVO_LVDS_BACKLIGHT_CNTL_EN (1 << 0) ++# define AVIVO_LVDS_BACKLIGHT_LEVEL_MASK 0x0000ff00 ++# define AVIVO_LVDS_BACKLIGHT_LEVEL_SHIFT 8 ++ ++#define AVIVO_GPIO_0 0x7e30 ++#define AVIVO_GPIO_1 0x7e40 ++#define AVIVO_GPIO_2 0x7e50 ++#define AVIVO_GPIO_3 0x7e60 ++ ++#define AVIVO_DC_GPIO_HPD_Y 0x7e9c ++ ++#define AVIVO_I2C_STATUS 0x7d30 ++# define AVIVO_I2C_STATUS_DONE (1 << 0) ++# define AVIVO_I2C_STATUS_NACK (1 << 1) ++# define AVIVO_I2C_STATUS_HALT (1 << 2) ++# define AVIVO_I2C_STATUS_GO (1 << 3) ++# define AVIVO_I2C_STATUS_MASK 0x7 ++/* If radeon_mm_i2c is to be believed, this is HALT, NACK, and maybe ++ * DONE? */ ++# define AVIVO_I2C_STATUS_CMD_RESET 0x7 ++# define AVIVO_I2C_STATUS_CMD_WAIT (1 << 3) ++#define AVIVO_I2C_STOP 0x7d34 ++#define AVIVO_I2C_START_CNTL 0x7d38 ++# define AVIVO_I2C_START (1 << 8) ++# define AVIVO_I2C_CONNECTOR0 (0 << 16) ++# define AVIVO_I2C_CONNECTOR1 (1 << 16) ++#define R520_I2C_START (1<<0) ++#define R520_I2C_STOP (1<<1) ++#define R520_I2C_RX (1<<2) ++#define R520_I2C_EN (1<<8) ++#define R520_I2C_DDC1 (0<<16) ++#define R520_I2C_DDC2 (1<<16) ++#define R520_I2C_DDC3 (2<<16) ++#define R520_I2C_DDC_MASK (3<<16) ++#define AVIVO_I2C_CONTROL2 0x7d3c ++# define AVIVO_I2C_7D3C_SIZE_SHIFT 8 ++# define AVIVO_I2C_7D3C_SIZE_MASK (0xf << 8) ++#define AVIVO_I2C_CONTROL3 0x7d40 ++/* Reading is done 4 bytes at a time: read the bottom 8 bits from ++ * 7d44, four times in a row. ++ * Writing is a little more complex. First write DATA with ++ * 0xnnnnnnzz, then 0xnnnnnnyy, where nnnnnn is some non-deterministic ++ * magic number, zz is, I think, the slave address, and yy is the byte ++ * you want to write. */ ++#define AVIVO_I2C_DATA 0x7d44 ++#define R520_I2C_ADDR_COUNT_MASK (0x7) ++#define R520_I2C_DATA_COUNT_SHIFT (8) ++#define R520_I2C_DATA_COUNT_MASK (0xF00) ++#define AVIVO_I2C_CNTL 0x7d50 ++# define AVIVO_I2C_EN (1 << 0) ++# define AVIVO_I2C_RESET (1 << 8) ++ ++#define R600_MC_VM_FB_LOCATION 0x2180 ++#define R600_MC_VM_AGP_TOP 0x2184 ++#define R600_MC_VM_AGP_BOT 0x2188 ++#define R600_MC_VM_AGP_BASE 0x218c ++#define R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190 ++#define R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194 ++#define R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198 ++ ++#define R600_BUS_CNTL 0x5420 ++#define R600_CONFIG_CNTL 0x5424 ++#define R600_CONFIG_MEMSIZE 0x5428 ++#define R600_CONFIG_F0_BASE 0x542C ++#define R600_CONFIG_APER_SIZE 0x5430 + #endif +diff --git a/src/radeon_render.c b/src/radeon_render.c +index 490dec1..a80d136 100644 +--- a/src/radeon_render.c ++++ b/src/radeon_render.c +@@ -317,7 +317,7 @@ static Bool RADEONSetupRenderByteswap(ScrnInfoPtr pScrn, int tex_bytepp) + { + RADEONInfoPtr info = RADEONPTR(pScrn); + unsigned char *RADEONMMIO = info->MMIO; +- CARD32 swapper = info->ModeReg.surface_cntl; ++ CARD32 swapper = info->ModeReg->surface_cntl; + + swapper &= ~(RADEON_NONSURF_AP0_SWP_16BPP | RADEON_NONSURF_AP1_SWP_16BPP | + RADEON_NONSURF_AP0_SWP_32BPP | RADEON_NONSURF_AP1_SWP_32BPP); +@@ -345,7 +345,7 @@ static void RADEONRestoreByteswap(RADEONInfoPtr info) + { + unsigned char *RADEONMMIO = info->MMIO; + +- OUTREG(RADEON_SURFACE_CNTL, info->ModeReg.surface_cntl); ++ OUTREG(RADEON_SURFACE_CNTL, info->ModeReg->surface_cntl); + } + #endif /* X_BYTE_ORDER == X_BIG_ENDIAN */ + +diff --git a/src/radeon_tv.c b/src/radeon_tv.c +index 2a8873c..5e9a9c8 100644 +--- a/src/radeon_tv.c ++++ b/src/radeon_tv.c +@@ -540,7 +540,7 @@ void RADEONInitTVRegisters(xf86OutputPtr output, RADEONSavePtr save, + save->dac_cntl &= ~RADEON_DAC_TVO_EN; + + if (IS_R300_VARIANT) +- save->gpiopad_a = info->SavedReg.gpiopad_a & ~1; ++ save->gpiopad_a = info->SavedReg->gpiopad_a & ~1; + + if (IsPrimary) { + save->disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK; +@@ -571,7 +571,7 @@ void RADEONUpdateHVPosition(xf86OutputPtr output, DisplayModePtr mode) + RADEONInfoPtr info = RADEONPTR(pScrn); + unsigned char *RADEONMMIO = info->MMIO; + Bool reloadTable; +- RADEONSavePtr restore = &info->ModeReg; ++ RADEONSavePtr restore = info->ModeReg; + + reloadTable = RADEONInitTVRestarts(output, restore, mode); + +diff --git a/src/radeon_tv.h b/src/radeon_tv.h +index 5c8c8c9..c4b7838 100644 +--- a/src/radeon_tv.h ++++ b/src/radeon_tv.h +@@ -3,11 +3,6 @@ + * Federico Ulivi + */ + +-/* +- * Maximum length of horizontal/vertical code timing tables for state storage +- */ +-#define MAX_H_CODE_TIMING_LEN 32 +-#define MAX_V_CODE_TIMING_LEN 32 + + /* + * Limits of h/v positions (hPos & vPos) +diff --git a/src/radeon_video.c b/src/radeon_video.c +index 3f0209e..a84662e 100644 +--- a/src/radeon_video.c ++++ b/src/radeon_video.c +@@ -1430,7 +1430,7 @@ RADEONAllocAdaptor(ScrnInfoPtr pScrn) + * 0 for PIXCLK < 175Mhz, and 1 (divide by 2) + * for higher clocks, sure makes life nicer + */ +- dot_clock = info->ModeReg.dot_clock_freq; ++ dot_clock = info->ModeReg->dot_clock_freq; + + if (dot_clock < 17500) + info->ecp_div = 0; +@@ -2156,7 +2156,7 @@ RADEONCopyData( + { + #if X_BYTE_ORDER == X_BIG_ENDIAN + unsigned char *RADEONMMIO = info->MMIO; +- unsigned int swapper = info->ModeReg.surface_cntl & ++ unsigned int swapper = info->ModeReg->surface_cntl & + ~(RADEON_NONSURF_AP0_SWP_32BPP | RADEON_NONSURF_AP1_SWP_32BPP | + RADEON_NONSURF_AP0_SWP_16BPP | RADEON_NONSURF_AP1_SWP_16BPP); + +@@ -2182,7 +2182,7 @@ RADEONCopyData( + + #if X_BYTE_ORDER == X_BIG_ENDIAN + /* restore byte swapping */ +- OUTREG(RADEON_SURFACE_CNTL, info->ModeReg.surface_cntl); ++ OUTREG(RADEON_SURFACE_CNTL, info->ModeReg->surface_cntl); + #endif + } + } +@@ -2238,7 +2238,7 @@ RADEONCopyRGB24Data( + { + #if X_BYTE_ORDER == X_BIG_ENDIAN + unsigned char *RADEONMMIO = info->MMIO; +- OUTREG(RADEON_SURFACE_CNTL, (info->ModeReg.surface_cntl ++ OUTREG(RADEON_SURFACE_CNTL, (info->ModeReg->surface_cntl + | RADEON_NONSURF_AP0_SWP_32BPP) + & ~RADEON_NONSURF_AP0_SWP_16BPP); + #endif +@@ -2254,7 +2254,7 @@ RADEONCopyRGB24Data( + + #if X_BYTE_ORDER == X_BIG_ENDIAN + /* restore byte swapping */ +- OUTREG(RADEON_SURFACE_CNTL, info->ModeReg.surface_cntl); ++ OUTREG(RADEON_SURFACE_CNTL, info->ModeReg->surface_cntl); + #endif + } + } +@@ -2333,7 +2333,7 @@ RADEONCopyMungedData( + + #if X_BYTE_ORDER == X_BIG_ENDIAN + unsigned char *RADEONMMIO = info->MMIO; +- OUTREG(RADEON_SURFACE_CNTL, (info->ModeReg.surface_cntl ++ OUTREG(RADEON_SURFACE_CNTL, (info->ModeReg->surface_cntl + | RADEON_NONSURF_AP0_SWP_32BPP) + & ~RADEON_NONSURF_AP0_SWP_16BPP); + #endif +@@ -2371,7 +2371,7 @@ RADEONCopyMungedData( + } + #if X_BYTE_ORDER == X_BIG_ENDIAN + /* restore byte swapping */ +- OUTREG(RADEON_SURFACE_CNTL, info->ModeReg.surface_cntl); ++ OUTREG(RADEON_SURFACE_CNTL, info->ModeReg->surface_cntl); + #endif + } + } +@@ -2552,9 +2552,9 @@ RADEONDisplayVideo( + + /* Figure out which head we are on for dot clock */ + if (radeon_crtc->crtc_id == 1) +- dot_clock = info->ModeReg.dot_clock_freq_2; ++ dot_clock = info->ModeReg->dot_clock_freq_2; + else +- dot_clock = info->ModeReg.dot_clock_freq; ++ dot_clock = info->ModeReg->dot_clock_freq; + + if (dot_clock < 17500) + ecp_div = 0; diff --git a/radeon-git-upstream-fixes.patch b/radeon-git-upstream-fixes.patch new file mode 100644 index 0000000..3b1ada5 --- /dev/null +++ b/radeon-git-upstream-fixes.patch @@ -0,0 +1,4789 @@ +commit ce4fa1cedec0cf56b9979dfaa12a8d3a7c643df4 +Author: Arkadiusz Miskiewicz +Date: Tue Dec 18 15:34:14 2007 -0500 + + RADEON: fix fd leak in lid detect code + +commit 20568f66f9a9a60a33bd9a69ccc14a891c656836 +Author: Arkadiusz Miskiewicz +Date: Tue Dec 18 15:32:10 2007 -0500 + + RADEON: more cleanups and warning fixes + +commit 1496194200adbcb044ec3977367a0908262e389c +Author: Arkadiusz Miskiewicz +Date: Tue Dec 18 15:29:53 2007 -0500 + + RADEON: driver cleanups, warning fixes + +commit 44d07c4ccce9acb5bd21a17acb082e91f7225764 +Author: Alex Deucher +Date: Mon Dec 17 18:56:12 2007 -0500 + + RADEON: typo from last commit + +commit 4da3782239921eb377216d4de4a9cc5bb55e0e8a +Author: Alex Deucher +Date: Mon Dec 17 18:51:31 2007 -0500 + + RADEON: add output enable masks + + add output enable masks for outputs that drive + more than one connector. Make sure we don't turn off + an output that's driving another connector. + +commit 5c5d2d19b2b032a06dd333b4ecc029aac342fb93 +Author: Alex Deucher +Date: Mon Dec 17 18:15:55 2007 -0500 + + RADEON: whitespace clean-ups + +commit 9f1d8220315c8894a17f2cc328025dc682b0c6e0 +Author: Alex Deucher +Date: Mon Dec 17 18:04:05 2007 -0500 + + RADEON: more PLL fixes + + - reduce the calculation accuracy + - certain LVDS panels seem to only like certain ref_divs + - add pll flags to handle special cases + - adjust the pll limits on legacy cards + +commit 4747c1f3cd4167b6a51d4864a297719ea48b9346 +Author: Alex Deucher +Date: Sun Dec 16 14:07:29 2007 -0500 + + RADEON: Make sure LVDS_EN bit is set when enabling LVDS + +commit b653e5a628bfa4dfb168e96f93f41eb910f409fb +Author: Michel Dänzer +Date: Sat Dec 15 00:50:10 2007 +0100 + + radeon: Default to 1x again with non-v3 AGP cards. + + Seems more reliable in general than what was set up by firmware - fingers + crossed... + +commit 6229825fa5d6715569098afbb21a40f7a2e7e6be +Author: Michel Dänzer +Date: Sat Dec 15 00:48:26 2007 +0100 + + radeon: Warning fixes. + + The lid detection code probably wouldn't work on other non-x86 platforms + though... + +commit 818ccf0fd4b5879171c5f20526d5a58638f8fde5 +Author: Fredrik Höglund +Date: Fri Dec 14 23:56:12 2007 +0100 + + RADEON: Fix the vertex coordinates for transformed pictures + + This partially fixes transformed pictures on R100/R200 based + cards. The texture still doesn't appear to be clamped correctly, + but since that doesn't matter for rotations at perpendicular + angles, I'm committing this now so randr rotation and reflection + will work properly. + +commit 3cfbcf4cafbdfdb33411d16e51fb1f77cd0f93dd +Author: Alex Deucher +Date: Fri Dec 14 17:11:00 2007 -0500 + + RADEON: Fix PLL set up on certain notebooks + + Some LVDS panels require specific PLL dividers as + specified in the bios tables. Make sure to use them + if the output is LVDS. + +commit a84d446fd301d456bcea8f7abdc52e5a30776412 +Author: Alex Deucher +Date: Fri Dec 14 02:17:14 2007 -0500 + + RADEON: select fb_div0 for LVDS on RV410 (x700) mobility + + Fixes bug 8038 + I wonder if desktop RV410 need a similar fix. + If your x700 laptop panel has problems after this let me know. + +commit 6ccf5b33d27218ae1c45ab93c122438ed536d8ba +Author: Alex Deucher +Date: Wed Dec 12 20:12:06 2007 -0500 + + RADEON: only enable vblanks if we want them + + should fix bug 13610 + +commit 1668f2056f56370f1b5681c13f1e14904e301216 +Author: Alex Deucher +Date: Wed Dec 12 19:39:08 2007 -0500 + + RADEON: use /proc/acpi to determine lid status + + Linux only + +commit 33a39947f7f79533cd90007a17d57b20126642c6 +Author: Alex Deucher +Date: Wed Dec 12 18:50:18 2007 -0500 + + RADEON: fix cursors when using rotation + + allocate separate cursor buffers for each crtc + +commit 9e5efdecd12092031a4aebce58747cb4a6f48f28 +Author: Arkadiusz Miskiewicz +Date: Tue Dec 11 23:53:03 2007 -0500 + + sparse fixes and cleanups from arekm + +commit f3d2ec3a5ae61215c792018320158750e7aa937c +Author: Alex Deucher +Date: Tue Dec 11 11:57:27 2007 -0500 + + RADEON: rewrite PLL computation + + Algorithm adapted from BeOS radeon driver with some tweaks by me. + Actually calulate and use the reference divider rather than using the bios default. + Also, always calculate the PLL, rather than falling back to bios dividers. + This should fix bugs 12913, 13590, 13533, possibly others. + +commit 9b125312ab6edc585e4f5931a6a6de81e13b6acc +Author: Alex Deucher +Date: Mon Dec 10 13:53:15 2007 -0500 + + RADEON: only update crtc values when RMX is active + +commit 3a161e1b5d80361e318ced8da5c19e797749d693 +Author: Alex Deucher +Date: Mon Dec 10 00:57:26 2007 -0500 + + RADEON: bios PLL cleanup + +commit 5896ca4097d439f59f90f397939132c061c3c364 +Author: LisaWu +Date: Fri Dec 7 09:45:05 2007 +0100 + + radeon: Use %u instead of %d for unsigned value. + +commit df44f8380268c27d3978c4e91d736f093322b8b8 +Author: Michel Dänzer +Date: Fri Dec 7 09:41:47 2007 +0100 + + radeon: Use gettimeofday instead of xf86getsecs. + +commit 64ab1cdf343a9a69e7e9e64f0bba77c54a94e9d0 +Author: James Cloos +Date: Thu Dec 6 15:51:12 2007 -0500 + + Add missing PHONY line for automatic ChangeLog generation + +commit 21ed435398e4a398dd8a0a5d7c1d4cc45e916332 +Author: Alex Deucher +Date: Tue Dec 4 17:08:58 2007 -0500 + + RADEON: add MacModel imac-g5-isight for iMac G5 iSight + + Thanks to Étienne Bersac for helping to figure this out. + +commit 54bfd522405d9fdfb69d3a59e111ac3d63483dbb +Author: Étienne Bersac +Date: Tue Dec 4 14:22:42 2007 -0500 + + RADEON: fix typo + +commit 5022d006cfc06ca0395981526b2c2c94c6878567 +Author: Michel Dänzer +Date: Sun Dec 2 17:27:33 2007 +0100 + + radeon: Further XVideo fixes. + + * Make sure pitch constraints are always met for DMA upload blits. + * RGB24 is not affected by endianness. + +commit 6ed55b70b23dfdc7b41103ea59c1df2bda5e41e6 +Author: Kusanagi Kouichi +Date: Sun Dec 2 17:18:46 2007 +0100 + + radeon: Fix crash with XVideo 24bit RGB images. + + See https://bugs.freedesktop.org/show_bug.cgi?id=13274 . + +commit a697b590899bb7704ec4d7ae9a9c3cbbfcaef382 +Author: Michel Dänzer +Date: Sun Dec 2 17:11:20 2007 +0100 + + Fix build against xserver master. + + (DE)ALLOCATE_LOCAL are gone. + +commit 00b4480aa2c5d7f751e34fc964f431b90b14c8d2 +Author: Alex Deucher +Date: Sat Dec 1 14:18:40 2007 -0500 + + RADEON: add options for force TV out as detected and to set TV standard + + Also fix a typo in internal tv-out parsing + +commit 0175b79987ef4d7b0ce8238c3bdde989e504516a +Author: Alex Deucher +Date: Fri Nov 30 15:37:42 2007 -0500 + + RADEON: rework MacModel option + + this brings in some previous research from Michel Dänzer, + Sjoerd Simons, and myself. Hopefully, the driver will pick + the correct MacModel in more cases. This also changes the + default connector table for desktop Macs to dual DVI rather + than DVI+VGA as that seems to be the case more often than not. + External TMDS chips are handled separately now as well. + Eventually we should add an option to allow the user to specify + what external TMDS chip they need, but we don't have enough info + yet, so we'll rely on OF to init the external chip in most cases + for now. + +commit 9840a0fd4fc8c980533fcd4a02c55cd0d5634b6d +Author: Alex Deucher +Date: Thu Nov 29 13:27:37 2007 -0500 + + RADEON: add MacModel "mini-internal" for minis with internal TMDS + + Some macs (minis and powerbooks) use internal tmds, others use external tmds + and not just for dual-link TMDS, it shows up with single-link as well. + Unforunately, there doesn't seem to be any good way to figure it out. + +commit 6f080d00e6f4f84d5e0d6b4eff302bf42c230e81 +Author: Arkadiusz Miskiewicz +Date: Mon Nov 26 12:43:30 2007 -0500 + + RADEON: fix backlight control on some laptops + + It seems the bios scratch regs are involved in backlight control + on some laptops. This patch fixes the problematic laptops and doesn't + seem to break the previous bios lid and output control fixes. + +commit dcf22aed87366f4625fb5042cb84fecccd9ceece +Author: Alex Deucher +Date: Mon Nov 26 11:10:03 2007 -0500 + + RADEON: only return status unknown for XPRESS chips + + this seems to cause more issues than it attempted to fix + so limit it to XPRESS chips for now. + +commit 206e280f02324641b4fe5a1986e26adf0e021fd4 +Author: Alex Deucher +Date: Mon Nov 26 09:39:27 2007 -0500 + + RADEON: fix typo in man page + +commit 197a62704742a4a19736c2637ac92d1dc5ab34ed +Author: Adam Jackson +Date: Thu Nov 22 20:26:23 2007 +1000 + + radeon: fix openoffice/render bug on r100 chips + +commit 64010fc4eae8359c01e430f64252931242c91435 +Author: Dave Airlie +Date: Thu Nov 22 20:25:31 2007 +1000 + + Revert "Disable RENDER acceleration by default on some RV200 chips." + + This reverts commit 145da701bf4fb9c0ad9f95620b20914ae0126852. + + pull in fix from ajax next commit + +commit 145da701bf4fb9c0ad9f95620b20914ae0126852 +Author: Stefan Dirsch +Date: Thu Nov 22 08:38:09 2007 +0100 + + Disable RENDER acceleration by default on some RV200 chips. + + Novell Bug #341699: Render acceleration is known to be broken + on at least "Radeon 7500 QW" and "Radeon Mobility M7 LW". + +commit e810c3ae9908cd57e95b1b091cded87cbfc12fdc +Author: Roland Scheidegger +Date: Thu Nov 22 02:37:55 2007 +0100 + + really do not set up surface regs for depth buf on r100-class igps (bug #13080) + + fix the if condition testing for these chips... + +commit c8872603454e6a4ffed9fc7d9adc2c364a429608 +Author: Dave Airlie +Date: Tue Nov 20 22:33:39 2007 +1000 + + radeon: restructure pci ids to avoid effort later + + This uses a single file with all the pciids and parameters for radeon + family and setup in it. I don't run the perl script at build time to avoid + a perl dependency on build but adding pci ids should be done via the csv file + with openoffice or gnumeric if possible. + +commit 49055d8aff91ff12186feaf5343c8fd2f96bcba0 +Author: Alex Deucher +Date: Thu Nov 15 22:56:09 2007 -0500 + + RADEON: set proper defaults for tv dac BGADJ/DACADJ + + we should get these values from the bios tables, but for now use + some reasonable defaults. This should fix the washed out color + problems on bugs 1082 and 12844. + +commit 821acf38b716ab87c3d07263d6e4a139fe54803f +Author: Alex Deucher +Date: Thu Nov 15 22:28:42 2007 -0500 + + RADEON: Make sure we set the MT properly for connected status unknown + +commit a94123f33ec6584fbdfc4b9ecd543d1357de8814 +Author: Alex Deucher +Date: Thu Nov 15 22:19:54 2007 -0500 + + Revert "Portability fix from netbsd" + + This reverts commit c9264aa53bf1470ad9104d1e7c4a8ce13c49c270. + This breaks damage support. See bug 13244 + +commit e9d721c31372db045550f9562534b28f16121bb9 +Author: Roland Scheidegger +Date: Tue Nov 13 23:42:42 2007 +0100 + + ignore sometime bogus agp_mode bit from chip (bug #13190) + + bit is wrong on at least X700 cards with rialto pcie-agp bridge chip, + should be safe to use just the bit from the bridge hopefully to make + agp setup work on these cards and not adversely affect others. +diff --git a/Makefile.am b/Makefile.am +index 2ae4852..ea2e4a3 100644 +--- a/Makefile.am ++++ b/Makefile.am +@@ -33,6 +33,8 @@ endif + EXTRA_DIST = README.ati README.r128 README.ati.sgml README.r128.sgml ChangeLog + CLEANFILES = ChangeLog + ++.PHONY: ChangeLog ++ + ChangeLog: + (GIT_DIR=$(top_srcdir)/.git git-log > .changelog.tmp && mv .changelog.tmp ChangeLog; rm -f .changelog.tmp) || (touch ChangeLog; echo 'git directory not found: installing possibly empty changelog.' >&2) + +diff --git a/configure.ac b/configure.ac +index 450d951..1570e54 100644 +--- a/configure.ac ++++ b/configure.ac +@@ -58,7 +58,7 @@ AC_ARG_ENABLE(dri, AC_HELP_STRING([--disable-dri], + + AC_ARG_ENABLE(exa, + AC_HELP_STRING([--disable-exa], +- [Disable EXA support [[default enabled]]]), ++ [Disable EXA support [[default=enabled]]]), + [EXA="$enableval"], + [EXA=yes]) + +@@ -79,7 +79,7 @@ sdkdir=$(pkg-config --variable=sdkdir xorg-server) + # Checks for header files. + AC_HEADER_STDC + +-if test "x$DRI" = xauto; then ++if test "$DRI" != no; then + AC_CHECK_FILE([${sdkdir}/dri.h], + [have_dri_h="yes"], [have_dri_h="no"]) + AC_CHECK_FILE([${sdkdir}/sarea.h], +diff --git a/man/radeon.man b/man/radeon.man +index 5d31eb1..3c4df23 100644 +--- a/man/radeon.man ++++ b/man/radeon.man +@@ -383,14 +383,14 @@ case. This is only useful for LVDS panels (laptop internal panels). + The default is + .B on. + .TP +-.BI "Option \*TVDACLoadDetect\*q \*q" boolean \*q ++.BI "Option \*qTVDACLoadDetect\*q \*q" boolean \*q + Enable load detection on the TV DAC. The TV DAC is used to drive both + TV-OUT and analog monitors. Load detection is often unreliable in the + TV DAC so it is disabled by default. + The default is + .B off. + .TP +-.BI "Option \*DefaultTMDSPLL\*q \*q" boolean \*q ++.BI "Option \*qDefaultTMDSPLL\*q \*q" boolean \*q + Use the default driver provided TMDS PLL values rather than the ones + provided by the bios. This option has no effect on Mac cards. Enable + this option if you are having problems with a DVI monitor using the +@@ -414,20 +414,59 @@ The default is + .TP + .BI "Option \*qMacModel\*q \*q" string \*q + .br +-Used to specify Mac models for connector tables and quirks. Only valid +- on PowerPC. ++Used to specify Mac models for connector tables and quirks. If you have ++a powerbook or mini with DVI that does not work properly, try the alternate ++ options as Apple does not seem to provide a good way of knowing whether ++ they use internal or external TMDS for DVI. Only valid on PowerPC. + .br + ibook \-\- ibooks + .br +-powerbook-duallink \-\- Powerbooks with external DVI ++powerbook-external \-\- Powerbooks with external DVI + .br +-powerbook \-\- Powerbooks with integrated DVI ++powerbook-internal \-\- Powerbooks with integrated DVI + .br +-mini \-\- Mac Mini ++powerbook-vga \-\- Powerbooks with VGA rather than DVI ++.br ++powerbook-duallink \-\- powerbook-external alias ++.br ++powerbook \-\- powerbook-internal alias ++.br ++mini-external \-\- Mac Mini with external DVI ++.br ++mini-internal \-\- Mac Mini with integrated DVI ++.br ++mini \-\- mini-external alias ++.br ++imac-g5-isight \-\- iMac G5 iSight ++.br ++The default value is ++.B undefined. ++.TP ++.BI "Option \*qTVStandard\*q \*q" string \*q ++.br ++Used to specify the default TV standard if you want to use something other than ++the bios default. Valid options are: ++.br ++ntsc ++.br ++pal ++.br ++pal-m ++.br ++pal-60 ++.br ++ntsc-j ++.br ++scart-pal + .br + The default value is + .B undefined. + .TP ++.BI "Option \*qForceTVOut\*q \*q" boolean \*q ++Enable this option to force TV Out to always be detected as attached. ++The default is ++.B off ++.TP + + .SH SEE ALSO + __xservername__(__appmansuffix__), __xconfigfile__(__filemansuffix__), xorgconfig(__appmansuffix__), Xserver(__appmansuffix__), X(__miscmansuffix__) +diff --git a/src/Makefile.am b/src/Makefile.am +index ff1e225..5152577 100644 +--- a/src/Makefile.am ++++ b/src/Makefile.am +@@ -171,7 +171,6 @@ EXTRA_DIST = \ + r128_reg.h \ + r128_sarea.h \ + r128_version.h \ +- radeon_chipset.h \ + radeon_common.h \ + radeon_commonfuncs.c \ + radeon_dri.h \ +@@ -191,4 +190,10 @@ EXTRA_DIST = \ + theatre.h \ + theatre_reg.h \ + atipciids.h \ +- atipcirename.h ++ atipcirename.h \ ++ ati_pciids_gen.h \ ++ radeon_chipinfo_gen.h \ ++ radeon_chipset_gen.h \ ++ radeon_pci_chipset_gen.h \ ++ pcidb/ati_pciids.csv \ ++ pcidb/parse_pci_ids.pl +diff --git a/src/ati_pciids_gen.h b/src/ati_pciids_gen.h +new file mode 100644 +index 0000000..ad54f64 +--- /dev/null ++++ b/src/ati_pciids_gen.h +@@ -0,0 +1,219 @@ ++#define PCI_CHIP_RV380_3150 0x3150 ++#define PCI_CHIP_RV380_3152 0x3152 ++#define PCI_CHIP_RV380_3154 0x3154 ++#define PCI_CHIP_RV380_3E50 0x3E50 ++#define PCI_CHIP_RV380_3E54 0x3E54 ++#define PCI_CHIP_RS100_4136 0x4136 ++#define PCI_CHIP_RS200_4137 0x4137 ++#define PCI_CHIP_R300_AD 0x4144 ++#define PCI_CHIP_R300_AE 0x4145 ++#define PCI_CHIP_R300_AF 0x4146 ++#define PCI_CHIP_R300_AG 0x4147 ++#define PCI_CHIP_R350_AH 0x4148 ++#define PCI_CHIP_R350_AI 0x4149 ++#define PCI_CHIP_R350_AJ 0x414A ++#define PCI_CHIP_R350_AK 0x414B ++#define PCI_CHIP_RV350_AP 0x4150 ++#define PCI_CHIP_RV350_AQ 0x4151 ++#define PCI_CHIP_RV360_AR 0x4152 ++#define PCI_CHIP_RV350_AS 0x4153 ++#define PCI_CHIP_RV350_AT 0x4154 ++#define PCI_CHIP_RV350_4155 0x4155 ++#define PCI_CHIP_RV350_AV 0x4156 ++#define PCI_CHIP_MACH32 0x4158 ++#define PCI_CHIP_RS250_4237 0x4237 ++#define PCI_CHIP_R200_BB 0x4242 ++#define PCI_CHIP_R200_BC 0x4243 ++#define PCI_CHIP_RS100_4336 0x4336 ++#define PCI_CHIP_RS200_4337 0x4337 ++#define PCI_CHIP_MACH64CT 0x4354 ++#define PCI_CHIP_MACH64CX 0x4358 ++#define PCI_CHIP_RS250_4437 0x4437 ++#define PCI_CHIP_MACH64ET 0x4554 ++#define PCI_CHIP_MACH64GB 0x4742 ++#define PCI_CHIP_MACH64GD 0x4744 ++#define PCI_CHIP_MACH64GI 0x4749 ++#define PCI_CHIP_MACH64GL 0x474C ++#define PCI_CHIP_MACH64GM 0x474D ++#define PCI_CHIP_MACH64GN 0x474E ++#define PCI_CHIP_MACH64GO 0x474F ++#define PCI_CHIP_MACH64GP 0x4750 ++#define PCI_CHIP_MACH64GQ 0x4751 ++#define PCI_CHIP_MACH64GR 0x4752 ++#define PCI_CHIP_MACH64GS 0x4753 ++#define PCI_CHIP_MACH64GT 0x4754 ++#define PCI_CHIP_MACH64GU 0x4755 ++#define PCI_CHIP_MACH64GV 0x4756 ++#define PCI_CHIP_MACH64GW 0x4757 ++#define PCI_CHIP_MACH64GX 0x4758 ++#define PCI_CHIP_MACH64GY 0x4759 ++#define PCI_CHIP_MACH64GZ 0x475A ++#define PCI_CHIP_RV250_If 0x4966 ++#define PCI_CHIP_RV250_Ig 0x4967 ++#define PCI_CHIP_R420_JH 0x4A48 ++#define PCI_CHIP_R420_JI 0x4A49 ++#define PCI_CHIP_R420_JJ 0x4A4A ++#define PCI_CHIP_R420_JK 0x4A4B ++#define PCI_CHIP_R420_JL 0x4A4C ++#define PCI_CHIP_R420_JM 0x4A4D ++#define PCI_CHIP_R420_JN 0x4A4E ++#define PCI_CHIP_R420_4A4F 0x4A4F ++#define PCI_CHIP_R420_JP 0x4A50 ++#define PCI_CHIP_R481_4B49 0x4B49 ++#define PCI_CHIP_R481_4B4A 0x4B4A ++#define PCI_CHIP_R481_4B4B 0x4B4B ++#define PCI_CHIP_R481_4B4C 0x4B4C ++#define PCI_CHIP_MACH64LB 0x4C42 ++#define PCI_CHIP_MACH64LD 0x4C44 ++#define PCI_CHIP_RAGE128LE 0x4C45 ++#define PCI_CHIP_RAGE128LF 0x4C46 ++#define PCI_CHIP_MACH64LG 0x4C47 ++#define PCI_CHIP_MACH64LI 0x4C49 ++#define PCI_CHIP_MACH64LM 0x4C4D ++#define PCI_CHIP_MACH64LN 0x4C4E ++#define PCI_CHIP_MACH64LP 0x4C50 ++#define PCI_CHIP_MACH64LQ 0x4C51 ++#define PCI_CHIP_MACH64LR 0x4C52 ++#define PCI_CHIP_MACH64LS 0x4C53 ++#define PCI_CHIP_RADEON_LW 0x4C57 ++#define PCI_CHIP_RADEON_LX 0x4C58 ++#define PCI_CHIP_RADEON_LY 0x4C59 ++#define PCI_CHIP_RADEON_LZ 0x4C5A ++#define PCI_CHIP_RV250_Ld 0x4C64 ++#define PCI_CHIP_RV250_Lf 0x4C66 ++#define PCI_CHIP_RV250_Lg 0x4C67 ++#define PCI_CHIP_RAGE128MF 0x4D46 ++#define PCI_CHIP_RAGE128ML 0x4D4C ++#define PCI_CHIP_R300_ND 0x4E44 ++#define PCI_CHIP_R300_NE 0x4E45 ++#define PCI_CHIP_R300_NF 0x4E46 ++#define PCI_CHIP_R300_NG 0x4E47 ++#define PCI_CHIP_R350_NH 0x4E48 ++#define PCI_CHIP_R350_NI 0x4E49 ++#define PCI_CHIP_R360_NJ 0x4E4A ++#define PCI_CHIP_R350_NK 0x4E4B ++#define PCI_CHIP_RV350_NP 0x4E50 ++#define PCI_CHIP_RV350_NQ 0x4E51 ++#define PCI_CHIP_RV350_NR 0x4E52 ++#define PCI_CHIP_RV350_NS 0x4E53 ++#define PCI_CHIP_RV350_NT 0x4E54 ++#define PCI_CHIP_RV350_NV 0x4E56 ++#define PCI_CHIP_RAGE128PA 0x5041 ++#define PCI_CHIP_RAGE128PB 0x5042 ++#define PCI_CHIP_RAGE128PC 0x5043 ++#define PCI_CHIP_RAGE128PD 0x5044 ++#define PCI_CHIP_RAGE128PE 0x5045 ++#define PCI_CHIP_RAGE128PF 0x5046 ++#define PCI_CHIP_RAGE128PG 0x5047 ++#define PCI_CHIP_RAGE128PH 0x5048 ++#define PCI_CHIP_RAGE128PI 0x5049 ++#define PCI_CHIP_RAGE128PJ 0x504A ++#define PCI_CHIP_RAGE128PK 0x504B ++#define PCI_CHIP_RAGE128PL 0x504C ++#define PCI_CHIP_RAGE128PM 0x504D ++#define PCI_CHIP_RAGE128PN 0x504E ++#define PCI_CHIP_RAGE128PO 0x504F ++#define PCI_CHIP_RAGE128PP 0x5050 ++#define PCI_CHIP_RAGE128PQ 0x5051 ++#define PCI_CHIP_RAGE128PR 0x5052 ++#define PCI_CHIP_RAGE128PS 0x5053 ++#define PCI_CHIP_RAGE128PT 0x5054 ++#define PCI_CHIP_RAGE128PU 0x5055 ++#define PCI_CHIP_RAGE128PV 0x5056 ++#define PCI_CHIP_RAGE128PW 0x5057 ++#define PCI_CHIP_RAGE128PX 0x5058 ++#define PCI_CHIP_RADEON_QD 0x5144 ++#define PCI_CHIP_RADEON_QE 0x5145 ++#define PCI_CHIP_RADEON_QF 0x5146 ++#define PCI_CHIP_RADEON_QG 0x5147 ++#define PCI_CHIP_R200_QH 0x5148 ++#define PCI_CHIP_R200_QL 0x514C ++#define PCI_CHIP_R200_QM 0x514D ++#define PCI_CHIP_RV200_QW 0x5157 ++#define PCI_CHIP_RV200_QX 0x5158 ++#define PCI_CHIP_RV100_QY 0x5159 ++#define PCI_CHIP_RV100_QZ 0x515A ++#define PCI_CHIP_RN50_515E 0x515E ++#define PCI_CHIP_RAGE128RE 0x5245 ++#define PCI_CHIP_RAGE128RF 0x5246 ++#define PCI_CHIP_RAGE128RG 0x5247 ++#define PCI_CHIP_RAGE128RK 0x524B ++#define PCI_CHIP_RAGE128RL 0x524C ++#define PCI_CHIP_RAGE128SE 0x5345 ++#define PCI_CHIP_RAGE128SF 0x5346 ++#define PCI_CHIP_RAGE128SG 0x5347 ++#define PCI_CHIP_RAGE128SH 0x5348 ++#define PCI_CHIP_RAGE128SK 0x534B ++#define PCI_CHIP_RAGE128SL 0x534C ++#define PCI_CHIP_RAGE128SM 0x534D ++#define PCI_CHIP_RAGE128SN 0x534E ++#define PCI_CHIP_RAGE128TF 0x5446 ++#define PCI_CHIP_RAGE128TL 0x544C ++#define PCI_CHIP_RAGE128TR 0x5452 ++#define PCI_CHIP_RAGE128TS 0x5453 ++#define PCI_CHIP_RAGE128TT 0x5454 ++#define PCI_CHIP_RAGE128TU 0x5455 ++#define PCI_CHIP_RV370_5460 0x5460 ++#define PCI_CHIP_RV370_5462 0x5462 ++#define PCI_CHIP_RV370_5464 0x5464 ++#define PCI_CHIP_R423_UH 0x5548 ++#define PCI_CHIP_R423_UI 0x5549 ++#define PCI_CHIP_R423_UJ 0x554A ++#define PCI_CHIP_R423_UK 0x554B ++#define PCI_CHIP_R430_554C 0x554C ++#define PCI_CHIP_R430_554D 0x554D ++#define PCI_CHIP_R430_554E 0x554E ++#define PCI_CHIP_R430_554F 0x554F ++#define PCI_CHIP_R423_5550 0x5550 ++#define PCI_CHIP_R423_UQ 0x5551 ++#define PCI_CHIP_R423_UR 0x5552 ++#define PCI_CHIP_R423_UT 0x5554 ++#define PCI_CHIP_RV410_564A 0x564A ++#define PCI_CHIP_RV410_564B 0x564B ++#define PCI_CHIP_RV410_564F 0x564F ++#define PCI_CHIP_RV410_5652 0x5652 ++#define PCI_CHIP_RV410_5653 0x5653 ++#define PCI_CHIP_MACH64VT 0x5654 ++#define PCI_CHIP_MACH64VU 0x5655 ++#define PCI_CHIP_MACH64VV 0x5656 ++#define PCI_CHIP_RS300_5834 0x5834 ++#define PCI_CHIP_RS300_5835 0x5835 ++#define PCI_CHIP_RS480_5954 0x5954 ++#define PCI_CHIP_RS480_5955 0x5955 ++#define PCI_CHIP_RV280_5960 0x5960 ++#define PCI_CHIP_RV280_5961 0x5961 ++#define PCI_CHIP_RV280_5962 0x5962 ++#define PCI_CHIP_RV280_5964 0x5964 ++#define PCI_CHIP_RV280_5965 0x5965 ++#define PCI_CHIP_RN50_5969 0x5969 ++#define PCI_CHIP_RS482_5974 0x5974 ++#define PCI_CHIP_RS485_5975 0x5975 ++#define PCI_CHIP_RS400_5A41 0x5A41 ++#define PCI_CHIP_RS400_5A42 0x5A42 ++#define PCI_CHIP_RC410_5A61 0x5A61 ++#define PCI_CHIP_RC410_5A62 0x5A62 ++#define PCI_CHIP_RV370_5B60 0x5B60 ++#define PCI_CHIP_RV370_5B62 0x5B62 ++#define PCI_CHIP_RV370_5B63 0x5B63 ++#define PCI_CHIP_RV370_5B64 0x5B64 ++#define PCI_CHIP_RV370_5B65 0x5B65 ++#define PCI_CHIP_RV280_5C61 0x5C61 ++#define PCI_CHIP_RV280_5C63 0x5C63 ++#define PCI_CHIP_R430_5D48 0x5D48 ++#define PCI_CHIP_R430_5D49 0x5D49 ++#define PCI_CHIP_R430_5D4A 0x5D4A ++#define PCI_CHIP_R480_5D4C 0x5D4C ++#define PCI_CHIP_R480_5D4D 0x5D4D ++#define PCI_CHIP_R480_5D4E 0x5D4E ++#define PCI_CHIP_R480_5D4F 0x5D4F ++#define PCI_CHIP_R480_5D50 0x5D50 ++#define PCI_CHIP_R480_5D52 0x5D52 ++#define PCI_CHIP_R423_5D57 0x5D57 ++#define PCI_CHIP_RV410_5E48 0x5E48 ++#define PCI_CHIP_RV410_5E4A 0x5E4A ++#define PCI_CHIP_RV410_5E4B 0x5E4B ++#define PCI_CHIP_RV410_5E4C 0x5E4C ++#define PCI_CHIP_RV410_5E4D 0x5E4D ++#define PCI_CHIP_RV410_5E4F 0x5E4F ++#define PCI_CHIP_RS350_7834 0x7834 ++#define PCI_CHIP_RS350_7835 0x7835 +diff --git a/src/atidri.c b/src/atidri.c +index bc862a8..0da1bc5 100644 +--- a/src/atidri.c ++++ b/src/atidri.c +@@ -553,11 +553,11 @@ static void ATIDRIMoveBuffers( WindowPtr pWin, DDXPointRec ptOldOrg, + + if (nbox > 1) { + /* Keep ordering in each band, reverse order of bands */ +- pboxNew1 = (BoxPtr)ALLOCATE_LOCAL(sizeof(BoxRec)*nbox); ++ pboxNew1 = (BoxPtr)xalloc(sizeof(BoxRec)*nbox); + if (!pboxNew1) return; +- pptNew1 = (DDXPointPtr)ALLOCATE_LOCAL(sizeof(DDXPointRec)*nbox); ++ pptNew1 = (DDXPointPtr)xalloc(sizeof(DDXPointRec)*nbox); + if (!pptNew1) { +- DEALLOCATE_LOCAL(pboxNew1); ++ xfree(pboxNew1); + return; + } + pboxBase = pboxNext = pbox+nbox-1; +@@ -588,13 +588,13 @@ static void ATIDRIMoveBuffers( WindowPtr pWin, DDXPointRec ptOldOrg, + + if (nbox > 1) { + /* reverse order of rects in each band */ +- pboxNew2 = (BoxPtr)ALLOCATE_LOCAL(sizeof(BoxRec)*nbox); +- pptNew2 = (DDXPointPtr)ALLOCATE_LOCAL(sizeof(DDXPointRec)*nbox); ++ pboxNew2 = (BoxPtr)xalloc(sizeof(BoxRec)*nbox); ++ pptNew2 = (DDXPointPtr)xalloc(sizeof(DDXPointRec)*nbox); + if (!pboxNew2 || !pptNew2) { +- DEALLOCATE_LOCAL(pptNew2); +- DEALLOCATE_LOCAL(pboxNew2); +- DEALLOCATE_LOCAL(pptNew1); +- DEALLOCATE_LOCAL(pboxNew1); ++ xfree(pptNew2); ++ xfree(pboxNew2); ++ xfree(pptNew1); ++ xfree(pboxNew1); + return; + } + pboxBase = pboxNext = pbox; +@@ -665,10 +665,10 @@ static void ATIDRIMoveBuffers( WindowPtr pWin, DDXPointRec ptOldOrg, + outf(SRC_OFF_PITCH, pATI->NewHW.dst_off_pitch); + outf(DST_OFF_PITCH, pATI->NewHW.src_off_pitch); + +- DEALLOCATE_LOCAL(pptNew2); +- DEALLOCATE_LOCAL(pboxNew2); +- DEALLOCATE_LOCAL(pptNew1); +- DEALLOCATE_LOCAL(pboxNew1); ++ xfree(pptNew2); ++ xfree(pboxNew2); ++ xfree(pptNew1); ++ xfree(pboxNew1); + + ATIDRIMarkSyncInt(pScreenInfo); + #endif +diff --git a/src/atipciids.h b/src/atipciids.h +index 2aa8a3e..f24f8fb 100644 +--- a/src/atipciids.h ++++ b/src/atipciids.h +@@ -38,253 +38,7 @@ + #define PCI_VENDOR_AMD 0x1022 + #define PCI_VENDOR_DELL 0x1028 + +-/* ATI */ +-#define PCI_CHIP_RV380_3150 0x3150 +-#define PCI_CHIP_RV380_3151 0x3151 +-#define PCI_CHIP_RV380_3152 0x3152 +-#define PCI_CHIP_RV380_3153 0x3153 +-#define PCI_CHIP_RV380_3154 0x3154 +-#define PCI_CHIP_RV380_3156 0x3156 +-#define PCI_CHIP_RV380_3E50 0x3E50 +-#define PCI_CHIP_RV380_3E51 0x3E51 +-#define PCI_CHIP_RV380_3E52 0x3E52 +-#define PCI_CHIP_RV380_3E53 0x3E53 +-#define PCI_CHIP_RV380_3E54 0x3E54 +-#define PCI_CHIP_RV380_3E56 0x3E56 +-#define PCI_CHIP_RS100_4136 0x4136 +-#define PCI_CHIP_RS200_4137 0x4137 +-#define PCI_CHIP_R300_AD 0x4144 +-#define PCI_CHIP_R300_AE 0x4145 +-#define PCI_CHIP_R300_AF 0x4146 +-#define PCI_CHIP_R300_AG 0x4147 +-#define PCI_CHIP_R350_AH 0x4148 +-#define PCI_CHIP_R350_AI 0x4149 +-#define PCI_CHIP_R350_AJ 0x414A +-#define PCI_CHIP_R350_AK 0x414B +-#define PCI_CHIP_RV350_AP 0x4150 +-#define PCI_CHIP_RV350_AQ 0x4151 +-#define PCI_CHIP_RV360_AR 0x4152 +-#define PCI_CHIP_RV350_AS 0x4153 +-#define PCI_CHIP_RV350_AT 0x4154 +-#define PCI_CHIP_RV350_4155 0x4155 +-#define PCI_CHIP_RV350_AV 0x4156 +-#define PCI_CHIP_MACH32 0x4158 +-#define PCI_CHIP_RS250_4237 0x4237 +-#define PCI_CHIP_R200_BB 0x4242 +-#define PCI_CHIP_R200_BC 0x4243 +-#define PCI_CHIP_RS100_4336 0x4336 +-#define PCI_CHIP_RS200_4337 0x4337 +-#define PCI_CHIP_MACH64CT 0x4354 +-#define PCI_CHIP_MACH64CX 0x4358 +-#define PCI_CHIP_RS250_4437 0x4437 +-#define PCI_CHIP_MACH64ET 0x4554 +-#define PCI_CHIP_MACH64GB 0x4742 +-#define PCI_CHIP_MACH64GD 0x4744 +-#define PCI_CHIP_MACH64GI 0x4749 +-#define PCI_CHIP_MACH64GL 0x474C +-#define PCI_CHIP_MACH64GM 0x474D +-#define PCI_CHIP_MACH64GN 0x474E +-#define PCI_CHIP_MACH64GO 0x474F +-#define PCI_CHIP_MACH64GP 0x4750 +-#define PCI_CHIP_MACH64GQ 0x4751 +-#define PCI_CHIP_MACH64GR 0x4752 +-#define PCI_CHIP_MACH64GS 0x4753 +-#define PCI_CHIP_MACH64GT 0x4754 +-#define PCI_CHIP_MACH64GU 0x4755 +-#define PCI_CHIP_MACH64GV 0x4756 +-#define PCI_CHIP_MACH64GW 0x4757 +-#define PCI_CHIP_MACH64GX 0x4758 +-#define PCI_CHIP_MACH64GY 0x4759 +-#define PCI_CHIP_MACH64GZ 0x475A +-#define PCI_CHIP_RV250_Id 0x4964 +-#define PCI_CHIP_RV250_Ie 0x4965 +-#define PCI_CHIP_RV250_If 0x4966 +-#define PCI_CHIP_RV250_Ig 0x4967 +-#define PCI_CHIP_R420_JH 0x4A48 +-#define PCI_CHIP_R420_JI 0x4A49 +-#define PCI_CHIP_R420_JJ 0x4A4A +-#define PCI_CHIP_R420_JK 0x4A4B +-#define PCI_CHIP_R420_JL 0x4A4C +-#define PCI_CHIP_R420_JM 0x4A4D +-#define PCI_CHIP_R420_JN 0x4A4E +-#define PCI_CHIP_R420_4A4F 0x4A4F +-#define PCI_CHIP_R420_JP 0x4A50 +-#define PCI_CHIP_R420_4A54 0x4A54 +-#define PCI_CHIP_R481_4B49 0x4B49 +-#define PCI_CHIP_R481_4B4A 0x4B4A +-#define PCI_CHIP_R481_4B4B 0x4B4B +-#define PCI_CHIP_R481_4B4C 0x4B4C +-#define PCI_CHIP_MACH64LB 0x4C42 +-#define PCI_CHIP_MACH64LD 0x4C44 +-#define PCI_CHIP_RAGE128LE 0x4C45 +-#define PCI_CHIP_RAGE128LF 0x4C46 +-#define PCI_CHIP_MACH64LG 0x4C47 +-#define PCI_CHIP_MACH64LI 0x4C49 +-#define PCI_CHIP_MACH64LM 0x4C4D +-#define PCI_CHIP_MACH64LN 0x4C4E +-#define PCI_CHIP_MACH64LP 0x4C50 +-#define PCI_CHIP_MACH64LQ 0x4C51 +-#define PCI_CHIP_MACH64LR 0x4C52 +-#define PCI_CHIP_MACH64LS 0x4C53 +-#define PCI_CHIP_RADEON_LW 0x4C57 +-#define PCI_CHIP_RADEON_LX 0x4C58 +-#define PCI_CHIP_RADEON_LY 0x4C59 +-#define PCI_CHIP_RADEON_LZ 0x4C5A +-#define PCI_CHIP_RV250_Ld 0x4C64 +-#define PCI_CHIP_RV250_Le 0x4C65 +-#define PCI_CHIP_RV250_Lf 0x4C66 +-#define PCI_CHIP_RV250_Lg 0x4C67 +-#define PCI_CHIP_RV250_Ln 0x4C6E +-#define PCI_CHIP_RAGE128MF 0x4D46 +-#define PCI_CHIP_RAGE128ML 0x4D4C +-#define PCI_CHIP_R300_ND 0x4E44 +-#define PCI_CHIP_R300_NE 0x4E45 +-#define PCI_CHIP_R300_NF 0x4E46 +-#define PCI_CHIP_R300_NG 0x4E47 +-#define PCI_CHIP_R350_NH 0x4E48 +-#define PCI_CHIP_R350_NI 0x4E49 +-#define PCI_CHIP_R360_NJ 0x4E4A +-#define PCI_CHIP_R350_NK 0x4E4B +-#define PCI_CHIP_RV350_NP 0x4E50 +-#define PCI_CHIP_RV350_NQ 0x4E51 +-#define PCI_CHIP_RV350_NR 0x4E52 +-#define PCI_CHIP_RV350_NS 0x4E53 +-#define PCI_CHIP_RV350_NT 0x4E54 +-#define PCI_CHIP_RV350_NV 0x4E56 +-#define PCI_CHIP_RAGE128PA 0x5041 +-#define PCI_CHIP_RAGE128PB 0x5042 +-#define PCI_CHIP_RAGE128PC 0x5043 +-#define PCI_CHIP_RAGE128PD 0x5044 +-#define PCI_CHIP_RAGE128PE 0x5045 +-#define PCI_CHIP_RAGE128PF 0x5046 +-#define PCI_CHIP_RAGE128PG 0x5047 +-#define PCI_CHIP_RAGE128PH 0x5048 +-#define PCI_CHIP_RAGE128PI 0x5049 +-#define PCI_CHIP_RAGE128PJ 0x504A +-#define PCI_CHIP_RAGE128PK 0x504B +-#define PCI_CHIP_RAGE128PL 0x504C +-#define PCI_CHIP_RAGE128PM 0x504D +-#define PCI_CHIP_RAGE128PN 0x504E +-#define PCI_CHIP_RAGE128PO 0x504F +-#define PCI_CHIP_RAGE128PP 0x5050 +-#define PCI_CHIP_RAGE128PQ 0x5051 +-#define PCI_CHIP_RAGE128PR 0x5052 +-#define PCI_CHIP_RAGE128PS 0x5053 +-#define PCI_CHIP_RAGE128PT 0x5054 +-#define PCI_CHIP_RAGE128PU 0x5055 +-#define PCI_CHIP_RAGE128PV 0x5056 +-#define PCI_CHIP_RAGE128PW 0x5057 +-#define PCI_CHIP_RAGE128PX 0x5058 +-#define PCI_CHIP_RADEON_QD 0x5144 +-#define PCI_CHIP_RADEON_QE 0x5145 +-#define PCI_CHIP_RADEON_QF 0x5146 +-#define PCI_CHIP_RADEON_QG 0x5147 +-#define PCI_CHIP_R200_QH 0x5148 +-#define PCI_CHIP_R200_QI 0x5149 +-#define PCI_CHIP_R200_QJ 0x514A +-#define PCI_CHIP_R200_QK 0x514B +-#define PCI_CHIP_R200_QL 0x514C +-#define PCI_CHIP_R200_QM 0x514D +-#define PCI_CHIP_R200_QN 0x514E +-#define PCI_CHIP_R200_QO 0x514F +-#define PCI_CHIP_RV200_QW 0x5157 +-#define PCI_CHIP_RV200_QX 0x5158 +-#define PCI_CHIP_RV100_QY 0x5159 +-#define PCI_CHIP_RV100_QZ 0x515A +-#define PCI_CHIP_RN50_515E 0x515E +-#define PCI_CHIP_RAGE128RE 0x5245 +-#define PCI_CHIP_RAGE128RF 0x5246 +-#define PCI_CHIP_RAGE128RG 0x5247 +-#define PCI_CHIP_RAGE128RK 0x524B +-#define PCI_CHIP_RAGE128RL 0x524C +-#define PCI_CHIP_RAGE128SE 0x5345 +-#define PCI_CHIP_RAGE128SF 0x5346 +-#define PCI_CHIP_RAGE128SG 0x5347 +-#define PCI_CHIP_RAGE128SH 0x5348 +-#define PCI_CHIP_RAGE128SK 0x534B +-#define PCI_CHIP_RAGE128SL 0x534C +-#define PCI_CHIP_RAGE128SM 0x534D +-#define PCI_CHIP_RAGE128SN 0x534E +-#define PCI_CHIP_RAGE128TF 0x5446 +-#define PCI_CHIP_RAGE128TL 0x544C +-#define PCI_CHIP_RAGE128TR 0x5452 +-#define PCI_CHIP_RAGE128TS 0x5453 +-#define PCI_CHIP_RAGE128TT 0x5454 +-#define PCI_CHIP_RAGE128TU 0x5455 +-#define PCI_CHIP_RV370_5460 0x5460 +-#define PCI_CHIP_RV370_5461 0x5461 +-#define PCI_CHIP_RV370_5462 0x5462 +-#define PCI_CHIP_RV370_5463 0x5463 +-#define PCI_CHIP_RV370_5464 0x5464 +-#define PCI_CHIP_RV370_5465 0x5465 +-#define PCI_CHIP_RV370_5466 0x5466 +-#define PCI_CHIP_RV370_5467 0x5467 +-#define PCI_CHIP_R423_UH 0x5548 +-#define PCI_CHIP_R423_UI 0x5549 +-#define PCI_CHIP_R423_UJ 0x554A +-#define PCI_CHIP_R423_UK 0x554B +-#define PCI_CHIP_R430_554C 0x554C +-#define PCI_CHIP_R430_554D 0x554D +-#define PCI_CHIP_R430_554E 0x554E +-#define PCI_CHIP_R430_554F 0x554F +-#define PCI_CHIP_R423_5550 0x5550 +-#define PCI_CHIP_R423_UQ 0x5551 +-#define PCI_CHIP_R423_UR 0x5552 +-#define PCI_CHIP_R423_UT 0x5554 +-#define PCI_CHIP_RV410_564A 0x564A +-#define PCI_CHIP_RV410_564B 0x564B +-#define PCI_CHIP_RV410_564F 0x564F +-#define PCI_CHIP_RV410_5652 0x5652 +-#define PCI_CHIP_RV410_5653 0x5653 +-#define PCI_CHIP_MACH64VT 0x5654 +-#define PCI_CHIP_MACH64VU 0x5655 +-#define PCI_CHIP_MACH64VV 0x5656 +-#define PCI_CHIP_RS300_5834 0x5834 +-#define PCI_CHIP_RS300_5835 0x5835 +-#define PCI_CHIP_RS300_5836 0x5836 +-#define PCI_CHIP_RS300_5837 0x5837 +-#define PCI_CHIP_RS480_5954 0x5954 +-#define PCI_CHIP_RS480_5955 0x5955 +-#define PCI_CHIP_RV280_5960 0x5960 +-#define PCI_CHIP_RV280_5961 0x5961 +-#define PCI_CHIP_RV280_5962 0x5962 +-#define PCI_CHIP_RV280_5964 0x5964 +-#define PCI_CHIP_RV280_5965 0x5965 +-#define PCI_CHIP_RN50_5969 0x5969 +-#define PCI_CHIP_RS482_5974 0x5974 +-#define PCI_CHIP_RS485_5975 0x5975 +-#define PCI_CHIP_RS400_5A41 0x5A41 +-#define PCI_CHIP_RS400_5A42 0x5A42 +-#define PCI_CHIP_RC410_5A61 0x5A61 +-#define PCI_CHIP_RC410_5A62 0x5A62 +-#define PCI_CHIP_RV370_5B60 0x5B60 +-#define PCI_CHIP_RV370_5B61 0x5B61 +-#define PCI_CHIP_RV370_5B62 0x5B62 +-#define PCI_CHIP_RV370_5B63 0x5B63 +-#define PCI_CHIP_RV370_5B64 0x5B64 +-#define PCI_CHIP_RV370_5B65 0x5B65 +-#define PCI_CHIP_RV370_5B66 0x5B66 +-#define PCI_CHIP_RV370_5B67 0x5B67 +-#define PCI_CHIP_RV280_5C61 0x5C61 +-#define PCI_CHIP_RV280_5C63 0x5C63 +-#define PCI_CHIP_R430_5D48 0x5D48 +-#define PCI_CHIP_R430_5D49 0x5D49 +-#define PCI_CHIP_R430_5D4A 0x5D4A +-#define PCI_CHIP_R480_5D4C 0x5D4C +-#define PCI_CHIP_R480_5D4D 0x5D4D +-#define PCI_CHIP_R480_5D4E 0x5D4E +-#define PCI_CHIP_R480_5D4F 0x5D4F +-#define PCI_CHIP_R480_5D50 0x5D50 +-#define PCI_CHIP_R480_5D52 0x5D52 +-#define PCI_CHIP_R423_5D57 0x5D57 +-#define PCI_CHIP_RV410_5E48 0x5E48 +-#define PCI_CHIP_RV410_5E4A 0x5E4A +-#define PCI_CHIP_RV410_5E4B 0x5E4B +-#define PCI_CHIP_RV410_5E4C 0x5E4C +-#define PCI_CHIP_RV410_5E4D 0x5E4D +-#define PCI_CHIP_RV410_5E4F 0x5E4F +-#define PCI_CHIP_RS350_7834 0x7834 +-#define PCI_CHIP_RS350_7835 0x7835 ++#include "ati_pciids_gen.h" + + /* Misc */ + #define PCI_CHIP_AMD761 0x700E +diff --git a/src/atividmem.c b/src/atividmem.c +index 8910c73..986ac0f 100644 +--- a/src/atividmem.c ++++ b/src/atividmem.c +@@ -103,14 +103,12 @@ ATIUnmapLinear + ATIPtr pATI + ) + { +- pciVideoPtr pVideo = pATI->PCIInfo; +- + if (pATI->pMemory) + { + #ifndef XSERVER_LIBPCIACCESS + xf86UnMapVidMem(iScreen, pATI->pMemory, pATI->LinearSize); + #else +- pci_device_unmap_range(pVideo, pATI->pMemory, pATI->LinearSize); ++ pci_device_unmap_range(pATI->PCIInfo, pATI->pMemory, pATI->LinearSize); + #endif + + #if X_BYTE_ORDER != X_LITTLE_ENDIAN +@@ -120,7 +118,7 @@ ATIUnmapLinear + #ifndef XSERVER_LIBPCIACCESS + xf86UnMapVidMem(iScreen, pATI->pMemoryLE, pATI->LinearSize); + #else +- pci_device_unmap_range(pVideo, pATI->pMemoryLE, pATI->LinearSize); ++ pci_device_unmap_range(pATI->PCIInfo, pATI->pMemoryLE, pATI->LinearSize); + #endif + } + +@@ -143,14 +141,12 @@ ATIUnmapMMIO + ATIPtr pATI + ) + { +- pciVideoPtr pVideo = pATI->PCIInfo; +- + if (pATI->pMMIO) + { + #ifndef XSERVER_LIBPCIACCESS + xf86UnMapVidMem(iScreen, pATI->pMMIO, getpagesize()); + #else +- pci_device_unmap_range(pVideo, pATI->pMMIO, getpagesize()); ++ pci_device_unmap_range(pATI->PCIInfo, pATI->pMMIO, getpagesize()); + #endif + } + +@@ -169,14 +165,12 @@ ATIUnmapCursor + ATIPtr pATI + ) + { +- pciVideoPtr pVideo = pATI->PCIInfo; +- + if (pATI->pCursorPage) + { + #ifndef XSERVER_LIBPCIACCESS + xf86UnMapVidMem(iScreen, pATI->pCursorPage, getpagesize()); + #else +- pci_device_unmap_range(pVideo, pATI->pCursorPage, getpagesize()); ++ pci_device_unmap_range(pATI->PCIInfo, pATI->pCursorPage, getpagesize()); + #endif + } + +diff --git a/src/pcidb/ati_pciids.csv b/src/pcidb/ati_pciids.csv +new file mode 100644 +index 0000000..f201cc4 +--- /dev/null ++++ b/src/pcidb/ati_pciids.csv +@@ -0,0 +1,220 @@ ++"#pciid","define","family","mobility","igp","nocrtc2","Nointtvout","singledac","name" ++"0x3150","RV380_3150","RV380",1,,,,,"ATI Radeon Mobility X600 (M24) 3150 (PCIE)" ++"0x3152","RV380_3152","RV380",1,,,,,"ATI Radeon Mobility X300 (M24) 3152 (PCIE)" ++"0x3154","RV380_3154","RV380",1,,,,,"ATI FireGL M24 GL 3154 (PCIE)" ++"0x3E50","RV380_3E50","RV380",,,,,,"ATI Radeon X600 (RV380) 3E50 (PCIE)" ++"0x3E54","RV380_3E54","RV380",,,,,,"ATI FireGL V3200 (RV380) 3E54 (PCIE)" ++"0x4136","RS100_4136","RS100",,1,,,,"ATI Radeon IGP320 (A3) 4136" ++"0x4137","RS200_4137","RS200",,1,,,,"ATI Radeon IGP330/340/350 (A4) 4137" ++"0x4144","R300_AD","R300",,,,,,"ATI Radeon 9500 AD (AGP)" ++"0x4145","R300_AE","R300",,,,,,"ATI Radeon 9500 AE (AGP)" ++"0x4146","R300_AF","R300",,,,,,"ATI Radeon 9600TX AF (AGP)" ++"0x4147","R300_AG","R300",,,,,,"ATI FireGL Z1 AG (AGP)" ++"0x4148","R350_AH","R350",,,,,,"ATI Radeon 9800SE AH (AGP)" ++"0x4149","R350_AI","R350",,,,,,"ATI Radeon 9800 AI (AGP)" ++"0x414A","R350_AJ","R350",,,,,,"ATI Radeon 9800 AJ (AGP)" ++"0x414B","R350_AK","R350",,,,,,"ATI FireGL X2 AK (AGP)" ++"0x4150","RV350_AP","RV350",,,,,,"ATI Radeon 9600 AP (AGP)" ++"0x4151","RV350_AQ","RV350",,,,,,"ATI Radeon 9600SE AQ (AGP)" ++"0x4152","RV360_AR","RV350",,,,,,"ATI Radeon 9600XT AR (AGP)" ++"0x4153","RV350_AS","RV350",,,,,,"ATI Radeon 9600 AS (AGP)" ++"0x4154","RV350_AT","RV350",,,,,,"ATI FireGL T2 AT (AGP)" ++"0x4155","RV350_4155","RV350",,,,,,"ATI Radeon 9650" ++"0x4156","RV350_AV","RV350",,,,,,"ATI FireGL RV360 AV (AGP)" ++"0x4158","MACH32","MACH32",,,,,, ++"0x4237","RS250_4237","RS200",,1,,,,"ATI Radeon 7000 IGP (A4+) 4237" ++"0x4242","R200_BB","R200",,,,1,,"ATI Radeon 8500 AIW BB (AGP)" ++"0x4243","R200_BC","R200",,,,1,,"ATI Radeon 8500 AIW BC (AGP)" ++"0x4336","RS100_4336","RS100",1,1,,,,"ATI Radeon IGP320M (U1) 4336" ++"0x4337","RS200_4337","RS200",1,1,,,,"ATI Radeon IGP330M/340M/350M (U2) 4337" ++"0x4354","MACH64CT","MACH64",,,,,, ++"0x4358","MACH64CX","MACH64",,,,,, ++"0x4437","RS250_4437","RS200",1,1,,,,"ATI Radeon Mobility 7000 IGP 4437" ++"0x4554","MACH64ET","MACH64",,,,,, ++"0x4742","MACH64GB","MACH64",,,,,, ++"0x4744","MACH64GD","MACH64",,,,,, ++"0x4749","MACH64GI","MACH64",,,,,, ++"0x474C","MACH64GL","MACH64",,,,,, ++"0x474D","MACH64GM","MACH64",,,,,, ++"0x474E","MACH64GN","MACH64",,,,,, ++"0x474F","MACH64GO","MACH64",,,,,, ++"0x4750","MACH64GP","MACH64",,,,,, ++"0x4751","MACH64GQ","MACH64",,,,,, ++"0x4752","MACH64GR","MACH64",,,,,, ++"0x4753","MACH64GS","MACH64",,,,,, ++"0x4754","MACH64GT","MACH64",,,,,, ++"0x4755","MACH64GU","MACH64",,,,,, ++"0x4756","MACH64GV","MACH64",,,,,, ++"0x4757","MACH64GW","MACH64",,,,,, ++"0x4758","MACH64GX","MACH64",,,,,, ++"0x4759","MACH64GY","MACH64",,,,,, ++"0x475A","MACH64GZ","MACH64",,,,,, ++"0x4966","RV250_If","RV250",,,,,,"ATI Radeon 9000/PRO If (AGP/PCI)" ++"0x4967","RV250_Ig","RV250",,,,,,"ATI Radeon 9000 Ig (AGP/PCI)" ++"0x4A48","R420_JH","R420",,,,,,"ATI Radeon X800 (R420) JH (AGP)" ++"0x4A49","R420_JI","R420",,,,,,"ATI Radeon X800PRO (R420) JI (AGP)" ++"0x4A4A","R420_JJ","R420",,,,,,"ATI Radeon X800SE (R420) JJ (AGP)" ++"0x4A4B","R420_JK","R420",,,,,,"ATI Radeon X800 (R420) JK (AGP)" ++"0x4A4C","R420_JL","R420",,,,,,"ATI Radeon X800 (R420) JL (AGP)" ++"0x4A4D","R420_JM","R420",,,,,,"ATI FireGL X3 (R420) JM (AGP)" ++"0x4A4E","R420_JN","R420",1,,,,,"ATI Radeon Mobility 9800 (M18) JN (AGP)" ++"0x4A4F","R420_4A4F","R420",,,,,,"ATI Radeon X800 SE (R420) (AGP)" ++"0x4A50","R420_JP","R420",,,,,,"ATI Radeon X800XT (R420) JP (AGP)" ++"0x4B49","R481_4B49","R420",,,,,,"ATI Radeon X850 XT (R480) (AGP)" ++"0x4B4A","R481_4B4A","R420",,,,,,"ATI Radeon X850 SE (R480) (AGP)" ++"0x4B4B","R481_4B4B","R420",,,,,,"ATI Radeon X850 PRO (R480) (AGP)" ++"0x4B4C","R481_4B4C","R420",,,,,,"ATI Radeon X850 XT PE (R480) (AGP)" ++"0x4C42","MACH64LB","MACH64",,,,,, ++"0x4C44","MACH64LD","MACH64",,,,,, ++"0x4C45","RAGE128LE","R128",,,,,, ++"0x4C46","RAGE128LF","R128",,,,,, ++"0x4C47","MACH64LG","MACH64",,,,,, ++"0x4C49","MACH64LI","MACH64",,,,,, ++"0x4C4D","MACH64LM","MACH64",,,,,, ++"0x4C4E","MACH64LN","MACH64",,,,,, ++"0x4C50","MACH64LP","MACH64",,,,,, ++"0x4C51","MACH64LQ","MACH64",,,,,, ++"0x4C52","MACH64LR","MACH64",,,,,, ++"0x4C53","MACH64LS","MACH64",,,,,, ++"0x4C57","RADEON_LW","RV200",1,,,,,"ATI Radeon Mobility M7 LW (AGP)" ++"0x4C58","RADEON_LX","RV200",1,,,,,"ATI Mobility FireGL 7800 M7 LX (AGP)" ++"0x4C59","RADEON_LY","RV100",1,,,,,"ATI Radeon Mobility M6 LY (AGP)" ++"0x4C5A","RADEON_LZ","RV100",1,,,,,"ATI Radeon Mobility M6 LZ (AGP)" ++"0x4C64","RV250_Ld","RV250",1,,,,,"ATI FireGL Mobility 9000 (M9) Ld (AGP)" ++"0x4C66","RV250_Lf","RV250",1,,,,,"ATI Radeon Mobility 9000 (M9) Lf (AGP)" ++"0x4C67","RV250_Lg","RV250",1,,,,,"ATI Radeon Mobility 9000 (M9) Lg (AGP)" ++"0x4D46","RAGE128MF","R128",,,,,, ++"0x4D4C","RAGE128ML","R128",,,,,, ++"0x4E44","R300_ND","R300",,,,,,"ATI Radeon 9700 Pro ND (AGP)" ++"0x4E45","R300_NE","R300",,,,,,"ATI Radeon 9700/9500Pro NE (AGP)" ++"0x4E46","R300_NF","R300",,,,,,"ATI Radeon 9600TX NF (AGP)" ++"0x4E47","R300_NG","R300",,,,,,"ATI FireGL X1 NG (AGP)" ++"0x4E48","R350_NH","R350",,,,,,"ATI Radeon 9800PRO NH (AGP)" ++"0x4E49","R350_NI","R350",,,,,,"ATI Radeon 9800 NI (AGP)" ++"0x4E4A","R360_NJ","R350",,,,,,"ATI FireGL X2 NK (AGP)" ++"0x4E4B","R350_NK","R350",,,,,,"ATI Radeon 9800XT NJ (AGP)" ++"0x4E50","RV350_NP","RV350",1,,,,,"ATI Radeon Mobility 9600/9700 (M10/M11) NP (AGP)" ++"0x4E51","RV350_NQ","RV350",1,,,,,"ATI Radeon Mobility 9600 (M10) NQ (AGP)" ++"0x4E52","RV350_NR","RV350",1,,,,,"ATI Radeon Mobility 9600 (M11) NR (AGP)" ++"0x4E53","RV350_NS","RV350",1,,,,,"ATI Radeon Mobility 9600 (M10) NS (AGP)" ++"0x4E54","RV350_NT","RV350",1,,,,,"ATI FireGL Mobility T2 (M10) NT (AGP)" ++"0x4E56","RV350_NV","RV350",1,,,,,"ATI FireGL Mobility T2e (M11) NV (AGP)" ++"0x5041","RAGE128PA","R128",,,,,, ++"0x5042","RAGE128PB","R128",,,,,, ++"0x5043","RAGE128PC","R128",,,,,, ++"0x5044","RAGE128PD","R128",,,,,, ++"0x5045","RAGE128PE","R128",,,,,, ++"0x5046","RAGE128PF","R128",,,,,, ++"0x5047","RAGE128PG","R128",,,,,, ++"0x5048","RAGE128PH","R128",,,,,, ++"0x5049","RAGE128PI","R128",,,,,, ++"0x504A","RAGE128PJ","R128",,,,,, ++"0x504B","RAGE128PK","R128",,,,,, ++"0x504C","RAGE128PL","R128",,,,,, ++"0x504D","RAGE128PM","R128",,,,,, ++"0x504E","RAGE128PN","R128",,,,,, ++"0x504F","RAGE128PO","R128",,,,,, ++"0x5050","RAGE128PP","R128",,,,,, ++"0x5051","RAGE128PQ","R128",,,,,, ++"0x5052","RAGE128PR","R128",,,,,, ++"0x5053","RAGE128PS","R128",,,,,, ++"0x5054","RAGE128PT","R128",,,,,, ++"0x5055","RAGE128PU","R128",,,,,, ++"0x5056","RAGE128PV","R128",,,,,, ++"0x5057","RAGE128PW","R128",,,,,, ++"0x5058","RAGE128PX","R128",,,,,, ++"0x5144","RADEON_QD","RADEON",,,1,1,,"ATI Radeon QD (AGP)" ++"0x5145","RADEON_QE","RADEON",,,1,1,,"ATI Radeon QE (AGP)" ++"0x5146","RADEON_QF","RADEON",,,1,1,,"ATI Radeon QF (AGP)" ++"0x5147","RADEON_QG","RADEON",,,1,1,,"ATI Radeon QG (AGP)" ++"0x5148","R200_QH","R200",,,,1,,"ATI FireGL 8700/8800 QH (AGP)" ++"0x514C","R200_QL","R200",,,,1,,"ATI Radeon 8500 QL (AGP)" ++"0x514D","R200_QM","R200",,,,1,,"ATI Radeon 9100 QM (AGP)" ++"0x5157","RV200_QW","RV200",,,,,,"ATI Radeon 7500 QW (AGP/PCI)" ++"0x5158","RV200_QX","RV200",,,,,,"ATI Radeon 7500 QX (AGP/PCI)" ++"0x5159","RV100_QY","RV100",,,,,,"ATI Radeon VE/7000 QY (AGP/PCI)" ++"0x515A","RV100_QZ","RV100",,,,,,"ATI Radeon VE/7000 QZ (AGP/PCI)" ++"0x515E","RN50_515E","RV100",,,1,,,"ATI ES1000 515E (PCI)" ++"0x5245","RAGE128RE","R128",,,,,, ++"0x5246","RAGE128RF","R128",,,,,, ++"0x5247","RAGE128RG","R128",,,,,, ++"0x524B","RAGE128RK","R128",,,,,, ++"0x524C","RAGE128RL","R128",,,,,, ++"0x5345","RAGE128SE","R128",,,,,, ++"0x5346","RAGE128SF","R128",,,,,, ++"0x5347","RAGE128SG","R128",,,,,, ++"0x5348","RAGE128SH","R128",,,,,, ++"0x534B","RAGE128SK","R128",,,,,, ++"0x534C","RAGE128SL","R128",,,,,, ++"0x534D","RAGE128SM","R128",,,,,, ++"0x534E","RAGE128SN","R128",,,,,, ++"0x5446","RAGE128TF","R128",,,,,, ++"0x544C","RAGE128TL","R128",,,,,, ++"0x5452","RAGE128TR","R128",,,,,, ++"0x5453","RAGE128TS","R128",,,,,, ++"0x5454","RAGE128TT","R128",,,,,, ++"0x5455","RAGE128TU","R128",,,,,, ++"0x5460","RV370_5460","RV380",1,,,,,"ATI Radeon Mobility X300 (M22) 5460 (PCIE)" ++"0x5462","RV370_5462","RV380",1,,,,,"ATI Radeon Mobility X600 SE (M24C) 5462 (PCIE)" ++"0x5464","RV370_5464","RV380",1,,,,,"ATI FireGL M22 GL 5464 (PCIE)" ++"0x5548","R423_UH","R420",,,,,,"ATI Radeon X800 (R423) UH (PCIE)" ++"0x5549","R423_UI","R420",,,,,,"ATI Radeon X800PRO (R423) UI (PCIE)" ++"0x554A","R423_UJ","R420",,,,,,"ATI Radeon X800LE (R423) UJ (PCIE)" ++"0x554B","R423_UK","R420",,,,,,"ATI Radeon X800SE (R423) UK (PCIE)" ++"0x554C","R430_554C","R420",,,,,,"ATI Radeon X800 XTP (R430) (PCIE)" ++"0x554D","R430_554D","R420",,,,,,"ATI Radeon X800 XL (R430) (PCIE)" ++"0x554E","R430_554E","R420",,,,,,"ATI Radeon X800 SE (R430) (PCIE)" ++"0x554F","R430_554F","R420",,,,,,"ATI Radeon X800 (R430) (PCIE)" ++"0x5550","R423_5550","R420",,,,,,"ATI FireGL V7100 (R423) (PCIE)" ++"0x5551","R423_UQ","R420",,,,,,"ATI FireGL V5100 (R423) UQ (PCIE)" ++"0x5552","R423_UR","R420",,,,,,"ATI FireGL unknown (R423) UR (PCIE)" ++"0x5554","R423_UT","R420",,,,,,"ATI FireGL unknown (R423) UT (PCIE)" ++"0x564A","RV410_564A","RV410",1,,,,,"ATI Mobility FireGL V5000 (M26) (PCIE)" ++"0x564B","RV410_564B","RV410",1,,,,,"ATI Mobility FireGL V5000 (M26) (PCIE)" ++"0x564F","RV410_564F","RV410",1,,,,,"ATI Mobility Radeon X700 XL (M26) (PCIE)" ++"0x5652","RV410_5652","RV410",1,,,,,"ATI Mobility Radeon X700 (M26) (PCIE)" ++"0x5653","RV410_5653","RV410",1,,,,,"ATI Mobility Radeon X700 (M26) (PCIE)" ++"0x5654","MACH64VT","MACH64",,,,,, ++"0x5655","MACH64VU","MACH64",,,,,, ++"0x5656","MACH64VV","MACH64",,,,,, ++"0x5834","RS300_5834","RS300",,1,,,1,"ATI Radeon 9100 IGP (A5) 5834" ++"0x5835","RS300_5835","RS300",1,1,,,1,"ATI Radeon Mobility 9100 IGP (U3) 5835" ++"0x5954","RS480_5954","RS400",,1,,,1,"ATI Radeon XPRESS 200 5954 (PCIE)" ++"0x5955","RS480_5955","RS400",1,1,,,1,"ATI Radeon XPRESS 200M 5955 (PCIE)" ++"0x5960","RV280_5960","RV280",,,,,,"ATI Radeon 9250 5960 (AGP)" ++"0x5961","RV280_5961","RV280",,,,,,"ATI Radeon 9200 5961 (AGP)" ++"0x5962","RV280_5962","RV280",,,,,,"ATI Radeon 9200 5962 (AGP)" ++"0x5964","RV280_5964","RV280",,,,,,"ATI Radeon 9200SE 5964 (AGP)" ++"0x5965","RV280_5965","RV280",,,,,,"ATI FireMV 2200 (PCI)" ++"0x5969","RN50_5969","RV100",,,1,,,"ATI ES1000 5969 (PCI)" ++"0x5974","RS482_5974","RS400",,1,,,1,"ATI Radeon XPRESS 200 5974 (PCIE)" ++"0x5975","RS485_5975","RS400",1,1,,,1,"ATI Radeon XPRESS 200M 5975 (PCIE)" ++"0x5A41","RS400_5A41","RS400",,1,,,1,"ATI Radeon XPRESS 200 5A41 (PCIE)" ++"0x5A42","RS400_5A42","RS400",1,1,,,1,"ATI Radeon XPRESS 200M 5A42 (PCIE)" ++"0x5A61","RC410_5A61","RS400",,1,,,1,"ATI Radeon XPRESS 200 5A61 (PCIE)" ++"0x5A62","RC410_5A62","RS400",1,1,,,1,"ATI Radeon XPRESS 200M 5A62 (PCIE)" ++"0x5B60","RV370_5B60","RV380",,,,,,"ATI Radeon X300 (RV370) 5B60 (PCIE)" ++"0x5B62","RV370_5B62","RV380",,,,,,"ATI Radeon X600 (RV370) 5B62 (PCIE)" ++"0x5B63","RV370_5B63","RV380",,,,,,"ATI Radeon X550 (RV370) 5B63 (PCIE)" ++"0x5B64","RV370_5B64","RV380",,,,,,"ATI FireGL V3100 (RV370) 5B64 (PCIE)" ++"0x5B65","RV370_5B65","RV380",,,,,,"ATI FireMV 2200 PCIE (RV370) 5B65 (PCIE)" ++"0x5C61","RV280_5C61","RV280",1,,,,,"ATI Radeon Mobility 9200 (M9+) 5C61 (AGP)" ++"0x5C63","RV280_5C63","RV280",1,,,,,"ATI Radeon Mobility 9200 (M9+) 5C63 (AGP)" ++"0x5D48","R430_5D48","R420",1,,,,,"ATI Mobility Radeon X800 XT (M28) (PCIE)" ++"0x5D49","R430_5D49","R420",1,,,,,"ATI Mobility FireGL V5100 (M28) (PCIE)" ++"0x5D4A","R430_5D4A","R420",1,,,,,"ATI Mobility Radeon X800 (M28) (PCIE)" ++"0x5D4C","R480_5D4C","R420",,,,,,"ATI Radeon X850 5D4C (PCIE)" ++"0x5D4D","R480_5D4D","R420",,,,,,"ATI Radeon X850 XT PE (R480) (PCIE)" ++"0x5D4E","R480_5D4E","R420",,,,,,"ATI Radeon X850 SE (R480) (PCIE)" ++"0x5D4F","R480_5D4F","R420",,,,,,"ATI Radeon X850 PRO (R480) (PCIE)" ++"0x5D50","R480_5D50","R420",,,,,,"ATI unknown Radeon / FireGL (R480) 5D50 (PCIE)" ++"0x5D52","R480_5D52","R420",,,,,,"ATI Radeon X850 XT (R480) (PCIE)" ++"0x5D57","R423_5D57","R420",,,,,,"ATI Radeon X800XT (R423) 5D57 (PCIE)" ++"0x5E48","RV410_5E48","RV410",,,,,,"ATI FireGL V5000 (RV410) (PCIE)" ++"0x5E4A","RV410_5E4A","RV410",,,,,,"ATI Radeon X700 XT (RV410) (PCIE)" ++"0x5E4B","RV410_5E4B","RV410",,,,,,"ATI Radeon X700 PRO (RV410) (PCIE)" ++"0x5E4C","RV410_5E4C","RV410",,,,,,"ATI Radeon X700 SE (RV410) (PCIE)" ++"0x5E4D","RV410_5E4D","RV410",,,,,,"ATI Radeon X700 (RV410) (PCIE)" ++"0x5E4F","RV410_5E4F","RV410",,,,,,"ATI Radeon X700 SE (RV410) (PCIE)" ++"0x7834","RS350_7834","RS300",,1,,,,"ATI Radeon 9100 PRO IGP 7834" ++"0x7835","RS350_7835","RS300",1,1,,,,"ATI Radeon Mobility 9200 IGP 7835" +diff --git a/src/pcidb/parse_pci_ids.pl b/src/pcidb/parse_pci_ids.pl +new file mode 100755 +index 0000000..e6eac76 +--- /dev/null ++++ b/src/pcidb/parse_pci_ids.pl +@@ -0,0 +1,94 @@ ++#!/usr/bin/perl ++# ++# Copyright 2007 Red Hat Inc. ++# This crappy script written by Dave Airlie to avoid hassle of adding ++# ids in every place. ++# ++use strict; ++use warnings; ++use Text::CSV_XS; ++ ++my $file = $ARGV[0]; ++ ++my $atioutfile = 'ati_pciids_gen.h'; ++my $radeonpcichipsetfile = 'radeon_pci_chipset_gen.h'; ++my $radeonchipsetfile = 'radeon_chipset_gen.h'; ++my $radeonchipinfofile = 'radeon_chipinfo_gen.h'; ++ ++my $csv = Text::CSV_XS->new(); ++ ++open (CSV, "<", $file) or die $!; ++ ++open (ATIOUT, ">", $atioutfile) or die; ++open (PCICHIPSET, ">", $radeonpcichipsetfile) or die; ++open (RADEONCHIPSET, ">", $radeonchipsetfile) or die; ++open (RADEONCHIPINFO, ">", $radeonchipinfofile) or die; ++ ++print RADEONCHIPSET "/* This file is autogenerated please do not edit */\n"; ++print RADEONCHIPSET "static SymTabRec RADEONChipsets[] = {\n"; ++print PCICHIPSET "/* This file is autogenerated please do not edit */\n"; ++print PCICHIPSET "PciChipsets RADEONPciChipsets[] = {\n"; ++print RADEONCHIPINFO "/* This file is autogenerated please do not edit */\n"; ++print RADEONCHIPINFO "RADEONCardInfo RADEONCards[] = {\n"; ++while () { ++ if ($csv->parse($_)) { ++ my @columns = $csv->fields(); ++ ++ if ((substr($columns[0], 0, 1) ne "#")) { ++ ++ print ATIOUT "#define PCI_CHIP_$columns[1] $columns[0]\n"; ++ ++ if (($columns[2] ne "R128") && ($columns[2] ne "MACH64") && ($columns[2] ne "MACH32")) { ++ print PCICHIPSET " { PCI_CHIP_$columns[1], PCI_CHIP_$columns[1], RES_SHARED_VGA },\n"; ++ ++ print RADEONCHIPSET " { PCI_CHIP_$columns[1], \"$columns[8]\" },\n"; ++ ++ print RADEONCHIPINFO " { $columns[0], CHIP_FAMILY_$columns[2], "; ++ ++ if ($columns[3] eq "1") { ++ print RADEONCHIPINFO "1, "; ++ } else { ++ print RADEONCHIPINFO "0, "; ++ } ++ ++ if ($columns[4] eq "1") { ++ print RADEONCHIPINFO "1, "; ++ } else { ++ print RADEONCHIPINFO "0, "; ++ } ++ ++ if ($columns[5] eq "1") { ++ print RADEONCHIPINFO "1, "; ++ } else { ++ print RADEONCHIPINFO "0, "; ++ } ++ ++ if ($columns[6] eq "1") { ++ print RADEONCHIPINFO "1, "; ++ } else { ++ print RADEONCHIPINFO "0, "; ++ } ++ ++ if ($columns[7] eq "1") { ++ print RADEONCHIPINFO "1 "; ++ } else { ++ print RADEONCHIPINFO "0 "; ++ } ++ ++ print RADEONCHIPINFO "},\n"; ++ } ++ } ++ } else { ++ my $err = $csv->error_input; ++ print "Failed to parse line: $err"; ++ } ++} ++ ++print RADEONCHIPINFO "};\n"; ++print RADEONCHIPSET " { -1, NULL }\n};\n"; ++print PCICHIPSET " { -1, -1, RES_UNDEFINED }\n};\n"; ++close CSV; ++close ATIOUT; ++close PCICHIPSET; ++close RADEONCHIPSET; ++close RADEONCHIPINFO; +diff --git a/src/r128_dri.c b/src/r128_dri.c +index fc91421..edb77ba 100644 +--- a/src/r128_dri.c ++++ b/src/r128_dri.c +@@ -80,9 +80,9 @@ static Bool R128InitVisualConfigs(ScreenPtr pScreen) + ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; + R128InfoPtr info = R128PTR(pScrn); + int numConfigs = 0; +- __GLXvisualConfig *pConfigs = 0; +- R128ConfigPrivPtr pR128Configs = 0; +- R128ConfigPrivPtr *pR128ConfigPtrs = 0; ++ __GLXvisualConfig *pConfigs = NULL; ++ R128ConfigPrivPtr pR128Configs = NULL; ++ R128ConfigPrivPtr *pR128ConfigPtrs = NULL; + int i, accum, stencil, db; + + switch (info->CurrentLayout.pixel_code) { +diff --git a/src/r128_probe.c b/src/r128_probe.c +index b2298df..0be21e8 100644 +--- a/src/r128_probe.c ++++ b/src/r128_probe.c +@@ -193,7 +193,7 @@ R128Probe(DriverPtr drv, int flags) + + pScrn = NULL; + if((pScrn = xf86ConfigPciEntity(pScrn, 0, usedChips[i], +- R128PciChipsets, 0, 0, 0, 0, 0))) ++ R128PciChipsets, NULL, NULL, NULL, NULL, NULL))) + { + pScrn->driverVersion = R128_VERSION_CURRENT; + pScrn->driverName = R128_DRIVER_NAME; +diff --git a/src/radeon.h b/src/radeon.h +index 532f04c..03db360 100644 +--- a/src/radeon.h ++++ b/src/radeon.h +@@ -158,7 +158,9 @@ typedef enum { + OPTION_MAC_MODEL, + #endif + OPTION_DEFAULT_TMDS_PLL, +- OPTION_TVDAC_LOAD_DETECT ++ OPTION_TVDAC_LOAD_DETECT, ++ OPTION_FORCE_TVOUT, ++ OPTION_TVSTD + } RADEONOpts; + + +@@ -286,6 +288,7 @@ typedef struct { + CARD32 dot_clock_freq; + CARD32 pll_output_freq; + int feedback_div; ++ int reference_div; + int post_div; + + /* PLL registers */ +@@ -298,6 +301,7 @@ typedef struct { + CARD32 dot_clock_freq_2; + CARD32 pll_output_freq_2; + int feedback_div_2; ++ int reference_div_2; + int post_div_2; + + /* PLL2 registers */ +@@ -362,12 +366,24 @@ typedef struct { + + } RADEONSaveRec, *RADEONSavePtr; + ++#define RADEON_PLL_USE_BIOS_DIVS (1 << 0) ++#define RADEON_PLL_NO_ODD_POST_DIV (1 << 1) ++#define RADEON_PLL_USE_REF_DIV (1 << 2) ++ + typedef struct { + CARD16 reference_freq; + CARD16 reference_div; + CARD32 min_pll_freq; + CARD32 max_pll_freq; + CARD16 xclk; ++ ++ CARD32 min_ref_div; ++ CARD32 max_ref_div; ++ CARD32 min_feedback_div; ++ CARD32 max_feedback_div; ++ CARD32 pll_in_min; ++ CARD32 pll_in_max; ++ CARD32 best_vco; + } RADEONPLLRec, *RADEONPLLPtr; + + typedef struct { +@@ -428,12 +444,22 @@ typedef enum { + CHIP_ERRATA_PLL_DELAY = 0x00000004 + } RADEONErrata; + ++typedef enum { ++ RADEON_DVOCHIP_NONE, ++ RADEON_SIL_164, ++ RADEON_SIL_1178 ++} RADEONExtTMDSChip; ++ + #if defined(__powerpc__) + typedef enum { +- RADEON_MAC_IBOOK = 0x00000001, +- RADEON_MAC_POWERBOOK_DL = 0x00000002, +- RADEON_MAC_POWERBOOK = 0x00000004, +- RADEON_MAC_MINI = 0x00000008 ++ RADEON_MAC_NONE, ++ RADEON_MAC_IBOOK, ++ RADEON_MAC_POWERBOOK_EXTERNAL, ++ RADEON_MAC_POWERBOOK_INTERNAL, ++ RADEON_MAC_POWERBOOK_VGA, ++ RADEON_MAC_MINI_EXTERNAL, ++ RADEON_MAC_MINI_INTERNAL, ++ RADEON_MAC_IMAC_G5_ISIGHT + } RADEONMacModel; + #endif + +@@ -444,6 +470,16 @@ typedef enum { + } RADEONCardType; + + typedef struct { ++ CARD32 pci_device_id; ++ RADEONChipFamily chip_family; ++ int mobility; ++ int igp; ++ int nocrtc2; ++ int nointtvout; ++ int singledac; ++} RADEONCardInfo; ++ ++typedef struct { + EntityInfoPtr pEnt; + pciVideoPtr PciInfo; + PCITAG PciTag; +@@ -525,10 +561,6 @@ typedef struct { + #endif + Bool accelOn; + xf86CursorInfoPtr cursor; +- CARD32 cursor_offset; +-#ifdef USE_XAA +- unsigned long cursor_end; +-#endif + Bool allowColorTiling; + Bool tilingEnabled; /* mirror of sarea->tiling_enabled */ + #ifdef ARGB_CURSOR +@@ -816,6 +848,15 @@ typedef struct { + #if defined(__powerpc__) + RADEONMacModel MacModel; + #endif ++ RADEONExtTMDSChip ext_tmds_chip; ++ ++ /* output enable masks for outputs shared across connectors */ ++ int output_crt1; ++ int output_crt2; ++ int output_dfp1; ++ int output_dfp2; ++ int output_lcd1; ++ int output_tv1; + + Rotation rotation; + void (*PointerMoved)(int, int, int); +diff --git a/src/radeon_accel.c b/src/radeon_accel.c +index 6028aff..ed7d1e9 100644 +--- a/src/radeon_accel.c ++++ b/src/radeon_accel.c +@@ -136,8 +136,8 @@ void RADEONWaitForFifoFunction(ScrnInfoPtr pScrn, int entries) + } + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "FIFO timed out: %u entries, stat=0x%08x\n", +- INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK, +- INREG(RADEON_RBBM_STATUS)); ++ (unsigned int)INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK, ++ (unsigned int)INREG(RADEON_RBBM_STATUS)); + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, + "FIFO timed out, resetting engine...\n"); + RADEONEngineReset(pScrn); +@@ -168,7 +168,7 @@ void RADEONEngineFlush(ScrnInfoPtr pScrn) + if (i == RADEON_TIMEOUT) { + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "DC flush timeout: %x\n", +- INREG(RADEON_RB3D_DSTCACHE_CTLSTAT)); ++ (unsigned int)INREG(RADEON_RB3D_DSTCACHE_CTLSTAT)); + } + } + +diff --git a/src/radeon_bios.c b/src/radeon_bios.c +index 1b46746..d150c4b 100644 +--- a/src/radeon_bios.c ++++ b/src/radeon_bios.c +@@ -48,13 +48,12 @@ Bool RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10) + int tmp; + unsigned short dptr; + +- if (!(info->VBIOS = xalloc( + #ifdef XSERVER_LIBPCIACCESS +- info->PciInfo->rom_size ++ info->VBIOS = xalloc(info->PciInfo->rom_size); + #else +- RADEON_VBIOS_SIZE ++ info->VBIOS = xalloc(RADEON_VBIOS_SIZE); + #endif +- ))) { ++ if (!info->VBIOS) { + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, + "Cannot allocate space for hold Video BIOS!\n"); + return FALSE; +@@ -469,15 +468,6 @@ Bool RADEONGetClockInfoFromBIOS (ScrnInfoPtr pScrn) + + info->sclk = RADEON_BIOS32(pll_info_block + 8) / 100.0; + info->mclk = RADEON_BIOS32(pll_info_block + 12) / 100.0; +- if (info->sclk == 0) info->sclk = 200; +- if (info->mclk == 0) info->mclk = 200; +- +- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "ref_freq: %d, min_pll: %u, " +- "max_pll: %u, xclk: %d, sclk: %f, mclk: %f\n", +- pll->reference_freq, (unsigned)pll->min_pll_freq, +- (unsigned)pll->max_pll_freq, pll->xclk, info->sclk, +- info->mclk); +- + } else { + pll_info_block = RADEON_BIOS16 (info->ROMHeaderStart + 0x30); + +@@ -490,8 +480,17 @@ Bool RADEONGetClockInfoFromBIOS (ScrnInfoPtr pScrn) + info->sclk = RADEON_BIOS16(pll_info_block + 8) / 100.0; + info->mclk = RADEON_BIOS16(pll_info_block + 10) / 100.0; + } ++ ++ if (info->sclk == 0) info->sclk = 200; ++ if (info->mclk == 0) info->mclk = 200; + } + ++ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "ref_freq: %d, min_pll: %u, " ++ "max_pll: %u, xclk: %d, sclk: %f, mclk: %f\n", ++ pll->reference_freq, (unsigned)pll->min_pll_freq, ++ (unsigned)pll->max_pll_freq, pll->xclk, info->sclk, ++ info->mclk); ++ + return TRUE; + } + +diff --git a/src/radeon_chipinfo_gen.h b/src/radeon_chipinfo_gen.h +new file mode 100644 +index 0000000..a12b225 +--- /dev/null ++++ b/src/radeon_chipinfo_gen.h +@@ -0,0 +1,140 @@ ++/* This file is autogenerated please do not edit */ ++RADEONCardInfo RADEONCards[] = { ++ { 0x3150, CHIP_FAMILY_RV380, 1, 0, 0, 0, 0 }, ++ { 0x3152, CHIP_FAMILY_RV380, 1, 0, 0, 0, 0 }, ++ { 0x3154, CHIP_FAMILY_RV380, 1, 0, 0, 0, 0 }, ++ { 0x3E50, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 }, ++ { 0x3E54, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 }, ++ { 0x4136, CHIP_FAMILY_RS100, 0, 1, 0, 0, 0 }, ++ { 0x4137, CHIP_FAMILY_RS200, 0, 1, 0, 0, 0 }, ++ { 0x4144, CHIP_FAMILY_R300, 0, 0, 0, 0, 0 }, ++ { 0x4145, CHIP_FAMILY_R300, 0, 0, 0, 0, 0 }, ++ { 0x4146, CHIP_FAMILY_R300, 0, 0, 0, 0, 0 }, ++ { 0x4147, CHIP_FAMILY_R300, 0, 0, 0, 0, 0 }, ++ { 0x4148, CHIP_FAMILY_R350, 0, 0, 0, 0, 0 }, ++ { 0x4149, CHIP_FAMILY_R350, 0, 0, 0, 0, 0 }, ++ { 0x414A, CHIP_FAMILY_R350, 0, 0, 0, 0, 0 }, ++ { 0x414B, CHIP_FAMILY_R350, 0, 0, 0, 0, 0 }, ++ { 0x4150, CHIP_FAMILY_RV350, 0, 0, 0, 0, 0 }, ++ { 0x4151, CHIP_FAMILY_RV350, 0, 0, 0, 0, 0 }, ++ { 0x4152, CHIP_FAMILY_RV350, 0, 0, 0, 0, 0 }, ++ { 0x4153, CHIP_FAMILY_RV350, 0, 0, 0, 0, 0 }, ++ { 0x4154, CHIP_FAMILY_RV350, 0, 0, 0, 0, 0 }, ++ { 0x4155, CHIP_FAMILY_RV350, 0, 0, 0, 0, 0 }, ++ { 0x4156, CHIP_FAMILY_RV350, 0, 0, 0, 0, 0 }, ++ { 0x4237, CHIP_FAMILY_RS200, 0, 1, 0, 0, 0 }, ++ { 0x4242, CHIP_FAMILY_R200, 0, 0, 0, 1, 0 }, ++ { 0x4243, CHIP_FAMILY_R200, 0, 0, 0, 1, 0 }, ++ { 0x4336, CHIP_FAMILY_RS100, 1, 1, 0, 0, 0 }, ++ { 0x4337, CHIP_FAMILY_RS200, 1, 1, 0, 0, 0 }, ++ { 0x4437, CHIP_FAMILY_RS200, 1, 1, 0, 0, 0 }, ++ { 0x4966, CHIP_FAMILY_RV250, 0, 0, 0, 0, 0 }, ++ { 0x4967, CHIP_FAMILY_RV250, 0, 0, 0, 0, 0 }, ++ { 0x4A48, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, ++ { 0x4A49, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, ++ { 0x4A4A, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, ++ { 0x4A4B, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, ++ { 0x4A4C, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, ++ { 0x4A4D, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, ++ { 0x4A4E, CHIP_FAMILY_R420, 1, 0, 0, 0, 0 }, ++ { 0x4A4F, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, ++ { 0x4A50, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, ++ { 0x4B49, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, ++ { 0x4B4A, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, ++ { 0x4B4B, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, ++ { 0x4B4C, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, ++ { 0x4C57, CHIP_FAMILY_RV200, 1, 0, 0, 0, 0 }, ++ { 0x4C58, CHIP_FAMILY_RV200, 1, 0, 0, 0, 0 }, ++ { 0x4C59, CHIP_FAMILY_RV100, 1, 0, 0, 0, 0 }, ++ { 0x4C5A, CHIP_FAMILY_RV100, 1, 0, 0, 0, 0 }, ++ { 0x4C64, CHIP_FAMILY_RV250, 1, 0, 0, 0, 0 }, ++ { 0x4C66, CHIP_FAMILY_RV250, 1, 0, 0, 0, 0 }, ++ { 0x4C67, CHIP_FAMILY_RV250, 1, 0, 0, 0, 0 }, ++ { 0x4E44, CHIP_FAMILY_R300, 0, 0, 0, 0, 0 }, ++ { 0x4E45, CHIP_FAMILY_R300, 0, 0, 0, 0, 0 }, ++ { 0x4E46, CHIP_FAMILY_R300, 0, 0, 0, 0, 0 }, ++ { 0x4E47, CHIP_FAMILY_R300, 0, 0, 0, 0, 0 }, ++ { 0x4E48, CHIP_FAMILY_R350, 0, 0, 0, 0, 0 }, ++ { 0x4E49, CHIP_FAMILY_R350, 0, 0, 0, 0, 0 }, ++ { 0x4E4A, CHIP_FAMILY_R350, 0, 0, 0, 0, 0 }, ++ { 0x4E4B, CHIP_FAMILY_R350, 0, 0, 0, 0, 0 }, ++ { 0x4E50, CHIP_FAMILY_RV350, 1, 0, 0, 0, 0 }, ++ { 0x4E51, CHIP_FAMILY_RV350, 1, 0, 0, 0, 0 }, ++ { 0x4E52, CHIP_FAMILY_RV350, 1, 0, 0, 0, 0 }, ++ { 0x4E53, CHIP_FAMILY_RV350, 1, 0, 0, 0, 0 }, ++ { 0x4E54, CHIP_FAMILY_RV350, 1, 0, 0, 0, 0 }, ++ { 0x4E56, CHIP_FAMILY_RV350, 1, 0, 0, 0, 0 }, ++ { 0x5144, CHIP_FAMILY_RADEON, 0, 0, 1, 1, 0 }, ++ { 0x5145, CHIP_FAMILY_RADEON, 0, 0, 1, 1, 0 }, ++ { 0x5146, CHIP_FAMILY_RADEON, 0, 0, 1, 1, 0 }, ++ { 0x5147, CHIP_FAMILY_RADEON, 0, 0, 1, 1, 0 }, ++ { 0x5148, CHIP_FAMILY_R200, 0, 0, 0, 1, 0 }, ++ { 0x514C, CHIP_FAMILY_R200, 0, 0, 0, 1, 0 }, ++ { 0x514D, CHIP_FAMILY_R200, 0, 0, 0, 1, 0 }, ++ { 0x5157, CHIP_FAMILY_RV200, 0, 0, 0, 0, 0 }, ++ { 0x5158, CHIP_FAMILY_RV200, 0, 0, 0, 0, 0 }, ++ { 0x5159, CHIP_FAMILY_RV100, 0, 0, 0, 0, 0 }, ++ { 0x515A, CHIP_FAMILY_RV100, 0, 0, 0, 0, 0 }, ++ { 0x515E, CHIP_FAMILY_RV100, 0, 0, 1, 0, 0 }, ++ { 0x5460, CHIP_FAMILY_RV380, 1, 0, 0, 0, 0 }, ++ { 0x5462, CHIP_FAMILY_RV380, 1, 0, 0, 0, 0 }, ++ { 0x5464, CHIP_FAMILY_RV380, 1, 0, 0, 0, 0 }, ++ { 0x5548, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, ++ { 0x5549, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, ++ { 0x554A, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, ++ { 0x554B, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, ++ { 0x554C, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, ++ { 0x554D, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, ++ { 0x554E, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, ++ { 0x554F, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, ++ { 0x5550, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, ++ { 0x5551, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, ++ { 0x5552, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, ++ { 0x5554, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, ++ { 0x564A, CHIP_FAMILY_RV410, 1, 0, 0, 0, 0 }, ++ { 0x564B, CHIP_FAMILY_RV410, 1, 0, 0, 0, 0 }, ++ { 0x564F, CHIP_FAMILY_RV410, 1, 0, 0, 0, 0 }, ++ { 0x5652, CHIP_FAMILY_RV410, 1, 0, 0, 0, 0 }, ++ { 0x5653, CHIP_FAMILY_RV410, 1, 0, 0, 0, 0 }, ++ { 0x5834, CHIP_FAMILY_RS300, 0, 1, 0, 0, 1 }, ++ { 0x5835, CHIP_FAMILY_RS300, 1, 1, 0, 0, 1 }, ++ { 0x5954, CHIP_FAMILY_RS400, 0, 1, 0, 0, 1 }, ++ { 0x5955, CHIP_FAMILY_RS400, 1, 1, 0, 0, 1 }, ++ { 0x5960, CHIP_FAMILY_RV280, 0, 0, 0, 0, 0 }, ++ { 0x5961, CHIP_FAMILY_RV280, 0, 0, 0, 0, 0 }, ++ { 0x5962, CHIP_FAMILY_RV280, 0, 0, 0, 0, 0 }, ++ { 0x5964, CHIP_FAMILY_RV280, 0, 0, 0, 0, 0 }, ++ { 0x5965, CHIP_FAMILY_RV280, 0, 0, 0, 0, 0 }, ++ { 0x5969, CHIP_FAMILY_RV100, 0, 0, 1, 0, 0 }, ++ { 0x5974, CHIP_FAMILY_RS400, 0, 1, 0, 0, 1 }, ++ { 0x5975, CHIP_FAMILY_RS400, 1, 1, 0, 0, 1 }, ++ { 0x5A41, CHIP_FAMILY_RS400, 0, 1, 0, 0, 1 }, ++ { 0x5A42, CHIP_FAMILY_RS400, 1, 1, 0, 0, 1 }, ++ { 0x5A61, CHIP_FAMILY_RS400, 0, 1, 0, 0, 1 }, ++ { 0x5A62, CHIP_FAMILY_RS400, 1, 1, 0, 0, 1 }, ++ { 0x5B60, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 }, ++ { 0x5B62, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 }, ++ { 0x5B63, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 }, ++ { 0x5B64, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 }, ++ { 0x5B65, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 }, ++ { 0x5C61, CHIP_FAMILY_RV280, 1, 0, 0, 0, 0 }, ++ { 0x5C63, CHIP_FAMILY_RV280, 1, 0, 0, 0, 0 }, ++ { 0x5D48, CHIP_FAMILY_R420, 1, 0, 0, 0, 0 }, ++ { 0x5D49, CHIP_FAMILY_R420, 1, 0, 0, 0, 0 }, ++ { 0x5D4A, CHIP_FAMILY_R420, 1, 0, 0, 0, 0 }, ++ { 0x5D4C, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, ++ { 0x5D4D, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, ++ { 0x5D4E, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, ++ { 0x5D4F, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, ++ { 0x5D50, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, ++ { 0x5D52, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, ++ { 0x5D57, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, ++ { 0x5E48, CHIP_FAMILY_RV410, 0, 0, 0, 0, 0 }, ++ { 0x5E4A, CHIP_FAMILY_RV410, 0, 0, 0, 0, 0 }, ++ { 0x5E4B, CHIP_FAMILY_RV410, 0, 0, 0, 0, 0 }, ++ { 0x5E4C, CHIP_FAMILY_RV410, 0, 0, 0, 0, 0 }, ++ { 0x5E4D, CHIP_FAMILY_RV410, 0, 0, 0, 0, 0 }, ++ { 0x5E4F, CHIP_FAMILY_RV410, 0, 0, 0, 0, 0 }, ++ { 0x7834, CHIP_FAMILY_RS300, 0, 1, 0, 0, 0 }, ++ { 0x7835, CHIP_FAMILY_RS300, 1, 1, 0, 0, 0 }, ++}; +diff --git a/src/radeon_chipset.h b/src/radeon_chipset.h +deleted file mode 100644 +index 890babd..0000000 +--- a/src/radeon_chipset.h ++++ /dev/null +@@ -1,142 +0,0 @@ +-static SymTabRec RADEONChipsets[] = { +- { PCI_CHIP_RADEON_QD, "ATI Radeon QD (AGP)" }, +- { PCI_CHIP_RADEON_QE, "ATI Radeon QE (AGP)" }, +- { PCI_CHIP_RADEON_QF, "ATI Radeon QF (AGP)" }, +- { PCI_CHIP_RADEON_QG, "ATI Radeon QG (AGP)" }, +- { PCI_CHIP_RV100_QY, "ATI Radeon VE/7000 QY (AGP/PCI)" }, +- { PCI_CHIP_RV100_QZ, "ATI Radeon VE/7000 QZ (AGP/PCI)" }, +- { PCI_CHIP_RN50_515E, "ATI ES1000 515E (PCI)" }, +- { PCI_CHIP_RN50_5969, "ATI ES1000 5969 (PCI)" }, +- { PCI_CHIP_RADEON_LW, "ATI Radeon Mobility M7 LW (AGP)" }, +- { PCI_CHIP_RADEON_LX, "ATI Mobility FireGL 7800 M7 LX (AGP)" }, +- { PCI_CHIP_RADEON_LY, "ATI Radeon Mobility M6 LY (AGP)" }, +- { PCI_CHIP_RADEON_LZ, "ATI Radeon Mobility M6 LZ (AGP)" }, +- { PCI_CHIP_RS100_4136, "ATI Radeon IGP320 (A3) 4136" }, +- { PCI_CHIP_RS100_4336, "ATI Radeon IGP320M (U1) 4336" }, +- { PCI_CHIP_RS200_4137, "ATI Radeon IGP330/340/350 (A4) 4137" }, +- { PCI_CHIP_RS200_4337, "ATI Radeon IGP330M/340M/350M (U2) 4337" }, +- { PCI_CHIP_RS250_4237, "ATI Radeon 7000 IGP (A4+) 4237" }, +- { PCI_CHIP_RS250_4437, "ATI Radeon Mobility 7000 IGP 4437" }, +- { PCI_CHIP_R200_QH, "ATI FireGL 8700/8800 QH (AGP)" }, +- { PCI_CHIP_R200_QL, "ATI Radeon 8500 QL (AGP)" }, +- { PCI_CHIP_R200_QM, "ATI Radeon 9100 QM (AGP)" }, +- { PCI_CHIP_R200_BB, "ATI Radeon 8500 AIW BB (AGP)" }, +- { PCI_CHIP_R200_BC, "ATI Radeon 8500 AIW BC (AGP)" }, +- { PCI_CHIP_RV200_QW, "ATI Radeon 7500 QW (AGP/PCI)" }, +- { PCI_CHIP_RV200_QX, "ATI Radeon 7500 QX (AGP/PCI)" }, +- { PCI_CHIP_RV250_If, "ATI Radeon 9000/PRO If (AGP/PCI)" }, +- { PCI_CHIP_RV250_Ig, "ATI Radeon 9000 Ig (AGP/PCI)" }, +- { PCI_CHIP_RV250_Ld, "ATI FireGL Mobility 9000 (M9) Ld (AGP)" }, +- { PCI_CHIP_RV250_Lf, "ATI Radeon Mobility 9000 (M9) Lf (AGP)" }, +- { PCI_CHIP_RV250_Lg, "ATI Radeon Mobility 9000 (M9) Lg (AGP)" }, +- { PCI_CHIP_RS300_5834, "ATI Radeon 9100 IGP (A5) 5834" }, +- { PCI_CHIP_RS300_5835, "ATI Radeon Mobility 9100 IGP (U3) 5835" }, +- { PCI_CHIP_RS350_7834, "ATI Radeon 9100 PRO IGP 7834" }, +- { PCI_CHIP_RS350_7835, "ATI Radeon Mobility 9200 IGP 7835" }, +- { PCI_CHIP_RV280_5960, "ATI Radeon 9250 5960 (AGP)" }, +- { PCI_CHIP_RV280_5961, "ATI Radeon 9200 5961 (AGP)" }, +- { PCI_CHIP_RV280_5962, "ATI Radeon 9200 5962 (AGP)" }, +- { PCI_CHIP_RV280_5964, "ATI Radeon 9200SE 5964 (AGP)" }, +- { PCI_CHIP_RV280_5965, "ATI FireMV 2200 (PCI)" }, +- { PCI_CHIP_RV280_5C61, "ATI Radeon Mobility 9200 (M9+) 5C61 (AGP)" }, +- { PCI_CHIP_RV280_5C63, "ATI Radeon Mobility 9200 (M9+) 5C63 (AGP)" }, +- { PCI_CHIP_R300_AD, "ATI Radeon 9500 AD (AGP)" }, +- { PCI_CHIP_R300_AE, "ATI Radeon 9500 AE (AGP)" }, +- { PCI_CHIP_R300_AF, "ATI Radeon 9600TX AF (AGP)" }, +- { PCI_CHIP_R300_AG, "ATI FireGL Z1 AG (AGP)" }, +- { PCI_CHIP_R300_ND, "ATI Radeon 9700 Pro ND (AGP)" }, +- { PCI_CHIP_R300_NE, "ATI Radeon 9700/9500Pro NE (AGP)" }, +- { PCI_CHIP_R300_NF, "ATI Radeon 9600TX NF (AGP)" }, +- { PCI_CHIP_R300_NG, "ATI FireGL X1 NG (AGP)" }, +- { PCI_CHIP_RV350_AP, "ATI Radeon 9600 AP (AGP)" }, +- { PCI_CHIP_RV350_AQ, "ATI Radeon 9600SE AQ (AGP)" }, +- { PCI_CHIP_RV360_AR, "ATI Radeon 9600XT AR (AGP)" }, +- { PCI_CHIP_RV350_AS, "ATI Radeon 9600 AS (AGP)" }, +- { PCI_CHIP_RV350_AT, "ATI FireGL T2 AT (AGP)" }, +- { PCI_CHIP_RV350_AV, "ATI FireGL RV360 AV (AGP)" }, +- { PCI_CHIP_RV350_NP, "ATI Radeon Mobility 9600/9700 (M10/M11) NP (AGP)" }, +- { PCI_CHIP_RV350_NQ, "ATI Radeon Mobility 9600 (M10) NQ (AGP)" }, +- { PCI_CHIP_RV350_NR, "ATI Radeon Mobility 9600 (M11) NR (AGP)" }, +- { PCI_CHIP_RV350_NS, "ATI Radeon Mobility 9600 (M10) NS (AGP)" }, +- { PCI_CHIP_RV350_NT, "ATI FireGL Mobility T2 (M10) NT (AGP)" }, +- { PCI_CHIP_RV350_NV, "ATI FireGL Mobility T2e (M11) NV (AGP)" }, +- { PCI_CHIP_RV350_4155, "ATI Radeon 9650" }, +- { PCI_CHIP_R350_AH, "ATI Radeon 9800SE AH (AGP)" }, +- { PCI_CHIP_R350_AI, "ATI Radeon 9800 AI (AGP)" }, +- { PCI_CHIP_R350_AJ, "ATI Radeon 9800 AJ (AGP)" }, +- { PCI_CHIP_R350_AK, "ATI FireGL X2 AK (AGP)" }, +- { PCI_CHIP_R350_NH, "ATI Radeon 9800PRO NH (AGP)" }, +- { PCI_CHIP_R350_NI, "ATI Radeon 9800 NI (AGP)" }, +- { PCI_CHIP_R350_NK, "ATI FireGL X2 NK (AGP)" }, +- { PCI_CHIP_R360_NJ, "ATI Radeon 9800XT NJ (AGP)" }, +- { PCI_CHIP_RV380_3E50, "ATI Radeon X600 (RV380) 3E50 (PCIE)" }, +- { PCI_CHIP_RV380_3E54, "ATI FireGL V3200 (RV380) 3E54 (PCIE)" }, +- { PCI_CHIP_RV380_3150, "ATI Radeon Mobility X600 (M24) 3150 (PCIE)" }, +- { PCI_CHIP_RV380_3152, "ATI Radeon Mobility X300 (M24) 3152 (PCIE)" }, +- { PCI_CHIP_RV380_3154, "ATI FireGL M24 GL 3154 (PCIE)" }, +- { PCI_CHIP_RV370_5B60, "ATI Radeon X300 (RV370) 5B60 (PCIE)" }, +- { PCI_CHIP_RV370_5B62, "ATI Radeon X600 (RV370) 5B62 (PCIE)" }, +- { PCI_CHIP_RV370_5B63, "ATI Radeon X550 (RV370) 5B63 (PCIE)" }, +- { PCI_CHIP_RV370_5B64, "ATI FireGL V3100 (RV370) 5B64 (PCIE)" }, +- { PCI_CHIP_RV370_5B65, "ATI FireMV 2200 PCIE (RV370) 5B65 (PCIE)" }, +- { PCI_CHIP_RV370_5460, "ATI Radeon Mobility X300 (M22) 5460 (PCIE)" }, +- { PCI_CHIP_RV370_5462, "ATI Radeon Mobility X600 SE (M24C) 5462 (PCIE)" }, +- { PCI_CHIP_RV370_5464, "ATI FireGL M22 GL 5464 (PCIE)" }, +- { PCI_CHIP_RS400_5A41, "ATI Radeon XPRESS 200 5A41 (PCIE)" }, +- { PCI_CHIP_RS400_5A42, "ATI Radeon XPRESS 200M 5A42 (PCIE)" }, +- { PCI_CHIP_RC410_5A61, "ATI Radeon XPRESS 200 5A61 (PCIE)" }, +- { PCI_CHIP_RC410_5A62, "ATI Radeon XPRESS 200M 5A62 (PCIE)" }, +- { PCI_CHIP_RS480_5954, "ATI Radeon XPRESS 200 5954 (PCIE)" }, +- { PCI_CHIP_RS480_5955, "ATI Radeon XPRESS 200M 5955 (PCIE)" }, +- { PCI_CHIP_RS482_5974, "ATI Radeon XPRESS 200 5974 (PCIE)" }, +- { PCI_CHIP_RS485_5975, "ATI Radeon XPRESS 200M 5975 (PCIE)" }, +- { PCI_CHIP_RV410_5E48, "ATI FireGL V5000 (RV410) (PCIE)" }, +- { PCI_CHIP_RV410_564A, "ATI Mobility FireGL V5000 (M26) (PCIE)" }, +- { PCI_CHIP_RV410_564B, "ATI Mobility FireGL V5000 (M26) (PCIE)" }, +- { PCI_CHIP_RV410_564F, "ATI Mobility Radeon X700 XL (M26) (PCIE)" }, +- { PCI_CHIP_RV410_5652, "ATI Mobility Radeon X700 (M26) (PCIE)" }, +- { PCI_CHIP_RV410_5653, "ATI Mobility Radeon X700 (M26) (PCIE)" }, +- { PCI_CHIP_RV410_5E4B, "ATI Radeon X700 PRO (RV410) (PCIE)" }, +- { PCI_CHIP_RV410_5E4A, "ATI Radeon X700 XT (RV410) (PCIE)" }, +- { PCI_CHIP_RV410_5E4D, "ATI Radeon X700 (RV410) (PCIE)" }, +- { PCI_CHIP_RV410_5E4C, "ATI Radeon X700 SE (RV410) (PCIE)" }, +- { PCI_CHIP_RV410_5E4F, "ATI Radeon X700 SE (RV410) (PCIE)" }, +- { PCI_CHIP_R420_JH, "ATI Radeon X800 (R420) JH (AGP)" }, +- { PCI_CHIP_R420_JI, "ATI Radeon X800PRO (R420) JI (AGP)" }, +- { PCI_CHIP_R420_JJ, "ATI Radeon X800SE (R420) JJ (AGP)" }, +- { PCI_CHIP_R420_JK, "ATI Radeon X800 (R420) JK (AGP)" }, +- { PCI_CHIP_R420_JL, "ATI Radeon X800 (R420) JL (AGP)" }, +- { PCI_CHIP_R420_JM, "ATI FireGL X3 (R420) JM (AGP)" }, +- { PCI_CHIP_R420_JN, "ATI Radeon Mobility 9800 (M18) JN (AGP)" }, +- { PCI_CHIP_R420_JP, "ATI Radeon X800XT (R420) JP (AGP)" }, +- { PCI_CHIP_R420_4A4F, "ATI Radeon X800 SE (R420) (AGP)" }, +- { PCI_CHIP_R420_4A54, "ATI Radeon AIW X800 VE (R420) JT (AGP)" }, +- { PCI_CHIP_R423_UH, "ATI Radeon X800 (R423) UH (PCIE)" }, +- { PCI_CHIP_R423_UI, "ATI Radeon X800PRO (R423) UI (PCIE)" }, +- { PCI_CHIP_R423_UJ, "ATI Radeon X800LE (R423) UJ (PCIE)" }, +- { PCI_CHIP_R423_UK, "ATI Radeon X800SE (R423) UK (PCIE)" }, +- { PCI_CHIP_R423_UQ, "ATI FireGL V5100 (R423) UQ (PCIE)" }, +- { PCI_CHIP_R423_UR, "ATI FireGL unknown (R423) UR (PCIE)" }, +- { PCI_CHIP_R423_UT, "ATI FireGL unknown (R423) UT (PCIE)" }, +- { PCI_CHIP_R423_5D57, "ATI Radeon X800XT (R423) 5D57 (PCIE)" }, +- { PCI_CHIP_R423_5550, "ATI FireGL V7100 (R423) (PCIE)" }, +- { PCI_CHIP_R430_5D49, "ATI Mobility FireGL V5100 (M28) (PCIE)" }, +- { PCI_CHIP_R430_5D4A, "ATI Mobility Radeon X800 (M28) (PCIE)" }, +- { PCI_CHIP_R430_5D48, "ATI Mobility Radeon X800 XT (M28) (PCIE)" }, +- { PCI_CHIP_R430_554F, "ATI Radeon X800 (R430) (PCIE)" }, +- { PCI_CHIP_R430_554D, "ATI Radeon X800 XL (R430) (PCIE)" }, +- { PCI_CHIP_R430_554E, "ATI Radeon X800 SE (R430) (PCIE)" }, +- { PCI_CHIP_R430_554C, "ATI Radeon X800 XTP (R430) (PCIE)" }, +- { PCI_CHIP_R480_5D4C, "ATI Radeon X850 5D4C (PCIE)" }, +- { PCI_CHIP_R480_5D50, "ATI unknown Radeon / FireGL (R480) 5D50 (PCIE)" }, +- { PCI_CHIP_R480_5D4E, "ATI Radeon X850 SE (R480) (PCIE)" }, +- { PCI_CHIP_R480_5D4F, "ATI Radeon X850 PRO (R480) (PCIE)" }, +- { PCI_CHIP_R480_5D52, "ATI Radeon X850 XT (R480) (PCIE)" }, +- { PCI_CHIP_R480_5D4D, "ATI Radeon X850 XT PE (R480) (PCIE)" }, +- { PCI_CHIP_R481_4B4B, "ATI Radeon X850 PRO (R480) (AGP)" }, +- { PCI_CHIP_R481_4B4A, "ATI Radeon X850 SE (R480) (AGP)" }, +- { PCI_CHIP_R481_4B49, "ATI Radeon X850 XT (R480) (AGP)" }, +- { PCI_CHIP_R481_4B4C, "ATI Radeon X850 XT PE (R480) (AGP)" }, +- +- { -1, NULL } +-}; +diff --git a/src/radeon_chipset_gen.h b/src/radeon_chipset_gen.h +new file mode 100644 +index 0000000..0a7a9c1 +--- /dev/null ++++ b/src/radeon_chipset_gen.h +@@ -0,0 +1,141 @@ ++/* This file is autogenerated please do not edit */ ++static SymTabRec RADEONChipsets[] = { ++ { PCI_CHIP_RV380_3150, "ATI Radeon Mobility X600 (M24) 3150 (PCIE)" }, ++ { PCI_CHIP_RV380_3152, "ATI Radeon Mobility X300 (M24) 3152 (PCIE)" }, ++ { PCI_CHIP_RV380_3154, "ATI FireGL M24 GL 3154 (PCIE)" }, ++ { PCI_CHIP_RV380_3E50, "ATI Radeon X600 (RV380) 3E50 (PCIE)" }, ++ { PCI_CHIP_RV380_3E54, "ATI FireGL V3200 (RV380) 3E54 (PCIE)" }, ++ { PCI_CHIP_RS100_4136, "ATI Radeon IGP320 (A3) 4136" }, ++ { PCI_CHIP_RS200_4137, "ATI Radeon IGP330/340/350 (A4) 4137" }, ++ { PCI_CHIP_R300_AD, "ATI Radeon 9500 AD (AGP)" }, ++ { PCI_CHIP_R300_AE, "ATI Radeon 9500 AE (AGP)" }, ++ { PCI_CHIP_R300_AF, "ATI Radeon 9600TX AF (AGP)" }, ++ { PCI_CHIP_R300_AG, "ATI FireGL Z1 AG (AGP)" }, ++ { PCI_CHIP_R350_AH, "ATI Radeon 9800SE AH (AGP)" }, ++ { PCI_CHIP_R350_AI, "ATI Radeon 9800 AI (AGP)" }, ++ { PCI_CHIP_R350_AJ, "ATI Radeon 9800 AJ (AGP)" }, ++ { PCI_CHIP_R350_AK, "ATI FireGL X2 AK (AGP)" }, ++ { PCI_CHIP_RV350_AP, "ATI Radeon 9600 AP (AGP)" }, ++ { PCI_CHIP_RV350_AQ, "ATI Radeon 9600SE AQ (AGP)" }, ++ { PCI_CHIP_RV360_AR, "ATI Radeon 9600XT AR (AGP)" }, ++ { PCI_CHIP_RV350_AS, "ATI Radeon 9600 AS (AGP)" }, ++ { PCI_CHIP_RV350_AT, "ATI FireGL T2 AT (AGP)" }, ++ { PCI_CHIP_RV350_4155, "ATI Radeon 9650" }, ++ { PCI_CHIP_RV350_AV, "ATI FireGL RV360 AV (AGP)" }, ++ { PCI_CHIP_RS250_4237, "ATI Radeon 7000 IGP (A4+) 4237" }, ++ { PCI_CHIP_R200_BB, "ATI Radeon 8500 AIW BB (AGP)" }, ++ { PCI_CHIP_R200_BC, "ATI Radeon 8500 AIW BC (AGP)" }, ++ { PCI_CHIP_RS100_4336, "ATI Radeon IGP320M (U1) 4336" }, ++ { PCI_CHIP_RS200_4337, "ATI Radeon IGP330M/340M/350M (U2) 4337" }, ++ { PCI_CHIP_RS250_4437, "ATI Radeon Mobility 7000 IGP 4437" }, ++ { PCI_CHIP_RV250_If, "ATI Radeon 9000/PRO If (AGP/PCI)" }, ++ { PCI_CHIP_RV250_Ig, "ATI Radeon 9000 Ig (AGP/PCI)" }, ++ { PCI_CHIP_R420_JH, "ATI Radeon X800 (R420) JH (AGP)" }, ++ { PCI_CHIP_R420_JI, "ATI Radeon X800PRO (R420) JI (AGP)" }, ++ { PCI_CHIP_R420_JJ, "ATI Radeon X800SE (R420) JJ (AGP)" }, ++ { PCI_CHIP_R420_JK, "ATI Radeon X800 (R420) JK (AGP)" }, ++ { PCI_CHIP_R420_JL, "ATI Radeon X800 (R420) JL (AGP)" }, ++ { PCI_CHIP_R420_JM, "ATI FireGL X3 (R420) JM (AGP)" }, ++ { PCI_CHIP_R420_JN, "ATI Radeon Mobility 9800 (M18) JN (AGP)" }, ++ { PCI_CHIP_R420_4A4F, "ATI Radeon X800 SE (R420) (AGP)" }, ++ { PCI_CHIP_R420_JP, "ATI Radeon X800XT (R420) JP (AGP)" }, ++ { PCI_CHIP_R481_4B49, "ATI Radeon X850 XT (R480) (AGP)" }, ++ { PCI_CHIP_R481_4B4A, "ATI Radeon X850 SE (R480) (AGP)" }, ++ { PCI_CHIP_R481_4B4B, "ATI Radeon X850 PRO (R480) (AGP)" }, ++ { PCI_CHIP_R481_4B4C, "ATI Radeon X850 XT PE (R480) (AGP)" }, ++ { PCI_CHIP_RADEON_LW, "ATI Radeon Mobility M7 LW (AGP)" }, ++ { PCI_CHIP_RADEON_LX, "ATI Mobility FireGL 7800 M7 LX (AGP)" }, ++ { PCI_CHIP_RADEON_LY, "ATI Radeon Mobility M6 LY (AGP)" }, ++ { PCI_CHIP_RADEON_LZ, "ATI Radeon Mobility M6 LZ (AGP)" }, ++ { PCI_CHIP_RV250_Ld, "ATI FireGL Mobility 9000 (M9) Ld (AGP)" }, ++ { PCI_CHIP_RV250_Lf, "ATI Radeon Mobility 9000 (M9) Lf (AGP)" }, ++ { PCI_CHIP_RV250_Lg, "ATI Radeon Mobility 9000 (M9) Lg (AGP)" }, ++ { PCI_CHIP_R300_ND, "ATI Radeon 9700 Pro ND (AGP)" }, ++ { PCI_CHIP_R300_NE, "ATI Radeon 9700/9500Pro NE (AGP)" }, ++ { PCI_CHIP_R300_NF, "ATI Radeon 9600TX NF (AGP)" }, ++ { PCI_CHIP_R300_NG, "ATI FireGL X1 NG (AGP)" }, ++ { PCI_CHIP_R350_NH, "ATI Radeon 9800PRO NH (AGP)" }, ++ { PCI_CHIP_R350_NI, "ATI Radeon 9800 NI (AGP)" }, ++ { PCI_CHIP_R360_NJ, "ATI FireGL X2 NK (AGP)" }, ++ { PCI_CHIP_R350_NK, "ATI Radeon 9800XT NJ (AGP)" }, ++ { PCI_CHIP_RV350_NP, "ATI Radeon Mobility 9600/9700 (M10/M11) NP (AGP)" }, ++ { PCI_CHIP_RV350_NQ, "ATI Radeon Mobility 9600 (M10) NQ (AGP)" }, ++ { PCI_CHIP_RV350_NR, "ATI Radeon Mobility 9600 (M11) NR (AGP)" }, ++ { PCI_CHIP_RV350_NS, "ATI Radeon Mobility 9600 (M10) NS (AGP)" }, ++ { PCI_CHIP_RV350_NT, "ATI FireGL Mobility T2 (M10) NT (AGP)" }, ++ { PCI_CHIP_RV350_NV, "ATI FireGL Mobility T2e (M11) NV (AGP)" }, ++ { PCI_CHIP_RADEON_QD, "ATI Radeon QD (AGP)" }, ++ { PCI_CHIP_RADEON_QE, "ATI Radeon QE (AGP)" }, ++ { PCI_CHIP_RADEON_QF, "ATI Radeon QF (AGP)" }, ++ { PCI_CHIP_RADEON_QG, "ATI Radeon QG (AGP)" }, ++ { PCI_CHIP_R200_QH, "ATI FireGL 8700/8800 QH (AGP)" }, ++ { PCI_CHIP_R200_QL, "ATI Radeon 8500 QL (AGP)" }, ++ { PCI_CHIP_R200_QM, "ATI Radeon 9100 QM (AGP)" }, ++ { PCI_CHIP_RV200_QW, "ATI Radeon 7500 QW (AGP/PCI)" }, ++ { PCI_CHIP_RV200_QX, "ATI Radeon 7500 QX (AGP/PCI)" }, ++ { PCI_CHIP_RV100_QY, "ATI Radeon VE/7000 QY (AGP/PCI)" }, ++ { PCI_CHIP_RV100_QZ, "ATI Radeon VE/7000 QZ (AGP/PCI)" }, ++ { PCI_CHIP_RN50_515E, "ATI ES1000 515E (PCI)" }, ++ { PCI_CHIP_RV370_5460, "ATI Radeon Mobility X300 (M22) 5460 (PCIE)" }, ++ { PCI_CHIP_RV370_5462, "ATI Radeon Mobility X600 SE (M24C) 5462 (PCIE)" }, ++ { PCI_CHIP_RV370_5464, "ATI FireGL M22 GL 5464 (PCIE)" }, ++ { PCI_CHIP_R423_UH, "ATI Radeon X800 (R423) UH (PCIE)" }, ++ { PCI_CHIP_R423_UI, "ATI Radeon X800PRO (R423) UI (PCIE)" }, ++ { PCI_CHIP_R423_UJ, "ATI Radeon X800LE (R423) UJ (PCIE)" }, ++ { PCI_CHIP_R423_UK, "ATI Radeon X800SE (R423) UK (PCIE)" }, ++ { PCI_CHIP_R430_554C, "ATI Radeon X800 XTP (R430) (PCIE)" }, ++ { PCI_CHIP_R430_554D, "ATI Radeon X800 XL (R430) (PCIE)" }, ++ { PCI_CHIP_R430_554E, "ATI Radeon X800 SE (R430) (PCIE)" }, ++ { PCI_CHIP_R430_554F, "ATI Radeon X800 (R430) (PCIE)" }, ++ { PCI_CHIP_R423_5550, "ATI FireGL V7100 (R423) (PCIE)" }, ++ { PCI_CHIP_R423_UQ, "ATI FireGL V5100 (R423) UQ (PCIE)" }, ++ { PCI_CHIP_R423_UR, "ATI FireGL unknown (R423) UR (PCIE)" }, ++ { PCI_CHIP_R423_UT, "ATI FireGL unknown (R423) UT (PCIE)" }, ++ { PCI_CHIP_RV410_564A, "ATI Mobility FireGL V5000 (M26) (PCIE)" }, ++ { PCI_CHIP_RV410_564B, "ATI Mobility FireGL V5000 (M26) (PCIE)" }, ++ { PCI_CHIP_RV410_564F, "ATI Mobility Radeon X700 XL (M26) (PCIE)" }, ++ { PCI_CHIP_RV410_5652, "ATI Mobility Radeon X700 (M26) (PCIE)" }, ++ { PCI_CHIP_RV410_5653, "ATI Mobility Radeon X700 (M26) (PCIE)" }, ++ { PCI_CHIP_RS300_5834, "ATI Radeon 9100 IGP (A5) 5834" }, ++ { PCI_CHIP_RS300_5835, "ATI Radeon Mobility 9100 IGP (U3) 5835" }, ++ { PCI_CHIP_RS480_5954, "ATI Radeon XPRESS 200 5954 (PCIE)" }, ++ { PCI_CHIP_RS480_5955, "ATI Radeon XPRESS 200M 5955 (PCIE)" }, ++ { PCI_CHIP_RV280_5960, "ATI Radeon 9250 5960 (AGP)" }, ++ { PCI_CHIP_RV280_5961, "ATI Radeon 9200 5961 (AGP)" }, ++ { PCI_CHIP_RV280_5962, "ATI Radeon 9200 5962 (AGP)" }, ++ { PCI_CHIP_RV280_5964, "ATI Radeon 9200SE 5964 (AGP)" }, ++ { PCI_CHIP_RV280_5965, "ATI FireMV 2200 (PCI)" }, ++ { PCI_CHIP_RN50_5969, "ATI ES1000 5969 (PCI)" }, ++ { PCI_CHIP_RS482_5974, "ATI Radeon XPRESS 200 5974 (PCIE)" }, ++ { PCI_CHIP_RS485_5975, "ATI Radeon XPRESS 200M 5975 (PCIE)" }, ++ { PCI_CHIP_RS400_5A41, "ATI Radeon XPRESS 200 5A41 (PCIE)" }, ++ { PCI_CHIP_RS400_5A42, "ATI Radeon XPRESS 200M 5A42 (PCIE)" }, ++ { PCI_CHIP_RC410_5A61, "ATI Radeon XPRESS 200 5A61 (PCIE)" }, ++ { PCI_CHIP_RC410_5A62, "ATI Radeon XPRESS 200M 5A62 (PCIE)" }, ++ { PCI_CHIP_RV370_5B60, "ATI Radeon X300 (RV370) 5B60 (PCIE)" }, ++ { PCI_CHIP_RV370_5B62, "ATI Radeon X600 (RV370) 5B62 (PCIE)" }, ++ { PCI_CHIP_RV370_5B63, "ATI Radeon X550 (RV370) 5B63 (PCIE)" }, ++ { PCI_CHIP_RV370_5B64, "ATI FireGL V3100 (RV370) 5B64 (PCIE)" }, ++ { PCI_CHIP_RV370_5B65, "ATI FireMV 2200 PCIE (RV370) 5B65 (PCIE)" }, ++ { PCI_CHIP_RV280_5C61, "ATI Radeon Mobility 9200 (M9+) 5C61 (AGP)" }, ++ { PCI_CHIP_RV280_5C63, "ATI Radeon Mobility 9200 (M9+) 5C63 (AGP)" }, ++ { PCI_CHIP_R430_5D48, "ATI Mobility Radeon X800 XT (M28) (PCIE)" }, ++ { PCI_CHIP_R430_5D49, "ATI Mobility FireGL V5100 (M28) (PCIE)" }, ++ { PCI_CHIP_R430_5D4A, "ATI Mobility Radeon X800 (M28) (PCIE)" }, ++ { PCI_CHIP_R480_5D4C, "ATI Radeon X850 5D4C (PCIE)" }, ++ { PCI_CHIP_R480_5D4D, "ATI Radeon X850 XT PE (R480) (PCIE)" }, ++ { PCI_CHIP_R480_5D4E, "ATI Radeon X850 SE (R480) (PCIE)" }, ++ { PCI_CHIP_R480_5D4F, "ATI Radeon X850 PRO (R480) (PCIE)" }, ++ { PCI_CHIP_R480_5D50, "ATI unknown Radeon / FireGL (R480) 5D50 (PCIE)" }, ++ { PCI_CHIP_R480_5D52, "ATI Radeon X850 XT (R480) (PCIE)" }, ++ { PCI_CHIP_R423_5D57, "ATI Radeon X800XT (R423) 5D57 (PCIE)" }, ++ { PCI_CHIP_RV410_5E48, "ATI FireGL V5000 (RV410) (PCIE)" }, ++ { PCI_CHIP_RV410_5E4A, "ATI Radeon X700 XT (RV410) (PCIE)" }, ++ { PCI_CHIP_RV410_5E4B, "ATI Radeon X700 PRO (RV410) (PCIE)" }, ++ { PCI_CHIP_RV410_5E4C, "ATI Radeon X700 SE (RV410) (PCIE)" }, ++ { PCI_CHIP_RV410_5E4D, "ATI Radeon X700 (RV410) (PCIE)" }, ++ { PCI_CHIP_RV410_5E4F, "ATI Radeon X700 SE (RV410) (PCIE)" }, ++ { PCI_CHIP_RS350_7834, "ATI Radeon 9100 PRO IGP 7834" }, ++ { PCI_CHIP_RS350_7835, "ATI Radeon Mobility 9200 IGP 7835" }, ++ { -1, NULL } ++}; +diff --git a/src/radeon_commonfuncs.c b/src/radeon_commonfuncs.c +index 6a999af..a1802f8 100644 +--- a/src/radeon_commonfuncs.c ++++ b/src/radeon_commonfuncs.c +@@ -174,8 +174,8 @@ void FUNC_NAME(RADEONWaitForIdle)(ScrnInfoPtr pScrn) + } + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "Idle timed out: %u entries, stat=0x%08x\n", +- INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK, +- INREG(RADEON_RBBM_STATUS)); ++ (unsigned int)INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK, ++ (unsigned int)INREG(RADEON_RBBM_STATUS)); + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, + "Idle timed out, resetting engine...\n"); + RADEONEngineReset(pScrn); +diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c +index de24273..07857dd 100644 +--- a/src/radeon_crtc.c ++++ b/src/radeon_crtc.c +@@ -145,15 +145,13 @@ RADEONInitCommonRegisters(RADEONSavePtr save, RADEONInfoPtr info) + static void + RADEONInitSurfaceCntl(xf86CrtcPtr crtc, RADEONSavePtr save) + { +- ScrnInfoPtr pScrn = crtc->scrn; +- + save->surface_cntl = 0; + + #if X_BYTE_ORDER == X_BIG_ENDIAN + /* We must set both apertures as they can be both used to map the entire + * video memory. -BenH. + */ +- switch (pScrn->bitsPerPixel) { ++ switch (crtc->scrn->bitsPerPixel) { + case 16: + save->surface_cntl |= RADEON_NONSURF_AP0_SWP_16BPP; + save->surface_cntl |= RADEON_NONSURF_AP1_SWP_16BPP; +@@ -606,19 +604,108 @@ RADEONInitCrtc2Registers(xf86CrtcPtr crtc, RADEONSavePtr save, + } + + +-/* Compute n/d with rounding */ + static int RADEONDiv(int n, int d) + { + return (n + (d / 2)) / d; + } + ++static void ++RADEONComputePLL(RADEONPLLPtr pll, ++ unsigned long freq, ++ CARD32 *chosen_dot_clock_freq, ++ CARD32 *chosen_feedback_div, ++ CARD32 *chosen_reference_div, ++ CARD32 *chosen_post_div, ++ int flags) ++{ ++ int post_divs[] = {1, 2, 4, 8, 3, 6, 12, 0}; ++ ++ int i; ++ ++ CARD32 min_ref_div = pll->min_ref_div; ++ CARD32 max_ref_div = pll->max_ref_div; ++ CARD32 best_vco = pll->best_vco; ++ CARD32 best_post_div = 1; ++ CARD32 best_ref_div = 1; ++ CARD32 best_feedback_div = 1; ++ CARD32 best_freq = 1; ++ CARD32 best_error = 0xffffffff; ++ CARD32 best_vco_diff = 1; ++ ++ freq = freq / 10; ++ ++ ErrorF("freq: %lu\n", freq); ++ ++ if (flags & RADEON_PLL_USE_REF_DIV) ++ min_ref_div = max_ref_div = pll->reference_div; ++ ++ for (i = 0; post_divs[i]; i++) { ++ int post_div = post_divs[i]; ++ CARD32 ref_div; ++ CARD32 vco = freq * post_div; ++ ++ if ((flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1)) ++ continue; ++ ++ if (vco < pll->min_pll_freq || vco > pll->max_pll_freq) ++ continue; ++ ++ for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) { ++ CARD32 feedback_div, current_freq, error, vco_diff; ++ CARD32 pll_in = pll->reference_freq / ref_div; ++ ++ if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max) ++ continue; ++ ++ feedback_div = RADEONDiv(freq * ref_div * post_div, ++ pll->reference_freq); ++ ++ if (feedback_div < pll->min_feedback_div || feedback_div > pll->max_feedback_div) ++ continue; ++ ++ current_freq = RADEONDiv(pll->reference_freq * feedback_div, ++ ref_div * post_div); ++ ++ error = abs(current_freq - freq); ++ vco_diff = abs(vco - best_vco); ++ ++ if ((best_vco == 0 && error < best_error) || ++ (best_vco != 0 && ++ (error < best_error - 1000 || ++ (abs(error - best_error) < 100 && vco_diff < best_vco_diff )))) { ++ best_post_div = post_div; ++ best_ref_div = ref_div; ++ best_feedback_div = feedback_div; ++ best_freq = current_freq; ++ best_error = error; ++ best_vco_diff = vco_diff; ++ } ++ } ++ } ++ ++ ErrorF("best_freq: %u\n", (unsigned)best_freq); ++ ErrorF("best_feedback_div: %u\n", (unsigned)best_feedback_div); ++ ErrorF("best_ref_div: %u\n", (unsigned)best_ref_div); ++ ErrorF("best_post_div: %u\n", (unsigned)best_post_div); ++ ++ *chosen_dot_clock_freq = best_freq; ++ *chosen_feedback_div = best_feedback_div; ++ *chosen_reference_div = best_ref_div; ++ *chosen_post_div = best_post_div; ++ ++} ++ + /* Define PLL registers for requested video mode */ + static void +-RADEONInitPLLRegisters(ScrnInfoPtr pScrn, RADEONInfoPtr info, +- RADEONSavePtr save, RADEONPLLPtr pll, +- double dot_clock) ++RADEONInitPLLRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save, ++ RADEONPLLPtr pll, DisplayModePtr mode, ++ int flags) + { +- unsigned long freq = dot_clock * 100; ++ RADEONInfoPtr info = RADEONPTR(pScrn); ++ CARD32 feedback_div = 0; ++ CARD32 reference_div = 0; ++ CARD32 post_divider = 0; ++ CARD32 freq = 0; + + struct { + int divider; +@@ -640,21 +727,19 @@ RADEONInitPLLRegisters(ScrnInfoPtr pScrn, RADEONInfoPtr info, + { 0, 0 } + }; + +- if (info->UseBiosDividers) { ++ ++ if ((flags & RADEON_PLL_USE_BIOS_DIVS) && info->UseBiosDividers) { + save->ppll_ref_div = info->RefDivider; + save->ppll_div_3 = info->FeedbackDivider | (info->PostDivider << 16); + save->htotal_cntl = 0; + return; + } + +- if (freq > pll->max_pll_freq) freq = pll->max_pll_freq; +- if (freq * 12 < pll->min_pll_freq) freq = pll->min_pll_freq / 12; ++ RADEONComputePLL(pll, mode->Clock, &freq, &feedback_div, &reference_div, &post_divider, flags); + + for (post_div = &post_divs[0]; post_div->divider; ++post_div) { +- save->pll_output_freq = post_div->divider * freq; +- +- if (save->pll_output_freq >= pll->min_pll_freq +- && save->pll_output_freq <= pll->max_pll_freq) break; ++ if (post_div->divider == post_divider) ++ break; + } + + if (!post_div->divider) { +@@ -663,19 +748,19 @@ RADEONInitPLLRegisters(ScrnInfoPtr pScrn, RADEONInfoPtr info, + } + + save->dot_clock_freq = freq; +- save->feedback_div = RADEONDiv(pll->reference_div +- * save->pll_output_freq, +- pll->reference_freq); +- save->post_div = post_div->divider; ++ save->feedback_div = feedback_div; ++ save->reference_div = reference_div; ++ save->post_div = post_divider; + + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, +- "dc=%u, of=%u, fd=%d, pd=%d\n", ++ "dc=%u, of=%u, fd=%d, rd=%d, pd=%d\n", + (unsigned)save->dot_clock_freq, + (unsigned)save->pll_output_freq, + save->feedback_div, ++ save->reference_div, + save->post_div); + +- save->ppll_ref_div = pll->reference_div; ++ save->ppll_ref_div = save->reference_div; + + #if defined(__powerpc__) + /* apparently programming this otherwise causes a hang??? */ +@@ -685,21 +770,24 @@ RADEONInitPLLRegisters(ScrnInfoPtr pScrn, RADEONInfoPtr info, + #endif + save->ppll_div_3 = (save->feedback_div | (post_div->bitvalue << 16)); + +- save->htotal_cntl = 0; ++ save->htotal_cntl = mode->HTotal & 0x7; + +- save->vclk_ecp_cntl = (info->SavedReg.vclk_ecp_cntl & +- ~RADEON_VCLK_SRC_SEL_MASK) | RADEON_VCLK_SRC_SEL_PPLLCLK; ++ save->vclk_ecp_cntl = (info->SavedReg.vclk_ecp_cntl & ++ ~RADEON_VCLK_SRC_SEL_MASK) | RADEON_VCLK_SRC_SEL_PPLLCLK; + + } + + /* Define PLL2 registers for requested video mode */ + static void + RADEONInitPLL2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save, +- RADEONPLLPtr pll, double dot_clock, +- int no_odd_postdiv) ++ RADEONPLLPtr pll, DisplayModePtr mode, ++ int flags) + { +- RADEONInfoPtr info = RADEONPTR(pScrn); +- unsigned long freq = dot_clock * 100; ++ RADEONInfoPtr info = RADEONPTR(pScrn); ++ CARD32 feedback_div = 0; ++ CARD32 reference_div = 0; ++ CARD32 post_divider = 0; ++ CARD32 freq = 0; + + struct { + int divider; +@@ -720,18 +808,18 @@ RADEONInitPLL2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save, + { 0, 0 } + }; + +- if (freq > pll->max_pll_freq) freq = pll->max_pll_freq; +- if (freq * 12 < pll->min_pll_freq) freq = pll->min_pll_freq / 12; ++ if ((flags & RADEON_PLL_USE_BIOS_DIVS) && info->UseBiosDividers) { ++ save->p2pll_ref_div = info->RefDivider; ++ save->p2pll_div_0 = info->FeedbackDivider | (info->PostDivider << 16); ++ save->htotal_cntl2 = 0; ++ return; ++ } ++ ++ RADEONComputePLL(pll, mode->Clock, &freq, &feedback_div, &reference_div, &post_divider, flags); + + for (post_div = &post_divs[0]; post_div->divider; ++post_div) { +- /* Odd post divider value don't work properly on the second digital +- * output +- */ +- if (no_odd_postdiv && (post_div->divider & 1)) +- continue; +- save->pll_output_freq_2 = post_div->divider * freq; +- if (save->pll_output_freq_2 >= pll->min_pll_freq +- && save->pll_output_freq_2 <= pll->max_pll_freq) break; ++ if (post_div->divider == post_divider) ++ break; + } + + if (!post_div->divider) { +@@ -740,26 +828,28 @@ RADEONInitPLL2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save, + } + + save->dot_clock_freq_2 = freq; +- save->feedback_div_2 = RADEONDiv(pll->reference_div +- * save->pll_output_freq_2, +- pll->reference_freq); +- save->post_div_2 = post_div->divider; ++ save->feedback_div_2 = feedback_div; ++ save->reference_div_2 = reference_div; ++ save->post_div_2 = post_divider; + + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, +- "dc=%u, of=%u, fd=%d, pd=%d\n", ++ "dc=%u, of=%u, fd=%d, rd=%d, pd=%d\n", + (unsigned)save->dot_clock_freq_2, + (unsigned)save->pll_output_freq_2, + save->feedback_div_2, ++ save->reference_div_2, + save->post_div_2); + +- save->p2pll_ref_div = pll->reference_div; ++ save->p2pll_ref_div = save->reference_div_2; ++ + save->p2pll_div_0 = (save->feedback_div_2 | + (post_div->bitvalue << 16)); +- save->htotal_cntl2 = 0; + +- save->pixclks_cntl = ((info->SavedReg.pixclks_cntl & +- ~(RADEON_PIX2CLK_SRC_SEL_MASK)) | +- RADEON_PIX2CLK_SRC_SEL_P2PLLCLK); ++ save->htotal_cntl2 = mode->HTotal & 0x7; ++ ++ save->pixclks_cntl = ((info->SavedReg.pixclks_cntl & ++ ~(RADEON_PIX2CLK_SRC_SEL_MASK)) | ++ RADEON_PIX2CLK_SRC_SEL_P2PLLCLK); + + } + +@@ -769,8 +859,8 @@ RADEONInitBIOSRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save) + RADEONInfoPtr info = RADEONPTR(pScrn); + + /* tell the bios not to muck with the hardware on events */ +- save->bios_4_scratch = 0; +- save->bios_5_scratch = 0xff00; ++ save->bios_4_scratch = 0x4; /* 0x4 needed for backlight */ ++ save->bios_5_scratch = (info->SavedReg.bios_5_scratch & 0xff) | 0xff00; /* bits 0-3 keep backlight level */ + save->bios_6_scratch = info->SavedReg.bios_6_scratch | 0x40000000; + + } +@@ -792,8 +882,8 @@ radeon_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode, + RADEONInfoPtr info = RADEONPTR(pScrn); + Bool tilingOld = info->tilingEnabled; + int i = 0; +- double dot_clock = 0; +- Bool no_odd_post_div = FALSE; ++ double dot_clock = 0; ++ int pll_flags = 0; + Bool update_tv_routing = FALSE; + + +@@ -818,7 +908,9 @@ radeon_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode, + + if (output->crtc == crtc) { + if (radeon_output->MonType != MT_CRT) +- no_odd_post_div = TRUE; ++ pll_flags |= RADEON_PLL_NO_ODD_POST_DIV; ++ if (radeon_output->MonType == MT_LCD) ++ pll_flags |= (RADEON_PLL_USE_BIOS_DIVS | RADEON_PLL_USE_REF_DIV); + } + } + +@@ -837,25 +929,25 @@ radeon_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode, + ErrorF("init crtc1\n"); + RADEONInitCrtcRegisters(crtc, &info->ModeReg, adjusted_mode); + RADEONInitCrtcBase(crtc, &info->ModeReg, x, y); +- dot_clock = adjusted_mode->Clock / 1000.0; +- if (dot_clock) { ++ dot_clock = adjusted_mode->Clock / 1000.0; ++ if (dot_clock) { + ErrorF("init pll1\n"); +- RADEONInitPLLRegisters(pScrn, info, &info->ModeReg, &info->pll, dot_clock); +- } else { +- info->ModeReg.ppll_ref_div = info->SavedReg.ppll_ref_div; +- info->ModeReg.ppll_div_3 = info->SavedReg.ppll_div_3; +- info->ModeReg.htotal_cntl = info->SavedReg.htotal_cntl; +- } ++ RADEONInitPLLRegisters(pScrn, &info->ModeReg, &info->pll, adjusted_mode, pll_flags); ++ } else { ++ info->ModeReg.ppll_ref_div = info->SavedReg.ppll_ref_div; ++ info->ModeReg.ppll_div_3 = info->SavedReg.ppll_div_3; ++ info->ModeReg.htotal_cntl = info->SavedReg.htotal_cntl; ++ } + break; + case 1: + ErrorF("init crtc2\n"); +- RADEONInitCrtc2Registers(crtc, &info->ModeReg, adjusted_mode); ++ RADEONInitCrtc2Registers(crtc, &info->ModeReg, adjusted_mode); + RADEONInitCrtc2Base(crtc, &info->ModeReg, x, y); +- dot_clock = adjusted_mode->Clock / 1000.0; +- if (dot_clock) { ++ dot_clock = adjusted_mode->Clock / 1000.0; ++ if (dot_clock) { + ErrorF("init pll2\n"); +- RADEONInitPLL2Registers(pScrn, &info->ModeReg, &info->pll, dot_clock, no_odd_post_div); +- } ++ RADEONInitPLL2Registers(pScrn, &info->ModeReg, &info->pll, adjusted_mode, pll_flags); ++ } + break; + } + +diff --git a/src/radeon_cursor.c b/src/radeon_cursor.c +index b8cfffd..ba1159c 100644 +--- a/src/radeon_cursor.c ++++ b/src/radeon_cursor.c +@@ -166,9 +166,9 @@ radeon_crtc_set_cursor_position (xf86CrtcPtr crtc, int x, int y) + | ((xorigin ? 0 : x) << 16) + | (yorigin ? 0 : y))); + RADEONCTRACE(("cursor_offset: 0x%x, yorigin: %d, stride: %d, temp %08X\n", +- info->cursor_offset + pScrn->fbOffset, yorigin, stride, temp)); ++ radeon_crtc->cursor_offset + pScrn->fbOffset, yorigin, stride, temp)); + OUTREG(RADEON_CUR_OFFSET, +- info->cursor_offset + pScrn->fbOffset + yorigin * stride); ++ radeon_crtc->cursor_offset + pScrn->fbOffset + yorigin * stride); + } else if (crtc_id == 1) { + OUTREG(RADEON_CUR2_HORZ_VERT_OFF, (RADEON_CUR2_LOCK + | (xorigin << 16) +@@ -177,9 +177,9 @@ radeon_crtc_set_cursor_position (xf86CrtcPtr crtc, int x, int y) + | ((xorigin ? 0 : x) << 16) + | (yorigin ? 0 : y))); + RADEONCTRACE(("cursor_offset2: 0x%x, yorigin: %d, stride: %d, temp %08X\n", +- info->cursor_offset + pScrn->fbOffset, yorigin, stride, temp)); ++ radeon_crtc->cursor_offset + pScrn->fbOffset, yorigin, stride, temp)); + OUTREG(RADEON_CUR2_OFFSET, +- info->cursor_offset + pScrn->fbOffset + yorigin * stride); ++ radeon_crtc->cursor_offset + pScrn->fbOffset + yorigin * stride); + } + + } +@@ -188,8 +188,9 @@ void + radeon_crtc_set_cursor_colors (xf86CrtcPtr crtc, int bg, int fg) + { + ScrnInfoPtr pScrn = crtc->scrn; ++ RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; + RADEONInfoPtr info = RADEONPTR(pScrn); +- CARD32 *pixels = (CARD32 *)(pointer)(info->FB + info->cursor_offset + pScrn->fbOffset); ++ CARD32 *pixels = (CARD32 *)(pointer)(info->FB + radeon_crtc->cursor_offset + pScrn->fbOffset); + int pixel, i; + CURSOR_SWAPPING_DECL_MMIO + +@@ -229,9 +230,10 @@ void + radeon_crtc_load_cursor_argb (xf86CrtcPtr crtc, CARD32 *image) + { + ScrnInfoPtr pScrn = crtc->scrn; ++ RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; + RADEONInfoPtr info = RADEONPTR(pScrn); +- unsigned char *RADEONMMIO = info->MMIO; +- CARD32 *d = (CARD32 *)(pointer)(info->FB + info->cursor_offset + pScrn->fbOffset); ++ CURSOR_SWAPPING_DECL_MMIO ++ CARD32 *d = (CARD32 *)(pointer)(info->FB + radeon_crtc->cursor_offset + pScrn->fbOffset); + + RADEONCTRACE(("RADEONLoadCursorARGB\n")); + +@@ -252,16 +254,18 @@ Bool RADEONCursorInit(ScreenPtr pScreen) + { + ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; + RADEONInfoPtr info = RADEONPTR(pScrn); ++ xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); + int width; + int width_bytes; + int height; + int size_bytes; +- ++ CARD32 cursor_offset = 0; ++ int c; + + size_bytes = CURSOR_WIDTH * 4 * CURSOR_HEIGHT; + width = pScrn->displayWidth; + width_bytes = width * (pScrn->bitsPerPixel / 8); +- height = (size_bytes + width_bytes - 1) / width_bytes; ++ height = ((size_bytes * xf86_config->num_crtc) + width_bytes - 1) / width_bytes; + + #ifdef USE_XAA + if (!info->useEXA) { +@@ -271,19 +275,30 @@ Bool RADEONCursorInit(ScreenPtr pScreen) + 256, NULL, NULL, NULL); + + if (!fbarea) { +- info->cursor_offset = 0; ++ cursor_offset = 0; + xf86DrvMsg(pScrn->scrnIndex, X_WARNING, + "Hardware cursor disabled" + " due to insufficient offscreen memory\n"); ++ return FALSE; + } else { +- info->cursor_offset = RADEON_ALIGN((fbarea->box.x1 + +- fbarea->box.y1 * width) * +- info->CurrentLayout.pixel_bytes, +- 256); +- info->cursor_end = info->cursor_offset + size_bytes; ++ cursor_offset = RADEON_ALIGN((fbarea->box.x1 + ++ fbarea->box.y1 * width) * ++ info->CurrentLayout.pixel_bytes, ++ 256); ++ ++ for (c = 0; c < xf86_config->num_crtc; c++) { ++ xf86CrtcPtr crtc = xf86_config->crtc[c]; ++ RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; ++ ++ radeon_crtc->cursor_offset = cursor_offset + (c * size_bytes); ++ ++ xf86DrvMsg(pScrn->scrnIndex, X_INFO, ++ "Using hardware cursor %d (scanline %u)\n", c, ++ (unsigned)(radeon_crtc->cursor_offset / pScrn->displayWidth ++ / info->CurrentLayout.pixel_bytes)); ++ } ++ + } +- RADEONCTRACE(("RADEONCursorInit (0x%08x-0x%08x)\n", +- info->cursor_offset, info->cursor_end)); + } + #endif + +diff --git a/src/radeon_display.c b/src/radeon_display.c +index 5c4fbfa..ea31a82 100644 +--- a/src/radeon_display.c ++++ b/src/radeon_display.c +@@ -163,7 +163,7 @@ void RADEONGetTVDacAdjInfo(xf86OutputPtr output) + ScrnInfoPtr pScrn = output->scrn; + RADEONInfoPtr info = RADEONPTR(pScrn); + RADEONOutputPrivatePtr radeon_output = output->driver_private; +- ++ + /* Todo: get this setting from BIOS */ + radeon_output->tv_dac_adj = default_tvdac_adj[info->ChipFamily]; + if (info->IsMobility) { /* some mobility chips may different */ +@@ -202,7 +202,7 @@ static void RADEONDacPowerSet(ScrnInfoPtr pScrn, Bool IsOn, Bool IsPrimaryDAC) + } else { + CARD32 tv_dac_cntl; + CARD32 fp2_gen_cntl; +- ++ + switch(info->ChipFamily) + { + case CHIP_FAMILY_R420: +@@ -259,19 +259,19 @@ void RADEONDisableDisplays(ScrnInfoPtr pScrn) { + + /* primary DAC */ + tmp = INREG(RADEON_CRTC_EXT_CNTL); +- tmp &= ~RADEON_CRTC_CRT_ON; ++ tmp &= ~RADEON_CRTC_CRT_ON; + OUTREG(RADEON_CRTC_EXT_CNTL, tmp); + RADEONDacPowerSet(pScrn, FALSE, TRUE); + + /* Secondary DAC */ + if (info->ChipFamily == CHIP_FAMILY_R200) { +- tmp = INREG(RADEON_FP2_GEN_CNTL); +- tmp &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN); +- OUTREG(RADEON_FP2_GEN_CNTL, tmp); ++ tmp = INREG(RADEON_FP2_GEN_CNTL); ++ tmp &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN); ++ OUTREG(RADEON_FP2_GEN_CNTL, tmp); + } else { +- tmp = INREG(RADEON_CRTC2_GEN_CNTL); +- tmp &= ~RADEON_CRTC2_CRT2_ON; +- OUTREG(RADEON_CRTC2_GEN_CNTL, tmp); ++ tmp = INREG(RADEON_CRTC2_GEN_CNTL); ++ tmp &= ~RADEON_CRTC2_CRT2_ON; ++ OUTREG(RADEON_CRTC2_GEN_CNTL, tmp); + } + RADEONDacPowerSet(pScrn, FALSE, FALSE); + +@@ -304,7 +304,7 @@ void RADEONDisableDisplays(ScrnInfoPtr pScrn) { + } + tmp = INREG(RADEON_LVDS_GEN_CNTL); + tmp |= RADEON_LVDS_DISPLAY_DIS; +- tmp &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON); ++ tmp &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN); + OUTREG(RADEON_LVDS_GEN_CNTL, tmp); + if (info->IsMobility || info->IsIGP) { + OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, tmpPixclksCntl); +@@ -322,130 +322,161 @@ void RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable) + unsigned char * RADEONMMIO = info->MMIO; + unsigned long tmp; + RADEONOutputPrivatePtr radeon_output; +- int tv_dac_change = 0; ++ int tv_dac_change = 0, o; + radeon_output = output->driver_private; ++ xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); ++ ++ for (o = 0; o < xf86_config->num_output; o++) { ++ if (output == xf86_config->output[o]) { ++ break; ++ } ++ } + + if (bEnable) { + ErrorF("enable montype: %d\n", radeon_output->MonType); +- if (radeon_output->MonType == MT_CRT) { +- if (radeon_output->DACType == DAC_PRIMARY) { +- tmp = INREG(RADEON_CRTC_EXT_CNTL); +- tmp |= RADEON_CRTC_CRT_ON; +- OUTREG(RADEON_CRTC_EXT_CNTL, tmp); +- save->crtc_ext_cntl |= RADEON_CRTC_CRT_ON; +- RADEONDacPowerSet(pScrn, bEnable, (radeon_output->DACType == DAC_PRIMARY)); +- } else if (radeon_output->DACType == DAC_TVDAC) { +- if (info->ChipFamily == CHIP_FAMILY_R200) { +- tmp = INREG(RADEON_FP2_GEN_CNTL); +- tmp |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN); +- OUTREG(RADEON_FP2_GEN_CNTL, tmp); +- save->fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN); +- } else { +- tmp = INREG(RADEON_CRTC2_GEN_CNTL); +- tmp |= RADEON_CRTC2_CRT2_ON; +- OUTREG(RADEON_CRTC2_GEN_CNTL, tmp); +- save->crtc2_gen_cntl |= RADEON_CRTC2_CRT2_ON; +- } +- tv_dac_change = 1; +- } +- } else if (radeon_output->MonType == MT_DFP) { +- if (radeon_output->TMDSType == TMDS_INT) { +- tmp = INREG(RADEON_FP_GEN_CNTL); +- tmp |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN); +- OUTREG(RADEON_FP_GEN_CNTL, tmp); +- save->fp_gen_cntl |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN); +- } else if (radeon_output->TMDSType == TMDS_EXT) { +- tmp = INREG(RADEON_FP2_GEN_CNTL); ++ if (radeon_output->MonType == MT_CRT) { ++ if (radeon_output->DACType == DAC_PRIMARY) { ++ info->output_crt1 |= (1 << o); ++ tmp = INREG(RADEON_CRTC_EXT_CNTL); ++ tmp |= RADEON_CRTC_CRT_ON; ++ OUTREG(RADEON_CRTC_EXT_CNTL, tmp); ++ save->crtc_ext_cntl |= RADEON_CRTC_CRT_ON; ++ RADEONDacPowerSet(pScrn, bEnable, (radeon_output->DACType == DAC_PRIMARY)); ++ } else if (radeon_output->DACType == DAC_TVDAC) { ++ info->output_crt2 |= (1 << o); ++ if (info->ChipFamily == CHIP_FAMILY_R200) { ++ tmp = INREG(RADEON_FP2_GEN_CNTL); ++ tmp |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN); ++ OUTREG(RADEON_FP2_GEN_CNTL, tmp); ++ save->fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN); ++ } else { ++ tmp = INREG(RADEON_CRTC2_GEN_CNTL); ++ tmp |= RADEON_CRTC2_CRT2_ON; ++ OUTREG(RADEON_CRTC2_GEN_CNTL, tmp); ++ save->crtc2_gen_cntl |= RADEON_CRTC2_CRT2_ON; ++ } ++ tv_dac_change = 1; ++ } ++ } else if (radeon_output->MonType == MT_DFP) { ++ if (radeon_output->TMDSType == TMDS_INT) { ++ info->output_dfp1 |= (1 << o); ++ tmp = INREG(RADEON_FP_GEN_CNTL); ++ tmp |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN); ++ OUTREG(RADEON_FP_GEN_CNTL, tmp); ++ save->fp_gen_cntl |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN); ++ } else if (radeon_output->TMDSType == TMDS_EXT) { ++ info->output_dfp2 |= (1 << o); ++ tmp = INREG(RADEON_FP2_GEN_CNTL); + tmp &= ~RADEON_FP2_BLANK_EN; +- tmp |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN); +- OUTREG(RADEON_FP2_GEN_CNTL, tmp); +- save->fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN); ++ tmp |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN); ++ OUTREG(RADEON_FP2_GEN_CNTL, tmp); ++ save->fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN); + save->fp2_gen_cntl &= ~RADEON_FP2_BLANK_EN; +- } +- } else if (radeon_output->MonType == MT_LCD) { +- tmp = INREG(RADEON_LVDS_GEN_CNTL); +- tmp |= (RADEON_LVDS_ON | RADEON_LVDS_BLON); +- tmp &= ~(RADEON_LVDS_DISPLAY_DIS); ++ } ++ } else if (radeon_output->MonType == MT_LCD) { ++ info->output_lcd1 |= (1 << o); ++ tmp = INREG(RADEON_LVDS_GEN_CNTL); ++ tmp |= (RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN); ++ tmp &= ~(RADEON_LVDS_DISPLAY_DIS); + usleep (radeon_output->PanelPwrDly * 1000); +- OUTREG(RADEON_LVDS_GEN_CNTL, tmp); +- save->lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_BLON); +- save->lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS); +- } else if (radeon_output->MonType == MT_STV || ++ OUTREG(RADEON_LVDS_GEN_CNTL, tmp); ++ save->lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN); ++ save->lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS); ++ } else if (radeon_output->MonType == MT_STV || + radeon_output->MonType == MT_CTV) { ++ info->output_tv1 |= (1 << o); + tmp = INREG(RADEON_TV_MASTER_CNTL); + tmp |= RADEON_TV_ON; + OUTREG(RADEON_TV_MASTER_CNTL, tmp); +- tv_dac_change = 2; ++ tv_dac_change = 2; + radeon_output->tv_on = TRUE; + } + } else { + ErrorF("disable montype: %d\n", radeon_output->MonType); +- if (radeon_output->MonType == MT_CRT) { +- if (radeon_output->DACType == DAC_PRIMARY) { +- tmp = INREG(RADEON_CRTC_EXT_CNTL); +- tmp &= ~RADEON_CRTC_CRT_ON; +- OUTREG(RADEON_CRTC_EXT_CNTL, tmp); +- save->crtc_ext_cntl &= ~RADEON_CRTC_CRT_ON; +- RADEONDacPowerSet(pScrn, bEnable, (radeon_output->DACType == DAC_PRIMARY)); +- } else if (radeon_output->DACType == DAC_TVDAC) { +- if (info->ChipFamily == CHIP_FAMILY_R200) { +- tmp = INREG(RADEON_FP2_GEN_CNTL); +- tmp &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN); +- OUTREG(RADEON_FP2_GEN_CNTL, tmp); +- save->fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN); +- } else { +- tmp = INREG(RADEON_CRTC2_GEN_CNTL); +- tmp &= ~RADEON_CRTC2_CRT2_ON; +- OUTREG(RADEON_CRTC2_GEN_CNTL, tmp); +- save->crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON; +- } +- tv_dac_change = 1; +- } +- } else if (radeon_output->MonType == MT_DFP) { +- if (radeon_output->TMDSType == TMDS_INT) { +- tmp = INREG(RADEON_FP_GEN_CNTL); +- tmp &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN); +- OUTREG(RADEON_FP_GEN_CNTL, tmp); +- save->fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN); +- } else if (radeon_output->TMDSType == TMDS_EXT) { +- tmp = INREG(RADEON_FP2_GEN_CNTL); +- tmp |= RADEON_FP2_BLANK_EN; +- tmp &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN); +- OUTREG(RADEON_FP2_GEN_CNTL, tmp); +- save->fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN); +- save->fp2_gen_cntl |= RADEON_FP2_BLANK_EN; +- } +- } else if (radeon_output->MonType == MT_LCD) { +- unsigned long tmpPixclksCntl = INPLL(pScrn, RADEON_PIXCLKS_CNTL); +- if (info->IsMobility || info->IsIGP) { +- /* Asic bug, when turning off LVDS_ON, we have to make sure +- RADEON_PIXCLK_LVDS_ALWAYS_ON bit is off +- */ +- OUTPLLP(pScrn, RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb); ++ if (radeon_output->MonType == MT_CRT) { ++ if (radeon_output->DACType == DAC_PRIMARY) { ++ info->output_crt1 &= ~(1 << o); ++ if (!info->output_crt1) { ++ tmp = INREG(RADEON_CRTC_EXT_CNTL); ++ tmp &= ~RADEON_CRTC_CRT_ON; ++ OUTREG(RADEON_CRTC_EXT_CNTL, tmp); ++ save->crtc_ext_cntl &= ~RADEON_CRTC_CRT_ON; ++ RADEONDacPowerSet(pScrn, bEnable, (radeon_output->DACType == DAC_PRIMARY)); ++ } ++ } else if (radeon_output->DACType == DAC_TVDAC) { ++ info->output_crt2 &= ~(1 << o); ++ tv_dac_change = 1; ++ if (!info->output_crt2) { ++ if (info->ChipFamily == CHIP_FAMILY_R200) { ++ tmp = INREG(RADEON_FP2_GEN_CNTL); ++ tmp &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN); ++ OUTREG(RADEON_FP2_GEN_CNTL, tmp); ++ save->fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN); ++ } else { ++ tmp = INREG(RADEON_CRTC2_GEN_CNTL); ++ tmp &= ~RADEON_CRTC2_CRT2_ON; ++ OUTREG(RADEON_CRTC2_GEN_CNTL, tmp); ++ save->crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON; ++ } ++ } + } +- tmp = INREG(RADEON_LVDS_GEN_CNTL); +- tmp |= RADEON_LVDS_DISPLAY_DIS; +- tmp &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON); +- OUTREG(RADEON_LVDS_GEN_CNTL, tmp); +- save->lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS; +- save->lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON); +- if (info->IsMobility || info->IsIGP) { +- OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, tmpPixclksCntl); ++ } else if (radeon_output->MonType == MT_DFP) { ++ if (radeon_output->TMDSType == TMDS_INT) { ++ info->output_dfp1 &= ~(1 << o); ++ if (!info->output_dfp1) { ++ tmp = INREG(RADEON_FP_GEN_CNTL); ++ tmp &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN); ++ OUTREG(RADEON_FP_GEN_CNTL, tmp); ++ save->fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN); ++ } ++ } else if (radeon_output->TMDSType == TMDS_EXT) { ++ info->output_dfp2 &= ~(1 << o); ++ if (!info->output_dfp2) { ++ tmp = INREG(RADEON_FP2_GEN_CNTL); ++ tmp |= RADEON_FP2_BLANK_EN; ++ tmp &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN); ++ OUTREG(RADEON_FP2_GEN_CNTL, tmp); ++ save->fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN); ++ save->fp2_gen_cntl |= RADEON_FP2_BLANK_EN; ++ } ++ } ++ } else if (radeon_output->MonType == MT_LCD) { ++ info->output_lcd1 &= ~(1 << o); ++ if (!info->output_lcd1) { ++ unsigned long tmpPixclksCntl = INPLL(pScrn, RADEON_PIXCLKS_CNTL); ++ if (info->IsMobility || info->IsIGP) { ++ /* Asic bug, when turning off LVDS_ON, we have to make sure ++ RADEON_PIXCLK_LVDS_ALWAYS_ON bit is off ++ */ ++ OUTPLLP(pScrn, RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb); ++ } ++ tmp = INREG(RADEON_LVDS_GEN_CNTL); ++ tmp |= RADEON_LVDS_DISPLAY_DIS; ++ tmp &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN); ++ OUTREG(RADEON_LVDS_GEN_CNTL, tmp); ++ save->lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS; ++ save->lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN); ++ if (info->IsMobility || info->IsIGP) { ++ OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, tmpPixclksCntl); ++ } ++ } ++ } else if (radeon_output->MonType == MT_STV || radeon_output->MonType == MT_CTV) { ++ info->output_tv1 &= ~(1 << o); ++ tv_dac_change = 2; ++ if (!info->output_tv1) { ++ tmp = INREG(RADEON_TV_MASTER_CNTL); ++ tmp &= ~RADEON_TV_ON; ++ OUTREG(RADEON_TV_MASTER_CNTL, tmp); ++ radeon_output->tv_on = FALSE; + } +- } else if (radeon_output->MonType == MT_STV || radeon_output->MonType == MT_CTV) { +- tmp = INREG(RADEON_TV_MASTER_CNTL); +- tmp &= ~RADEON_TV_ON; +- OUTREG(RADEON_TV_MASTER_CNTL, tmp); +- tv_dac_change = 2; +- radeon_output->tv_on = FALSE; + } + } + + if (tv_dac_change) { + if (bEnable) +- info->tv_dac_enable_mask |= tv_dac_change; ++ info->tv_dac_enable_mask |= tv_dac_change; + else +- info->tv_dac_enable_mask &= ~tv_dac_change; ++ info->tv_dac_enable_mask &= ~tv_dac_change; + + if (bEnable && info->tv_dac_enable_mask) + RADEONDacPowerSet(pScrn, bEnable, (radeon_output->DACType == DAC_PRIMARY)); +@@ -487,13 +518,13 @@ void RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_b + int stop_req, max_stop_req; + float read_return_rate, time_disp1_drop_priority; + +- /* +- * Set display0/1 priority up on r3/4xx in the memory controller for +- * high res modes if the user specifies HIGH for displaypriority ++ /* ++ * Set display0/1 priority up on r3/4xx in the memory controller for ++ * high res modes if the user specifies HIGH for displaypriority + * option. + */ + if ((info->DispPriority == 2) && IS_R300_VARIANT) { +- CARD32 mc_init_misc_lat_timer = INREG(R300_MC_INIT_MISC_LAT_TIMER); ++ CARD32 mc_init_misc_lat_timer = INREG(R300_MC_INIT_MISC_LAT_TIMER); + if (pRADEONEnt->pCrtc[1]->enabled) { + mc_init_misc_lat_timer |= 0x1100; /* display 0 and 1 */ + } else { +@@ -522,14 +553,14 @@ void RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_b + peak_disp_bw += (pix_clk2 * pixel_bytes2); + + if (peak_disp_bw >= mem_bw * min_mem_eff) { +- xf86DrvMsg(pScrn->scrnIndex, X_WARNING, ++ xf86DrvMsg(pScrn->scrnIndex, X_WARNING, + "You may not have enough display bandwidth for current mode\n" + "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n"); +- } ++ } + + /* CRTC1 + Set GRPH_BUFFER_CNTL register using h/w defined optimal values. +- GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ] ++ GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ] + */ + stop_req = mode1->HDisplay * info->CurrentLayout.pixel_bytes / 16; + +@@ -540,7 +571,7 @@ void RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_b + max_stop_req = 0x7c; + if (stop_req > max_stop_req) + stop_req = max_stop_req; +- ++ + /* Get values from the EXT_MEM_CNTL register...converting its contents. */ + temp = INREG(RADEON_MEM_TIMING_CNTL); + if ((info->ChipFamily == CHIP_FAMILY_RV100) || info->IsIGP) { /* RV100, M6, IGPs */ +@@ -552,8 +583,8 @@ void RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_b + mem_trp = MemTrpMemTimingCntl[ (temp & 0x700) >> 8]; + mem_tras = MemTrasMemTimingCntl[(temp & 0xf000) >> 12]; + } +- +- /* Get values from the MEM_SDRAM_MODE_REG register...converting its */ ++ ++ /* Get values from the MEM_SDRAM_MODE_REG register...converting its */ + temp = INREG(RADEON_MEM_SDRAM_MODE_REG); + data = (temp & (7<<20)) >> 20; + if ((info->ChipFamily == CHIP_FAMILY_RV100) || info->IsIGP) { /* RV100, M6, IGPs */ +@@ -625,7 +656,7 @@ void RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_b + } + + mc_latency_sclk = sclk_delay / sclk_eff; +- ++ + if (info->IsDDR) { + if (info->RamWidth == 32) { + k1 = 40; +@@ -667,7 +698,7 @@ void RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_b + /* + Find the critical point of the display buffer. + */ +- critical_point= (CARD32)(disp_drain_rate * disp_latency + 0.5); ++ critical_point= (CARD32)(disp_drain_rate * disp_latency + 0.5); + + /* ???? */ + /* +@@ -682,7 +713,7 @@ void RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_b + The critical point should never be above max_stop_req-4. Setting + GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time. + */ +- if (max_stop_req - critical_point < 4) critical_point = 0; ++ if (max_stop_req - critical_point < 4) critical_point = 0; + + if (critical_point == 0 && mode2 && info->ChipFamily == CHIP_FAMILY_R300) { + /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/ +@@ -712,7 +743,7 @@ void RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_b + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "GRPH_BUFFER_CNTL from %x to %x\n", + (unsigned int)info->SavedReg.grph_buffer_cntl, +- INREG(RADEON_GRPH_BUFFER_CNTL)); ++ (unsigned int)INREG(RADEON_GRPH_BUFFER_CNTL)); + + if (mode2) { + stop_req = mode2->HDisplay * pixel_bytes2 / 16; +@@ -733,7 +764,7 @@ void RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_b + RADEON_GRPH_CRITICAL_AT_SOF | + RADEON_GRPH_STOP_CNTL); + +- if ((info->ChipFamily == CHIP_FAMILY_RS100) || ++ if ((info->ChipFamily == CHIP_FAMILY_RS100) || + (info->ChipFamily == CHIP_FAMILY_RS200)) + critical_point2 = 0; + else { +@@ -762,7 +793,7 @@ void RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_b + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "GRPH2_BUFFER_CNTL from %x to %x\n", + (unsigned int)info->SavedReg.grph2_buffer_cntl, +- INREG(RADEON_GRPH2_BUFFER_CNTL)); ++ (unsigned int)INREG(RADEON_GRPH2_BUFFER_CNTL)); + } + } + +@@ -810,7 +841,7 @@ void RADEONBlank(ScrnInfoPtr pScrn) + + for (c = 0; c < xf86_config->num_crtc; c++) { + crtc = xf86_config->crtc[c]; +- for (o = 0; o < xf86_config->num_output; o++) { ++ for (o = 0; o < xf86_config->num_output; o++) { + output = xf86_config->output[o]; + if (output->crtc != crtc) + continue; +@@ -833,7 +864,7 @@ void RADEONUnblank(ScrnInfoPtr pScrn) + if(!crtc->enabled) + continue; + crtc->funcs->dpms(crtc, DPMSModeOn); +- for (o = 0; o < xf86_config->num_output; o++) { ++ for (o = 0; o < xf86_config->num_output; o++) { + output = xf86_config->output[o]; + if (output->crtc != crtc) + continue; +diff --git a/src/radeon_dri.c b/src/radeon_dri.c +index 2c533b1..3190451 100644 +--- a/src/radeon_dri.c ++++ b/src/radeon_dri.c +@@ -559,12 +559,12 @@ static void RADEONDRIMoveBuffers(WindowPtr pParent, DDXPointRec ptOldOrg, + + if (nbox > 1) { + /* Keep ordering in each band, reverse order of bands */ +- pboxNew1 = (BoxPtr)ALLOCATE_LOCAL(sizeof(BoxRec)*nbox); ++ pboxNew1 = (BoxPtr)xalloc(sizeof(BoxRec)*nbox); + if (!pboxNew1) return; + +- pptNew1 = (DDXPointPtr)ALLOCATE_LOCAL(sizeof(DDXPointRec)*nbox); ++ pptNew1 = (DDXPointPtr)xalloc(sizeof(DDXPointRec)*nbox); + if (!pptNew1) { +- DEALLOCATE_LOCAL(pboxNew1); ++ xfree(pboxNew1); + return; + } + +@@ -601,14 +601,14 @@ static void RADEONDRIMoveBuffers(WindowPtr pParent, DDXPointRec ptOldOrg, + + if (nbox > 1) { + /* reverse order of rects in each band */ +- pboxNew2 = (BoxPtr)ALLOCATE_LOCAL(sizeof(BoxRec)*nbox); +- pptNew2 = (DDXPointPtr)ALLOCATE_LOCAL(sizeof(DDXPointRec)*nbox); ++ pboxNew2 = (BoxPtr)xalloc(sizeof(BoxRec)*nbox); ++ pptNew2 = (DDXPointPtr)xalloc(sizeof(DDXPointRec)*nbox); + + if (!pboxNew2 || !pptNew2) { +- DEALLOCATE_LOCAL(pptNew2); +- DEALLOCATE_LOCAL(pboxNew2); +- DEALLOCATE_LOCAL(pptNew1); +- DEALLOCATE_LOCAL(pboxNew1); ++ xfree(pptNew2); ++ xfree(pboxNew2); ++ xfree(pptNew1); ++ xfree(pboxNew1); + return; + } + +@@ -679,10 +679,10 @@ static void RADEONDRIMoveBuffers(WindowPtr pParent, DDXPointRec ptOldOrg, + + info->dst_pitch_offset = info->frontPitchOffset;; + +- DEALLOCATE_LOCAL(pptNew2); +- DEALLOCATE_LOCAL(pboxNew2); +- DEALLOCATE_LOCAL(pptNew1); +- DEALLOCATE_LOCAL(pboxNew1); ++ xfree(pptNew2); ++ xfree(pboxNew2); ++ xfree(pptNew1); ++ xfree(pboxNew1); + + info->accel->NeedToSync = TRUE; + #endif /* USE_XAA */ +@@ -722,20 +722,13 @@ static Bool RADEONSetAgpMode(RADEONInfoPtr info, ScreenPtr pScreen) + unsigned long mode = drmAgpGetMode(info->drmFD); /* Default mode */ + unsigned int vendor = drmAgpVendorId(info->drmFD); + unsigned int device = drmAgpDeviceId(info->drmFD); +- CARD32 agp_status = INREG(RADEON_AGP_STATUS) & mode; ++ /* ignore agp 3.0 mode bit from the chip as it's buggy on some cards with ++ pcie-agp rialto bridge chip - use the one from bridge which must match */ ++ CARD32 agp_status = (INREG(RADEON_AGP_STATUS) | RADEON_AGPv3_MODE) & mode; + Bool is_v3 = (agp_status & RADEON_AGPv3_MODE); +- unsigned int defaultMode; +- MessageType from; +- +- if (is_v3) { +- defaultMode = (agp_status & RADEON_AGPv3_8X_MODE) ? 8 : 4; +- } else { +- if (agp_status & RADEON_AGP_4X_MODE) defaultMode = 4; +- else if (agp_status & RADEON_AGP_2X_MODE) defaultMode = 2; +- else defaultMode = 1; +- } +- +- from = X_DEFAULT; ++ unsigned int defaultMode = is_v3 ? ++ ((agp_status & RADEON_AGPv3_8X_MODE) ? 8 : 4) : 1; ++ MessageType from = X_DEFAULT; + + if (xf86GetOptValInteger(info->Options, OPTION_AGP_MODE, &info->agpMode)) { + if ((info->agpMode < (is_v3 ? 4 : 1)) || +@@ -1359,6 +1352,9 @@ Bool RADEONDRISetVBlankInterrupt(ScrnInfoPtr pScrn, Bool on) + xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); + int value = 0; + ++ if (!info->want_vblank_interrupts) ++ on = FALSE; ++ + if (info->directRenderingEnabled && info->pKernelDRMVersion->version_minor >= 28) { + if (on) { + if (xf86_config->num_crtc > 1 && xf86_config->crtc[1]->enabled) +diff --git a/src/radeon_driver.c b/src/radeon_driver.c +index e027379..25b2119 100644 +--- a/src/radeon_driver.c ++++ b/src/radeon_driver.c +@@ -90,7 +90,6 @@ + + /* X and server generic header files */ + #include "xf86.h" +-#include "xf86_ansic.h" /* For xf86getsecs() */ + #include "xf86_OSproc.h" + #include "xf86RAC.h" + #include "xf86RandR12.h" +@@ -107,9 +106,10 @@ + #include + + #include "atipciids.h" +-#include "radeon_chipset.h" ++#include "radeon_chipset_gen.h" + + ++#include "radeon_chipinfo_gen.h" + + /* Forward definitions for driver functions */ + static Bool RADEONCloseScreen(int scrnIndex, ScreenPtr pScreen); +@@ -191,6 +191,8 @@ static const OptionInfoRec RADEONOptions[] = { + { OPTION_MAC_MODEL, "MacModel", OPTV_STRING, {0}, FALSE }, + #endif + { OPTION_TVDAC_LOAD_DETECT, "TVDACLoadDetect", OPTV_BOOLEAN, {0}, FALSE }, ++ { OPTION_FORCE_TVOUT, "ForceTVOut", OPTV_BOOLEAN, {0}, FALSE }, ++ { OPTION_TVSTD, "TVStandard", OPTV_STRING, {0}, FALSE }, + { -1, NULL, OPTV_NONE, {0}, FALSE } + }; + +@@ -802,8 +804,8 @@ static Bool RADEONProbePLLParameters(ScrnInfoPtr pScrn) + unsigned xclk, tmp, ref_div; + int hTotal, vTotal, num, denom, m, n; + float hz, prev_xtal, vclk, xtal, mpll, spll; +- long start_secs, start_usecs, stop_secs, stop_usecs, total_usecs; +- long to1_secs, to1_usecs, to2_secs, to2_usecs; ++ long total_usecs; ++ struct timeval start, stop, to1, to2; + unsigned int f1, f2, f3; + int tries = 0; + +@@ -813,32 +815,32 @@ static Bool RADEONProbePLLParameters(ScrnInfoPtr pScrn) + if (++tries > 10) + goto failed; + +- xf86getsecs(&to1_secs, &to1_usecs); ++ gettimeofday(&to1, NULL); + f1 = INREG(RADEON_CRTC_CRNT_FRAME); + for (;;) { + f2 = INREG(RADEON_CRTC_CRNT_FRAME); + if (f1 != f2) + break; +- xf86getsecs(&to2_secs, &to2_usecs); +- if ((to2_secs - to1_secs) > 1) { ++ gettimeofday(&to2, NULL); ++ if ((to2.tv_sec - to1.tv_sec) > 1) { + xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Clock not counting...\n"); + goto failed; + } + } +- xf86getsecs(&start_secs, &start_usecs); ++ gettimeofday(&start, NULL); + for(;;) { + f3 = INREG(RADEON_CRTC_CRNT_FRAME); + if (f3 != f2) + break; +- xf86getsecs(&to2_secs, &to2_usecs); +- if ((to2_secs - start_secs) > 1) ++ gettimeofday(&to2, NULL); ++ if ((to2.tv_sec - start.tv_sec) > 1) + goto failed; + } +- xf86getsecs(&stop_secs, &stop_usecs); ++ gettimeofday(&stop, NULL); + +- if ((stop_secs - start_secs) != 0) ++ if ((stop.tv_sec - start.tv_sec) != 0) + goto again; +- total_usecs = abs(stop_usecs - start_usecs); ++ total_usecs = abs(stop.tv_usec - start.tv_usec); + if (total_usecs == 0) + goto again; + hz = 1000000.0/(float)total_usecs; +@@ -1061,8 +1063,17 @@ static void RADEONGetClockInfo(ScrnInfoPtr pScrn) + info->RamWidth / 16); + } + ++ /* card limits for computing PLLs */ ++ pll->min_ref_div = 2; ++ pll->max_ref_div = 0x3ff; ++ pll->min_feedback_div = 4; ++ pll->max_feedback_div = 0x7ff; ++ pll->pll_in_min = 40; ++ pll->pll_in_max = 500; ++ pll->best_vco = 0; ++ + xf86DrvMsg (pScrn->scrnIndex, X_INFO, +- "PLL parameters: rf=%d rd=%d min=%d max=%d; xclk=%d\n", ++ "PLL parameters: rf=%u rd=%u min=%u max=%u; xclk=%u\n", + pll->reference_freq, + pll->reference_div, + (unsigned)pll->min_pll_freq, (unsigned)pll->max_pll_freq, +@@ -1472,6 +1483,7 @@ static Bool RADEONPreInitChipType(ScrnInfoPtr pScrn) + GDevPtr dev = pEnt->device; + unsigned char *RADEONMMIO = info->MMIO; + MessageType from = X_PROBED; ++ int i; + #ifdef XF86DRI + const char *s; + uint32_t cmd_stat; +@@ -1511,20 +1523,25 @@ static Bool RADEONPreInitChipType(ScrnInfoPtr pScrn) + info->IsDellServer = FALSE; + info->HasSingleDAC = FALSE; + info->InternalTVOut = TRUE; +- switch (info->Chipset) { +- case PCI_CHIP_RADEON_LY: +- case PCI_CHIP_RADEON_LZ: +- info->IsMobility = TRUE; +- info->ChipFamily = CHIP_FAMILY_RV100; +- break; + ++ for (i = 0; i < sizeof(RADEONCards) / sizeof(RADEONCardInfo); i++) { ++ if (info->Chipset == RADEONCards[i].pci_device_id) { ++ RADEONCardInfo *card = &RADEONCards[i]; ++ info->ChipFamily = card->chip_family; ++ info->IsMobility = card->mobility; ++ info->IsIGP = card->igp; ++ pRADEONEnt->HasCRTC2 = !card->nocrtc2; ++ info->HasSingleDAC = card->singledac; ++ info->InternalTVOut = !card->nointtvout; ++ break; ++ } ++ } ++ ++ switch (info->Chipset) { + case PCI_CHIP_RN50_515E: /* RN50 is based on the RV100 but 3D isn't guaranteed to work. YMMV. */ + case PCI_CHIP_RN50_5969: +- pRADEONEnt->HasCRTC2 = FALSE; + case PCI_CHIP_RV100_QY: + case PCI_CHIP_RV100_QZ: +- info->ChipFamily = CHIP_FAMILY_RV100; +- + /* DELL triple-head configuration. */ + if ((PCI_SUB_VENDOR_ID(info->PciInfo) == PCI_VENDOR_DELL) && + ((PCI_SUB_DEVICE_ID(info->PciInfo) == 0x016c) || +@@ -1540,220 +1557,9 @@ static Bool RADEONPreInitChipType(ScrnInfoPtr pScrn) + info->IsDellServer = TRUE; + xf86DrvMsg(pScrn->scrnIndex, X_INFO, "DELL server detected, force to special setup\n"); + } +- +- break; +- +- case PCI_CHIP_RS100_4336: +- info->IsMobility = TRUE; +- case PCI_CHIP_RS100_4136: +- info->ChipFamily = CHIP_FAMILY_RS100; +- info->IsIGP = TRUE; +- break; +- +- case PCI_CHIP_RS200_4337: +- info->IsMobility = TRUE; +- case PCI_CHIP_RS200_4137: +- info->ChipFamily = CHIP_FAMILY_RS200; +- info->IsIGP = TRUE; +- break; +- +- case PCI_CHIP_RS250_4437: +- info->IsMobility = TRUE; +- case PCI_CHIP_RS250_4237: +- info->ChipFamily = CHIP_FAMILY_RS200; +- info->IsIGP = TRUE; +- break; +- +- case PCI_CHIP_R200_BB: +- case PCI_CHIP_R200_BC: +- case PCI_CHIP_R200_QH: +- case PCI_CHIP_R200_QL: +- case PCI_CHIP_R200_QM: +- info->ChipFamily = CHIP_FAMILY_R200; +- info->InternalTVOut = FALSE; +- break; +- +- case PCI_CHIP_RADEON_LW: +- case PCI_CHIP_RADEON_LX: +- info->IsMobility = TRUE; +- case PCI_CHIP_RV200_QW: /* RV200 desktop */ +- case PCI_CHIP_RV200_QX: +- info->ChipFamily = CHIP_FAMILY_RV200; +- break; +- +- case PCI_CHIP_RV250_Ld: +- case PCI_CHIP_RV250_Lf: +- case PCI_CHIP_RV250_Lg: +- info->IsMobility = TRUE; +- case PCI_CHIP_RV250_If: +- case PCI_CHIP_RV250_Ig: +- info->ChipFamily = CHIP_FAMILY_RV250; +- break; +- +- case PCI_CHIP_RS300_5835: +- case PCI_CHIP_RS350_7835: +- info->IsMobility = TRUE; +- case PCI_CHIP_RS300_5834: +- case PCI_CHIP_RS350_7834: +- info->ChipFamily = CHIP_FAMILY_RS300; +- info->IsIGP = TRUE; +- info->HasSingleDAC = TRUE; +- break; +- +- case PCI_CHIP_RV280_5C61: +- case PCI_CHIP_RV280_5C63: +- info->IsMobility = TRUE; +- case PCI_CHIP_RV280_5960: +- case PCI_CHIP_RV280_5961: +- case PCI_CHIP_RV280_5962: +- case PCI_CHIP_RV280_5964: +- case PCI_CHIP_RV280_5965: +- info->ChipFamily = CHIP_FAMILY_RV280; + break; +- +- case PCI_CHIP_R300_AD: +- case PCI_CHIP_R300_AE: +- case PCI_CHIP_R300_AF: +- case PCI_CHIP_R300_AG: +- case PCI_CHIP_R300_ND: +- case PCI_CHIP_R300_NE: +- case PCI_CHIP_R300_NF: +- case PCI_CHIP_R300_NG: +- info->ChipFamily = CHIP_FAMILY_R300; +- break; +- +- case PCI_CHIP_RV350_NP: +- case PCI_CHIP_RV350_NQ: +- case PCI_CHIP_RV350_NR: +- case PCI_CHIP_RV350_NS: +- case PCI_CHIP_RV350_NT: +- case PCI_CHIP_RV350_NV: +- info->IsMobility = TRUE; +- case PCI_CHIP_RV350_AP: +- case PCI_CHIP_RV350_AQ: +- case PCI_CHIP_RV360_AR: +- case PCI_CHIP_RV350_AS: +- case PCI_CHIP_RV350_AT: +- case PCI_CHIP_RV350_AV: +- case PCI_CHIP_RV350_4155: +- info->ChipFamily = CHIP_FAMILY_RV350; +- break; +- +- case PCI_CHIP_R350_AH: +- case PCI_CHIP_R350_AI: +- case PCI_CHIP_R350_AJ: +- case PCI_CHIP_R350_AK: +- case PCI_CHIP_R350_NH: +- case PCI_CHIP_R350_NI: +- case PCI_CHIP_R350_NK: +- case PCI_CHIP_R360_NJ: +- info->ChipFamily = CHIP_FAMILY_R350; +- break; +- +- case PCI_CHIP_RV380_3150: +- case PCI_CHIP_RV380_3152: +- case PCI_CHIP_RV380_3154: +- info->IsMobility = TRUE; +- case PCI_CHIP_RV380_3E50: +- case PCI_CHIP_RV380_3E54: +- info->ChipFamily = CHIP_FAMILY_RV380; +- break; +- +- case PCI_CHIP_RV370_5460: +- case PCI_CHIP_RV370_5462: +- case PCI_CHIP_RV370_5464: +- info->IsMobility = TRUE; +- case PCI_CHIP_RV370_5B60: +- case PCI_CHIP_RV370_5B62: +- case PCI_CHIP_RV370_5B63: +- case PCI_CHIP_RV370_5B64: +- case PCI_CHIP_RV370_5B65: +- info->ChipFamily = CHIP_FAMILY_RV380; +- break; +- +- case PCI_CHIP_RS400_5A42: +- case PCI_CHIP_RC410_5A62: +- case PCI_CHIP_RS480_5955: +- case PCI_CHIP_RS485_5975: +- info->IsMobility = TRUE; +- case PCI_CHIP_RS400_5A41: +- case PCI_CHIP_RC410_5A61: +- case PCI_CHIP_RS480_5954: +- case PCI_CHIP_RS482_5974: +- info->ChipFamily = CHIP_FAMILY_RS400; +- info->IsIGP = TRUE; +- info->HasSingleDAC = TRUE; +- break; +- +- case PCI_CHIP_RV410_564A: +- case PCI_CHIP_RV410_564B: +- case PCI_CHIP_RV410_564F: +- case PCI_CHIP_RV410_5652: +- case PCI_CHIP_RV410_5653: +- info->IsMobility = TRUE; +- case PCI_CHIP_RV410_5E48: +- case PCI_CHIP_RV410_5E4B: +- case PCI_CHIP_RV410_5E4A: +- case PCI_CHIP_RV410_5E4D: +- case PCI_CHIP_RV410_5E4C: +- case PCI_CHIP_RV410_5E4F: +- info->ChipFamily = CHIP_FAMILY_RV410; +- break; +- +- case PCI_CHIP_R420_JN: +- info->IsMobility = TRUE; +- case PCI_CHIP_R420_JH: +- case PCI_CHIP_R420_JI: +- case PCI_CHIP_R420_JJ: +- case PCI_CHIP_R420_JK: +- case PCI_CHIP_R420_JL: +- case PCI_CHIP_R420_JM: +- case PCI_CHIP_R420_JP: +- case PCI_CHIP_R420_4A4F: +- info->ChipFamily = CHIP_FAMILY_R420; +- break; +- +- case PCI_CHIP_R423_UH: +- case PCI_CHIP_R423_UI: +- case PCI_CHIP_R423_UJ: +- case PCI_CHIP_R423_UK: +- case PCI_CHIP_R423_UQ: +- case PCI_CHIP_R423_UR: +- case PCI_CHIP_R423_UT: +- case PCI_CHIP_R423_5D57: +- case PCI_CHIP_R423_5550: +- info->ChipFamily = CHIP_FAMILY_R420; +- break; +- +- case PCI_CHIP_R430_5D49: +- case PCI_CHIP_R430_5D4A: +- case PCI_CHIP_R430_5D48: +- info->IsMobility = TRUE; +- case PCI_CHIP_R430_554F: +- case PCI_CHIP_R430_554D: +- case PCI_CHIP_R430_554E: +- case PCI_CHIP_R430_554C: +- info->ChipFamily = CHIP_FAMILY_R420; /*CHIP_FAMILY_R430*/ +- break; +- +- case PCI_CHIP_R480_5D4C: +- case PCI_CHIP_R480_5D50: +- case PCI_CHIP_R480_5D4E: +- case PCI_CHIP_R480_5D4F: +- case PCI_CHIP_R480_5D52: +- case PCI_CHIP_R480_5D4D: +- case PCI_CHIP_R481_4B4B: +- case PCI_CHIP_R481_4B4A: +- case PCI_CHIP_R481_4B49: +- case PCI_CHIP_R481_4B4C: +- info->ChipFamily = CHIP_FAMILY_R420; /*CHIP_FAMILY_R480*/ +- break; +- + default: +- /* Original Radeon/7200 */ +- info->ChipFamily = CHIP_FAMILY_RADEON; +- pRADEONEnt->HasCRTC2 = FALSE; +- info->InternalTVOut = FALSE; ++ break; + } + + +@@ -3736,10 +3542,6 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, + if (!info->useEXA) { + int width, height; + +- xf86DrvMsg(pScrn->scrnIndex, X_INFO, +- "Using hardware cursor (scanline %u)\n", +- (unsigned)(info->cursor_offset / pScrn->displayWidth +- / info->CurrentLayout.pixel_bytes)); + if (xf86QueryLargestOffscreenArea(pScreen, &width, &height, + 0, 0, 0)) { + xf86DrvMsg(scrnIndex, X_INFO, +@@ -3754,7 +3556,6 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, + xf86DrvMsg(scrnIndex, X_INFO, "Using software cursor\n"); + } + } else { +- info->cursor_offset = 0; + xf86DrvMsg(scrnIndex, X_INFO, "Using software cursor\n"); + } + +@@ -4237,6 +4038,10 @@ void RADEONRestoreLVDSRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore) + if (info->IsMobility) { + OUTREG(RADEON_LVDS_GEN_CNTL, restore->lvds_gen_cntl); + OUTREG(RADEON_LVDS_PLL_CNTL, restore->lvds_pll_cntl); ++ ++ if (info->ChipFamily == CHIP_FAMILY_RV410) { ++ OUTREG(RADEON_CLOCK_CNTL_INDEX, 0); ++ } + } + + } +@@ -4245,10 +4050,13 @@ void RADEONRestoreBIOSRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore) + { + RADEONInfoPtr info = RADEONPTR(pScrn); + unsigned char *RADEONMMIO = info->MMIO; ++ CARD32 bios_5_scratch = INREG(RADEON_BIOS_5_SCRATCH); + CARD32 bios_6_scratch = INREG(RADEON_BIOS_6_SCRATCH); + + OUTREG(RADEON_BIOS_4_SCRATCH, restore->bios_4_scratch); +- OUTREG(RADEON_BIOS_5_SCRATCH, restore->bios_5_scratch); ++ bios_5_scratch &= 0xF; ++ bios_5_scratch |= (restore->bios_5_scratch & ~0xF); ++ OUTREG(RADEON_BIOS_5_SCRATCH, bios_5_scratch); + if (restore->bios_6_scratch & 0x40000000) + bios_6_scratch |= 0x40000000; + else +@@ -4904,9 +4712,9 @@ void RADEONChangeSurfaces(ScrnInfoPtr pScrn) + retvalue = drmCommandWrite(info->drmFD, DRM_RADEON_SURF_FREE, + &drmsurffree, sizeof(drmsurffree)); + +- if ((info->ChipFamily != CHIP_FAMILY_RV100) || +- (info->ChipFamily != CHIP_FAMILY_RS100) || +- (info->ChipFamily != CHIP_FAMILY_RS200)) { ++ if (!((info->ChipFamily == CHIP_FAMILY_RV100) || ++ (info->ChipFamily == CHIP_FAMILY_RS100) || ++ (info->ChipFamily == CHIP_FAMILY_RS200))) { + drmsurffree.address = info->depthOffset; + retvalue = drmCommandWrite(info->drmFD, DRM_RADEON_SURF_FREE, + &drmsurffree, sizeof(drmsurffree)); +@@ -4961,9 +4769,10 @@ void RADEONChangeSurfaces(ScrnInfoPtr pScrn) + } + + /* rv100 and probably the derivative igps don't have depth tiling on all the time? */ +- if (info->have3DWindows && ((info->ChipFamily != CHIP_FAMILY_RV100) || +- (info->ChipFamily != CHIP_FAMILY_RS100) || +- (info->ChipFamily != CHIP_FAMILY_RS200))) { ++ if (info->have3DWindows && ++ (!((info->ChipFamily == CHIP_FAMILY_RV100) || ++ (info->ChipFamily == CHIP_FAMILY_RS100) || ++ (info->ChipFamily == CHIP_FAMILY_RS200)))) { + drmRadeonSurfaceAlloc drmsurfalloc; + drmsurfalloc.size = depthBufferSize; + drmsurfalloc.address = info->depthOffset; +diff --git a/src/radeon_exa.c b/src/radeon_exa.c +index 8a12e1b..4da4841 100644 +--- a/src/radeon_exa.c ++++ b/src/radeon_exa.c +@@ -374,6 +374,7 @@ Bool RADEONSetupMemEXA (ScreenPtr pScreen) + { + ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; + RADEONInfoPtr info = RADEONPTR(pScrn); ++ xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); + int cpp = info->CurrentLayout.pixel_bytes; + int screen_size; + int byteStride = pScrn->displayWidth * cpp; +@@ -405,14 +406,23 @@ Bool RADEONSetupMemEXA (ScreenPtr pScreen) + /* Reserve static area for hardware cursor */ + if (!xf86ReturnOptValBool(info->Options, OPTION_SW_CURSOR, FALSE)) { + int cursor_size = 64 * 4 * 64; ++ int c; + +- info->cursor_offset = info->exa->offScreenBase; ++ for (c = 0; c < xf86_config->num_crtc; c++) { ++ xf86CrtcPtr crtc = xf86_config->crtc[c]; ++ RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; ++ ++ radeon_crtc->cursor_offset = info->exa->offScreenBase; ++ info->exa->offScreenBase += cursor_size; ++ ++ xf86DrvMsg(pScrn->scrnIndex, X_INFO, ++ "Will use %d kb for hardware cursor %d at offset 0x%08x\n", ++ (cursor_size * xf86_config->num_crtc) / 1024, ++ c, ++ (unsigned int)radeon_crtc->cursor_offset); ++ } + +- xf86DrvMsg(pScrn->scrnIndex, X_INFO, +- "Will use %d kb for hardware cursor at offset 0x%08x\n", +- cursor_size / 1024, (unsigned int)info->cursor_offset); + +- info->exa->offScreenBase += cursor_size; + } + + #if defined(XF86DRI) +diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c +index 9251569..eae69c4 100644 +--- a/src/radeon_exa_render.c ++++ b/src/radeon_exa_render.c +@@ -736,6 +736,21 @@ do { \ + + #endif /* !ACCEL_CP */ + ++#ifdef ONLY_ONCE ++static inline void transformPoint(PictTransform *transform, xPointFixed *point) ++{ ++ PictVector v; ++ v.vector[0] = point->x; ++ v.vector[1] = point->y; ++ v.vector[2] = xFixed1; ++ PictureTransformPoint(transform, &v); ++ point->x = v.vector[0]; ++ point->y = v.vector[1]; ++} ++#endif ++ ++#define xFixedToFloat(f) (((float) (f)) / 65536) ++ + static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst, + int srcX, int srcY, + int maskX, int maskY, +@@ -744,7 +759,8 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst, + { + RINFO_FROM_SCREEN(pDst->drawable.pScreen); + int srcXend, srcYend, maskXend, maskYend; +- PictVector v; ++ xPointFixed srcTopLeft, srcTopRight, srcBottomLeft, srcBottomRight; ++ xPointFixed maskTopLeft, maskTopRight, maskBottomLeft, maskBottomRight; + ACCEL_PREAMBLE(); + + ENTER_DRAW(0); +@@ -756,33 +772,36 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst, + srcYend = srcY + h; + maskXend = maskX + w; + maskYend = maskY + h; ++ ++ srcTopLeft.x = IntToxFixed(srcX); ++ srcTopLeft.y = IntToxFixed(srcY); ++ srcTopRight.x = IntToxFixed(srcX + w); ++ srcTopRight.y = IntToxFixed(srcY); ++ srcBottomLeft.x = IntToxFixed(srcX); ++ srcBottomLeft.y = IntToxFixed(srcY + h); ++ srcBottomRight.x = IntToxFixed(srcX + w); ++ srcBottomRight.y = IntToxFixed(srcY + h); ++ ++ maskTopLeft.x = IntToxFixed(maskX); ++ maskTopLeft.y = IntToxFixed(maskY); ++ maskTopRight.x = IntToxFixed(maskX + w); ++ maskTopRight.y = IntToxFixed(maskY); ++ maskBottomLeft.x = IntToxFixed(maskX); ++ maskBottomLeft.y = IntToxFixed(maskY + h); ++ maskBottomRight.x = IntToxFixed(maskX + w); ++ maskBottomRight.y = IntToxFixed(maskY + h); ++ + if (is_transform[0]) { +- v.vector[0] = IntToxFixed(srcX); +- v.vector[1] = IntToxFixed(srcY); +- v.vector[2] = xFixed1; +- PictureTransformPoint(transform[0], &v); +- srcX = xFixedToInt(v.vector[0]); +- srcY = xFixedToInt(v.vector[1]); +- v.vector[0] = IntToxFixed(srcXend); +- v.vector[1] = IntToxFixed(srcYend); +- v.vector[2] = xFixed1; +- PictureTransformPoint(transform[0], &v); +- srcXend = xFixedToInt(v.vector[0]); +- srcYend = xFixedToInt(v.vector[1]); ++ transformPoint(transform[0], &srcTopLeft); ++ transformPoint(transform[0], &srcTopRight); ++ transformPoint(transform[0], &srcBottomLeft); ++ transformPoint(transform[0], &srcBottomRight); + } + if (is_transform[1]) { +- v.vector[0] = IntToxFixed(maskX); +- v.vector[1] = IntToxFixed(maskY); +- v.vector[2] = xFixed1; +- PictureTransformPoint(transform[1], &v); +- maskX = xFixedToInt(v.vector[0]); +- maskY = xFixedToInt(v.vector[1]); +- v.vector[0] = IntToxFixed(maskXend); +- v.vector[1] = IntToxFixed(maskYend); +- v.vector[2] = xFixed1; +- PictureTransformPoint(transform[1], &v); +- maskXend = xFixedToInt(v.vector[0]); +- maskYend = xFixedToInt(v.vector[1]); ++ transformPoint(transform[1], &maskTopLeft); ++ transformPoint(transform[1], &maskTopRight); ++ transformPoint(transform[1], &maskBottomLeft); ++ transformPoint(transform[1], &maskBottomRight); + } + + #ifdef ACCEL_CP +@@ -828,18 +847,18 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst, + VTX_OUT(dstX + w, dstY + h, srcXend, srcYend, maskXend, maskYend); + VTX_OUT(dstX + w, dstY, srcXend, srcY, maskXend, maskY); + } else { +- VTX_OUT((float)dstX, (float)dstY, +- (float)srcX / info->texW[0], (float)srcY / info->texH[0], +- (float)maskX / info->texW[1], (float)maskY / info->texH[1]); +- VTX_OUT((float)dstX, (float)(dstY + h), +- (float)srcX / info->texW[0], (float)srcYend / info->texH[0], +- (float)maskX / info->texW[1], (float)maskYend / info->texH[1]); +- VTX_OUT((float)(dstX + w), (float)(dstY + h), +- (float)srcXend / info->texW[0], (float)srcYend / info->texH[0], +- (float)maskXend / info->texW[1], (float)maskYend / info->texH[1]); +- VTX_OUT((float)(dstX + w), (float)dstY, +- (float)srcXend / info->texW[0], (float)srcY / info->texH[0], +- (float)maskXend / info->texW[1], (float)maskY / info->texH[1]); ++ VTX_OUT((float)dstX, (float)dstY, ++ xFixedToFloat(srcTopLeft.x) / info->texW[0], xFixedToFloat(srcTopLeft.y) / info->texH[0], ++ xFixedToFloat(maskTopLeft.x) / info->texW[1], xFixedToFloat(maskTopLeft.y) / info->texH[1]); ++ VTX_OUT((float)dstX, (float)(dstY + h), ++ xFixedToFloat(srcBottomLeft.x) / info->texW[0], xFixedToFloat(srcBottomLeft.y) / info->texH[0], ++ xFixedToFloat(maskBottomLeft.x) / info->texW[1], xFixedToFloat(maskBottomLeft.y) / info->texH[1]); ++ VTX_OUT((float)(dstX + w), (float)(dstY + h), ++ xFixedToFloat(srcBottomRight.x) / info->texW[0], xFixedToFloat(srcBottomRight.y) / info->texH[0], ++ xFixedToFloat(maskBottomRight.x) / info->texW[1], xFixedToFloat(maskBottomRight.y) / info->texH[1]); ++ VTX_OUT((float)(dstX + w), (float)dstY, ++ xFixedToFloat(srcTopRight.x) / info->texW[0], xFixedToFloat(srcTopRight.y) / info->texH[0], ++ xFixedToFloat(maskTopRight.x) / info->texW[1], xFixedToFloat(maskTopRight.y) / info->texH[1]); + } + + #ifdef ACCEL_CP +diff --git a/src/radeon_output.c b/src/radeon_output.c +index 599a89c..6454460 100644 +--- a/src/radeon_output.c ++++ b/src/radeon_output.c +@@ -218,22 +218,33 @@ RADEONRestoreDVOChip(ScrnInfoPtr pScrn, xf86OutputPtr output) + (CARD32)~(RADEON_GPIO_A_0 | RADEON_GPIO_A_1)); + + if (!RADEONInitExtTMDSInfoFromBIOS(output)) { +- /* do mac stuff here */ +-#if defined(__powerpc__) + if (radeon_output->DVOChip) { +- switch(info->MacModel) { +- case RADEON_MAC_POWERBOOK_DL: ++ switch(info->ext_tmds_chip) { ++ case RADEON_SIL_164: + RADEONDVOWriteByte(radeon_output->DVOChip, 0x08, 0x30); + RADEONDVOWriteByte(radeon_output->DVOChip, 0x09, 0x00); + RADEONDVOWriteByte(radeon_output->DVOChip, 0x0a, 0x90); + RADEONDVOWriteByte(radeon_output->DVOChip, 0x0c, 0x89); + RADEONDVOWriteByte(radeon_output->DVOChip, 0x08, 0x3b); + break; ++#if 0 ++ /* needs work see bug 10418 */ ++ case RADEON_SIL_1178: ++ RADEONDVOWriteByte(radeon_output->DVOChip, 0x0f, 0x44); ++ RADEONDVOWriteByte(radeon_output->DVOChip, 0x0f, 0x4c); ++ RADEONDVOWriteByte(radeon_output->DVOChip, 0x0e, 0x01); ++ RADEONDVOWriteByte(radeon_output->DVOChip, 0x0a, 0x80); ++ RADEONDVOWriteByte(radeon_output->DVOChip, 0x09, 0x30); ++ RADEONDVOWriteByte(radeon_output->DVOChip, 0x0c, 0xc9); ++ RADEONDVOWriteByte(radeon_output->DVOChip, 0x0d, 0x70); ++ RADEONDVOWriteByte(radeon_output->DVOChip, 0x08, 0x32); ++ RADEONDVOWriteByte(radeon_output->DVOChip, 0x08, 0x33); ++ break; ++#endif + default: + break; + } + } +-#endif + } + } + +@@ -623,11 +634,18 @@ void RADEONConnectorFindMonitor(ScrnInfoPtr pScrn, xf86OutputPtr output) + + if (radeon_output->MonType == MT_UNKNOWN) { + if (radeon_output->type == OUTPUT_STV || radeon_output->type == OUTPUT_CTV) { +- if (info->InternalTVOut) { +- if (radeon_output->load_detection) +- radeon_output->MonType = radeon_detect_tv(pScrn); ++ if (xf86ReturnOptValBool(info->Options, OPTION_FORCE_TVOUT, FALSE)) { ++ if (radeon_output->type == OUTPUT_STV) ++ radeon_output->MonType = MT_STV; + else +- radeon_output->MonType = MT_NONE; ++ radeon_output->MonType = MT_CTV; ++ } else { ++ if (info->InternalTVOut) { ++ if (radeon_output->load_detection) ++ radeon_output->MonType = radeon_detect_tv(pScrn); ++ else ++ radeon_output->MonType = MT_NONE; ++ } + } + } else { + radeon_output->MonType = RADEONDisplayDDCConnected(pScrn, output); +@@ -666,6 +684,52 @@ void RADEONConnectorFindMonitor(ScrnInfoPtr pScrn, xf86OutputPtr output) + } + } + ++#ifndef __powerpc__ ++ ++static RADEONMonitorType ++RADEONDetectLidStatus(ScrnInfoPtr pScrn) ++{ ++ RADEONInfoPtr info = RADEONPTR(pScrn); ++ RADEONMonitorType MonType = MT_NONE; ++#ifdef __linux__ ++ char lidline[50]; /* 50 should be sufficient for our purposes */ ++ FILE *f = fopen ("/proc/acpi/button/lid/LID/state", "r"); ++ ++ if (f != NULL) { ++ while (fgets(lidline, sizeof lidline, f)) { ++ if (!strncmp(lidline, "state:", strlen ("state:"))) { ++ if (strstr(lidline, "open")) { ++ fclose(f); ++ ErrorF("proc lid open\n"); ++ return MT_LCD; ++ } ++ else if (strstr(lidline, "closed")) { ++ fclose(f); ++ ErrorF("proc lid closed\n"); ++ return MT_NONE; ++ } ++ } ++ } ++ fclose(f); ++ } ++#endif ++ ++ if (!info->IsAtomBios) { ++ unsigned char *RADEONMMIO = info->MMIO; ++ ++ /* see if the lid is closed -- only works at boot */ ++ if (INREG(RADEON_BIOS_6_SCRATCH) & 0x10) ++ MonType = MT_NONE; ++ else ++ MonType = MT_LCD; ++ } else ++ MonType = MT_LCD; ++ ++ return MonType; ++} ++ ++#endif /* __powerpc__ */ ++ + static RADEONMonitorType RADEONPortCheckNonDDC(ScrnInfoPtr pScrn, xf86OutputPtr output) + { + RADEONOutputPrivatePtr radeon_output = output->driver_private; +@@ -673,21 +737,10 @@ static RADEONMonitorType RADEONPortCheckNonDDC(ScrnInfoPtr pScrn, xf86OutputPtr + + if (radeon_output->type == OUTPUT_LVDS) { + #if defined(__powerpc__) +- /* not sure on ppc, OF? */ ++ MonType = MT_LCD; + #else +- RADEONInfoPtr info = RADEONPTR(pScrn); +- +- if (!info->IsAtomBios) { +- unsigned char *RADEONMMIO = info->MMIO; +- +- /* see if the lid is closed -- only works at boot */ +- if (INREG(RADEON_BIOS_6_SCRATCH) & 0x10) +- MonType = MT_NONE; +- else +- MonType = MT_LCD; +- } else ++ MonType = RADEONDetectLidStatus(pScrn); + #endif +- MonType = MT_LCD; + } /*else if (radeon_output->type == OUTPUT_DVI) { + if (radeon_output->TMDSType == TMDS_INT) { + if (INREG(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE) +@@ -782,7 +835,7 @@ radeon_mode_fixup(xf86OutputPtr output, DisplayModePtr mode, + } + + /* update timing for LVDS and DFP if RMX is active */ +- if ((radeon_output->MonType == MT_LCD) || (radeon_output->Flags & RADEON_USE_RMX)) { ++ if (radeon_output->Flags & RADEON_USE_RMX) { + /* set to the panel's native mode */ + adjusted_mode->HTotal = radeon_output->PanelXRes + radeon_output->HBlank; + adjusted_mode->HSyncStart = radeon_output->PanelXRes + radeon_output->HOverPlus; +@@ -937,7 +990,10 @@ static void RADEONInitLVDSRegisters(xf86OutputPtr output, RADEONSavePtr save, + + save->lvds_gen_cntl = info->SavedReg.lvds_gen_cntl; + save->lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS; +- save->lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON); ++ save->lvds_gen_cntl &= ~(RADEON_LVDS_ON | ++ RADEON_LVDS_BLON | ++ RADEON_LVDS_EN | ++ RADEON_LVDS_RST_FM); + + if (IS_R300_VARIANT) + save->lvds_pll_cntl &= ~(R300_LVDS_SRC_SEL_MASK); +@@ -1039,11 +1095,12 @@ static void RADEONInitDACRegisters(xf86OutputPtr output, RADEONSavePtr save, + save->dac_macro_cntl = info->SavedReg.dac_macro_cntl; + } + +-/* XXX: fix me */ + static void +-RADEONInitTvDacCntl(ScrnInfoPtr pScrn, RADEONSavePtr save) ++RADEONInitTvDacCntl(xf86OutputPtr output, RADEONSavePtr save) + { ++ ScrnInfoPtr pScrn = output->scrn; + RADEONInfoPtr info = RADEONPTR(pScrn); ++ RADEONOutputPrivatePtr radeon_output = output->driver_private; + + if (info->ChipFamily == CHIP_FAMILY_R420 || + info->ChipFamily == CHIP_FAMILY_RV410) { +@@ -1064,10 +1121,11 @@ RADEONInitTvDacCntl(ScrnInfoPtr pScrn, RADEONSavePtr save) + RADEON_TV_DAC_GDACPD | + RADEON_TV_DAC_GDACPD); + } +- /* FIXME: doesn't make sense, this just replaces the previous value... */ ++ + save->tv_dac_cntl |= (RADEON_TV_DAC_NBLANK | +- RADEON_TV_DAC_NHOLD | +- RADEON_TV_DAC_STD_PS2); ++ RADEON_TV_DAC_NHOLD | ++ RADEON_TV_DAC_STD_PS2 | ++ radeon_output->tv_dac_adj); + + } + +@@ -1078,7 +1136,7 @@ static void RADEONInitDAC2Registers(xf86OutputPtr output, RADEONSavePtr save, + RADEONInfoPtr info = RADEONPTR(pScrn); + + /*0x0028023;*/ +- RADEONInitTvDacCntl(pScrn, save); ++ RADEONInitTvDacCntl(output, save); + + if (IS_R300_VARIANT) + save->gpiopad_a = info->SavedReg.gpiopad_a | 1; +@@ -1670,10 +1728,16 @@ radeon_detect(xf86OutputPtr output) + /* default to unknown for flaky chips/connectors + * so we can get something on the screen + */ +- if (((radeon_output->type == OUTPUT_VGA || radeon_output->type == OUTPUT_DVI) && +- radeon_output->DACType == DAC_TVDAC) || +- (info->IsIGP && radeon_output->type == OUTPUT_DVI)) ++ if ((radeon_output->type == OUTPUT_VGA || radeon_output->type == OUTPUT_DVI) && ++ (radeon_output->DACType == DAC_TVDAC) && ++ (info->ChipFamily == CHIP_FAMILY_RS400)) { ++ radeon_output->MonType = MT_CRT; ++ return XF86OutputStatusUnknown; ++ } else if ((info->ChipFamily == CHIP_FAMILY_RS400) && ++ radeon_output->type == OUTPUT_DVI) { ++ radeon_output->MonType = MT_DFP; /* MT_LCD ??? */ + return XF86OutputStatusUnknown; ++ } + } + + if (connected) +@@ -1740,6 +1804,7 @@ radeon_create_resources(xf86OutputPtr output) + INT32 range[2]; + int data, err; + const char *s; ++ char *optstr; + + /* backlight control */ + if (radeon_output->type == OUTPUT_LVDS) { +@@ -1975,6 +2040,26 @@ radeon_create_resources(xf86OutputPtr output) + s = "ntsc"; + break; + } ++ ++ optstr = (char *)xf86GetOptValString(info->Options, OPTION_TVSTD); ++ if (optstr) { ++ if (!strncmp("ntsc", optstr, strlen("ntsc"))) ++ radeon_output->tvStd = TV_STD_NTSC; ++ else if (!strncmp("pal", optstr, strlen("pal"))) ++ radeon_output->tvStd = TV_STD_PAL; ++ else if (!strncmp("pal-m", optstr, strlen("pal-m"))) ++ radeon_output->tvStd = TV_STD_PAL_M; ++ else if (!strncmp("pal-60", optstr, strlen("pal-60"))) ++ radeon_output->tvStd = TV_STD_PAL_60; ++ else if (!strncmp("ntsc-j", optstr, strlen("ntsc-j"))) ++ radeon_output->tvStd = TV_STD_NTSC_J; ++ else if (!strncmp("scart-pal", optstr, strlen("scart-pal"))) ++ radeon_output->tvStd = TV_STD_SCART_PAL; ++ else { ++ xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Invalid TV Standard: %s\n", optstr); ++ } ++ } ++ + err = RRChangeOutputProperty(output->randr_output, tv_std_atom, + XA_STRING, 8, PropModeReplace, strlen(s), (pointer)s, + FALSE, FALSE); +@@ -2623,6 +2708,7 @@ void RADEONInitConnector(xf86OutputPtr output) + if (radeon_output->type == OUTPUT_STV || + radeon_output->type == OUTPUT_CTV) { + RADEONGetTVInfo(output); ++ RADEONGetTVDacAdjInfo(output); + } + + if (radeon_output->DACType == DAC_TVDAC) { +@@ -2658,7 +2744,7 @@ static Bool RADEONSetupAppleConnectors(ScrnInfoPtr pScrn) + info->BiosConnector[2].DDCType = DDC_NONE_DETECTED; + info->BiosConnector[2].valid = TRUE; + return TRUE; +- case RADEON_MAC_POWERBOOK_DL: ++ case RADEON_MAC_POWERBOOK_EXTERNAL: + info->BiosConnector[0].DDCType = DDC_DVI; + info->BiosConnector[0].DACType = DAC_NONE; + info->BiosConnector[0].TMDSType = TMDS_NONE; +@@ -2677,7 +2763,7 @@ static Bool RADEONSetupAppleConnectors(ScrnInfoPtr pScrn) + info->BiosConnector[2].DDCType = DDC_NONE_DETECTED; + info->BiosConnector[2].valid = TRUE; + return TRUE; +- case RADEON_MAC_POWERBOOK: ++ case RADEON_MAC_POWERBOOK_INTERNAL: + info->BiosConnector[0].DDCType = DDC_DVI; + info->BiosConnector[0].DACType = DAC_NONE; + info->BiosConnector[0].TMDSType = TMDS_NONE; +@@ -2696,7 +2782,26 @@ static Bool RADEONSetupAppleConnectors(ScrnInfoPtr pScrn) + info->BiosConnector[2].DDCType = DDC_NONE_DETECTED; + info->BiosConnector[2].valid = TRUE; + return TRUE; +- case RADEON_MAC_MINI: ++ case RADEON_MAC_POWERBOOK_VGA: ++ info->BiosConnector[0].DDCType = DDC_DVI; ++ info->BiosConnector[0].DACType = DAC_NONE; ++ info->BiosConnector[0].TMDSType = TMDS_NONE; ++ info->BiosConnector[0].ConnectorType = CONNECTOR_CRT; ++ info->BiosConnector[0].valid = TRUE; ++ ++ info->BiosConnector[1].DDCType = DDC_VGA; ++ info->BiosConnector[1].DACType = DAC_PRIMARY; ++ info->BiosConnector[1].TMDSType = TMDS_INT; ++ info->BiosConnector[1].ConnectorType = CONNECTOR_DVI_I; ++ info->BiosConnector[1].valid = TRUE; ++ ++ info->BiosConnector[2].ConnectorType = CONNECTOR_STV; ++ info->BiosConnector[2].DACType = DAC_TVDAC; ++ info->BiosConnector[2].TMDSType = TMDS_NONE; ++ info->BiosConnector[2].DDCType = DDC_NONE_DETECTED; ++ info->BiosConnector[2].valid = TRUE; ++ return TRUE; ++ case RADEON_MAC_MINI_EXTERNAL: + info->BiosConnector[0].DDCType = DDC_CRT2; + info->BiosConnector[0].DACType = DAC_TVDAC; + info->BiosConnector[0].TMDSType = TMDS_EXT; +@@ -2709,6 +2814,38 @@ static Bool RADEONSetupAppleConnectors(ScrnInfoPtr pScrn) + info->BiosConnector[1].DDCType = DDC_NONE_DETECTED; + info->BiosConnector[1].valid = TRUE; + return TRUE; ++ case RADEON_MAC_MINI_INTERNAL: ++ info->BiosConnector[0].DDCType = DDC_CRT2; ++ info->BiosConnector[0].DACType = DAC_TVDAC; ++ info->BiosConnector[0].TMDSType = TMDS_INT; ++ info->BiosConnector[0].ConnectorType = CONNECTOR_DVI_I; ++ info->BiosConnector[0].valid = TRUE; ++ ++ info->BiosConnector[1].ConnectorType = CONNECTOR_STV; ++ info->BiosConnector[1].DACType = DAC_TVDAC; ++ info->BiosConnector[1].TMDSType = TMDS_NONE; ++ info->BiosConnector[1].DDCType = DDC_NONE_DETECTED; ++ info->BiosConnector[1].valid = TRUE; ++ return TRUE; ++ case RADEON_MAC_IMAC_G5_ISIGHT: ++ info->BiosConnector[0].DDCType = DDC_MONID; ++ info->BiosConnector[0].DACType = DAC_NONE; ++ info->BiosConnector[0].TMDSType = TMDS_INT; ++ info->BiosConnector[0].ConnectorType = CONNECTOR_DVI_D; ++ info->BiosConnector[0].valid = TRUE; ++ ++ info->BiosConnector[1].DDCType = DDC_DVI; ++ info->BiosConnector[1].DACType = DAC_TVDAC; ++ info->BiosConnector[1].TMDSType = TMDS_NONE; ++ info->BiosConnector[1].ConnectorType = CONNECTOR_CRT; ++ info->BiosConnector[1].valid = TRUE; ++ ++ info->BiosConnector[2].ConnectorType = CONNECTOR_STV; ++ info->BiosConnector[2].DACType = DAC_TVDAC; ++ info->BiosConnector[2].TMDSType = TMDS_NONE; ++ info->BiosConnector[2].DDCType = DDC_NONE_DETECTED; ++ info->BiosConnector[2].valid = TRUE; ++ return TRUE; + default: + return FALSE; + } +@@ -2793,11 +2930,19 @@ static void RADEONSetupGenericConnectors(ScrnInfoPtr pScrn) + info->BiosConnector[0].ConnectorType = CONNECTOR_DVI_I; + info->BiosConnector[0].valid = TRUE; + ++#if defined(__powerpc__) + info->BiosConnector[1].DDCType = DDC_VGA; + info->BiosConnector[1].DACType = DAC_PRIMARY; + info->BiosConnector[1].TMDSType = TMDS_EXT; ++ info->BiosConnector[1].ConnectorType = CONNECTOR_DVI_I; ++ info->BiosConnector[1].valid = TRUE; ++#else ++ info->BiosConnector[1].DDCType = DDC_VGA; ++ info->BiosConnector[1].DACType = DAC_PRIMARY; ++ info->BiosConnector[1].TMDSType = TMDS_NONE; + info->BiosConnector[1].ConnectorType = CONNECTOR_CRT; + info->BiosConnector[1].valid = TRUE; ++#endif + } + } + +@@ -2826,40 +2971,81 @@ static void RADEONSetupGenericConnectors(ScrnInfoPtr pScrn) + * in /proc/cpuinfo (on Linux) */ + static RADEONMacModel RADEONDetectMacModel(ScrnInfoPtr pScrn) + { ++ RADEONInfoPtr info = RADEONPTR(pScrn); + RADEONMacModel ret = 0; + #ifdef __linux__ + char cpuline[50]; /* 50 should be sufficient for our purposes */ + FILE *f = fopen ("/proc/cpuinfo", "r"); + ++ /* Some macs (minis and powerbooks) use internal tmds, others use external tmds ++ * and not just for dual-link TMDS, it shows up with single-link as well. ++ * Unforunately, there doesn't seem to be any good way to figure it out. ++ */ ++ ++ /* ++ * PowerBook5,[1-5]: external tmds, single-link ++ * PowerBook5,[789]: external tmds, dual-link ++ * PowerBook5,6: external tmds, single-link or dual-link ++ * need to add another option to specify the external tmds chip ++ * or find out what's used and add it. ++ */ ++ ++ + if (f != NULL) { + while (fgets(cpuline, sizeof cpuline, f)) { + if (!strncmp(cpuline, "machine", strlen ("machine"))) { +- if (strstr(cpuline, "PowerBook5,6") || +- strstr(cpuline, "PowerBook5,7") || ++ if (strstr(cpuline, "PowerBook5,1") || ++ strstr(cpuline, "PowerBook5,2") || ++ strstr(cpuline, "PowerBook5,3") || ++ strstr(cpuline, "PowerBook5,4") || ++ strstr(cpuline, "PowerBook5,5")) { ++ ret = RADEON_MAC_POWERBOOK_EXTERNAL; /* single link */ ++ info->ext_tmds_chip = RADEON_SIL_164; /* works on 5,2 */ ++ break; ++ } ++ ++ if (strstr(cpuline, "PowerBook5,6")) { ++ ret = RADEON_MAC_POWERBOOK_EXTERNAL; /* dual or single link */ ++ break; ++ } ++ ++ if (strstr(cpuline, "PowerBook5,7") || + strstr(cpuline, "PowerBook5,8") || + strstr(cpuline, "PowerBook5,9")) { +- ret = RADEON_MAC_POWERBOOK_DL; ++ ret = RADEON_MAC_POWERBOOK_EXTERNAL; /* dual link */ ++ info->ext_tmds_chip = RADEON_SIL_1178; /* guess */ ++ break; ++ } ++ ++ if (strstr(cpuline, "PowerBook3,3")) { ++ ret = RADEON_MAC_POWERBOOK_VGA; /* vga rather than dvi */ + break; + } + +- if (strstr(cpuline, "PowerMac10,1") || +- strstr(cpuline, "PowerMac10,2")) { +- ret = RADEON_MAC_MINI; ++ if (strstr(cpuline, "PowerMac10,1")) { ++ ret = RADEON_MAC_MINI_INTERNAL; /* internal tmds */ ++ break; ++ } ++ if (strstr(cpuline, "PowerMac10,2")) { ++ ret = RADEON_MAC_MINI_EXTERNAL; /* external tmds */ + break; + } + } else if (!strncmp(cpuline, "detected as", strlen("detected as"))) { +- if (strstr(cpuline, "iBook")) { +- ret = RADEON_MAC_IBOOK; ++ if (strstr(cpuline, "iBook")) { ++ ret = RADEON_MAC_IBOOK; + break; + } else if (strstr(cpuline, "PowerBook")) { +- ret = RADEON_MAC_POWERBOOK_DL; ++ ret = RADEON_MAC_POWERBOOK_INTERNAL; /* internal tmds */ + break; +- } ++ } else if (strstr(cpuline, "iMac G5 (iSight)")) { ++ ret = RADEON_MAC_IMAC_G5_ISIGHT; ++ break; ++ } + +- /* No known PowerMac model detected */ +- break; +- } +- } ++ /* No known PowerMac model detected */ ++ break; ++ } ++ } + + fclose (f); + } else +@@ -2871,10 +3057,13 @@ static RADEONMacModel RADEONDetectMacModel(ScrnInfoPtr pScrn) + + if (ret) { + xf86DrvMsg(pScrn->scrnIndex, X_DEFAULT, "Detected %s.\n", +- ret == RADEON_MAC_POWERBOOK_DL ? "PowerBook with dual link DVI" : +- ret == RADEON_MAC_POWERBOOK ? "PowerBook with single link DVI" : ++ ret == RADEON_MAC_POWERBOOK_EXTERNAL ? "PowerBook with external DVI" : ++ ret == RADEON_MAC_POWERBOOK_INTERNAL ? "PowerBook with integrated DVI" : ++ ret == RADEON_MAC_POWERBOOK_VGA ? "PowerBook with VGA" : + ret == RADEON_MAC_IBOOK ? "iBook" : +- "Mac Mini"); ++ ret == RADEON_MAC_MINI_EXTERNAL ? "Mac Mini with external DVI" : ++ ret == RADEON_MAC_MINI_INTERNAL ? "Mac Mini with integrated DVI" : ++ "iMac G5 iSight"); + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + "If this is not correct, try Option \"MacModel\" and " + "consider reporting to the\n"); +@@ -2921,12 +3110,24 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn) + if (optstr) { + if (!strncmp("ibook", optstr, strlen("ibook"))) + info->MacModel = RADEON_MAC_IBOOK; +- else if (!strncmp("powerbook-duallink", optstr, strlen("powerbook-duallink"))) +- info->MacModel = RADEON_MAC_POWERBOOK_DL; +- else if (!strncmp("powerbook", optstr, strlen("powerbook"))) +- info->MacModel = RADEON_MAC_POWERBOOK; +- else if (!strncmp("mini", optstr, strlen("mini"))) +- info->MacModel = RADEON_MAC_MINI; ++ else if (!strncmp("powerbook-duallink", optstr, strlen("powerbook-duallink"))) /* alias */ ++ info->MacModel = RADEON_MAC_POWERBOOK_EXTERNAL; ++ else if (!strncmp("powerbook-external", optstr, strlen("powerbook-external"))) ++ info->MacModel = RADEON_MAC_POWERBOOK_EXTERNAL; ++ else if (!strncmp("powerbook-internal", optstr, strlen("powerbook-internal"))) ++ info->MacModel = RADEON_MAC_POWERBOOK_INTERNAL; ++ else if (!strncmp("powerbook-vga", optstr, strlen("powerbook-vga"))) ++ info->MacModel = RADEON_MAC_POWERBOOK_VGA; ++ else if (!strncmp("powerbook", optstr, strlen("powerbook"))) /* alias */ ++ info->MacModel = RADEON_MAC_POWERBOOK_INTERNAL; ++ else if (!strncmp("mini-internal", optstr, strlen("mini-internal"))) ++ info->MacModel = RADEON_MAC_MINI_INTERNAL; ++ else if (!strncmp("mini-external", optstr, strlen("mini-external"))) ++ info->MacModel = RADEON_MAC_MINI_EXTERNAL; ++ else if (!strncmp("mini", optstr, strlen("mini"))) /* alias */ ++ info->MacModel = RADEON_MAC_MINI_EXTERNAL; ++ else if (!strncmp("imac-g5-isight", optstr, strlen("imac-g5-isight"))) ++ info->MacModel = RADEON_MAC_IMAC_G5_ISIGHT; + else { + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Invalid Mac Model: %s\n", optstr); + } +@@ -3009,6 +3210,14 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn) + } + } + ++ /* clear the enable masks */ ++ info->output_crt1 = 0; ++ info->output_crt2 = 0; ++ info->output_dfp1 = 0; ++ info->output_dfp2 = 0; ++ info->output_lcd1 = 0; ++ info->output_tv1 = 0; ++ + for (i = 0 ; i < RADEON_MAX_BIOS_CONNECTOR; i++) { + if (info->BiosConnector[i].valid) { + RADEONOutputPrivatePtr radeon_output = xnfcalloc(sizeof(RADEONOutputPrivateRec), 1); +diff --git a/src/radeon_pci_chipset_gen.h b/src/radeon_pci_chipset_gen.h +new file mode 100644 +index 0000000..7a36242 +--- /dev/null ++++ b/src/radeon_pci_chipset_gen.h +@@ -0,0 +1,141 @@ ++/* This file is autogenerated please do not edit */ ++PciChipsets RADEONPciChipsets[] = { ++ { PCI_CHIP_RV380_3150, PCI_CHIP_RV380_3150, RES_SHARED_VGA }, ++ { PCI_CHIP_RV380_3152, PCI_CHIP_RV380_3152, RES_SHARED_VGA }, ++ { PCI_CHIP_RV380_3154, PCI_CHIP_RV380_3154, RES_SHARED_VGA }, ++ { PCI_CHIP_RV380_3E50, PCI_CHIP_RV380_3E50, RES_SHARED_VGA }, ++ { PCI_CHIP_RV380_3E54, PCI_CHIP_RV380_3E54, RES_SHARED_VGA }, ++ { PCI_CHIP_RS100_4136, PCI_CHIP_RS100_4136, RES_SHARED_VGA }, ++ { PCI_CHIP_RS200_4137, PCI_CHIP_RS200_4137, RES_SHARED_VGA }, ++ { PCI_CHIP_R300_AD, PCI_CHIP_R300_AD, RES_SHARED_VGA }, ++ { PCI_CHIP_R300_AE, PCI_CHIP_R300_AE, RES_SHARED_VGA }, ++ { PCI_CHIP_R300_AF, PCI_CHIP_R300_AF, RES_SHARED_VGA }, ++ { PCI_CHIP_R300_AG, PCI_CHIP_R300_AG, RES_SHARED_VGA }, ++ { PCI_CHIP_R350_AH, PCI_CHIP_R350_AH, RES_SHARED_VGA }, ++ { PCI_CHIP_R350_AI, PCI_CHIP_R350_AI, RES_SHARED_VGA }, ++ { PCI_CHIP_R350_AJ, PCI_CHIP_R350_AJ, RES_SHARED_VGA }, ++ { PCI_CHIP_R350_AK, PCI_CHIP_R350_AK, RES_SHARED_VGA }, ++ { PCI_CHIP_RV350_AP, PCI_CHIP_RV350_AP, RES_SHARED_VGA }, ++ { PCI_CHIP_RV350_AQ, PCI_CHIP_RV350_AQ, RES_SHARED_VGA }, ++ { PCI_CHIP_RV360_AR, PCI_CHIP_RV360_AR, RES_SHARED_VGA }, ++ { PCI_CHIP_RV350_AS, PCI_CHIP_RV350_AS, RES_SHARED_VGA }, ++ { PCI_CHIP_RV350_AT, PCI_CHIP_RV350_AT, RES_SHARED_VGA }, ++ { PCI_CHIP_RV350_4155, PCI_CHIP_RV350_4155, RES_SHARED_VGA }, ++ { PCI_CHIP_RV350_AV, PCI_CHIP_RV350_AV, RES_SHARED_VGA }, ++ { PCI_CHIP_RS250_4237, PCI_CHIP_RS250_4237, RES_SHARED_VGA }, ++ { PCI_CHIP_R200_BB, PCI_CHIP_R200_BB, RES_SHARED_VGA }, ++ { PCI_CHIP_R200_BC, PCI_CHIP_R200_BC, RES_SHARED_VGA }, ++ { PCI_CHIP_RS100_4336, PCI_CHIP_RS100_4336, RES_SHARED_VGA }, ++ { PCI_CHIP_RS200_4337, PCI_CHIP_RS200_4337, RES_SHARED_VGA }, ++ { PCI_CHIP_RS250_4437, PCI_CHIP_RS250_4437, RES_SHARED_VGA }, ++ { PCI_CHIP_RV250_If, PCI_CHIP_RV250_If, RES_SHARED_VGA }, ++ { PCI_CHIP_RV250_Ig, PCI_CHIP_RV250_Ig, RES_SHARED_VGA }, ++ { PCI_CHIP_R420_JH, PCI_CHIP_R420_JH, RES_SHARED_VGA }, ++ { PCI_CHIP_R420_JI, PCI_CHIP_R420_JI, RES_SHARED_VGA }, ++ { PCI_CHIP_R420_JJ, PCI_CHIP_R420_JJ, RES_SHARED_VGA }, ++ { PCI_CHIP_R420_JK, PCI_CHIP_R420_JK, RES_SHARED_VGA }, ++ { PCI_CHIP_R420_JL, PCI_CHIP_R420_JL, RES_SHARED_VGA }, ++ { PCI_CHIP_R420_JM, PCI_CHIP_R420_JM, RES_SHARED_VGA }, ++ { PCI_CHIP_R420_JN, PCI_CHIP_R420_JN, RES_SHARED_VGA }, ++ { PCI_CHIP_R420_4A4F, PCI_CHIP_R420_4A4F, RES_SHARED_VGA }, ++ { PCI_CHIP_R420_JP, PCI_CHIP_R420_JP, RES_SHARED_VGA }, ++ { PCI_CHIP_R481_4B49, PCI_CHIP_R481_4B49, RES_SHARED_VGA }, ++ { PCI_CHIP_R481_4B4A, PCI_CHIP_R481_4B4A, RES_SHARED_VGA }, ++ { PCI_CHIP_R481_4B4B, PCI_CHIP_R481_4B4B, RES_SHARED_VGA }, ++ { PCI_CHIP_R481_4B4C, PCI_CHIP_R481_4B4C, RES_SHARED_VGA }, ++ { PCI_CHIP_RADEON_LW, PCI_CHIP_RADEON_LW, RES_SHARED_VGA }, ++ { PCI_CHIP_RADEON_LX, PCI_CHIP_RADEON_LX, RES_SHARED_VGA }, ++ { PCI_CHIP_RADEON_LY, PCI_CHIP_RADEON_LY, RES_SHARED_VGA }, ++ { PCI_CHIP_RADEON_LZ, PCI_CHIP_RADEON_LZ, RES_SHARED_VGA }, ++ { PCI_CHIP_RV250_Ld, PCI_CHIP_RV250_Ld, RES_SHARED_VGA }, ++ { PCI_CHIP_RV250_Lf, PCI_CHIP_RV250_Lf, RES_SHARED_VGA }, ++ { PCI_CHIP_RV250_Lg, PCI_CHIP_RV250_Lg, RES_SHARED_VGA }, ++ { PCI_CHIP_R300_ND, PCI_CHIP_R300_ND, RES_SHARED_VGA }, ++ { PCI_CHIP_R300_NE, PCI_CHIP_R300_NE, RES_SHARED_VGA }, ++ { PCI_CHIP_R300_NF, PCI_CHIP_R300_NF, RES_SHARED_VGA }, ++ { PCI_CHIP_R300_NG, PCI_CHIP_R300_NG, RES_SHARED_VGA }, ++ { PCI_CHIP_R350_NH, PCI_CHIP_R350_NH, RES_SHARED_VGA }, ++ { PCI_CHIP_R350_NI, PCI_CHIP_R350_NI, RES_SHARED_VGA }, ++ { PCI_CHIP_R360_NJ, PCI_CHIP_R360_NJ, RES_SHARED_VGA }, ++ { PCI_CHIP_R350_NK, PCI_CHIP_R350_NK, RES_SHARED_VGA }, ++ { PCI_CHIP_RV350_NP, PCI_CHIP_RV350_NP, RES_SHARED_VGA }, ++ { PCI_CHIP_RV350_NQ, PCI_CHIP_RV350_NQ, RES_SHARED_VGA }, ++ { PCI_CHIP_RV350_NR, PCI_CHIP_RV350_NR, RES_SHARED_VGA }, ++ { PCI_CHIP_RV350_NS, PCI_CHIP_RV350_NS, RES_SHARED_VGA }, ++ { PCI_CHIP_RV350_NT, PCI_CHIP_RV350_NT, RES_SHARED_VGA }, ++ { PCI_CHIP_RV350_NV, PCI_CHIP_RV350_NV, RES_SHARED_VGA }, ++ { PCI_CHIP_RADEON_QD, PCI_CHIP_RADEON_QD, RES_SHARED_VGA }, ++ { PCI_CHIP_RADEON_QE, PCI_CHIP_RADEON_QE, RES_SHARED_VGA }, ++ { PCI_CHIP_RADEON_QF, PCI_CHIP_RADEON_QF, RES_SHARED_VGA }, ++ { PCI_CHIP_RADEON_QG, PCI_CHIP_RADEON_QG, RES_SHARED_VGA }, ++ { PCI_CHIP_R200_QH, PCI_CHIP_R200_QH, RES_SHARED_VGA }, ++ { PCI_CHIP_R200_QL, PCI_CHIP_R200_QL, RES_SHARED_VGA }, ++ { PCI_CHIP_R200_QM, PCI_CHIP_R200_QM, RES_SHARED_VGA }, ++ { PCI_CHIP_RV200_QW, PCI_CHIP_RV200_QW, RES_SHARED_VGA }, ++ { PCI_CHIP_RV200_QX, PCI_CHIP_RV200_QX, RES_SHARED_VGA }, ++ { PCI_CHIP_RV100_QY, PCI_CHIP_RV100_QY, RES_SHARED_VGA }, ++ { PCI_CHIP_RV100_QZ, PCI_CHIP_RV100_QZ, RES_SHARED_VGA }, ++ { PCI_CHIP_RN50_515E, PCI_CHIP_RN50_515E, RES_SHARED_VGA }, ++ { PCI_CHIP_RV370_5460, PCI_CHIP_RV370_5460, RES_SHARED_VGA }, ++ { PCI_CHIP_RV370_5462, PCI_CHIP_RV370_5462, RES_SHARED_VGA }, ++ { PCI_CHIP_RV370_5464, PCI_CHIP_RV370_5464, RES_SHARED_VGA }, ++ { PCI_CHIP_R423_UH, PCI_CHIP_R423_UH, RES_SHARED_VGA }, ++ { PCI_CHIP_R423_UI, PCI_CHIP_R423_UI, RES_SHARED_VGA }, ++ { PCI_CHIP_R423_UJ, PCI_CHIP_R423_UJ, RES_SHARED_VGA }, ++ { PCI_CHIP_R423_UK, PCI_CHIP_R423_UK, RES_SHARED_VGA }, ++ { PCI_CHIP_R430_554C, PCI_CHIP_R430_554C, RES_SHARED_VGA }, ++ { PCI_CHIP_R430_554D, PCI_CHIP_R430_554D, RES_SHARED_VGA }, ++ { PCI_CHIP_R430_554E, PCI_CHIP_R430_554E, RES_SHARED_VGA }, ++ { PCI_CHIP_R430_554F, PCI_CHIP_R430_554F, RES_SHARED_VGA }, ++ { PCI_CHIP_R423_5550, PCI_CHIP_R423_5550, RES_SHARED_VGA }, ++ { PCI_CHIP_R423_UQ, PCI_CHIP_R423_UQ, RES_SHARED_VGA }, ++ { PCI_CHIP_R423_UR, PCI_CHIP_R423_UR, RES_SHARED_VGA }, ++ { PCI_CHIP_R423_UT, PCI_CHIP_R423_UT, RES_SHARED_VGA }, ++ { PCI_CHIP_RV410_564A, PCI_CHIP_RV410_564A, RES_SHARED_VGA }, ++ { PCI_CHIP_RV410_564B, PCI_CHIP_RV410_564B, RES_SHARED_VGA }, ++ { PCI_CHIP_RV410_564F, PCI_CHIP_RV410_564F, RES_SHARED_VGA }, ++ { PCI_CHIP_RV410_5652, PCI_CHIP_RV410_5652, RES_SHARED_VGA }, ++ { PCI_CHIP_RV410_5653, PCI_CHIP_RV410_5653, RES_SHARED_VGA }, ++ { PCI_CHIP_RS300_5834, PCI_CHIP_RS300_5834, RES_SHARED_VGA }, ++ { PCI_CHIP_RS300_5835, PCI_CHIP_RS300_5835, RES_SHARED_VGA }, ++ { PCI_CHIP_RS480_5954, PCI_CHIP_RS480_5954, RES_SHARED_VGA }, ++ { PCI_CHIP_RS480_5955, PCI_CHIP_RS480_5955, RES_SHARED_VGA }, ++ { PCI_CHIP_RV280_5960, PCI_CHIP_RV280_5960, RES_SHARED_VGA }, ++ { PCI_CHIP_RV280_5961, PCI_CHIP_RV280_5961, RES_SHARED_VGA }, ++ { PCI_CHIP_RV280_5962, PCI_CHIP_RV280_5962, RES_SHARED_VGA }, ++ { PCI_CHIP_RV280_5964, PCI_CHIP_RV280_5964, RES_SHARED_VGA }, ++ { PCI_CHIP_RV280_5965, PCI_CHIP_RV280_5965, RES_SHARED_VGA }, ++ { PCI_CHIP_RN50_5969, PCI_CHIP_RN50_5969, RES_SHARED_VGA }, ++ { PCI_CHIP_RS482_5974, PCI_CHIP_RS482_5974, RES_SHARED_VGA }, ++ { PCI_CHIP_RS485_5975, PCI_CHIP_RS485_5975, RES_SHARED_VGA }, ++ { PCI_CHIP_RS400_5A41, PCI_CHIP_RS400_5A41, RES_SHARED_VGA }, ++ { PCI_CHIP_RS400_5A42, PCI_CHIP_RS400_5A42, RES_SHARED_VGA }, ++ { PCI_CHIP_RC410_5A61, PCI_CHIP_RC410_5A61, RES_SHARED_VGA }, ++ { PCI_CHIP_RC410_5A62, PCI_CHIP_RC410_5A62, RES_SHARED_VGA }, ++ { PCI_CHIP_RV370_5B60, PCI_CHIP_RV370_5B60, RES_SHARED_VGA }, ++ { PCI_CHIP_RV370_5B62, PCI_CHIP_RV370_5B62, RES_SHARED_VGA }, ++ { PCI_CHIP_RV370_5B63, PCI_CHIP_RV370_5B63, RES_SHARED_VGA }, ++ { PCI_CHIP_RV370_5B64, PCI_CHIP_RV370_5B64, RES_SHARED_VGA }, ++ { PCI_CHIP_RV370_5B65, PCI_CHIP_RV370_5B65, RES_SHARED_VGA }, ++ { PCI_CHIP_RV280_5C61, PCI_CHIP_RV280_5C61, RES_SHARED_VGA }, ++ { PCI_CHIP_RV280_5C63, PCI_CHIP_RV280_5C63, RES_SHARED_VGA }, ++ { PCI_CHIP_R430_5D48, PCI_CHIP_R430_5D48, RES_SHARED_VGA }, ++ { PCI_CHIP_R430_5D49, PCI_CHIP_R430_5D49, RES_SHARED_VGA }, ++ { PCI_CHIP_R430_5D4A, PCI_CHIP_R430_5D4A, RES_SHARED_VGA }, ++ { PCI_CHIP_R480_5D4C, PCI_CHIP_R480_5D4C, RES_SHARED_VGA }, ++ { PCI_CHIP_R480_5D4D, PCI_CHIP_R480_5D4D, RES_SHARED_VGA }, ++ { PCI_CHIP_R480_5D4E, PCI_CHIP_R480_5D4E, RES_SHARED_VGA }, ++ { PCI_CHIP_R480_5D4F, PCI_CHIP_R480_5D4F, RES_SHARED_VGA }, ++ { PCI_CHIP_R480_5D50, PCI_CHIP_R480_5D50, RES_SHARED_VGA }, ++ { PCI_CHIP_R480_5D52, PCI_CHIP_R480_5D52, RES_SHARED_VGA }, ++ { PCI_CHIP_R423_5D57, PCI_CHIP_R423_5D57, RES_SHARED_VGA }, ++ { PCI_CHIP_RV410_5E48, PCI_CHIP_RV410_5E48, RES_SHARED_VGA }, ++ { PCI_CHIP_RV410_5E4A, PCI_CHIP_RV410_5E4A, RES_SHARED_VGA }, ++ { PCI_CHIP_RV410_5E4B, PCI_CHIP_RV410_5E4B, RES_SHARED_VGA }, ++ { PCI_CHIP_RV410_5E4C, PCI_CHIP_RV410_5E4C, RES_SHARED_VGA }, ++ { PCI_CHIP_RV410_5E4D, PCI_CHIP_RV410_5E4D, RES_SHARED_VGA }, ++ { PCI_CHIP_RV410_5E4F, PCI_CHIP_RV410_5E4F, RES_SHARED_VGA }, ++ { PCI_CHIP_RS350_7834, PCI_CHIP_RS350_7834, RES_SHARED_VGA }, ++ { PCI_CHIP_RS350_7835, PCI_CHIP_RS350_7835, RES_SHARED_VGA }, ++ { -1, -1, RES_UNDEFINED } ++}; +diff --git a/src/radeon_probe.c b/src/radeon_probe.c +index d68a956..baea47c 100644 +--- a/src/radeon_probe.c ++++ b/src/radeon_probe.c +@@ -51,150 +51,9 @@ + #include + #include "xf86Resources.h" + +-#include "radeon_chipset.h" ++#include "radeon_chipset_gen.h" + +-PciChipsets RADEONPciChipsets[] = { +- { PCI_CHIP_RADEON_QD, PCI_CHIP_RADEON_QD, RES_SHARED_VGA }, +- { PCI_CHIP_RADEON_QE, PCI_CHIP_RADEON_QE, RES_SHARED_VGA }, +- { PCI_CHIP_RADEON_QF, PCI_CHIP_RADEON_QF, RES_SHARED_VGA }, +- { PCI_CHIP_RADEON_QG, PCI_CHIP_RADEON_QG, RES_SHARED_VGA }, +- { PCI_CHIP_RV100_QY, PCI_CHIP_RV100_QY, RES_SHARED_VGA }, +- { PCI_CHIP_RV100_QZ, PCI_CHIP_RV100_QZ, RES_SHARED_VGA }, +- { PCI_CHIP_RN50_515E, PCI_CHIP_RN50_515E, RES_SHARED_VGA }, +- { PCI_CHIP_RN50_5969, PCI_CHIP_RN50_5969, RES_SHARED_VGA }, +- { PCI_CHIP_RADEON_LW, PCI_CHIP_RADEON_LW, RES_SHARED_VGA }, +- { PCI_CHIP_RADEON_LX, PCI_CHIP_RADEON_LX, RES_SHARED_VGA }, +- { PCI_CHIP_RADEON_LY, PCI_CHIP_RADEON_LY, RES_SHARED_VGA }, +- { PCI_CHIP_RADEON_LZ, PCI_CHIP_RADEON_LZ, RES_SHARED_VGA }, +- { PCI_CHIP_RS100_4136, PCI_CHIP_RS100_4136, RES_SHARED_VGA }, +- { PCI_CHIP_RS100_4336, PCI_CHIP_RS100_4336, RES_SHARED_VGA }, +- { PCI_CHIP_RS200_4137, PCI_CHIP_RS200_4137, RES_SHARED_VGA }, +- { PCI_CHIP_RS200_4337, PCI_CHIP_RS200_4337, RES_SHARED_VGA }, +- { PCI_CHIP_RS250_4237, PCI_CHIP_RS250_4237, RES_SHARED_VGA }, +- { PCI_CHIP_RS250_4437, PCI_CHIP_RS250_4437, RES_SHARED_VGA }, +- { PCI_CHIP_R200_QH, PCI_CHIP_R200_QH, RES_SHARED_VGA }, +- { PCI_CHIP_R200_QL, PCI_CHIP_R200_QL, RES_SHARED_VGA }, +- { PCI_CHIP_R200_QM, PCI_CHIP_R200_QM, RES_SHARED_VGA }, +- { PCI_CHIP_R200_BB, PCI_CHIP_R200_BB, RES_SHARED_VGA }, +- { PCI_CHIP_R200_BC, PCI_CHIP_R200_BC, RES_SHARED_VGA }, +- { PCI_CHIP_RV200_QW, PCI_CHIP_RV200_QW, RES_SHARED_VGA }, +- { PCI_CHIP_RV200_QX, PCI_CHIP_RV200_QX, RES_SHARED_VGA }, +- { PCI_CHIP_RV250_If, PCI_CHIP_RV250_If, RES_SHARED_VGA }, +- { PCI_CHIP_RV250_Ig, PCI_CHIP_RV250_Ig, RES_SHARED_VGA }, +- { PCI_CHIP_RV250_Ld, PCI_CHIP_RV250_Ld, RES_SHARED_VGA }, +- { PCI_CHIP_RV250_Lf, PCI_CHIP_RV250_Lf, RES_SHARED_VGA }, +- { PCI_CHIP_RV250_Lg, PCI_CHIP_RV250_Lg, RES_SHARED_VGA }, +- { PCI_CHIP_RS300_5834, PCI_CHIP_RS300_5834, RES_SHARED_VGA }, +- { PCI_CHIP_RS300_5835, PCI_CHIP_RS300_5835, RES_SHARED_VGA }, +- { PCI_CHIP_RS350_7834, PCI_CHIP_RS350_7834, RES_SHARED_VGA }, +- { PCI_CHIP_RS350_7835, PCI_CHIP_RS350_7835, RES_SHARED_VGA }, +- { PCI_CHIP_RV280_5960, PCI_CHIP_RV280_5960, RES_SHARED_VGA }, +- { PCI_CHIP_RV280_5961, PCI_CHIP_RV280_5961, RES_SHARED_VGA }, +- { PCI_CHIP_RV280_5962, PCI_CHIP_RV280_5962, RES_SHARED_VGA }, +- { PCI_CHIP_RV280_5964, PCI_CHIP_RV280_5964, RES_SHARED_VGA }, +- { PCI_CHIP_RV280_5965, PCI_CHIP_RV280_5965, RES_SHARED_VGA }, +- { PCI_CHIP_RV280_5C61, PCI_CHIP_RV280_5C61, RES_SHARED_VGA }, +- { PCI_CHIP_RV280_5C63, PCI_CHIP_RV280_5C63, RES_SHARED_VGA }, +- { PCI_CHIP_R300_AD, PCI_CHIP_R300_AD, RES_SHARED_VGA }, +- { PCI_CHIP_R300_AE, PCI_CHIP_R300_AE, RES_SHARED_VGA }, +- { PCI_CHIP_R300_AF, PCI_CHIP_R300_AF, RES_SHARED_VGA }, +- { PCI_CHIP_R300_AG, PCI_CHIP_R300_AG, RES_SHARED_VGA }, +- { PCI_CHIP_R300_ND, PCI_CHIP_R300_ND, RES_SHARED_VGA }, +- { PCI_CHIP_R300_NE, PCI_CHIP_R300_NE, RES_SHARED_VGA }, +- { PCI_CHIP_R300_NF, PCI_CHIP_R300_NF, RES_SHARED_VGA }, +- { PCI_CHIP_R300_NG, PCI_CHIP_R300_NG, RES_SHARED_VGA }, +- { PCI_CHIP_RV350_AP, PCI_CHIP_RV350_AP, RES_SHARED_VGA }, +- { PCI_CHIP_RV350_AQ, PCI_CHIP_RV350_AQ, RES_SHARED_VGA }, +- { PCI_CHIP_RV360_AR, PCI_CHIP_RV360_AR, RES_SHARED_VGA }, +- { PCI_CHIP_RV350_AS, PCI_CHIP_RV350_AS, RES_SHARED_VGA }, +- { PCI_CHIP_RV350_AT, PCI_CHIP_RV350_AT, RES_SHARED_VGA }, +- { PCI_CHIP_RV350_AV, PCI_CHIP_RV350_AV, RES_SHARED_VGA }, +- { PCI_CHIP_RV350_NP, PCI_CHIP_RV350_NP, RES_SHARED_VGA }, +- { PCI_CHIP_RV350_NQ, PCI_CHIP_RV350_NQ, RES_SHARED_VGA }, +- { PCI_CHIP_RV350_NR, PCI_CHIP_RV350_NR, RES_SHARED_VGA }, +- { PCI_CHIP_RV350_NS, PCI_CHIP_RV350_NS, RES_SHARED_VGA }, +- { PCI_CHIP_RV350_NT, PCI_CHIP_RV350_NT, RES_SHARED_VGA }, +- { PCI_CHIP_RV350_NV, PCI_CHIP_RV350_NV, RES_SHARED_VGA }, +- { PCI_CHIP_RV350_4155, PCI_CHIP_RV350_4155, RES_SHARED_VGA }, +- { PCI_CHIP_R350_AH, PCI_CHIP_R350_AH, RES_SHARED_VGA }, +- { PCI_CHIP_R350_AI, PCI_CHIP_R350_AI, RES_SHARED_VGA }, +- { PCI_CHIP_R350_AJ, PCI_CHIP_R350_AJ, RES_SHARED_VGA }, +- { PCI_CHIP_R350_AK, PCI_CHIP_R350_AK, RES_SHARED_VGA }, +- { PCI_CHIP_R350_NH, PCI_CHIP_R350_NH, RES_SHARED_VGA }, +- { PCI_CHIP_R350_NI, PCI_CHIP_R350_NI, RES_SHARED_VGA }, +- { PCI_CHIP_R350_NK, PCI_CHIP_R350_NK, RES_SHARED_VGA }, +- { PCI_CHIP_R360_NJ, PCI_CHIP_R360_NJ, RES_SHARED_VGA }, +- { PCI_CHIP_RV380_3E50, PCI_CHIP_RV380_3E50, RES_SHARED_VGA }, +- { PCI_CHIP_RV380_3E54, PCI_CHIP_RV380_3E54, RES_SHARED_VGA }, +- { PCI_CHIP_RV380_3150, PCI_CHIP_RV380_3150, RES_SHARED_VGA }, +- { PCI_CHIP_RV380_3152, PCI_CHIP_RV380_3152, RES_SHARED_VGA }, +- { PCI_CHIP_RV380_3154, PCI_CHIP_RV380_3154, RES_SHARED_VGA }, +- { PCI_CHIP_RV370_5B60, PCI_CHIP_RV370_5B60, RES_SHARED_VGA }, +- { PCI_CHIP_RV370_5B62, PCI_CHIP_RV370_5B62, RES_SHARED_VGA }, +- { PCI_CHIP_RV370_5B63, PCI_CHIP_RV370_5B63, RES_SHARED_VGA }, +- { PCI_CHIP_RV370_5B64, PCI_CHIP_RV370_5B64, RES_SHARED_VGA }, +- { PCI_CHIP_RV370_5B65, PCI_CHIP_RV370_5B65, RES_SHARED_VGA }, +- { PCI_CHIP_RV370_5460, PCI_CHIP_RV370_5460, RES_SHARED_VGA }, +- { PCI_CHIP_RV370_5462, PCI_CHIP_RV370_5462, RES_SHARED_VGA }, +- { PCI_CHIP_RV370_5464, PCI_CHIP_RV370_5464, RES_SHARED_VGA }, +- { PCI_CHIP_RS400_5A41, PCI_CHIP_RS400_5A41, RES_SHARED_VGA }, +- { PCI_CHIP_RS400_5A42, PCI_CHIP_RS400_5A42, RES_SHARED_VGA }, +- { PCI_CHIP_RC410_5A61, PCI_CHIP_RC410_5A61, RES_SHARED_VGA }, +- { PCI_CHIP_RC410_5A62, PCI_CHIP_RC410_5A62, RES_SHARED_VGA }, +- { PCI_CHIP_RS480_5954, PCI_CHIP_RS480_5954, RES_SHARED_VGA }, +- { PCI_CHIP_RS480_5955, PCI_CHIP_RS480_5955, RES_SHARED_VGA }, +- { PCI_CHIP_RS482_5974, PCI_CHIP_RS482_5974, RES_SHARED_VGA }, +- { PCI_CHIP_RS485_5975, PCI_CHIP_RS485_5975, RES_SHARED_VGA }, +- { PCI_CHIP_RV410_5E48, PCI_CHIP_RV410_5E48, RES_SHARED_VGA }, +- { PCI_CHIP_RV410_564A, PCI_CHIP_RV410_564A, RES_SHARED_VGA }, +- { PCI_CHIP_RV410_564B, PCI_CHIP_RV410_564B, RES_SHARED_VGA }, +- { PCI_CHIP_RV410_564F, PCI_CHIP_RV410_564F, RES_SHARED_VGA }, +- { PCI_CHIP_RV410_5652, PCI_CHIP_RV410_5652, RES_SHARED_VGA }, +- { PCI_CHIP_RV410_5653, PCI_CHIP_RV410_5653, RES_SHARED_VGA }, +- { PCI_CHIP_RV410_5E4B, PCI_CHIP_RV410_5E4B, RES_SHARED_VGA }, +- { PCI_CHIP_RV410_5E4A, PCI_CHIP_RV410_5E4A, RES_SHARED_VGA }, +- { PCI_CHIP_RV410_5E4D, PCI_CHIP_RV410_5E4D, RES_SHARED_VGA }, +- { PCI_CHIP_RV410_5E4C, PCI_CHIP_RV410_5E4C, RES_SHARED_VGA }, +- { PCI_CHIP_RV410_5E4F, PCI_CHIP_RV410_5E4F, RES_SHARED_VGA }, +- { PCI_CHIP_R420_JH, PCI_CHIP_R420_JH, RES_SHARED_VGA }, +- { PCI_CHIP_R420_JI, PCI_CHIP_R420_JI, RES_SHARED_VGA }, +- { PCI_CHIP_R420_JJ, PCI_CHIP_R420_JJ, RES_SHARED_VGA }, +- { PCI_CHIP_R420_JK, PCI_CHIP_R420_JK, RES_SHARED_VGA }, +- { PCI_CHIP_R420_JL, PCI_CHIP_R420_JL, RES_SHARED_VGA }, +- { PCI_CHIP_R420_JM, PCI_CHIP_R420_JM, RES_SHARED_VGA }, +- { PCI_CHIP_R420_JN, PCI_CHIP_R420_JN, RES_SHARED_VGA }, +- { PCI_CHIP_R420_JP, PCI_CHIP_R420_JP, RES_SHARED_VGA }, +- { PCI_CHIP_R420_4A4F, PCI_CHIP_R420_4A4F, RES_SHARED_VGA }, +- { PCI_CHIP_R420_4A54, PCI_CHIP_R420_4A54, RES_SHARED_VGA }, +- { PCI_CHIP_R423_UH, PCI_CHIP_R423_UH, RES_SHARED_VGA }, +- { PCI_CHIP_R423_UI, PCI_CHIP_R423_UI, RES_SHARED_VGA }, +- { PCI_CHIP_R423_UJ, PCI_CHIP_R423_UJ, RES_SHARED_VGA }, +- { PCI_CHIP_R423_UK, PCI_CHIP_R423_UK, RES_SHARED_VGA }, +- { PCI_CHIP_R423_UQ, PCI_CHIP_R423_UQ, RES_SHARED_VGA }, +- { PCI_CHIP_R423_UR, PCI_CHIP_R423_UR, RES_SHARED_VGA }, +- { PCI_CHIP_R423_UT, PCI_CHIP_R423_UT, RES_SHARED_VGA }, +- { PCI_CHIP_R423_5D57, PCI_CHIP_R423_5D57, RES_SHARED_VGA }, +- { PCI_CHIP_R423_5550, PCI_CHIP_R423_5550, RES_SHARED_VGA }, +- { PCI_CHIP_R430_5D49, PCI_CHIP_R430_5D49, RES_SHARED_VGA }, +- { PCI_CHIP_R430_5D4A, PCI_CHIP_R430_5D4A, RES_SHARED_VGA }, +- { PCI_CHIP_R430_5D48, PCI_CHIP_R430_5D48, RES_SHARED_VGA }, +- { PCI_CHIP_R430_554F, PCI_CHIP_R430_554F, RES_SHARED_VGA }, +- { PCI_CHIP_R430_554D, PCI_CHIP_R430_554D, RES_SHARED_VGA }, +- { PCI_CHIP_R430_554E, PCI_CHIP_R430_554E, RES_SHARED_VGA }, +- { PCI_CHIP_R430_554C, PCI_CHIP_R430_554C, RES_SHARED_VGA }, +- { PCI_CHIP_R480_5D4C, PCI_CHIP_R480_5D4C, RES_SHARED_VGA }, +- { PCI_CHIP_R480_5D50, PCI_CHIP_R480_5D50, RES_SHARED_VGA }, +- { PCI_CHIP_R480_5D4E, PCI_CHIP_R480_5D4E, RES_SHARED_VGA }, +- { PCI_CHIP_R480_5D4F, PCI_CHIP_R480_5D4F, RES_SHARED_VGA }, +- { PCI_CHIP_R480_5D52, PCI_CHIP_R480_5D52, RES_SHARED_VGA }, +- { PCI_CHIP_R480_5D4D, PCI_CHIP_R480_5D4D, RES_SHARED_VGA }, +- { PCI_CHIP_R481_4B4B, PCI_CHIP_R481_4B4B, RES_SHARED_VGA }, +- { PCI_CHIP_R481_4B4A, PCI_CHIP_R481_4B4A, RES_SHARED_VGA }, +- { PCI_CHIP_R481_4B49, PCI_CHIP_R481_4B49, RES_SHARED_VGA }, +- { PCI_CHIP_R481_4B4C, PCI_CHIP_R481_4B4C, RES_SHARED_VGA }, +- +- { -1, -1, RES_UNDEFINED } +-}; ++#include "radeon_pci_chipset_gen.h" + + int gRADEONEntityIndex = -1; + +diff --git a/src/radeon_probe.h b/src/radeon_probe.h +index 66ece94..7f8ce45 100644 +--- a/src/radeon_probe.h ++++ b/src/radeon_probe.h +@@ -166,6 +166,7 @@ typedef struct _RADEONCrtcPrivateRec { + #endif + int crtc_id; + int binding; ++ CARD32 cursor_offset; + /* Lookup table values to be set when the CRTC is enabled */ + CARD8 lut_r[256], lut_g[256], lut_b[256]; + } RADEONCrtcPrivateRec, *RADEONCrtcPrivatePtr; +diff --git a/src/radeon_reg.h b/src/radeon_reg.h +index 2653339..6e4e383 100644 +--- a/src/radeon_reg.h ++++ b/src/radeon_reg.h +@@ -916,6 +916,7 @@ + # define RADEON_LVDS_DISPLAY_DIS (1 << 1) + # define RADEON_LVDS_PANEL_TYPE (1 << 2) + # define RADEON_LVDS_PANEL_FORMAT (1 << 3) ++# define RADEON_LVDS_RST_FM (1 << 6) + # define RADEON_LVDS_EN (1 << 7) + # define RADEON_LVDS_BL_MOD_LEVEL_SHIFT 8 + # define RADEON_LVDS_BL_MOD_LEVEL_MASK (0xff << 8) +diff --git a/src/radeon_render.c b/src/radeon_render.c +index 5074fe1..490dec1 100644 +--- a/src/radeon_render.c ++++ b/src/radeon_render.c +@@ -392,7 +392,7 @@ static Bool FUNC_NAME(R100SetupTexture)( + #endif + ACCEL_PREAMBLE(); + +- if ((width > 2048) || (height > 2048)) ++ if ((width > 2047) || (height > 2047)) + return FALSE; + + txformat = RadeonGetTextureFormat(format); +@@ -424,7 +424,7 @@ static Bool FUNC_NAME(R100SetupTexture)( + txformat |= ATILog2(width) << RADEON_TXFORMAT_WIDTH_SHIFT; + txformat |= ATILog2(height) << RADEON_TXFORMAT_HEIGHT_SHIFT; + } else { +- tex_size = ((height - 1) << 16) | (width - 1); ++ tex_size = (height << 16) | width; + txformat |= RADEON_TXFORMAT_NON_POWER2; + } + +diff --git a/src/radeon_tv.c b/src/radeon_tv.c +index 3a26a0a..2a8873c 100644 +--- a/src/radeon_tv.c ++++ b/src/radeon_tv.c +@@ -434,7 +434,7 @@ void RADEONInitTVRegisters(xf86OutputPtr output, RADEONSavePtr save, + + save->tv_vscaler_cntl2 = ((save->tv_vscaler_cntl2 & 0x00fffff0) + | (0x10 << 24) +- | RADEON_DITHER_MODE ++ | RADEON_DITHER_MODE + | RADEON_Y_OUTPUT_DITHER_EN + | RADEON_UV_OUTPUT_DITHER_EN + | RADEON_UV_TO_BUF_DITHER_EN); +@@ -444,10 +444,12 @@ void RADEONInitTVRegisters(xf86OutputPtr output, RADEONSavePtr save, + tmp = (tmp << RADEON_UV_OUTPUT_POST_SCALE_SHIFT) | 0x000b0000; + save->tv_timing_cntl = tmp; + +- save->tv_dac_cntl = RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD | (8 << 16) | (6 << 20); ++ save->tv_dac_cntl = (RADEON_TV_DAC_NBLANK | ++ RADEON_TV_DAC_NHOLD | ++ radeon_output->tv_dac_adj /*(8 << 16) | (6 << 20)*/); + + if (radeon_output->tvStd == TV_STD_NTSC || +- radeon_output->tvStd == TV_STD_NTSC_J) ++ radeon_output->tvStd == TV_STD_NTSC_J) + save->tv_dac_cntl |= RADEON_TV_DAC_STD_NTSC; + else + save->tv_dac_cntl |= RADEON_TV_DAC_STD_PAL; +diff --git a/src/radeon_video.c b/src/radeon_video.c +index 26857a5..3f0209e 100644 +--- a/src/radeon_video.c ++++ b/src/radeon_video.c +@@ -414,11 +414,11 @@ static XF86AttributeRec Attributes[NUM_DEC_ATTRIBUTES+1] = + + #define FOURCC_RGB24 0x00000000 + +-#define XVIMAGE_RGB24(byte_order) \ ++#define XVIMAGE_RGB24 \ + { \ + FOURCC_RGB24, \ + XvRGB, \ +- byte_order, \ ++ LSBFirst, \ + { 'R', 'G', 'B', 0, \ + 0x00,0x00,0x00,0x10,0x80,0x00,0x00,0xAA,0x00,0x38,0x9B,0x71}, \ + 24, \ +@@ -473,15 +473,14 @@ static XF86ImageRec Images[NUM_IMAGES] = + { + #if X_BYTE_ORDER == X_BIG_ENDIAN + XVIMAGE_RGBA32(MSBFirst), +- XVIMAGE_RGB24(MSBFirst), + XVIMAGE_RGBT16(MSBFirst), + XVIMAGE_RGB16(MSBFirst), + #else + XVIMAGE_RGBA32(LSBFirst), +- XVIMAGE_RGB24(LSBFirst), + XVIMAGE_RGBT16(LSBFirst), + XVIMAGE_RGB16(LSBFirst), + #endif ++ XVIMAGE_RGB24, + XVIMAGE_YUY2, + XVIMAGE_UYVY, + XVIMAGE_YV12, +@@ -2199,7 +2198,7 @@ RADEONCopyRGB24Data( + unsigned int w + ){ + CARD32 *dptr; +- CARD8 *sptr = 0; ++ CARD8 *sptr; + int i,j; + RADEONInfoPtr info = RADEONPTR(pScrn); + #ifdef XF86DRI +@@ -2210,11 +2209,9 @@ RADEONCopyRGB24Data( + int x, y; + unsigned int hpass; + +- /* XXX Fix endian flip on R300 */ +- + RADEONHostDataParams( pScrn, dst, dstPitch, 4, &dstPitchOff, &x, &y ); + +- while ( (dptr = ( CARD32* )RADEONHostDataBlit( pScrn, 4, w, dstPitch, ++ while ( (dptr = ( CARD32* )RADEONHostDataBlit( pScrn, 4, w, dstPitchOff, + &bufPitch, x, &y, &h, + &hpass )) ) + { +@@ -2224,11 +2221,11 @@ RADEONCopyRGB24Data( + + for ( i = 0 ; i < w; i++, sptr += 3 ) + { +- *dptr++ = (sptr[0] << 24) | (sptr[1] << 16) | sptr[2]; ++ dptr[i] = (sptr[2] << 16) | (sptr[1] << 8) | sptr[0]; + } + +- src += hpass * srcPitch; +- dptr += hpass * bufPitch; ++ src += srcPitch; ++ dptr += bufPitch / 4; + } + } + +@@ -2246,14 +2243,12 @@ RADEONCopyRGB24Data( + & ~RADEON_NONSURF_AP0_SWP_16BPP); + #endif + +- for(j=0;j0;i--){ +- dptr[0]=((sptr[0])<<24)|((sptr[1])<<16)|(sptr[2]); +- dptr++; +- sptr+=3; ++ for (i = 0; i < w; i++, sptr += 3) { ++ dptr[i] = (sptr[2] << 16) | (sptr[1] << 8) | sptr[0]; + } + } + +@@ -2927,17 +2922,17 @@ RADEONPutImage( + + switch(id) { + case FOURCC_RGB24: +- dstPitch=(width*4+0x0f)&(~0x0f); +- srcPitch=width*3; ++ dstPitch = width * 4; ++ srcPitch = width * 3; + break; + case FOURCC_RGBA32: +- dstPitch=(width*4+0x0f)&(~0x0f); +- srcPitch=width*4; ++ dstPitch = width * 4; ++ srcPitch = width * 4; + break; + case FOURCC_RGB16: + case FOURCC_RGBT16: +- dstPitch=(width*2+0x0f)&(~0x0f); +- srcPitch=(width*2+3)&(~0x03); ++ dstPitch = width * 2; ++ srcPitch = (width * 2 + 3) & ~3; + break; + case FOURCC_YV12: + case FOURCC_I420: +@@ -2950,11 +2945,20 @@ RADEONPutImage( + case FOURCC_UYVY: + case FOURCC_YUY2: + default: +- dstPitch = ((width << 1) + 63) & ~63; +- srcPitch = (width << 1); ++ dstPitch = width * 2; ++ srcPitch = width * 2; + break; + } + ++#ifdef XF86DRI ++ if (info->directRenderingEnabled && info->DMAForXv) { ++ /* The upload blit only supports multiples of 64 bytes */ ++ dstPitch = (dstPitch + 63) & ~63; ++ } else ++#endif ++ /* The overlay only supports multiples of 16 bytes */ ++ dstPitch = (dstPitch + 15) & ~15; ++ + new_size = dstPitch * height; + if (id == FOURCC_YV12 || id == FOURCC_I420) { + new_size += (dstPitch >> 1) * ((height + 1) & ~1); diff --git a/radeon.xinf b/radeon.xinf index 1eaf4e1..06cd5f3 100644 --- a/radeon.xinf +++ b/radeon.xinf @@ -195,3 +195,135 @@ alias pcivideo:v00001002d00005F57sv*sd*bc*sc*i* radeon # R423 alias pcivideo:v00001002d00007834sv*sd*bc*sc*i* radeon # 9100 IGP alias pcivideo:v00001002d00007835sv*sd*bc*sc*i* radeon # 9200 IGP alias pcivideo:v00001002d00007C37sv*sd*bc*sc*i* radeon # RV350 +alias pcivideo:v00001002d00007100sv*sd*bc*sc*i* radeon # +alias pcivideo:v00001002d00007101sv*sd*bc*sc*i* radeon # +alias pcivideo:v00001002d00007102sv*sd*bc*sc*i* radeon # +alias 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pcivideo:v00001002d000071C5sv*sd*bc*sc*i* radeon # +alias pcivideo:v00001002d000071C6sv*sd*bc*sc*i* radeon # +alias pcivideo:v00001002d000071C7sv*sd*bc*sc*i* radeon # +alias pcivideo:v00001002d000071CDsv*sd*bc*sc*i* radeon # +alias pcivideo:v00001002d000071CEsv*sd*bc*sc*i* radeon # +alias pcivideo:v00001002d000071D2sv*sd*bc*sc*i* radeon # +alias pcivideo:v00001002d000071D4sv*sd*bc*sc*i* radeon # +alias pcivideo:v00001002d000071D5sv*sd*bc*sc*i* radeon # +alias pcivideo:v00001002d000071D6sv*sd*bc*sc*i* radeon # +alias pcivideo:v00001002d000071DAsv*sd*bc*sc*i* radeon # +alias pcivideo:v00001002d000071DEsv*sd*bc*sc*i* radeon # +alias pcivideo:v00001002d00007200sv*sd*bc*sc*i* radeon # +alias pcivideo:v00001002d00007210sv*sd*bc*sc*i* radeon # +alias pcivideo:v00001002d00007211sv*sd*bc*sc*i* radeon # +alias pcivideo:v00001002d00007240sv*sd*bc*sc*i* radeon # +alias pcivideo:v00001002d00007243sv*sd*bc*sc*i* radeon # +alias pcivideo:v00001002d00007244sv*sd*bc*sc*i* radeon # +alias pcivideo:v00001002d00007245sv*sd*bc*sc*i* radeon # +alias pcivideo:v00001002d00007246sv*sd*bc*sc*i* radeon # +alias pcivideo:v00001002d00007247sv*sd*bc*sc*i* radeon # +alias pcivideo:v00001002d00007248sv*sd*bc*sc*i* radeon # +alias pcivideo:v00001002d00007249sv*sd*bc*sc*i* radeon # +alias pcivideo:v00001002d0000724Asv*sd*bc*sc*i* radeon # +alias pcivideo:v00001002d0000724Bsv*sd*bc*sc*i* radeon # +alias pcivideo:v00001002d0000724Csv*sd*bc*sc*i* radeon # +alias pcivideo:v00001002d0000724Dsv*sd*bc*sc*i* radeon # +alias pcivideo:v00001002d0000724Esv*sd*bc*sc*i* radeon # +alias pcivideo:v00001002d0000724Fsv*sd*bc*sc*i* radeon # +alias pcivideo:v00001002d00007280sv*sd*bc*sc*i* radeon # +alias pcivideo:v00001002d00007281sv*sd*bc*sc*i* radeon # +alias pcivideo:v00001002d00007283sv*sd*bc*sc*i* radeon # +alias pcivideo:v00001002d00007284sv*sd*bc*sc*i* radeon # +alias pcivideo:v00001002d00007287sv*sd*bc*sc*i* radeon # +alias pcivideo:v00001002d00007288sv*sd*bc*sc*i* radeon # +alias pcivideo:v00001002d00007289sv*sd*bc*sc*i* radeon # +alias pcivideo:v00001002d0000728Bsv*sd*bc*sc*i* radeon # +alias pcivideo:v00001002d0000728Csv*sd*bc*sc*i* radeon # +alias pcivideo:v00001002d00007290sv*sd*bc*sc*i* radeon # +alias pcivideo:v00001002d00007291sv*sd*bc*sc*i* radeon # +alias pcivideo:v00001002d00007293sv*sd*bc*sc*i* radeon # +alias pcivideo:v00001002d00007297sv*sd*bc*sc*i* radeon # +alias pcivideo:v00001002d0000791Esv*sd*bc*sc*i* radeon # +alias pcivideo:v00001002d0000791Fsv*sd*bc*sc*i* radeon # +alias pcivideo:v00001002d0000796Csv*sd*bc*sc*i* radeon # +alias pcivideo:v00001002d0000796Dsv*sd*bc*sc*i* radeon # +alias pcivideo:v00001002d0000796Esv*sd*bc*sc*i* radeon # +alias pcivideo:v00001002d0000796Fsv*sd*bc*sc*i* radeon # +alias pcivideo:v00001002d00009400sv*sd*bc*sc*i* radeon # +alias pcivideo:v00001002d00009401sv*sd*bc*sc*i* radeon # +alias pcivideo:v00001002d00009402sv*sd*bc*sc*i* radeon # +alias pcivideo:v00001002d00009403sv*sd*bc*sc*i* radeon # +alias pcivideo:v00001002d00009405sv*sd*bc*sc*i* radeon # +alias pcivideo:v00001002d0000940Asv*sd*bc*sc*i* radeon # +alias pcivideo:v00001002d0000940Bsv*sd*bc*sc*i* radeon # +alias pcivideo:v00001002d0000940Fsv*sd*bc*sc*i* radeon # +alias pcivideo:v00001002d000094C0sv*sd*bc*sc*i* radeon # +alias pcivideo:v00001002d000094C1sv*sd*bc*sc*i* radeon # +alias pcivideo:v00001002d000094C3sv*sd*bc*sc*i* radeon # +alias pcivideo:v00001002d000094C4sv*sd*bc*sc*i* radeon # +alias pcivideo:v00001002d000094C5sv*sd*bc*sc*i* radeon # +alias pcivideo:v00001002d000094C6sv*sd*bc*sc*i* radeon # +alias pcivideo:v00001002d000094C7sv*sd*bc*sc*i* radeon # +alias pcivideo:v00001002d000094C8sv*sd*bc*sc*i* radeon # +alias pcivideo:v00001002d000094C9sv*sd*bc*sc*i* radeon # +alias pcivideo:v00001002d000094CBsv*sd*bc*sc*i* radeon # +alias pcivideo:v00001002d000094CCsv*sd*bc*sc*i* radeon # +alias pcivideo:v00001002d00009580sv*sd*bc*sc*i* radeon # +alias pcivideo:v00001002d00009581sv*sd*bc*sc*i* radeon # +alias pcivideo:v00001002d00009583sv*sd*bc*sc*i* radeon # +alias pcivideo:v00001002d00009586sv*sd*bc*sc*i* radeon # +alias pcivideo:v00001002d00009587sv*sd*bc*sc*i* radeon # +alias pcivideo:v00001002d00009588sv*sd*bc*sc*i* radeon # +alias pcivideo:v00001002d00009589sv*sd*bc*sc*i* radeon # +alias pcivideo:v00001002d0000958Asv*sd*bc*sc*i* radeon # +alias pcivideo:v00001002d0000958Bsv*sd*bc*sc*i* radeon # +alias pcivideo:v00001002d0000958Csv*sd*bc*sc*i* radeon # +alias pcivideo:v00001002d0000958Dsv*sd*bc*sc*i* radeon # +alias pcivideo:v00001002d0000958Esv*sd*bc*sc*i* radeon # diff --git a/xorg-x11-drv-ati.spec b/xorg-x11-drv-ati.spec index c1ffef4..2425fd4 100644 --- a/xorg-x11-drv-ati.spec +++ b/xorg-x11-drv-ati.spec @@ -5,7 +5,7 @@ Summary: Xorg X11 ati video driver Name: xorg-x11-drv-ati Version: 6.7.196 -Release: 2%{?dist} +Release: 3%{?dist} URL: http://www.x.org License: MIT Group: User Interface/X Hardware Support @@ -17,14 +17,13 @@ Source2: r128.xinf Source3: radeon.xinf # Radeon patches (0-99) -Patch2: radeon-6.6.3-renderaccel-buglet.patch +Patch2: radeon-git-upstream-fixes.patch +Patch3: radeon-6.7.196-atombios-support.patch Patch4: radeon-6.7.196-faster-ddc.patch -Patch5: radeon-6.7.196-alloca.patch # Rage 128 patches (100-199) # mach64 patches (200-299) -Patch200: ati-6.7.196-alloca.patch # ati wrapperloader patches (300-399) @@ -43,10 +42,9 @@ X.Org X11 ati video driver. %prep %setup -q -n %{tarball}-%{version} -%patch2 -p1 -b .renderaccel +%patch2 -p1 -b .upstream +%patch3 -p1 -b .atombios %patch4 -p1 -b .ddc -%patch5 -p1 -b .alloca-radeon -%patch200 -p1 -b .alloca-ati %build %configure --disable-static @@ -88,6 +86,10 @@ rm -rf $RPM_BUILD_ROOT %{_mandir}/man4/radeon.4* %changelog +* Wed Dec 19 2007 Dave Airlie 6.7.196-3 +- radeon-git-upstream-fixes.patch - update for latest git master +- radeon-6.7.196-atombios-support.patch - update for r500/r600 + * Mon Dec 17 2007 Adam Jackson 6.7.196-2 - *-6.7.196-alloca.patch: Fix ALLOCATE_LOCAL failures.