From 0701393f3f70e487eb1963b3e3ce33e8ac24b821 Mon Sep 17 00:00:00 2001 From: Xavier Bachelot Date: Jun 18 2009 23:45:04 +0000 Subject: add 4 new patches --- diff --git a/openchrome-0.2.903-disable_TMDS_by_default.patch b/openchrome-0.2.903-disable_TMDS_by_default.patch new file mode 100644 index 0000000..1c1e972 --- /dev/null +++ b/openchrome-0.2.903-disable_TMDS_by_default.patch @@ -0,0 +1,17 @@ +Index: src/via_mode.c +=================================================================== +--- src/via_mode.c (revision 750) ++++ src/via_mode.c (working copy) +@@ -449,9 +449,12 @@ + if (pBIOSInfo->CrtPresent) + pBIOSInfo->CrtActive = TRUE; + ++#if 0 ++ # FIXME : DFP must be activated with the ActiveDevice option + /* DFP */ + if (pBIOSInfo->DfpPresent) + pBIOSInfo->DfpActive = TRUE; ++#endif + + } else { + if (pVia->ActiveDevice & VIA_DEVICE_LCD) { diff --git a/openchrome-0.2.903-fix_cursor_on_secondary.patch b/openchrome-0.2.903-fix_cursor_on_secondary.patch new file mode 100644 index 0000000..88735b9 --- /dev/null +++ b/openchrome-0.2.903-fix_cursor_on_secondary.patch @@ -0,0 +1,216 @@ +Index: src/via_cursor.c +=================================================================== +--- src/via_cursor.c (wersja 751) ++++ src/via_cursor.c (kopia robocza) +@@ -290,19 +286,36 @@ + CARD32 temp; + CARD32 control = pVia->CursorRegControl; + +- temp = +- (1 << 30) | +- (1 << 29) | +- (1 << 28) | +- (1 << 26) | +- (1 << 25) | +- (1 << 2) | +- (1 << 0); ++ switch(pVia->Chipset) { ++ case VIA_CX700: ++ case VIA_P4M890: ++ case VIA_P4M900: ++ case VIA_VX800: ++ if (pVia->pBIOSInfo->FirstCRTC->IsActive) { ++ VIASETREG(VIA_REG_HI_CONTROL0, 0x36000005); ++ } ++ if (pVia->pBIOSInfo->SecondCRTC->IsActive) { ++ VIASETREG(VIA_REG_HI_CONTROL1, 0xb6000005); ++ } ++ break; ++ ++ default: ++ /* temp = 0x36000005 */ ++ temp = ++ (1 << 29) | ++ (1 << 28) | ++ (1 << 26) | ++ (1 << 25) | ++ (1 << 2) | ++ (1 << 0); + +- if (pVia->CursorPipe) +- temp |= (1 << 31); ++ temp |= (1 << 30); + +- VIASETREG(control, temp); ++ /* Duoview */ ++ if (pVia->CursorPipe) ++ temp |= (1 << 31); ++ VIASETREG(control, temp); ++ } + } + + void +@@ -313,7 +326,24 @@ + CARD32 control = pVia->CursorRegControl; + + temp = VIAGETREG(control); +- VIASETREG(control, temp & 0xFFFFFFFE); ++ switch(pVia->Chipset) { ++ case VIA_CX700: ++ case VIA_P4M890: ++ case VIA_P4M900: ++ case VIA_VX800: ++ if (pVia->pBIOSInfo->FirstCRTC->IsActive) { ++ temp = VIAGETREG(VIA_REG_HI_CONTROL0); ++ VIASETREG(VIA_REG_HI_CONTROL0, temp & 0xFFFFFFFA); ++ } ++ if (pVia->pBIOSInfo->SecondCRTC->IsActive) { ++ temp = VIAGETREG(VIA_REG_HI_CONTROL1); ++ VIASETREG(VIA_REG_HI_CONTROL1, temp & 0xFFFFFFFA); ++ } ++ break; ++ ++ default: ++ VIASETREG(control, temp & 0xFFFFFFFA); ++ } + } + + static void +@@ -340,13 +370,41 @@ + yoff = 0; + } + +- temp = VIAGETREG(control); +- VIASETREG(control, temp & 0xFFFFFFFE); ++ switch(pVia->Chipset) { ++ case VIA_CX700: ++ case VIA_P4M890: ++ case VIA_P4M900: ++ case VIA_VX800: ++ if (pVia->pBIOSInfo->FirstCRTC->IsActive) { ++ temp = VIAGETREG(VIA_REG_HI_CONTROL0); ++ VIASETREG(VIA_REG_HI_CONTROL0, temp & 0xFFFFFFFE); ++ ++ VIASETREG(VIA_REG_HI_POS0, ((x << 16) | (y & 0x07ff))); ++ VIASETREG(VIA_REG_HI_OFFSET0, ((xoff << 16) | (yoff & 0x07ff))); + +- VIASETREG(pos, ((x << 16) | (y & 0x07ff))); +- VIASETREG(offset, ((xoff << 16) | (yoff & 0x07ff))); ++ VIASETREG(VIA_REG_HI_CONTROL0, temp); ++ } ++ if (pVia->pBIOSInfo->SecondCRTC->IsActive) { ++ temp = VIAGETREG(VIA_REG_HI_CONTROL1); ++ VIASETREG(VIA_REG_HI_CONTROL1, temp & 0xFFFFFFFE); + +- VIASETREG(control, temp); ++ VIASETREG(VIA_REG_HI_POS1, ((x << 16) | (y & 0x07ff))); ++ VIASETREG(VIA_REG_HI_OFFSET1, ((xoff << 16) | (yoff & 0x07ff))); ++ ++ VIASETREG(VIA_REG_HI_CONTROL1, temp); ++ } ++ break; ++ ++ default: ++ temp = VIAGETREG(control); ++ VIASETREG(control, temp & 0xFFFFFFFE); ++ ++ VIASETREG(pos, ((x << 16) | (y & 0x07ff))); ++ VIASETREG(offset, ((xoff << 16) | (yoff & 0x07ff))); ++ ++ VIASETREG(control, temp); ++ } ++ + } + + static Bool +@@ -397,18 +455,34 @@ + if (pVia->CursorARGBSupported) { + #define ARGB_PER_CHUNK (8 * sizeof (chunk) / 2) + for (i = 0; i < (pVia->CursorMaxWidth * pVia->CursorMaxHeight / ARGB_PER_CHUNK); i++) { +- chunk = *s++; +- for (j = 0; j < ARGB_PER_CHUNK; j++, chunk >>= 2) ++ chunk = *s++; ++ for (j = 0; j < ARGB_PER_CHUNK; j++, chunk >>= 2) + *dst++ = mono_cursor_color[chunk & 3]; + } + + pVia->CursorFG = mono_cursor_color[3]; + pVia->CursorBG = mono_cursor_color[2]; +- } else { +- memcpy(dst, src, pVia->CursorSize); +- } +- +- VIASETREG(control, temp); ++ } else { ++ memcpy(dst, src, pVia->CursorSize); ++ } ++ switch(pVia->Chipset) { ++ case VIA_CX700: ++ case VIA_P4M890: ++ case VIA_P4M900: ++ case VIA_VX800: ++ if (pVia->pBIOSInfo->FirstCRTC->IsActive) { ++ temp = VIAGETREG(VIA_REG_HI_CONTROL0); ++ VIASETREG(VIA_REG_HI_CONTROL0, temp & 0xFFFFFFFE); ++ } ++ if (pVia->pBIOSInfo->SecondCRTC->IsActive) { ++ temp = VIAGETREG(VIA_REG_HI_CONTROL1); ++ VIASETREG(VIA_REG_HI_CONTROL1, temp & 0xFFFFFFFE); ++ } ++ break; ++ ++ default: ++ VIASETREG(control, temp); ++ } + } + + static void +@@ -441,7 +515,23 @@ + pVia->CursorFG = fg; + pVia->CursorBG = bg; + +- VIASETREG(control, temp); ++ switch(pVia->Chipset) { ++ case VIA_CX700: ++ case VIA_P4M890: ++ case VIA_P4M900: ++ case VIA_VX800: ++ if (pVia->pBIOSInfo->FirstCRTC->IsActive) { ++ temp = VIAGETREG(VIA_REG_HI_CONTROL0); ++ VIASETREG(VIA_REG_HI_CONTROL0, temp & 0xFFFFFFFE); ++ } ++ if (pVia->pBIOSInfo->SecondCRTC->IsActive) { ++ temp = VIAGETREG(VIA_REG_HI_CONTROL1); ++ VIASETREG(VIA_REG_HI_CONTROL1, temp & 0xFFFFFFFE); ++ } ++ break; ++ default: ++ VIASETREG(control, temp); ++ } + } + + static void +@@ -486,5 +576,22 @@ + for (x = 0; x < pVia->CursorMaxWidth; x++) + *dst++ = 0; + +- VIASETREG(control, temp); ++ switch(pVia->Chipset) { ++ case VIA_CX700: ++ case VIA_P4M890: ++ case VIA_P4M900: ++ case VIA_VX800: ++ if (pVia->pBIOSInfo->FirstCRTC->IsActive) { ++ temp = VIAGETREG(VIA_REG_HI_CONTROL0); ++ VIASETREG(VIA_REG_HI_CONTROL0, temp & 0xFFFFFFFE); ++ } ++ if (pVia->pBIOSInfo->SecondCRTC->IsActive) { ++ temp = VIAGETREG(VIA_REG_HI_CONTROL1); ++ VIASETREG(VIA_REG_HI_CONTROL1, temp & 0xFFFFFFFE); ++ } ++ break; ++ ++ default: ++ VIASETREG(control, temp); ++ } + } diff --git a/openchrome-0.2.903-pll_rework.patch b/openchrome-0.2.903-pll_rework.patch new file mode 100644 index 0000000..ad07862 --- /dev/null +++ b/openchrome-0.2.903-pll_rework.patch @@ -0,0 +1,294 @@ +--- src/via_mode.c 2009-06-16 23:17:42.000000000 +0200 ++++ src/via_mode.c 2009-06-16 22:43:58.000000000 +0200 +@@ -974,21 +974,35 @@ + * + */ + static void +-ViaSetPrimaryDotclock(ScrnInfoPtr pScrn, CARD32 clock) ++ViaSetDotclock(ScrnInfoPtr pScrn, CARD32 clock, int base, int probase) + { + vgaHWPtr hwp = VGAHWPTR(pScrn); + VIAPtr pVia = VIAPTR(pScrn); + + DEBUG(xf86DrvMsg(hwp->pScrn->scrnIndex, X_INFO, +- "ViaSetPrimaryDotclock to 0x%06x\n", (unsigned)clock)); ++ "ViaSetDotclock to 0x%06x\n", (unsigned)clock)); + + if ((pVia->Chipset == VIA_CLE266) || (pVia->Chipset == VIA_KM400)) { +- hwp->writeSeq(hwp, 0x46, clock >> 8); +- hwp->writeSeq(hwp, 0x47, clock & 0xFF); ++ hwp->writeSeq(hwp, base, clock >> 8); ++ hwp->writeSeq(hwp, base+1, clock & 0xFF); + } else { /* unichrome pro */ +- hwp->writeSeq(hwp, 0x44, clock >> 16); +- hwp->writeSeq(hwp, 0x45, (clock >> 8) & 0xFF); +- hwp->writeSeq(hwp, 0x46, clock & 0xFF); ++ union pllparams pll; ++ int dtz, dr, dn, dm; ++ pll.packed = clock; ++ dtz = pll.params.dtz; ++ dr = pll.params.dr; ++ dn = pll.params.dn; ++ dm = pll.params.dm; ++ ++ /* The VX855 does not modify dm/dn, but earlier chipsets do. */ ++ if (pVia->Chipset != VIA_VX855) { ++ dm -= 2; ++ dn -= 2; ++ } ++ ++ hwp->writeSeq(hwp, probase, dm & 0xff); ++ hwp->writeSeq(hwp, probase+1, ((dm >> 8) & 0x03) | (dr << 2) | ((dtz & 1) << 7)); ++ hwp->writeSeq(hwp, probase+2, (dn & 0x7f) | ((dtz & 2) << 6)); + } + + ViaSeqMask(hwp, 0x40, 0x02, 0x02); +@@ -999,25 +1013,28 @@ + * + */ + static void +-ViaSetSecondaryDotclock(ScrnInfoPtr pScrn, CARD32 clock) ++ViaSetPrimaryDotclock(ScrnInfoPtr pScrn, CARD32 clock) + { +- vgaHWPtr hwp = VGAHWPTR(pScrn); +- VIAPtr pVia = VIAPTR(pScrn); +- +- DEBUG(xf86DrvMsg(hwp->pScrn->scrnIndex, X_INFO, +- "ViaSetSecondaryDotclock to 0x%06x\n", (unsigned)clock)); ++ ViaSetDotclock(pScrn, clock, 0x46, 0x44); ++} + +- if ((pVia->Chipset == VIA_CLE266) || (pVia->Chipset == VIA_KM400)) { +- hwp->writeSeq(hwp, 0x44, clock >> 8); +- hwp->writeSeq(hwp, 0x45, clock & 0xFF); +- } else { /* unichrome pro */ +- hwp->writeSeq(hwp, 0x4A, clock >> 16); +- hwp->writeSeq(hwp, 0x4B, (clock >> 8) & 0xFF); +- hwp->writeSeq(hwp, 0x4C, clock & 0xFF); +- } ++/* ++ * ++ */ ++static void ++ViaSetSecondaryDotclock(ScrnInfoPtr pScrn, CARD32 clock) ++{ ++ ViaSetDotclock(pScrn, clock, 0x44, 0x4A); ++} + +- ViaSeqMask(hwp, 0x40, 0x04, 0x04); +- ViaSeqMask(hwp, 0x40, 0x00, 0x04); ++/* ++ * ++ */ ++static void ++ViaSetECKDotclock(ScrnInfoPtr pScrn, CARD32 clock) ++{ ++ /* Does the non-pro chip have an ECK clock ? */ ++ ViaSetDotclock(pScrn, clock, 0, 0x47); + } + + /* +@@ -1287,15 +1304,16 @@ + { + double fvco, fout, fref, err, minErr; + CARD32 dr = 0, dn, dm, maxdm, maxdn; +- CARD32 factual, bestClock; +- ++ CARD32 factual; ++ union pllparams bestClock; ++ + fref = 14.318e6; + fout = (double)clock * 1.e3; + + factual = ~0; +- maxdm = factual / 14318000U - 2; ++ maxdm = factual / 14318000U; + minErr = 1.e10; +- bestClock = 0U; ++ bestClock.packed = 0U; + + do { + fvco = fout * (1 << dr); +@@ -1306,30 +1324,31 @@ + } + + if (clock < 30000) +- maxdn = 6; ++ maxdn = 8; + else if (clock < 45000) +- maxdn = 5; ++ maxdn = 7; + else if (clock < 170000) +- maxdn = 4; ++ maxdn = 6; + else +- maxdn = 3; ++ maxdn = 5; + +- for (dn = 0; dn < maxdn; ++dn) { +- for (dm = 0; dm < maxdm; ++dm) { +- factual = 14318000U * (dm + 2); +- factual /= (dn + 2) << dr; ++ for (dn = 2; dn < maxdn; ++dn) { ++ for (dm = 2; dm < maxdm; ++dm) { ++ factual = 14318000U * dm; ++ factual /= dn << dr; + if ((err = fabs((double)factual / fout - 1.)) < 0.005) { + if (err < minErr) { + minErr = err; +- bestClock = ((dm & 0xff) << 16) | +- (((1 << 7) | (dr << 2) | ((dm & 0x300) >> 8)) << 8) +- | (dn & 0x7f); ++ bestClock.params.dtz = 1; ++ bestClock.params.dr = dr; ++ bestClock.params.dn = dn; ++ bestClock.params.dm = dm; + } + } + } + } + +- return bestClock; ++ return bestClock.packed; + } + + /* +@@ -1356,15 +1375,10 @@ + "ViaComputeDotClock %d : %04x : %04x\n", + mode->Clock, best1, best2)); + return best2; +- } else if (pVia->Chipset == VIA_VX855) { +- for (i = 0; ViaDotClocks[i].DotClock; i++) +- if (ViaDotClocks[i].DotClock == mode->Clock && +- ViaDotClocks[i].Chrome9HCM) +- return ViaDotClocks[i].Chrome9HCM; + } else { + for (i = 0; ViaDotClocks[i].DotClock; i++) + if (ViaDotClocks[i].DotClock == mode->Clock) +- return ViaDotClocks[i].UniChromePro; ++ return ViaDotClocks[i].UniChromePro.packed; + return ViaComputeProDotClock(mode->Clock); + } + +--- src/via_mode.h 2009-06-16 23:08:20.000000000 +0200 ++++ src/via_mode.h 2009-06-16 22:43:58.000000000 +0200 +@@ -35,7 +35,16 @@ + #define VIA_BW_DDR400 498000000 /* > 1920x1080@60Hz@32bpp */ + #define VIA_BW_DDR667 922000000 + +- ++union pllparams { ++ struct { ++ CARD32 dtz : 2; ++ CARD32 dr : 3; ++ CARD32 dn : 7; ++ CARD32 dm :10; ++ } params; ++ CARD32 packed; ++}; ++ + /* + * simple lookup table for dotclocks + * +@@ -43,57 +52,51 @@ + static struct ViaDotClock { + int DotClock; + CARD16 UniChrome; +- CARD32 UniChromePro; +- CARD32 Chrome9HCM; ++ union pllparams UniChromePro; + } ViaDotClocks[] = { +- { 25200, 0x513C, 0xa79004 }, +- { 25312, 0xC763, 0xc49005 }, +- { 26591, 0x471A, 0xce9005 }, +- { 31500, 0xC558, 0xae9003, 0xb01005 }, +- { 31704, 0x471F, 0xaf9002 }, +- { 32663, 0xC449, 0x479000 }, +- { 33750, 0x4721, 0x959002, 0x921004 }, +- { 35500, 0x5877, 0x759001 }, +- { 36000, 0x5879, 0x9f9002, 0xa11004 }, +- { 39822, 0xC459, 0x578c02 }, +- { 40000, 0x515F, 0x848c04, 0x700c05 }, +- { 41164, 0x4417, 0x2c8c00 }, +- { 46981, 0x5069, 0x678c02, 0x690c04 }, +- { 49500, 0xC353, 0xa48c04, 0x530c03 }, +- { 50000, 0xC354, 0x368c00 }, +- { 56300, 0x4F76, 0x3d8c00, 0x9d0c05 }, +- { 57284, 0x4E70, 0x3e8c00 }, +- { 64995, 0x0D3B, 0x6b8c01, 0x6d0c03 }, +- { 65000, 0x0D3B, 0x6b8c01, 0x6d0c03 }, /* Slightly unstable on PM800 */ +- { 65028, 0x866D, 0x6b8c01 }, +- { 74480, 0x156E, 0x288800, 0xd10c05 }, +- { 75000, 0x156E, 0x288800 }, +- { 78800, 0x442C, 0x2a8800, 0x6e0805 }, +- { 81135, 0x0622, 0x428801 }, +- { 81613, 0x4539, 0x708803, 0x720805 }, +- { 94500, 0x4542, 0x4d8801, 0x840805 }, +- { 108000, 0x0B53, 0x778802, 0x970805 }, +- { 108280, 0x4879, 0x778802 }, +- { 122000, 0x0D6F, 0x428800 }, +- { 122726, 0x073C, 0x878802, 0xac0805 }, +- { 135000, 0x0742, 0x6f8801, 0xbd0805}, +- { 148500, 0x0853, 0x518800, 0xd00805}, +- { 155800, 0x0857, 0x558402 }, +- { 157500, 0x422C, 0x2a8400, 0x6e0405 }, +- { 161793, 0x4571, 0x6f8403 }, +- { 162000, 0x0A71, 0x6f8403, 0x710405 }, +- { 175500, 0x4231, 0x2f8400 }, +- { 189000, 0x0542, 0x4d8401 }, +- { 202500, 0x0763, 0x6F8402, 0x8e0405 }, +- { 204800, 0x0764, 0x548401 }, +- { 218300, 0x043D, 0x3b8400, 0x990405 }, +- { 229500, 0x0660, 0x3e8400, 0xa10405 }, /* Not tested on Pro */ +- { 234000, 0, 0xa20403, 0xa40405 }, +- { 267250, 0, 0xb90403, 0xbb0405 }, +- { 297500, 0, 0xce0403, 0xd00405 }, +- { 339500, 0, 0x5d0002, 0x770005 }, +- { 340772, 0, 0x750003, 0x770005 }, +- { 0, 0, 0 } ++ { 25200, 0x513C, /* 0xa79004 */ { 1, 4, 6, 169 } }, ++ { 25312, 0xC763, /* 0xc49005 */ { 1, 4, 7, 198 } }, ++ { 26591, 0x471A, /* 0xce9005 */ { 1, 4, 7, 208 } }, ++ { 31500, 0xC558, /* 0xae9003 */ { 1, 4, 5, 176 } }, ++ { 31704, 0x471F, /* 0xaf9002 */ { 1, 4, 4, 177 } }, ++ { 32663, 0xC449, /* 0x479000 */ { 1, 4, 2, 73 } }, ++ { 33750, 0x4721, /* 0x959002 */ { 1, 4, 4, 151 } }, ++ { 35500, 0x5877, /* 0x759001 */ { 1, 4, 3, 119 } }, ++ { 36000, 0x5879, /* 0x9f9002 */ { 1, 4, 4, 161 } }, ++ { 39822, 0xC459, /* 0x578c02 */ { 1, 3, 4, 89 } }, ++ { 40000, 0x515F, /* 0x848c04 */ { 1, 3, 6, 134 } }, ++ { 41164, 0x4417, /* 0x2c8c00 */ { 1, 3, 2, 46 } }, ++ { 46981, 0x5069, /* 0x678c02 */ { 1, 3, 4, 105 } }, ++ { 49500, 0xC353, /* 0xa48c04 */ { 3, 3, 5, 138 } }, ++ { 50000, 0xC354, /* 0x368c00 */ { 1, 3, 2, 56 } }, ++ { 56300, 0x4F76, /* 0x3d8c00 */ { 1, 3, 2, 63 } }, ++ { 57284, 0x4E70, /* 0x3e8c00 */ { 1, 3, 2, 64 } }, ++ { 64995, 0x0D3B, /* 0x6b8c01 */ { 1, 3, 3, 109 } }, ++ { 65000, 0x0D3B, /* 0x6b8c01 */ { 1, 3, 3, 109 } }, /* Slightly unstable on PM800 */ ++ { 65028, 0x866D, /* 0x6b8c01 */ { 1, 3, 3, 109 } }, ++ { 74480, 0x156E, /* 0x288800 */ { 1, 2, 2, 42 } }, ++ { 75000, 0x156E, /* 0x288800 */ { 1, 2, 2, 42 } }, ++ { 78800, 0x442C, /* 0x2a8800 */ { 1, 2, 2, 44 } }, ++ { 81135, 0x0622, /* 0x428801 */ { 1, 2, 3, 68 } }, ++ { 81613, 0x4539, /* 0x708803 */ { 1, 2, 5, 114 } }, ++ { 94500, 0x4542, /* 0x4d8801 */ { 1, 2, 3, 79 } }, ++ { 108000, 0x0B53, /* 0x778802 */ { 1, 2, 4, 121 } }, ++ { 108280, 0x4879, /* 0x778802 */ { 1, 2, 4, 121 } }, ++ { 122000, 0x0D6F, /* 0x428800 */ { 1, 2, 2, 68 } }, ++ { 122726, 0x073C, /* 0x878802 */ { 1, 2, 4, 137 } }, ++ { 135000, 0x0742, /* 0x6f8801 */ { 1, 2, 3, 113 } }, ++ { 148500, 0x0853, /* 0x518800 */ { 1, 2, 2, 83 } }, ++ { 155800, 0x0857, /* 0x558402 */ { 1, 1, 4, 87 } }, ++ { 157500, 0x422C, /* 0x2a8400 */ { 1, 1, 2, 44 } }, ++ { 161793, 0x4571, /* 0x6f8403 */ { 1, 1, 5, 113 } }, ++ { 162000, 0x0A71, /* 0x6f8403 */ { 1, 1, 5, 113 } }, ++ { 175500, 0x4231, /* 0x2f8400 */ { 1, 1, 2, 49 } }, ++ { 189000, 0x0542, /* 0x4d8401 */ { 1, 1, 3, 79 } }, ++ { 202500, 0x0763, /* 0x6F8402 */ { 1, 1, 4, 113 } }, ++ { 204800, 0x0764, /* 0x548401 */ { 1, 1, 3, 86 } }, ++ { 218300, 0x043D, /* 0x3b8400 */ { 1, 1, 2, 61 } }, ++ { 229500, 0x0660, /* 0x3e8400 */ { 1, 1, 2, 64 } }, /* Not tested on Pro } */ ++ { 0, 0, { 0, 0, 0, 0 } } + }; + + /* diff --git a/openchrome-0.2.903-vx855_support.patch b/openchrome-0.2.903-vx855_support.patch new file mode 100644 index 0000000..06749a7 --- /dev/null +++ b/openchrome-0.2.903-vx855_support.patch @@ -0,0 +1,678 @@ +Index: src/via_id.h +=================================================================== +--- src/via_id.h (revision 751) ++++ src/via_id.h (working copy) +@@ -38,6 +38,7 @@ + VIA_CX700, + VIA_P4M890, + VIA_VX800, ++ VIA_VX855, + VIA_LAST + }; + +@@ -54,6 +55,7 @@ + #define PCI_CHIP_VT3324 0x3157 /* CX700 */ + #define PCI_CHIP_VT3327 0x3343 /* P4M890 */ + #define PCI_CHIP_VT3353 0x1122 /* VX800 */ ++#define PCI_CHIP_VT3409 0x5122 /* VX855/VX875 */ + + /* There is some conflicting information about the two major revisions of + * the CLE266, often labelled Ax and Cx. The dividing line seems to be +Index: src/via_video.c +=================================================================== +--- src/via_video.c (revision 751) ++++ src/via_video.c (working copy) +@@ -277,6 +277,7 @@ + pVia->ChipId != PCI_CHIP_VT3314 && + pVia->ChipId != PCI_CHIP_VT3327 && + pVia->ChipId != PCI_CHIP_VT3336 && ++ pVia->ChipId != PCI_CHIP_VT3409 && + pVia->ChipId != PCI_CHIP_VT3364 && + pVia->ChipId != PCI_CHIP_VT3324 && + pVia->ChipId != PCI_CHIP_VT3353) { +Index: src/via_mode.c +=================================================================== +--- src/via_mode.c (revision 751) ++++ src/via_mode.c (working copy) +@@ -371,17 +371,20 @@ + } + } + +- if ((pVia->Chipset == VIA_CX700) || (pVia->Chipset == VIA_VX800)) { +- +- if (ViaDFPDetect(pScrn)) { +- pBIOSInfo->DfpPresent = TRUE; +- xf86DrvMsg(pScrn->scrnIndex, X_INFO, +- "DFP is connected.\n"); +- } else { +- pBIOSInfo->DfpPresent = FALSE; +- xf86DrvMsg(pScrn->scrnIndex, X_INFO, +- "DFP is disconnected.\n"); +- } ++ switch (pVia->Chipset) { ++ case VIA_CX700: ++ case VIA_VX800: ++ case VIA_VX855: ++ if (ViaDFPDetect(pScrn)) { ++ pBIOSInfo->DfpPresent = TRUE; ++ xf86DrvMsg(pScrn->scrnIndex, X_INFO, ++ "DFP is connected.\n"); ++ } else { ++ pBIOSInfo->DfpPresent = FALSE; ++ xf86DrvMsg(pScrn->scrnIndex, X_INFO, ++ "DFP is disconnected.\n"); ++ } ++ break; + } + } + +@@ -496,8 +499,14 @@ + pBIOSInfo->FirstCRTC->IsActive = TRUE ; + if (pBIOSInfo->Panel->IsActive) { + pVia->pBIOSInfo->SecondCRTC->IsActive = TRUE ; +- if (pVia->Chipset == VIA_P4M900 || pVia->Chipset == VIA_CX700 || pVia->Chipset == VIA_VX800 ) +- pVia->pBIOSInfo->Lvds->IsActive = TRUE ; ++ switch (pVia->Chipset) { ++ case VIA_P4M900: ++ case VIA_CX700: ++ case VIA_VX800: ++ case VIA_VX855: ++ pVia->pBIOSInfo->Lvds->IsActive = TRUE ; ++ break; ++ } + } + } + +@@ -1347,6 +1356,11 @@ + "ViaComputeDotClock %d : %04x : %04x\n", + mode->Clock, best1, best2)); + return best2; ++ } else if (pVia->Chipset == VIA_VX855) { ++ for (i = 0; ViaDotClocks[i].DotClock; i++) ++ if (ViaDotClocks[i].DotClock == mode->Clock && ++ ViaDotClocks[i].Chrome9HCM) ++ return ViaDotClocks[i].Chrome9HCM; + } else { + for (i = 0; ViaDotClocks[i].DotClock; i++) + if (ViaDotClocks[i].DotClock == mode->Clock) +Index: src/via_mode.h +=================================================================== +--- src/via_mode.h (revision 751) ++++ src/via_mode.h (working copy) +@@ -44,49 +44,55 @@ + int DotClock; + CARD16 UniChrome; + CARD32 UniChromePro; ++ CARD32 Chrome9HCM; + } ViaDotClocks[] = { + { 25200, 0x513C, 0xa79004 }, + { 25312, 0xC763, 0xc49005 }, + { 26591, 0x471A, 0xce9005 }, +- { 31500, 0xC558, 0xae9003 }, ++ { 31500, 0xC558, 0xae9003, 0xb01005 }, + { 31704, 0x471F, 0xaf9002 }, + { 32663, 0xC449, 0x479000 }, +- { 33750, 0x4721, 0x959002 }, ++ { 33750, 0x4721, 0x959002, 0x921004 }, + { 35500, 0x5877, 0x759001 }, +- { 36000, 0x5879, 0x9f9002 }, ++ { 36000, 0x5879, 0x9f9002, 0xa11004 }, + { 39822, 0xC459, 0x578c02 }, +- { 40000, 0x515F, 0x848c04 }, ++ { 40000, 0x515F, 0x848c04, 0x700c05 }, + { 41164, 0x4417, 0x2c8c00 }, +- { 46981, 0x5069, 0x678c02 }, +- { 49500, 0xC353, 0xa48c04 }, ++ { 46981, 0x5069, 0x678c02, 0x690c04 }, ++ { 49500, 0xC353, 0xa48c04, 0x530c03 }, + { 50000, 0xC354, 0x368c00 }, +- { 56300, 0x4F76, 0x3d8c00 }, ++ { 56300, 0x4F76, 0x3d8c00, 0x9d0c05 }, + { 57284, 0x4E70, 0x3e8c00 }, +- { 64995, 0x0D3B, 0x6b8c01 }, +- { 65000, 0x0D3B, 0x6b8c01 }, /* Slightly unstable on PM800 */ ++ { 64995, 0x0D3B, 0x6b8c01, 0x6d0c03 }, ++ { 65000, 0x0D3B, 0x6b8c01, 0x6d0c03 }, /* Slightly unstable on PM800 */ + { 65028, 0x866D, 0x6b8c01 }, +- { 74480, 0x156E, 0x288800 }, ++ { 74480, 0x156E, 0x288800, 0xd10c05 }, + { 75000, 0x156E, 0x288800 }, +- { 78800, 0x442C, 0x2a8800 }, ++ { 78800, 0x442C, 0x2a8800, 0x6e0805 }, + { 81135, 0x0622, 0x428801 }, +- { 81613, 0x4539, 0x708803 }, +- { 94500, 0x4542, 0x4d8801 }, +- { 108000, 0x0B53, 0x778802 }, ++ { 81613, 0x4539, 0x708803, 0x720805 }, ++ { 94500, 0x4542, 0x4d8801, 0x840805 }, ++ { 108000, 0x0B53, 0x778802, 0x970805 }, + { 108280, 0x4879, 0x778802 }, + { 122000, 0x0D6F, 0x428800 }, +- { 122726, 0x073C, 0x878802 }, +- { 135000, 0x0742, 0x6f8801 }, +- { 148500, 0x0853, 0x518800 }, ++ { 122726, 0x073C, 0x878802, 0xac0805 }, ++ { 135000, 0x0742, 0x6f8801, 0xbd0805}, ++ { 148500, 0x0853, 0x518800, 0xd00805}, + { 155800, 0x0857, 0x558402 }, +- { 157500, 0x422C, 0x2a8400 }, ++ { 157500, 0x422C, 0x2a8400, 0x6e0405 }, + { 161793, 0x4571, 0x6f8403 }, +- { 162000, 0x0A71, 0x6f8403 }, ++ { 162000, 0x0A71, 0x6f8403, 0x710405 }, + { 175500, 0x4231, 0x2f8400 }, + { 189000, 0x0542, 0x4d8401 }, +- { 202500, 0x0763, 0x6F8402 }, ++ { 202500, 0x0763, 0x6F8402, 0x8e0405 }, + { 204800, 0x0764, 0x548401 }, +- { 218300, 0x043D, 0x3b8400 }, +- { 229500, 0x0660, 0x3e8400 }, /* Not tested on Pro */ ++ { 218300, 0x043D, 0x3b8400, 0x990405 }, ++ { 229500, 0x0660, 0x3e8400, 0xa10405 }, /* Not tested on Pro */ ++ { 234000, 0, 0xa20403, 0xa40405 }, ++ { 267250, 0, 0xb90403, 0xbb0405 }, ++ { 297500, 0, 0xce0403, 0xd00405 }, ++ { 339500, 0, 0x5d0002, 0x770005 }, ++ { 340772, 0, 0x750003, 0x770005 }, + { 0, 0, 0 } + }; + +Index: src/via_driver.c +=================================================================== +--- src/via_driver.c (revision 751) ++++ src/via_driver.c (working copy) +@@ -128,6 +128,7 @@ + VIA_DEVICE_MATCH (PCI_CHIP_VT3324, 0 ), + VIA_DEVICE_MATCH (PCI_CHIP_VT3327, 0 ), + VIA_DEVICE_MATCH (PCI_CHIP_VT3353, 0 ), ++ VIA_DEVICE_MATCH (PCI_CHIP_VT3409, 0 ), + { 0, 0, 0 }, + }; + +@@ -164,6 +165,7 @@ + {VIA_CX700, "CX700/VX700"}, + {VIA_P4M890, "P4M890"}, + {VIA_VX800, "VX800"}, ++ {VIA_VX855, "VX855"}, + {-1, NULL } + }; + +@@ -179,6 +181,7 @@ + {VIA_CX700, PCI_CHIP_VT3324, RES_SHARED_VGA}, + {VIA_P4M890, PCI_CHIP_VT3327, RES_SHARED_VGA}, + {VIA_VX800, PCI_CHIP_VT3353, RES_SHARED_VGA}, ++ {VIA_VX855, PCI_CHIP_VT3409, RES_SHARED_VGA}, + {-1, -1, RES_UNDEFINED} + }; + +@@ -908,6 +911,7 @@ + pVia->UseLegacyModeSwitch = FALSE; + break; + case VIA_VX800: ++ case VIA_VX855: + pVia->VideoEngine = VIDEO_ENGINE_CME; + /* pVia->agpEnable = FALSE; + pVia->dmaXV = FALSE;*/ +@@ -1180,6 +1184,7 @@ + case VIA_P4M900: + case VIA_CX700: + case VIA_VX800: ++ case VIA_VX855: + #ifdef XSERVER_LIBPCIACCESS + pci_device_cfg_read_u8(vgaDevice, &videoRam, 0xA1); + #else +@@ -1926,8 +1931,16 @@ + viaAccelSync(pScrn); + + /* A soft reset helps to avoid a 3D hang on VT switch. */ +- if (pVia->Chipset != VIA_K8M890 && pVia->Chipset != VIA_P4M900 && pVia->Chipset != VIA_VX800) +- hwp->writeSeq(hwp, 0x1A, pVia->SavedReg.SR1A | 0x40); ++ switch (pVia->Chipset) { ++ case VIA_K8M890: ++ case VIA_P4M900: ++ case VIA_VX800: ++ case VIA_VX855: ++ break; ++ default: ++ hwp->writeSeq(hwp, 0x1A, pVia->SavedReg.SR1A | 0x40); ++ break; ++ } + + #ifdef XF86DRI + if (pVia->directRenderingEnabled) { +@@ -2103,8 +2116,13 @@ + } + + /* Save TMDS status */ +- if ((pVia->Chipset == VIA_CX700) || (pVia->Chipset == VIA_VX800)) +- Regs->CRD2 = hwp->readCrtc(hwp, 0xD2); ++ switch (pVia->Chipset) { ++ case VIA_CX700: ++ case VIA_VX800: ++ case VIA_VX855: ++ Regs->CRD2 = hwp->readCrtc(hwp, 0xD2); ++ break; ++ } + + vgaHWProtect(pScrn, FALSE); + } +@@ -2219,8 +2237,13 @@ + } + + /* Restore TMDS status */ +- if ((pVia->Chipset == VIA_CX700) || (pVia->Chipset == VIA_VX800)) +- hwp->writeCrtc(hwp, 0xD2, Regs->CRD2); ++ switch (pVia->Chipset) { ++ case VIA_CX700: ++ case VIA_VX800: ++ case VIA_VX855: ++ hwp->writeCrtc(hwp, 0xD2, Regs->CRD2); ++ break; ++ } + + if (pBIOSInfo->Panel->IsActive) + ViaLCDPower(pScrn, TRUE); +@@ -2245,6 +2268,7 @@ + case VIA_CX700: + case VIA_P4M900: + case VIA_VX800: ++ case VIA_VX855: + ViaSeqMask(hwp, 0x1A, 0x08, 0x08); + break; + default: +@@ -2267,6 +2291,7 @@ + case VIA_CX700: + case VIA_P4M900: + case VIA_VX800: ++ case VIA_VX855: + ViaSeqMask(hwp, 0x1A, 0x00, 0x08); + break; + default: +@@ -2956,13 +2981,19 @@ + * to detect when the display is using the secondary head. + * TODO: This should be enabled for other chipsets as well. + */ +- if ((pVia->Chipset == VIA_P4M900 || pVia->Chipset == VIA_VX800) && pVia->pBIOSInfo->Panel->IsActive) { +- /* +- * Since we are using virtual, we need to adjust +- * the offset to match the framebuffer alignment. +- */ +- if (pScrn->displayWidth != mode->CrtcHDisplay) +- ViaSecondCRTCHorizontalOffset(pScrn); ++ if (pVia->pBIOSInfo->Panel->IsActive) { ++ switch (pVia->Chipset) { ++ case VIA_P4M900: ++ case VIA_VX800: ++ case VIA_VX855: ++ /* ++ * Since we are using virtual, we need to adjust ++ * the offset to match the framebuffer alignment. ++ */ ++ if (pScrn->displayWidth != mode->CrtcHDisplay) ++ ViaSecondCRTCHorizontalOffset(pScrn); ++ break; ++ } + } + } + +@@ -2996,9 +3027,16 @@ + viaAccelSync(pScrn); + + /* A soft reset avoids a 3D hang after X restart. */ +- if (pVia->Chipset != VIA_K8M890 && pVia->Chipset != VIA_P4M900 && +- pVia->Chipset != VIA_VX800) +- hwp->writeSeq(hwp, 0x1A, pVia->SavedReg.SR1A | 0x40); ++ switch (pVia->Chipset) { ++ case VIA_K8M890: ++ case VIA_P4M900: ++ case VIA_VX800: ++ case VIA_VX855: ++ break; ++ default : ++ hwp->writeSeq(hwp, 0x1A, pVia->SavedReg.SR1A | 0x40); ++ break; ++ } + + if (!pVia->IsSecondary) { + /* Turn off all video activities. */ +Index: src/via_crtc.c +=================================================================== +--- src/via_crtc.c (revision 751) ++++ src/via_crtc.c (working copy) +@@ -173,6 +173,7 @@ + case VIA_CX700: + case VIA_P4M900: + case VIA_VX800: ++ case VIA_VX855: + break; + default: + ViaSeqMask(hwp, 0x16, 0x08, 0xBF); +@@ -276,6 +277,7 @@ + case VIA_CX700: + case VIA_P4M900: + case VIA_VX800: ++ case VIA_VX855: + break; + default: + /* some leftovers */ +@@ -310,6 +312,7 @@ + case VIA_CX700: + case VIA_P4M900: + case VIA_VX800: ++ case VIA_VX855: + break; + default: + /* some leftovers */ +@@ -429,6 +432,7 @@ + case VIA_CX700: + case VIA_P4M900: + case VIA_VX800: ++ case VIA_VX855: + break; + default: + ViaSeqMask(hwp, 0x16, 0x08, 0xBF); +@@ -512,6 +516,7 @@ + case VIA_CX700: + case VIA_P4M900: + case VIA_VX800: ++ case VIA_VX855: + break; + default: + /* some leftovers */ +Index: src/via_swov.c +=================================================================== +--- src/via_swov.c (revision 751) ++++ src/via_swov.c (working copy) +@@ -282,6 +282,7 @@ + HWDiff->dwNeedV1Prefetch = VID_HWDIFF_FALSE; + break; + case VIA_VX800: ++ case VIA_VX855: + HWDiff->dwThreeHQVBuffer = VID_HWDIFF_TRUE; + HWDiff->dwHQVFetchByteUnit = VID_HWDIFF_TRUE; + HWDiff->dwSupportTwoColorKey = VID_HWDIFF_TRUE; +@@ -784,6 +785,7 @@ + case PCI_CHIP_VT3324: + case PCI_CHIP_VT3327: + case PCI_CHIP_VT3353: ++ case PCI_CHIP_VT3409: + model = 0; + break; + case PCI_CHIP_CLE3122: +@@ -922,6 +924,7 @@ + case PCI_CHIP_VT3324: + case PCI_CHIP_VT3364: + case PCI_CHIP_VT3353: ++ case PCI_CHIP_VT3409: + case PCI_CHIP_CLE3122: + VIDOutD(V1_ColorSpaceReg_2, col2); + VIDOutD(V1_ColorSpaceReg_1, col1); +@@ -951,6 +954,7 @@ + case PCI_CHIP_VT3324: + case PCI_CHIP_VT3364: + case PCI_CHIP_VT3353: ++ case PCI_CHIP_VT3409: + return (VIDEO_HQV_INUSE | SW_USE_HQV | VIDEO_1_INUSE + | VIDEO_ACTIVE | VIDEO_SHOW); + case PCI_CHIP_CLE3122: +@@ -990,6 +994,8 @@ + case PCI_CHIP_VT3364: + case PCI_CHIP_VT3353: + return V3_ENABLE | VIDEO_EXPIRE_NUM_VT3336; ++ case PCI_CHIP_VT3409: ++ return V3_ENABLE | VIDEO_EXPIRE_NUM_VT3409; + case PCI_CHIP_CLE3122: + if (CLE266_REV_IS_CX(pVia->ChipRev)) + return V3_ENABLE | V3_EXPIRE_NUM_F; +@@ -1269,24 +1275,28 @@ + static void + SetFIFO_V3(VIAPtr pVia, CARD8 depth, CARD8 prethreshold, CARD8 threshold) + { +- if ((pVia->ChipId == PCI_CHIP_VT3314) +- || (pVia->ChipId == PCI_CHIP_VT3324) +- || (pVia->ChipId == PCI_CHIP_VT3327 +- || (pVia->ChipId == PCI_CHIP_VT3353))) { +- SaveVideoRegister(pVia, ALPHA_V3_FIFO_CONTROL, +- (VIDInD(ALPHA_V3_FIFO_CONTROL) & ALPHA_FIFO_MASK) +- | ((depth - 1) & 0xff) | ((threshold & 0xff) << 8)); +- SaveVideoRegister(pVia, ALPHA_V3_PREFIFO_CONTROL, +- (VIDInD(ALPHA_V3_PREFIFO_CONTROL) +- & ~V3_FIFO_MASK_3314) | (prethreshold & 0xff)); +- } else { +- SaveVideoRegister(pVia, ALPHA_V3_FIFO_CONTROL, +- (VIDInD(ALPHA_V3_FIFO_CONTROL) & ALPHA_FIFO_MASK) +- | ((depth - 1) & 0xff) | ((threshold & 0xff) << 8)); +- SaveVideoRegister(pVia, ALPHA_V3_PREFIFO_CONTROL, +- (VIDInD(ALPHA_V3_PREFIFO_CONTROL) & ~V3_FIFO_MASK) +- | (prethreshold & 0x7f)); +- } ++ switch (pVia->ChipId) { ++ case PCI_CHIP_VT3314: ++ case PCI_CHIP_VT3324: ++ case PCI_CHIP_VT3327: ++ case PCI_CHIP_VT3353: ++ case PCI_CHIP_VT3409: ++ SaveVideoRegister(pVia, ALPHA_V3_FIFO_CONTROL, ++ (VIDInD(ALPHA_V3_FIFO_CONTROL) & ALPHA_FIFO_MASK) ++ | ((depth - 1) & 0xff) | ((threshold & 0xff) << 8)); ++ SaveVideoRegister(pVia, ALPHA_V3_PREFIFO_CONTROL, ++ (VIDInD(ALPHA_V3_PREFIFO_CONTROL) ++ & ~V3_FIFO_MASK_3314) | (prethreshold & 0xff)); ++ break; ++ default : ++ SaveVideoRegister(pVia, ALPHA_V3_FIFO_CONTROL, ++ (VIDInD(ALPHA_V3_FIFO_CONTROL) & ALPHA_FIFO_MASK) ++ | ((depth - 1) & 0xff) | ((threshold & 0xff) << 8)); ++ SaveVideoRegister(pVia, ALPHA_V3_PREFIFO_CONTROL, ++ (VIDInD(ALPHA_V3_PREFIFO_CONTROL) & ~V3_FIFO_MASK) ++ | (prethreshold & 0x7f)); ++ break; ++ } + } + + static void +@@ -1335,6 +1345,7 @@ + case PCI_CHIP_VT3324: + case PCI_CHIP_VT3364: + case PCI_CHIP_VT3353: ++ case PCI_CHIP_VT3409: + SetFIFO_V3(pVia, 225, 200, 250); + break; + case PCI_CHIP_VT3204: +@@ -1367,6 +1378,7 @@ + case PCI_CHIP_VT3324: + case PCI_CHIP_VT3364: + case PCI_CHIP_VT3353: ++ case PCI_CHIP_VT3409: + SetFIFO_V3(pVia, 225, 200, 250); + break; + case PCI_CHIP_VT3204: +@@ -2011,7 +2023,7 @@ + if (pVia->VideoEngine == VIDEO_ENGINE_CME) { + VIDOutD(HQV_SRC_DATA_OFFSET_CONTROL1,0); + VIDOutD(HQV_SRC_DATA_OFFSET_CONTROL3,((pUpdate->SrcRight - 1 ) << 16) | (pUpdate->SrcBottom - 1)); +- if (pVia->Chipset == VIA_VX800) { ++ if (pVia->Chipset == VIA_VX800 || pVia->Chipset == VIA_VX855) { + VIDOutD(HQV_SRC_DATA_OFFSET_CONTROL2,0); + VIDOutD(HQV_SRC_DATA_OFFSET_CONTROL4,((pUpdate->SrcRight - 1 ) << 16) | (pUpdate->SrcBottom - 1)); + } +Index: src/via_bandwidth.c +=================================================================== +--- src/via_bandwidth.c (revision 751) ++++ src/via_bandwidth.c (working copy) +@@ -244,6 +244,11 @@ + hwp->writeSeq(hwp, 0x18, 0x26); /* 152/4 = 38 */ + hwp->writeSeq(hwp, 0x22, 0x10); /* 64/4 = 16 */ + break; ++ case VIA_VX855: ++ hwp->writeSeq(hwp, 0x16, 0x50); /* 320/4 = 80 */ ++ hwp->writeSeq(hwp, 0x17, 0xC7); /* 400/2-1 = 199 */ ++ hwp->writeSeq(hwp, 0x18, 0x50); /* 320/4 = 80 */ ++ hwp->writeSeq(hwp, 0x22, 0x28); /* 160/4 = 40 */ + default: + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "ViaSetPrimaryFIFO: " + "Chipset %d not implemented\n", pVia->Chipset); +@@ -412,6 +417,8 @@ + else + ViaCrtcMask(hwp, 0x94, 0x20, 0x7F); + break; ++ case VIA_VX855: ++ break; + default: + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "ViaSetSecondaryFIFO: " + "Chipset %d not implemented\n", pVia->Chipset); +Index: src/via_accel.c +=================================================================== +--- src/via_accel.c (revision 751) ++++ src/via_accel.c (working copy) +@@ -195,6 +195,7 @@ + */ + switch (pVia->Chipset) { + case VIA_VX800: ++ case VIA_VX855: + while ((VIAGETREG(VIA_REG_STATUS) & + (VIA_CMD_RGTR_BUSY_H5 | VIA_2D_ENG_BUSY_H5)) + && (loop++ < MAXLOOP)) ; +@@ -471,7 +472,7 @@ + VIASETREG(i, 0x0); + } + +- if (pVia->Chipset == VIA_VX800) { ++ if (pVia->Chipset == VIA_VX800 || pVia->Chipset == VIA_VX855) { + for (i = 0x44; i < 0x5c; i += 4) { + VIASETREG(i, 0x0); + } +@@ -480,6 +481,7 @@ + /* Make the VIA_REG() macro magic work */ + switch (pVia->Chipset) { + case VIA_VX800: ++ case VIA_VX855: + pVia->TwodRegs = via_2d_regs_m1; + break; + default: +@@ -527,6 +529,7 @@ + + switch (pVia->Chipset) { + case VIA_VX800: ++ case VIA_VX855: + while ((VIAGETREG(VIA_REG_STATUS) & + (VIA_CMD_RGTR_BUSY_H5 | VIA_2D_ENG_BUSY_H5 | VIA_3D_ENG_BUSY_H5)) + && (loop++ < MAXLOOP)) ; +@@ -587,7 +590,7 @@ + unsigned val = (dstPitch >> 3) << 16 | (srcPitch >> 3); + RING_VARS; + +- if (pVia->Chipset != VIA_VX800) { ++ if (pVia->Chipset != VIA_VX800 && pVia->Chipset != VIA_VX855) { + val |= VIA_PITCH_ENABLE; + } + OUT_RING_H1(VIA_REG(pVia, PITCH), val); +@@ -1289,17 +1292,23 @@ + * test with x11perf -shmput500! + */ + +- if (pVia->Chipset != VIA_K8M800 && +- pVia->Chipset != VIA_K8M890 && +- pVia->Chipset != VIA_P4M900 && +- pVia->Chipset != VIA_VX800) +- xaaptr->ImageWriteFlags |= NO_GXCOPY; ++ switch (pVia->Chipset) { ++ case VIA_K8M800: ++ case VIA_K8M890: ++ case VIA_P4M900: ++ case VIA_VX800: ++ case VIA_VX855: ++ break; ++ default: ++ xaaptr->ImageWriteFlags |= NO_GXCOPY; ++ break; ++ } + + xaaptr->SetupForImageWrite = viaSetupForImageWrite; + xaaptr->SubsequentImageWriteRect = viaSubsequentImageWriteRect; + xaaptr->ImageWriteBase = pVia->BltBase; + +- if (pVia->Chipset == VIA_VX800) ++ if (pVia->Chipset == VIA_VX800 || pVia->Chipset == VIA_VX855) + xaaptr->ImageWriteRange = VIA_MMIO_BLTSIZE; + else + xaaptr->ImageWriteRange = (64 * 1024); +Index: src/via_cursor.c +=================================================================== +--- src/via_cursor.c (revision 751) ++++ src/via_cursor.c (working copy) +@@ -97,6 +97,7 @@ + case VIA_P4M890: + case VIA_P4M900: + case VIA_VX800: ++ case VIA_VX855: + if (pVia->pBIOSInfo->FirstCRTC->IsActive) { + pVia->CursorRegControl = VIA_REG_HI_CONTROL0; + pVia->CursorRegBase = VIA_REG_HI_BASE0; +@@ -164,6 +165,7 @@ + case VIA_P4M890: + case VIA_P4M900: + case VIA_VX800: ++ case VIA_VX855: + if (pVia->pBIOSInfo->FirstCRTC->IsActive) { + VIASETREG(VIA_REG_PRIM_HI_INVTCOLOR, 0x00FFFFFF); + VIASETREG(VIA_REG_V327_HI_INVTCOLOR, 0x00FFFFFF); +@@ -222,6 +224,7 @@ + case VIA_P4M890: + case VIA_P4M900: + case VIA_VX800: ++ case VIA_VX855: + if (pVia->pBIOSInfo->FirstCRTC->IsActive) { + pVia->CursorPrimHiInvtColor = VIAGETREG(VIA_REG_PRIM_HI_INVTCOLOR); + pVia->CursorV327HiInvtColor = VIAGETREG(VIA_REG_V327_HI_INVTCOLOR); +@@ -261,6 +264,7 @@ + case VIA_P4M890: + case VIA_P4M900: + case VIA_VX800: ++ case VIA_VX855: + if (pVia->pBIOSInfo->FirstCRTC->IsActive) { + VIASETREG(VIA_REG_PRIM_HI_INVTCOLOR, pVia->CursorPrimHiInvtColor); + VIASETREG(VIA_REG_V327_HI_INVTCOLOR, pVia->CursorV327HiInvtColor); +Index: src/via_xvmc.c +=================================================================== +--- src/via_xvmc.c (revision 751) ++++ src/via_xvmc.c (working copy) +@@ -322,6 +322,7 @@ + if ((pVia->Chipset == VIA_KM400) || + (pVia->Chipset == VIA_CX700) || + (pVia->Chipset == VIA_VX800) || ++ (pVia->Chipset == VIA_VX855) || + (pVia->Chipset == VIA_K8M890) || + (pVia->Chipset == VIA_P4M900)) { + xf86DrvMsg(pScrn->scrnIndex, X_WARNING, +Index: src/via.h +=================================================================== +--- src/via.h (revision 751) ++++ src/via.h (working copy) +@@ -327,6 +327,12 @@ + #define VIDEO_FIFO_PRETHRESHOLD_VT3336 250 + #define VIDEO_EXPIRE_NUM_VT3336 31 + ++/* Those values are only valid for IGA1 */ ++#define VIDEO_FIFO_DEPTH_VT3409 400 ++#define VIDEO_FIFO_THRESHOLD_VT3409 320 ++#define VIDEO_FIFO_PRETHRESHOLD_VT3409 230 ++#define VIDEO_EXPIRE_NUM_VT3409 160 ++ + /* ALPHA_V3_FIFO_CONTROL 0x278 + * IA2 has 32 level FIFO for packet mode video format + * 32 level FIFO for planar mode video YV12. with extension reg 230 bit 21 enable +Index: src/via_id.c +=================================================================== +--- src/via_id.c (revision 751) ++++ src/via_id.c (working copy) +@@ -222,6 +222,9 @@ + {"Samsung NC20", VIA_VX800, 0x144d, 0xc04e, VIA_DEVICE_CRT | VIA_DEVICE_LCD}, + {"Quanta DreamBook Light IL1", VIA_VX800, 0x152d, 0x0771, VIA_DEVICE_CRT | VIA_DEVICE_LCD}, + ++ /*** VX855 ***/ ++ {"VIA VT8562C", VIA_VX855, 0x1106, 0x5122, VIA_DEVICE_CRT}, ++ + /* keep this */ + {NULL, VIA_UNKNOWN, 0x0000, 0x0000, VIA_DEVICE_NONE} + };