diff -up xorg-server-1.3.0.0/hw/xfree86/modes/xf86EdidModes.c.edid-quirks xorg-server-1.3.0.0/hw/xfree86/modes/xf86EdidModes.c
--- xorg-server-1.3.0.0/hw/xfree86/modes/xf86EdidModes.c.edid-quirks	2007-04-18 00:33:14.000000000 -0400
+++ xorg-server-1.3.0.0/hw/xfree86/modes/xf86EdidModes.c	2007-09-17 14:37:36.000000000 -0400
@@ -49,32 +49,12 @@
 
 typedef enum {
     DDC_QUIRK_NONE = 0,
-    /* Force detailed sync polarity to -h +v */
-    DDC_QUIRK_DT_SYNC_HM_VP = 1 << 0,
     /* First detailed mode is bogus, prefer largest mode at 60hz */
-    DDC_QUIRK_PREFER_LARGE_60 = 1 << 1,
+    DDC_QUIRK_PREFER_LARGE_60 = 1 << 0,
     /* 135MHz clock is too high, drop a bit */
-    DDC_QUIRK_135_CLOCK_TOO_HIGH = 1 << 2
+    DDC_QUIRK_135_CLOCK_TOO_HIGH = 1 << 1
 } ddc_quirk_t;
 
-static Bool quirk_dt_sync_hm_vp (int scrnIndex, xf86MonPtr DDC)
-{
-    /* Belinea 1924S1W */
-    if (memcmp (DDC->vendor.name, "MAX", 4) == 0 &&
-	DDC->vendor.prod_id == 1932)
-	return TRUE;
-    /* Belinea 10 20 30W */
-    if (memcmp (DDC->vendor.name, "MAX", 4) == 0 &&
-	DDC->vendor.prod_id == 2007)
-	return TRUE;
-    /* ViewSonic VX2025wm (bug #9941) */
-    if (memcmp (DDC->vendor.name, "VSC", 4) == 0 &&
-	DDC->vendor.prod_id == 58653)
-	return TRUE;
-
-    return FALSE;
-}
-
 static Bool quirk_prefer_large_60 (int scrnIndex, xf86MonPtr DDC)
 {
     /* Belinea 10 15 55 */
@@ -87,9 +67,10 @@ static Bool quirk_prefer_large_60 (int s
 	DDC->vendor.prod_id == 44358)
 	return TRUE;
 
-    /* Samsung SyncMaster 226BW */
+    /* Samsung SyncMaster 22[56]BW */
     if (memcmp (DDC->vendor.name, "SAM", 4) == 0 &&
-	DDC->vendor.prod_id == 638)
+	(DDC->vendor.prod_id == 638 ||
+	 DDC->vendor.prod_id == 596))
 	return TRUE;
     
     return FALSE;
@@ -112,10 +93,6 @@ typedef struct {
 } ddc_quirk_map_t;
 
 static const ddc_quirk_map_t ddc_quirks[] = {
-    { 
-	quirk_dt_sync_hm_vp,	DDC_QUIRK_DT_SYNC_HM_VP,
-	"Set detailed timing sync polarity to -h +v"
-    },
     {
 	quirk_prefer_large_60,   DDC_QUIRK_PREFER_LARGE_60,
 	"Detailed timing is not preferred, use largest mode at 60Hz"
@@ -251,20 +228,15 @@ DDCModeFromDetailedTiming(int scrnIndex,
     if (timing->interlaced)
         Mode->Flags |= V_INTERLACE;
 
-    if (quirks & DDC_QUIRK_DT_SYNC_HM_VP)
-	Mode->Flags |= V_NHSYNC | V_PVSYNC;
+    if (timing->misc & 0x02)
+	Mode->Flags |= V_PVSYNC;
     else
-    {
-	if (timing->misc & 0x02)
-	    Mode->Flags |= V_PHSYNC;
-	else
-	    Mode->Flags |= V_NHSYNC;
+	Mode->Flags |= V_NVSYNC;
     
-	if (timing->misc & 0x01)
-	    Mode->Flags |= V_PVSYNC;
-	else
-	    Mode->Flags |= V_NVSYNC;
-    }
+    if (timing->misc & 0x01)
+	Mode->Flags |= V_PHSYNC;
+    else
+	Mode->Flags |= V_NHSYNC;
 
     return Mode;
 }