Fix:
FAIL: gdb.arch/powerpc-power6.exp: Power6 disassembly dsub
FAIL: gdb.arch/powerpc-power6.exp: Power6 disassembly dmul
FAIL: gdb.arch/powerpc-power6.exp: Power6 disassembly ddiv
FAIL: gdb.arch/powerpc-power6.exp: Power6 disassembly dcmpu
2007-10-15 Peter Bergner <bergner@vnet.ibm.com>
* ppc-opc.c (powerpc_opcodes): Fix the first two operands of
dquaiq. to use the TE and FRT macros.
--- ./opcodes/ppc-opc.c 16 Oct 2007 02:26:30 -0000 1.100
+++ ./opcodes/ppc-opc.c 16 Oct 2007 02:55:30 -0000 1.101
@@ -4680,7 +4680,7 @@ const struct powerpc_opcode powerpc_opco
{ "dscliq.", ZRC(63,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
{ "dquaiq", ZRC(63,67,0), Z2_MASK, POWER6, { TE, FRT, FRB, RMC } },
-{ "dquaiq.", ZRC(63,67,1), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } },
+{ "dquaiq.", ZRC(63,67,1), Z2_MASK, POWER6, { TE, FRT, FRB, RMC } },
{ "mtfsb0", XRC(63,70,0), XRARB_MASK, COM, { BT } },
{ "mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, { BT } },
2007-10-15 Peter Bergner <bergner@vnet.ibm.com>
* ppc-opc.c (TE): Correct signedness.
(powerpc_opcodes): Sort psq_st and psq_stu according to major
opcode number.
--- ./opcodes/ppc-opc.c 24 Aug 2007 00:56:30 -0000 1.99
+++ ./opcodes/ppc-opc.c 16 Oct 2007 02:26:30 -0000 1.100
@@ -492,13 +492,13 @@ const struct powerpc_operand powerpc_ope
#define VS VD
{ 0x1f, 21, NULL, NULL, PPC_OPERAND_VR },
- /* The SIMM field in a VX form instruction. */
+ /* The SIMM field in a VX form instruction, and TE in Z form. */
#define SIMM VD + 1
+#define TE SIMM
{ 0x1f, 16, NULL, NULL, PPC_OPERAND_SIGNED},
- /* The UIMM field in a VX form instruction, and TE in Z form. */
+ /* The UIMM field in a VX form instruction. */
#define UIMM SIMM + 1
-#define TE UIMM
{ 0x1f, 16, NULL, NULL, 0 },
/* The SHB field in a VA form instruction. */
@@ -4495,9 +4495,6 @@ const struct powerpc_opcode powerpc_opco
{ "fnmadds", A(59,31,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
{ "fnmadds.",A(59,31,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
-{ "psq_st", OP(60), OP_MASK, PPCPS, { FRS, PSD, RA, PSW, PSQ } },
-{ "psq_stu", OP(61), OP_MASK, PPCPS, { FRS, PSD, RA, PSW, PSQ } },
-
{ "dmul", XRC(59,34,0), X_MASK, POWER6, { FRT, FRA, FRB } },
{ "dmul.", XRC(59,34,1), X_MASK, POWER6, { FRT, FRA, FRB } },
@@ -4561,6 +4558,9 @@ const struct powerpc_opcode powerpc_opco
{ "stfq", OP(60), OP_MASK, POWER2, { FRS, D, RA } },
+{ "psq_st", OP(60), OP_MASK, PPCPS, { FRS, PSD, RA, PSW, PSQ } },
+{ "psq_stu", OP(61), OP_MASK, PPCPS, { FRS, PSD, RA, PSW, PSQ } },
+
{ "stfqu", OP(61), OP_MASK, POWER2, { FRS, D, RA } },
{ "stfdp", OP(61), OP_MASK, POWER6, { FRT, D, RA0 } },