diff -rup binutils.orig/bfd/elf64-ppc.c binutils-2.35.1/bfd/elf64-ppc.c
--- binutils.orig/bfd/elf64-ppc.c 2020-10-08 13:50:31.429909431 +0100
+++ binutils-2.35.1/bfd/elf64-ppc.c 2020-10-08 13:56:26.045817623 +0100
@@ -114,7 +114,7 @@ static bfd_vma opd_entry_value
#define elf_backend_adjust_dynamic_symbol ppc64_elf_adjust_dynamic_symbol
#define elf_backend_hide_symbol ppc64_elf_hide_symbol
#define elf_backend_maybe_function_sym ppc64_elf_maybe_function_sym
-#define elf_backend_always_size_sections ppc64_elf_func_desc_adjust
+#define elf_backend_always_size_sections ppc64_elf_edit
#define elf_backend_size_dynamic_sections ppc64_elf_size_dynamic_sections
#define elf_backend_hash_symbol ppc64_elf_hash_symbol
#define elf_backend_init_index_section _bfd_elf_init_2_index_sections
@@ -211,9 +211,10 @@ static bfd_vma opd_entry_value
#define PLD_R12_PC 0x04100000e5800000ULL
#define PNOP 0x0700000000000000ULL
-/* __glink_PLTresolve stub instructions. We enter with the index in R0. */
+/* __glink_PLTresolve stub instructions. We enter with the index in
+ R0 for ELFv1, and the address of a glink branch in R12 for ELFv2. */
#define GLINK_PLTRESOLVE_SIZE(htab) \
- (8u + (htab->opd_abi ? 11 * 4 : 14 * 4))
+ (8u + (htab->opd_abi ? 11 * 4 : htab->has_plt_localentry0 ? 14 * 4 : 13 * 4))
/* 0: */
/* .quad plt0-1f */
/* __glink: */
@@ -229,11 +230,14 @@ static bfd_vma opd_entry_value
/* mtctr %12 */
/* ld %11,16(%11) */
/* bctr */
-#define MFLR_R0 0x7c0802a6 /* mflr %r0 */
-#define MTLR_R0 0x7c0803a6 /* mtlr %r0 */
-#define SUB_R12_R12_R11 0x7d8b6050 /* subf %r12,%r11,%r12 */
-#define ADDI_R0_R12 0x380c0000 /* addi %r0,%r12,0 */
-#define SRDI_R0_R0_2 0x7800f082 /* rldicl %r0,%r0,62,2 */
+
+#define MFLR_R0 0x7c0802a6 /* mflr %r0 */
+#define MTLR_R0 0x7c0803a6 /* mtlr %r0 */
+#define SUB_R12_R12_R11 0x7d8b6050 /* subf %r12,%r11,%r12 */
+#define ADDI_R0_R12 0x380c0000 /* addi %r0,%r12,0 */
+#define SRDI_R0_R0_2 0x7800f082 /* rldicl %r0,%r0,62,2 */
+#define LD_R0_0R11 0xe80b0000 /* ld %r0,0(%r11) */
+#define ADD_R11_R0_R11 0x7d605a14 /* add %r11,%r0,%r11 */
/* Pad with this. */
#define NOP 0x60000000
@@ -6338,13 +6342,13 @@ static const struct sfpr_def_parms save_
};
/* Called near the start of bfd_elf_size_dynamic_sections. We use
- this hook to a) provide some gcc support functions, and b) transfer
- dynamic linking information gathered so far on function code symbol
- entries, to their corresponding function descriptor symbol entries. */
+ this hook to a) run the edit functions in this file, b) provide
+ some gcc support functions, and c) transfer dynamic linking
+ information gathered so far on function code symbol entries, to
+ their corresponding function descriptor symbol entries. */
static bfd_boolean
-ppc64_elf_func_desc_adjust (bfd *obfd ATTRIBUTE_UNUSED,
- struct bfd_link_info *info)
+ppc64_elf_edit (bfd *obfd ATTRIBUTE_UNUSED, struct bfd_link_info *info)
{
struct ppc_link_hash_table *htab;
@@ -6352,6 +6356,9 @@ ppc64_elf_func_desc_adjust (bfd *obfd AT
if (htab == NULL)
return FALSE;
+ /* Call back into the linker, which then runs the edit functions. */
+ htab->params->edit ();
+
/* Provide any missing _save* and _rest* functions. */
if (htab->sfpr != NULL)
{
@@ -7692,9 +7699,11 @@ ppc64_elf_inline_plt (struct bfd_link_in
return TRUE;
}
-/* Set htab->tls_get_addr and call the generic ELF tls_setup function. */
+/* Set htab->tls_get_addr and various other info specific to TLS.
+ This needs to run before dynamic symbols are processed in
+ bfd_elf_size_dynamic_sections. */
-asection *
+bfd_boolean
ppc64_elf_tls_setup (struct bfd_link_info *info)
{
struct ppc_link_hash_table *htab;
@@ -7702,7 +7711,7 @@ ppc64_elf_tls_setup (struct bfd_link_inf
htab = ppc_hash_table (info);
if (htab == NULL)
- return NULL;
+ return FALSE;
if (abiversion (info->output_bfd) == 1)
htab->opd_abi = 1;
@@ -7728,6 +7737,19 @@ ppc64_elf_tls_setup (struct bfd_link_inf
--plt-localentry can cause trouble. */
if (htab->params->plt_localentry0 < 0)
htab->params->plt_localentry0 = 0;
+ if (htab->params->plt_localentry0 && htab->has_power10_relocs)
+ {
+ /* The issue is that __glink_PLTresolve saves r2, which is done
+ because glibc ld.so _dl_runtime_resolve restores r2 to support
+ a glibc plt call optimisation where global entry code is
+ skipped on calls that resolve to the same binary. The
+ __glink_PLTresolve save of r2 is incompatible with code
+ making tail calls, because the tail call might go via the
+ resolver and thus overwrite the proper saved r2. */
+ _bfd_error_handler (_("warning: --plt-localentry is incompatible with "
+ "power10 pc-relative code"));
+ htab->params->plt_localentry0 = 0;
+ }
if (htab->params->plt_localentry0
&& elf_link_hash_lookup (&htab->elf, "GLIBC_2.26",
FALSE, FALSE, FALSE) == NULL)
@@ -7824,7 +7846,7 @@ ppc64_elf_tls_setup (struct bfd_link_inf
_bfd_elf_strtab_delref (elf_hash_table (info)->dynstr,
opt_fd->dynstr_index);
if (!bfd_elf_link_record_dynamic_symbol (info, opt_fd))
- return NULL;
+ return FALSE;
}
if (tga_fd != NULL)
{
@@ -7883,7 +7905,7 @@ ppc64_elf_tls_setup (struct bfd_link_inf
&& htab->params->no_tls_get_addr_regsave == -1)
htab->params->no_tls_get_addr_regsave = 0;
- return _bfd_elf_tls_setup (info->output_bfd, info);
+ return TRUE;
}
/* Return TRUE iff REL is a branch reloc with a global symbol matching
@@ -10832,62 +10854,60 @@ eh_advance_size (unsigned int delta)
static inline unsigned int
plt_stub_size (struct ppc_link_hash_table *htab,
struct ppc_stub_hash_entry *stub_entry,
- bfd_vma off)
+ bfd_vma off,
+ unsigned int odd)
{
unsigned size;
if (stub_entry->stub_type >= ppc_stub_plt_call_notoc)
{
if (htab->params->power10_stubs != 0)
- {
- bfd_vma start = (stub_entry->stub_offset
- + stub_entry->group->stub_sec->output_offset
- + stub_entry->group->stub_sec->output_section->vma);
- if (stub_entry->stub_type > ppc_stub_plt_call_notoc)
- start += 4;
- size = 8 + size_power10_offset (off, start & 4);
- }
+ size = 8 + size_power10_offset (off, odd);
else
size = 8 + size_offset (off - 8);
if (stub_entry->stub_type > ppc_stub_plt_call_notoc)
size += 4;
- return size;
}
-
- size = 12;
- if (ALWAYS_EMIT_R2SAVE
- || stub_entry->stub_type == ppc_stub_plt_call_r2save)
- size += 4;
- if (PPC_HA (off) != 0)
- size += 4;
- if (htab->opd_abi)
+ else
{
- size += 4;
- if (htab->params->plt_static_chain)
+ size = 12;
+ if (ALWAYS_EMIT_R2SAVE
+ || stub_entry->stub_type == ppc_stub_plt_call_r2save)
size += 4;
- if (htab->params->plt_thread_safe
- && htab->elf.dynamic_sections_created
- && stub_entry->h != NULL
- && stub_entry->h->elf.dynindx != -1)
- size += 8;
- if (PPC_HA (off + 8 + 8 * htab->params->plt_static_chain) != PPC_HA (off))
+ if (PPC_HA (off) != 0)
size += 4;
+ if (htab->opd_abi)
+ {
+ size += 4;
+ if (htab->params->plt_static_chain)
+ size += 4;
+ if (htab->params->plt_thread_safe
+ && htab->elf.dynamic_sections_created
+ && stub_entry->h != NULL
+ && stub_entry->h->elf.dynindx != -1)
+ size += 8;
+ if (PPC_HA (off + 8 + 8 * htab->params->plt_static_chain)
+ != PPC_HA (off))
+ size += 4;
+ }
}
if (stub_entry->h != NULL
&& is_tls_get_addr (&stub_entry->h->elf, htab)
&& htab->params->tls_get_addr_opt)
{
- if (htab->params->no_tls_get_addr_regsave)
+ if (!htab->params->no_tls_get_addr_regsave)
{
- size += 7 * 4;
- if (stub_entry->stub_type == ppc_stub_plt_call_r2save)
- size += 6 * 4;
+ size += 30 * 4;
+ if (stub_entry->stub_type == ppc_stub_plt_call_r2save
+ || stub_entry->stub_type == ppc_stub_plt_call_both)
+ size += 4;
}
else
{
- size += 30 * 4;
- if (stub_entry->stub_type == ppc_stub_plt_call_r2save)
- size += 4;
+ size += 7 * 4;
+ if (stub_entry->stub_type == ppc_stub_plt_call_r2save
+ || stub_entry->stub_type == ppc_stub_plt_call_both)
+ size += 6 * 4;
}
}
return size;
@@ -10902,7 +10922,8 @@ plt_stub_size (struct ppc_link_hash_tabl
static inline unsigned int
plt_stub_pad (struct ppc_link_hash_table *htab,
struct ppc_stub_hash_entry *stub_entry,
- bfd_vma plt_off)
+ bfd_vma plt_off,
+ unsigned int odd)
{
int stub_align;
unsigned stub_size;
@@ -10917,7 +10938,7 @@ plt_stub_pad (struct ppc_link_hash_table
}
stub_align = 1 << -htab->params->plt_stub_align;
- stub_size = plt_stub_size (htab, stub_entry, plt_off);
+ stub_size = plt_stub_size (htab, stub_entry, plt_off, odd);
if (((stub_off + stub_size - 1) & -stub_align) - (stub_off & -stub_align)
> ((stub_size - 1) & -stub_align))
return stub_align - (stub_off & (stub_align - 1));
@@ -11112,14 +11133,12 @@ build_plt_stub (struct ppc_link_hash_tab
#define MR_R3_R0 0x7c030378
#define BCTRL 0x4e800421
-static inline bfd_byte *
-build_tls_get_addr_stub (struct ppc_link_hash_table *htab,
+static bfd_byte *
+build_tls_get_addr_head (struct ppc_link_hash_table *htab,
struct ppc_stub_hash_entry *stub_entry,
- bfd_byte *p, bfd_vma offset, Elf_Internal_Rela *r)
+ bfd_byte *p)
{
bfd *obfd = htab->params->stub_bfd;
- bfd_byte *loc = p;
- unsigned int i;
bfd_put_32 (obfd, LD_R0_0R3 + 0, p), p += 4;
bfd_put_32 (obfd, LD_R12_0R3 + 8, p), p += 4;
@@ -11128,21 +11147,43 @@ build_tls_get_addr_stub (struct ppc_link
bfd_put_32 (obfd, ADD_R3_R12_R13, p), p += 4;
bfd_put_32 (obfd, BEQLR, p), p += 4;
bfd_put_32 (obfd, MR_R3_R0, p), p += 4;
- if (htab->params->no_tls_get_addr_regsave)
- {
- if (r != NULL)
- r[0].r_offset += 7 * 4;
- if (stub_entry->stub_type != ppc_stub_plt_call_r2save)
- return build_plt_stub (htab, stub_entry, p, offset, r);
+ if (!htab->params->no_tls_get_addr_regsave)
+ p = tls_get_addr_prologue (obfd, p, htab);
+ else if (stub_entry->stub_type == ppc_stub_plt_call_r2save
+ || stub_entry->stub_type == ppc_stub_plt_call_both)
+ {
bfd_put_32 (obfd, MFLR_R0, p);
p += 4;
bfd_put_32 (obfd, STD_R0_0R1 + STK_LINKER (htab), p);
p += 4;
+ }
+ return p;
+}
- if (r != NULL)
- r[0].r_offset += 2 * 4;
- p = build_plt_stub (htab, stub_entry, p, offset, r);
+static bfd_byte *
+build_tls_get_addr_tail (struct ppc_link_hash_table *htab,
+ struct ppc_stub_hash_entry *stub_entry,
+ bfd_byte *p,
+ bfd_byte *loc)
+{
+ bfd *obfd = htab->params->stub_bfd;
+
+ if (!htab->params->no_tls_get_addr_regsave)
+ {
+ bfd_put_32 (obfd, BCTRL, p - 4);
+
+ if (stub_entry->stub_type == ppc_stub_plt_call_r2save
+ || stub_entry->stub_type == ppc_stub_plt_call_both)
+ {
+ bfd_put_32 (obfd, LD_R2_0R1 + STK_TOC (htab), p);
+ p += 4;
+ }
+ p = tls_get_addr_epilogue (obfd, p, htab);
+ }
+ else if (stub_entry->stub_type == ppc_stub_plt_call_r2save
+ || stub_entry->stub_type == ppc_stub_plt_call_both)
+ {
bfd_put_32 (obfd, BCTRL, p - 4);
bfd_put_32 (obfd, LD_R2_0R1 + STK_TOC (htab), p);
@@ -11154,24 +11195,6 @@ build_tls_get_addr_stub (struct ppc_link
bfd_put_32 (obfd, BLR, p);
p += 4;
}
- else
- {
- p = tls_get_addr_prologue (obfd, p, htab);
-
- if (r != NULL)
- r[0].r_offset += 18 * 4;
-
- p = build_plt_stub (htab, stub_entry, p, offset, r);
- bfd_put_32 (obfd, BCTRL, p - 4);
-
- if (stub_entry->stub_type == ppc_stub_plt_call_r2save)
- {
- bfd_put_32 (obfd, LD_R2_0R1 + STK_TOC (htab), p);
- p += 4;
- }
-
- p = tls_get_addr_epilogue (obfd, p, htab);
- }
if (htab->glink_eh_frame != NULL
&& htab->glink_eh_frame->size != 0)
@@ -11180,21 +11203,11 @@ build_tls_get_addr_stub (struct ppc_link
base = htab->glink_eh_frame->contents + stub_entry->group->eh_base + 17;
eh = base + stub_entry->group->eh_size;
- if (htab->params->no_tls_get_addr_regsave)
- {
- unsigned int lr_used, delta;
- lr_used = stub_entry->stub_offset + (p - 20 - loc);
- delta = lr_used - stub_entry->group->lr_restore;
- stub_entry->group->lr_restore = lr_used + 16;
- eh = eh_advance (htab->elf.dynobj, eh, delta);
- *eh++ = DW_CFA_offset_extended_sf;
- *eh++ = 65;
- *eh++ = -(STK_LINKER (htab) / 8) & 0x7f;
- *eh++ = DW_CFA_advance_loc + 4;
- }
- else
+
+ if (!htab->params->no_tls_get_addr_regsave)
{
- unsigned int cfa_updt, delta;
+ unsigned int cfa_updt, delta, i;
+
/* After the bctrl, lr has been modified so we need to emit
.eh_frame info saying the return address is on the stack. In
fact we must put the EH info at or before the call rather
@@ -11233,10 +11246,27 @@ build_tls_get_addr_stub (struct ppc_link
for (i = 4; i < 12; i++)
*eh++ = DW_CFA_restore + i;
*eh++ = DW_CFA_advance_loc + 2;
+ *eh++ = DW_CFA_restore_extended;
+ *eh++ = 65;
+ stub_entry->group->eh_size = eh - base;
+ }
+ else if (stub_entry->stub_type == ppc_stub_plt_call_r2save
+ || stub_entry->stub_type == ppc_stub_plt_call_both)
+ {
+ unsigned int lr_used, delta;
+
+ lr_used = stub_entry->stub_offset + (p - 20 - loc);
+ delta = lr_used - stub_entry->group->lr_restore;
+ stub_entry->group->lr_restore = lr_used + 16;
+ eh = eh_advance (htab->elf.dynobj, eh, delta);
+ *eh++ = DW_CFA_offset_extended_sf;
+ *eh++ = 65;
+ *eh++ = -(STK_LINKER (htab) / 8) & 0x7f;
+ *eh++ = DW_CFA_advance_loc + 4;
+ *eh++ = DW_CFA_restore_extended;
+ *eh++ = 65;
+ stub_entry->group->eh_size = eh - base;
}
- *eh++ = DW_CFA_restore_extended;
- *eh++ = 65;
- stub_entry->group->eh_size = eh - base;
}
return p;
}
@@ -11370,6 +11400,7 @@ ppc_build_one_stub (struct bfd_hash_entr
struct ppc_branch_hash_entry *br_entry;
struct bfd_link_info *info;
struct ppc_link_hash_table *htab;
+ bfd *obfd;
bfd_byte *loc;
bfd_byte *p, *relp;
bfd_vma targ, off;
@@ -11377,6 +11408,7 @@ ppc_build_one_stub (struct bfd_hash_entr
asection *plt;
int num_rel;
int odd;
+ bfd_boolean is_tga;
/* Massage our args to the form they really have. */
stub_entry = (struct ppc_stub_hash_entry *) gen_entry;
@@ -11426,6 +11458,7 @@ ppc_build_one_stub (struct bfd_hash_entr
off = targ - off;
p = loc;
+ obfd = htab->params->stub_bfd;
if (stub_entry->stub_type == ppc_stub_long_branch_r2off)
{
bfd_vma r2off = get_r2off (info, stub_entry);
@@ -11435,23 +11468,21 @@ ppc_build_one_stub (struct bfd_hash_entr
htab->stub_error = TRUE;
return FALSE;
}
- bfd_put_32 (htab->params->stub_bfd, STD_R2_0R1 + STK_TOC (htab), p);
+ bfd_put_32 (obfd, STD_R2_0R1 + STK_TOC (htab), p);
p += 4;
if (PPC_HA (r2off) != 0)
{
- bfd_put_32 (htab->params->stub_bfd,
- ADDIS_R2_R2 | PPC_HA (r2off), p);
+ bfd_put_32 (obfd, ADDIS_R2_R2 | PPC_HA (r2off), p);
p += 4;
}
if (PPC_LO (r2off) != 0)
{
- bfd_put_32 (htab->params->stub_bfd,
- ADDI_R2_R2 | PPC_LO (r2off), p);
+ bfd_put_32 (obfd, ADDI_R2_R2 | PPC_LO (r2off), p);
p += 4;
}
off -= p - loc;
}
- bfd_put_32 (htab->params->stub_bfd, B_DOT | (off & 0x3fffffc), p);
+ bfd_put_32 (obfd, B_DOT | (off & 0x3fffffc), p);
p += 4;
if (off + (1 << 25) >= (bfd_vma) (1 << 26))
@@ -11577,19 +11608,17 @@ ppc_build_one_stub (struct bfd_hash_entr
}
p = loc;
+ obfd = htab->params->stub_bfd;
if (stub_entry->stub_type != ppc_stub_plt_branch_r2off)
{
if (PPC_HA (off) != 0)
{
- bfd_put_32 (htab->params->stub_bfd,
- ADDIS_R12_R2 | PPC_HA (off), p);
+ bfd_put_32 (obfd, ADDIS_R12_R2 | PPC_HA (off), p);
p += 4;
- bfd_put_32 (htab->params->stub_bfd,
- LD_R12_0R12 | PPC_LO (off), p);
+ bfd_put_32 (obfd, LD_R12_0R12 | PPC_LO (off), p);
}
else
- bfd_put_32 (htab->params->stub_bfd,
- LD_R12_0R2 | PPC_LO (off), p);
+ bfd_put_32 (obfd, LD_R12_0R2 | PPC_LO (off), p);
}
else
{
@@ -11601,36 +11630,32 @@ ppc_build_one_stub (struct bfd_hash_entr
return FALSE;
}
- bfd_put_32 (htab->params->stub_bfd, STD_R2_0R1 + STK_TOC (htab), p);
+ bfd_put_32 (obfd, STD_R2_0R1 + STK_TOC (htab), p);
p += 4;
if (PPC_HA (off) != 0)
{
- bfd_put_32 (htab->params->stub_bfd,
- ADDIS_R12_R2 | PPC_HA (off), p);
+ bfd_put_32 (obfd, ADDIS_R12_R2 | PPC_HA (off), p);
p += 4;
- bfd_put_32 (htab->params->stub_bfd,
- LD_R12_0R12 | PPC_LO (off), p);
+ bfd_put_32 (obfd, LD_R12_0R12 | PPC_LO (off), p);
}
else
- bfd_put_32 (htab->params->stub_bfd, LD_R12_0R2 | PPC_LO (off), p);
+ bfd_put_32 (obfd, LD_R12_0R2 | PPC_LO (off), p);
if (PPC_HA (r2off) != 0)
{
p += 4;
- bfd_put_32 (htab->params->stub_bfd,
- ADDIS_R2_R2 | PPC_HA (r2off), p);
+ bfd_put_32 (obfd, ADDIS_R2_R2 | PPC_HA (r2off), p);
}
if (PPC_LO (r2off) != 0)
{
p += 4;
- bfd_put_32 (htab->params->stub_bfd,
- ADDI_R2_R2 | PPC_LO (r2off), p);
+ bfd_put_32 (obfd, ADDI_R2_R2 | PPC_LO (r2off), p);
}
}
p += 4;
- bfd_put_32 (htab->params->stub_bfd, MTCTR_R12, p);
+ bfd_put_32 (obfd, MTCTR_R12, p);
p += 4;
- bfd_put_32 (htab->params->stub_bfd, BCTR, p);
+ bfd_put_32 (obfd, BCTR, p);
p += 4;
break;
@@ -11644,12 +11669,23 @@ ppc_build_one_stub (struct bfd_hash_entr
off = (stub_entry->stub_offset
+ stub_entry->group->stub_sec->output_offset
+ stub_entry->group->stub_sec->output_section->vma);
+ obfd = htab->params->stub_bfd;
+ is_tga = ((stub_entry->stub_type == ppc_stub_plt_call_notoc
+ || stub_entry->stub_type == ppc_stub_plt_call_both)
+ && stub_entry->h != NULL
+ && is_tls_get_addr (&stub_entry->h->elf, htab)
+ && htab->params->tls_get_addr_opt);
+ if (is_tga)
+ {
+ p = build_tls_get_addr_head (htab, stub_entry, p);
+ off += p - loc;
+ }
if (stub_entry->stub_type == ppc_stub_long_branch_both
|| stub_entry->stub_type == ppc_stub_plt_branch_both
|| stub_entry->stub_type == ppc_stub_plt_call_both)
{
off += 4;
- bfd_put_32 (htab->params->stub_bfd, STD_R2_0R1 + STK_TOC (htab), p);
+ bfd_put_32 (obfd, STD_R2_0R1 + STK_TOC (htab), p);
p += 4;
}
if (stub_entry->stub_type >= ppc_stub_plt_call_notoc)
@@ -11682,17 +11718,39 @@ ppc_build_one_stub (struct bfd_hash_entr
if (htab->params->power10_stubs != 0)
{
bfd_boolean load = stub_entry->stub_type >= ppc_stub_plt_call_notoc;
- p = build_power10_offset (htab->params->stub_bfd, p, off, odd, load);
+ p = build_power10_offset (obfd, p, off, odd, load);
}
else
{
+ if (htab->glink_eh_frame != NULL
+ && htab->glink_eh_frame->size != 0)
+ {
+ bfd_byte *base, *eh;
+ unsigned int lr_used, delta;
+
+ base = (htab->glink_eh_frame->contents
+ + stub_entry->group->eh_base + 17);
+ eh = base + stub_entry->group->eh_size;
+ lr_used = stub_entry->stub_offset + (p - loc) + 8;
+ delta = lr_used - stub_entry->group->lr_restore;
+ stub_entry->group->lr_restore = lr_used + 8;
+ eh = eh_advance (htab->elf.dynobj, eh, delta);
+ *eh++ = DW_CFA_register;
+ *eh++ = 65;
+ *eh++ = 12;
+ *eh++ = DW_CFA_advance_loc + 2;
+ *eh++ = DW_CFA_restore_extended;
+ *eh++ = 65;
+ stub_entry->group->eh_size = eh - base;
+ }
+
/* The notoc stubs calculate their target (either a PLT entry or
the global entry point of a function) relative to the PC
returned by the "bcl" two instructions past the start of the
sequence emitted by build_offset. The offset is therefore 8
less than calculated from the start of the sequence. */
off -= 8;
- p = build_offset (htab->params->stub_bfd, p, off,
+ p = build_offset (obfd, p, off,
stub_entry->stub_type >= ppc_stub_plt_call_notoc);
}
@@ -11704,17 +11762,19 @@ ppc_build_one_stub (struct bfd_hash_entr
+ stub_entry->group->stub_sec->output_offset
+ stub_entry->group->stub_sec->output_section->vma
+ (p - loc));
- bfd_put_32 (htab->params->stub_bfd,
- B_DOT | ((targ - from) & 0x3fffffc), p);
+ bfd_put_32 (obfd, B_DOT | ((targ - from) & 0x3fffffc), p);
}
else
{
- bfd_put_32 (htab->params->stub_bfd, MTCTR_R12, p);
+ bfd_put_32 (obfd, MTCTR_R12, p);
p += 4;
- bfd_put_32 (htab->params->stub_bfd, BCTR, p);
+ bfd_put_32 (obfd, BCTR, p);
}
p += 4;
+ if (is_tga)
+ p = build_tls_get_addr_tail (htab, stub_entry, p, loc);
+
if (info->emitrelocations)
{
bfd_vma roff = relp - stub_entry->group->stub_sec->contents;
@@ -11745,33 +11805,6 @@ ppc_build_one_stub (struct bfd_hash_entr
return FALSE;
}
}
-
- if (htab->params->power10_stubs == 0
- && htab->glink_eh_frame != NULL
- && htab->glink_eh_frame->size != 0)
- {
- bfd_byte *base, *eh;
- unsigned int lr_used, delta;
-
- base = (htab->glink_eh_frame->contents
- + stub_entry->group->eh_base + 17);
- eh = base + stub_entry->group->eh_size;
- lr_used = stub_entry->stub_offset + 8;
- if (stub_entry->stub_type == ppc_stub_long_branch_both
- || stub_entry->stub_type == ppc_stub_plt_branch_both
- || stub_entry->stub_type == ppc_stub_plt_call_both)
- lr_used += 4;
- delta = lr_used - stub_entry->group->lr_restore;
- stub_entry->group->lr_restore = lr_used + 8;
- eh = eh_advance (htab->elf.dynobj, eh, delta);
- *eh++ = DW_CFA_register;
- *eh++ = 65;
- *eh++ = 12;
- *eh++ = DW_CFA_advance_loc + 2;
- *eh++ = DW_CFA_restore_extended;
- *eh++ = 65;
- stub_entry->group->eh_size = eh - base;
- }
break;
case ppc_stub_plt_call:
@@ -11840,12 +11873,20 @@ ppc_build_one_stub (struct bfd_hash_entr
r[0].r_offset += 2;
r[0].r_addend = targ;
}
- if (stub_entry->h != NULL
- && is_tls_get_addr (&stub_entry->h->elf, htab)
- && htab->params->tls_get_addr_opt)
- p = build_tls_get_addr_stub (htab, stub_entry, loc, off, r);
- else
- p = build_plt_stub (htab, stub_entry, loc, off, r);
+ p = loc;
+ obfd = htab->params->stub_bfd;
+ is_tga = (stub_entry->h != NULL
+ && is_tls_get_addr (&stub_entry->h->elf, htab)
+ && htab->params->tls_get_addr_opt);
+ if (is_tga)
+ {
+ p = build_tls_get_addr_head (htab, stub_entry, p);
+ if (r != NULL)
+ r[0].r_offset += p - loc;
+ }
+ p = build_plt_stub (htab, stub_entry, p, off, r);
+ if (is_tga)
+ p = build_tls_get_addr_tail (htab, stub_entry, p, loc);
break;
case ppc_stub_save_res:
@@ -12141,11 +12182,19 @@ ppc_size_one_stub (struct bfd_hash_entry
case ppc_stub_plt_call_notoc:
case ppc_stub_plt_call_both:
- off = (stub_entry->stub_offset
- + stub_entry->group->stub_sec->output_offset
- + stub_entry->group->stub_sec->output_section->vma);
+ lr_used = 0;
+ if (stub_entry->h != NULL
+ && is_tls_get_addr (&stub_entry->h->elf, htab)
+ && htab->params->tls_get_addr_opt)
+ {
+ lr_used += 7 * 4;
+ if (!htab->params->no_tls_get_addr_regsave)
+ lr_used += 11 * 4;
+ else if (stub_entry->stub_type == ppc_stub_plt_call_both)
+ lr_used += 2 * 4;
+ }
if (stub_entry->stub_type == ppc_stub_plt_call_both)
- off += 4;
+ lr_used += 4;
targ = stub_entry->plt_ent->plt.offset & ~1;
if (targ >= (bfd_vma) -2)
abort ();
@@ -12161,16 +12210,21 @@ ppc_size_one_stub (struct bfd_hash_entry
plt = htab->pltlocal;
}
targ += plt->output_offset + plt->output_section->vma;
+ off = (stub_entry->stub_offset
+ + stub_entry->group->stub_sec->output_offset
+ + stub_entry->group->stub_sec->output_section->vma
+ + lr_used);
odd = off & 4;
off = targ - off;
if (htab->params->plt_stub_align != 0)
{
- unsigned pad = plt_stub_pad (htab, stub_entry, off);
+ unsigned pad = plt_stub_pad (htab, stub_entry, off, odd);
stub_entry->group->stub_sec->size += pad;
stub_entry->stub_offset = stub_entry->group->stub_sec->size;
off -= pad;
+ odd ^= pad & 4;
}
if (info->emitrelocations)
@@ -12184,15 +12238,13 @@ ppc_size_one_stub (struct bfd_hash_entry
stub_entry->group->stub_sec->flags |= SEC_RELOC;
}
- size = plt_stub_size (htab, stub_entry, off);
+ size = plt_stub_size (htab, stub_entry, off, odd);
if (htab->params->power10_stubs == 0)
{
/* After the bcl, lr has been modified so we need to emit
.eh_frame info saying the return address is in r12. */
- lr_used = stub_entry->stub_offset + 8;
- if (stub_entry->stub_type == ppc_stub_plt_call_both)
- lr_used += 4;
+ lr_used += stub_entry->stub_offset + 8;
/* The eh_frame info will consist of a DW_CFA_advance_loc or
variant, DW_CFA_register, 65, 12, DW_CFA_advance_loc+2,
DW_CFA_restore_extended 65. */
@@ -12200,6 +12252,30 @@ ppc_size_one_stub (struct bfd_hash_entry
stub_entry->group->eh_size += eh_advance_size (delta) + 6;
stub_entry->group->lr_restore = lr_used + 8;
}
+ if ((stub_entry->stub_type == ppc_stub_plt_call_notoc
+ || stub_entry->stub_type == ppc_stub_plt_call_both)
+ && stub_entry->h != NULL
+ && is_tls_get_addr (&stub_entry->h->elf, htab)
+ && htab->params->tls_get_addr_opt)
+ {
+ if (!htab->params->no_tls_get_addr_regsave)
+ {
+ unsigned int cfa_updt = stub_entry->stub_offset + 18 * 4;
+ delta = cfa_updt - stub_entry->group->lr_restore;
+ stub_entry->group->eh_size += eh_advance_size (delta);
+ stub_entry->group->eh_size += htab->opd_abi ? 36 : 35;
+ stub_entry->group->lr_restore
+ = stub_entry->stub_offset + size - 4;
+ }
+ else if (stub_entry->stub_type == ppc_stub_plt_call_both)
+ {
+ lr_used = stub_entry->stub_offset + size - 20;
+ delta = lr_used - stub_entry->group->lr_restore;
+ stub_entry->group->eh_size += eh_advance_size (delta) + 6;
+ stub_entry->group->lr_restore
+ = stub_entry->stub_offset + size - 4;
+ }
+ }
break;
case ppc_stub_plt_call:
@@ -12225,7 +12301,7 @@ ppc_size_one_stub (struct bfd_hash_entry
if (htab->params->plt_stub_align != 0)
{
- unsigned pad = plt_stub_pad (htab, stub_entry, off);
+ unsigned pad = plt_stub_pad (htab, stub_entry, off, 0);
stub_entry->group->stub_sec->size += pad;
stub_entry->stub_offset = stub_entry->group->stub_sec->size;
@@ -12242,14 +12318,22 @@ ppc_size_one_stub (struct bfd_hash_entry
stub_entry->group->stub_sec->flags |= SEC_RELOC;
}
- size = plt_stub_size (htab, stub_entry, off);
+ size = plt_stub_size (htab, stub_entry, off, 0);
if (stub_entry->h != NULL
&& is_tls_get_addr (&stub_entry->h->elf, htab)
&& htab->params->tls_get_addr_opt
&& stub_entry->stub_type == ppc_stub_plt_call_r2save)
{
- if (htab->params->no_tls_get_addr_regsave)
+ if (!htab->params->no_tls_get_addr_regsave)
+ {
+ /* Adjustments to r1 need to be described. */
+ unsigned int cfa_updt = stub_entry->stub_offset + 18 * 4;
+ delta = cfa_updt - stub_entry->group->lr_restore;
+ stub_entry->group->eh_size += eh_advance_size (delta);
+ stub_entry->group->eh_size += htab->opd_abi ? 36 : 35;
+ }
+ else
{
lr_used = stub_entry->stub_offset + size - 20;
/* The eh_frame info will consist of a DW_CFA_advance_loc
@@ -12258,15 +12342,7 @@ ppc_size_one_stub (struct bfd_hash_entry
delta = lr_used - stub_entry->group->lr_restore;
stub_entry->group->eh_size += eh_advance_size (delta) + 6;
}
- else
- {
- /* Adjustments to r1 need to be described. */
- unsigned int cfa_updt = stub_entry->stub_offset + 18 * 4;
- delta = cfa_updt - stub_entry->group->lr_restore;
- stub_entry->group->eh_size += eh_advance_size (delta);
- stub_entry->group->eh_size += htab->opd_abi ? 36 : 35;
- }
- stub_entry->group->lr_restore = size - 4;
+ stub_entry->group->lr_restore = stub_entry->stub_offset + size - 4;
}
break;
@@ -13812,11 +13888,11 @@ ppc64_elf_size_stubs (struct bfd_link_in
/* Augmentation. */
p += 1;
- *p++ = DW_CFA_advance_loc + 1;
+ *p++ = DW_CFA_advance_loc + (htab->has_plt_localentry0 ? 3 : 2);
*p++ = DW_CFA_register;
*p++ = 65;
*p++ = htab->opd_abi ? 12 : 0;
- *p++ = DW_CFA_advance_loc + (htab->opd_abi ? 5 : 7);
+ *p++ = DW_CFA_advance_loc + (htab->opd_abi ? 4 : 2);
*p++ = DW_CFA_restore_extended;
*p++ = 65;
p += ((24 + align - 1) & -align) - 24;
@@ -14412,23 +14488,60 @@ ppc64_elf_build_stubs (struct bfd_link_i
}
else
{
+ unsigned int insn;
+
+ /* 0:
+ . .quad plt0-1f # plt0 entry relative to 1:
+ #
+ # We get here with r12 initially @ a glink branch
+ # Load the address of _dl_runtime_resolve from plt0 and
+ # jump to it, with r0 set to the index of the PLT entry
+ # to be resolved and r11 the link map.
+ __glink_PLTresolve:
+ . std %r2,24(%r1) # optional
+ . mflr %r0
+ . bcl 20,31,1f
+ 1:
+ . mflr %r11
+ . mtlr %r0
+ . ld %r0,(0b-1b)(%r11)
+ . sub %r12,%r12,%r11
+ . add %r11,%r0,%r11
+ . addi %r0,%r12,1b-2f
+ . ld %r12,0(%r11)
+ . srdi %r0,%r0,2
+ . mtctr %r12
+ . ld %r11,8(%r11)
+ . bctr
+ 2:
+ . b __glink_PLTresolve
+ . ...
+ . b __glink_PLTresolve */
+
+ if (htab->has_plt_localentry0)
+ {
+ bfd_put_32 (htab->glink->owner, STD_R2_0R1 + 24, p);
+ p += 4;
+ }
bfd_put_32 (htab->glink->owner, MFLR_R0, p);
p += 4;
bfd_put_32 (htab->glink->owner, BCL_20_31, p);
p += 4;
bfd_put_32 (htab->glink->owner, MFLR_R11, p);
p += 4;
- bfd_put_32 (htab->glink->owner, STD_R2_0R1 + 24, p);
- p += 4;
- bfd_put_32 (htab->glink->owner, LD_R2_0R11 | (-16 & 0xfffc), p);
- p += 4;
bfd_put_32 (htab->glink->owner, MTLR_R0, p);
p += 4;
+ if (htab->has_plt_localentry0)
+ insn = LD_R0_0R11 | (-20 & 0xfffc);
+ else
+ insn = LD_R0_0R11 | (-16 & 0xfffc);
+ bfd_put_32 (htab->glink->owner, insn, p);
+ p += 4;
bfd_put_32 (htab->glink->owner, SUB_R12_R12_R11, p);
p += 4;
- bfd_put_32 (htab->glink->owner, ADD_R11_R2_R11, p);
+ bfd_put_32 (htab->glink->owner, ADD_R11_R0_R11, p);
p += 4;
- bfd_put_32 (htab->glink->owner, ADDI_R0_R12 | (-48 & 0xffff), p);
+ bfd_put_32 (htab->glink->owner, ADDI_R0_R12 | (-44 & 0xffff), p);
p += 4;
bfd_put_32 (htab->glink->owner, LD_R12_0R11, p);
p += 4;
@@ -15878,22 +15991,25 @@ ppc64_elf_relocate_section (bfd *output_
addend = 0;
reloc_dest = DEST_STUB;
- if (((stub_entry->stub_type == ppc_stub_plt_call
- && ALWAYS_EMIT_R2SAVE)
- || stub_entry->stub_type == ppc_stub_plt_call_r2save
- || stub_entry->stub_type == ppc_stub_plt_call_both)
- && !(h != NULL
- && is_tls_get_addr (&h->elf, htab)
- && htab->params->tls_get_addr_opt)
- && rel + 1 < relend
- && rel[1].r_offset == rel->r_offset + 4
- && ELF64_R_TYPE (rel[1].r_info) == R_PPC64_TOCSAVE)
- relocation += 4;
- else if ((stub_entry->stub_type == ppc_stub_long_branch_both
- || stub_entry->stub_type == ppc_stub_plt_branch_both
- || stub_entry->stub_type == ppc_stub_plt_call_both)
- && r_type == R_PPC64_REL24_NOTOC)
- relocation += 4;
+ if ((((stub_entry->stub_type == ppc_stub_plt_call
+ && ALWAYS_EMIT_R2SAVE)
+ || stub_entry->stub_type == ppc_stub_plt_call_r2save
+ || stub_entry->stub_type == ppc_stub_plt_call_both)
+ && rel + 1 < relend
+ && rel[1].r_offset == rel->r_offset + 4
+ && ELF64_R_TYPE (rel[1].r_info) == R_PPC64_TOCSAVE)
+ || ((stub_entry->stub_type == ppc_stub_long_branch_both
+ || stub_entry->stub_type == ppc_stub_plt_branch_both
+ || stub_entry->stub_type == ppc_stub_plt_call_both)
+ && r_type == R_PPC64_REL24_NOTOC))
+ {
+ /* Skip over the r2 store at the start of the stub. */
+ if (!(stub_entry->stub_type >= ppc_stub_plt_call
+ && htab->params->tls_get_addr_opt
+ && h != NULL
+ && is_tls_get_addr (&h->elf, htab)))
+ relocation += 4;
+ }
if (r_type == R_PPC64_REL24_NOTOC
&& (stub_entry->stub_type == ppc_stub_plt_call_notoc
@@ -15942,7 +16058,8 @@ ppc64_elf_relocate_section (bfd *output_
break;
case R_PPC64_GOT16_DS:
- if ((h ? h->elf.type : ELF_ST_TYPE (sym->st_info)) == STT_GNU_IFUNC)
+ if ((h ? h->elf.type : ELF_ST_TYPE (sym->st_info)) == STT_GNU_IFUNC
+ || !htab->do_toc_opt)
break;
from = TOCstart + htab->sec_info[input_section->id].toc_off;
if (relocation + addend - from + 0x8000 < 0x10000
@@ -15961,7 +16078,8 @@ ppc64_elf_relocate_section (bfd *output_
case R_PPC64_GOT16_LO_DS:
case R_PPC64_GOT16_HA:
- if ((h ? h->elf.type : ELF_ST_TYPE (sym->st_info)) == STT_GNU_IFUNC)
+ if ((h ? h->elf.type : ELF_ST_TYPE (sym->st_info)) == STT_GNU_IFUNC
+ || !htab->do_toc_opt)
break;
from = TOCstart + htab->sec_info[input_section->id].toc_off;
if (relocation + addend - from + 0x80008000ULL < 0x100000000ULL
@@ -15984,34 +16102,38 @@ ppc64_elf_relocate_section (bfd *output_
break;
case R_PPC64_GOT_PCREL34:
- if ((h ? h->elf.type : ELF_ST_TYPE (sym->st_info)) == STT_GNU_IFUNC)
+ if ((h ? h->elf.type : ELF_ST_TYPE (sym->st_info)) == STT_GNU_IFUNC
+ || !htab->do_toc_opt)
break;
from = (rel->r_offset
+ input_section->output_section->vma
+ input_section->output_offset);
- if (relocation - from + (1ULL << 33) < 1ULL << 34
- && SYMBOL_REFERENCES_LOCAL (info, &h->elf))
- {
- offset = rel->r_offset;
- pinsn = bfd_get_32 (input_bfd, contents + offset);
- pinsn <<= 32;
- pinsn |= bfd_get_32 (input_bfd, contents + offset + 4);
- if ((pinsn & ((-1ULL << 50) | (63ULL << 26)))
- == ((1ULL << 58) | (1ULL << 52) | (57ULL << 26) /* pld */))
- {
- /* Replace with paddi. */
- pinsn += (2ULL << 56) + (14ULL << 26) - (57ULL << 26);
- r_type = R_PPC64_PCREL34;
- rel->r_info = ELF64_R_INFO (r_symndx, r_type);
- bfd_put_32 (input_bfd, pinsn >> 32, contents + offset);
- bfd_put_32 (input_bfd, pinsn, contents + offset + 4);
- goto pcrelopt;
- }
- }
- break;
+ if (!(relocation - from + (1ULL << 33) < 1ULL << 34
+ && SYMBOL_REFERENCES_LOCAL (info, &h->elf)))
+ break;
+
+ offset = rel->r_offset;
+ pinsn = bfd_get_32 (input_bfd, contents + offset);
+ pinsn <<= 32;
+ pinsn |= bfd_get_32 (input_bfd, contents + offset + 4);
+ if ((pinsn & ((-1ULL << 50) | (63ULL << 26)))
+ != ((1ULL << 58) | (1ULL << 52) | (57ULL << 26) /* pld */))
+ break;
+
+ /* Replace with paddi. */
+ pinsn += (2ULL << 56) + (14ULL << 26) - (57ULL << 26);
+ r_type = R_PPC64_PCREL34;
+ rel->r_info = ELF64_R_INFO (r_symndx, r_type);
+ bfd_put_32 (input_bfd, pinsn >> 32, contents + offset);
+ bfd_put_32 (input_bfd, pinsn, contents + offset + 4);
+ /* Fall through. */
case R_PPC64_PCREL34:
- if (SYMBOL_REFERENCES_LOCAL (info, &h->elf))
+ if (!htab->params->no_pcrel_opt
+ && rel + 1 < relend
+ && rel[1].r_offset == rel->r_offset
+ && rel[1].r_info == ELF64_R_INFO (0, R_PPC64_PCREL_OPT)
+ && SYMBOL_REFERENCES_LOCAL (info, &h->elf))
{
offset = rel->r_offset;
pinsn = bfd_get_32 (input_bfd, contents + offset);
@@ -16021,43 +16143,37 @@ ppc64_elf_relocate_section (bfd *output_
== ((1ULL << 58) | (2ULL << 56) | (1ULL << 52)
| (14ULL << 26) /* paddi */))
{
- pcrelopt:
- if (rel + 1 < relend
- && rel[1].r_offset == offset
- && rel[1].r_info == ELF64_R_INFO (0, R_PPC64_PCREL_OPT))
- {
- bfd_vma off2 = rel[1].r_addend;
- if (off2 == 0)
- /* zero means next insn. */
- off2 = 8;
- off2 += offset;
- if (off2 + 4 <= input_section->size)
+ bfd_vma off2 = rel[1].r_addend;
+ if (off2 == 0)
+ /* zero means next insn. */
+ off2 = 8;
+ off2 += offset;
+ if (off2 + 4 <= input_section->size)
+ {
+ uint64_t pinsn2;
+ bfd_signed_vma addend_off;
+ pinsn2 = bfd_get_32 (input_bfd, contents + off2);
+ pinsn2 <<= 32;
+ if ((pinsn2 & (63ULL << 58)) == 1ULL << 58)
{
- uint64_t pinsn2;
- bfd_signed_vma addend_off;
- pinsn2 = bfd_get_32 (input_bfd, contents + off2);
- pinsn2 <<= 32;
+ if (off2 + 8 > input_section->size)
+ break;
+ pinsn2 |= bfd_get_32 (input_bfd,
+ contents + off2 + 4);
+ }
+ if (xlate_pcrel_opt (&pinsn, &pinsn2, &addend_off))
+ {
+ addend += addend_off;
+ rel->r_addend = addend;
+ bfd_put_32 (input_bfd, pinsn >> 32,
+ contents + offset);
+ bfd_put_32 (input_bfd, pinsn,
+ contents + offset + 4);
+ bfd_put_32 (input_bfd, pinsn2 >> 32,
+ contents + off2);
if ((pinsn2 & (63ULL << 58)) == 1ULL << 58)
- {
- if (off2 + 8 > input_section->size)
- break;
- pinsn2 |= bfd_get_32 (input_bfd,
- contents + off2 + 4);
- }
- if (xlate_pcrel_opt (&pinsn, &pinsn2, &addend_off))
- {
- addend += addend_off;
- rel->r_addend = addend;
- bfd_put_32 (input_bfd, pinsn >> 32,
- contents + offset);
- bfd_put_32 (input_bfd, pinsn,
- contents + offset + 4);
- bfd_put_32 (input_bfd, pinsn2 >> 32,
- contents + off2);
- if ((pinsn2 & (63ULL << 58)) == 1ULL << 58)
- bfd_put_32 (input_bfd, pinsn2,
- contents + off2 + 4);
- }
+ bfd_put_32 (input_bfd, pinsn2,
+ contents + off2 + 4);
}
}
}
diff -rup binutils.orig/bfd/elf64-ppc.h binutils-2.35.1/bfd/elf64-ppc.h
--- binutils.orig/bfd/elf64-ppc.h 2020-10-08 13:50:31.430909427 +0100
+++ binutils-2.35.1/bfd/elf64-ppc.h 2020-10-08 13:55:41.515954725 +0100
@@ -27,6 +27,7 @@ struct ppc64_elf_params
/* Linker call-backs. */
asection * (*add_stub_section) (const char *, asection *);
void (*layout_sections_again) (void);
+ void (*edit) (void);
/* Maximum size of a group of input sections that can be handled by
one stub section. A value of +/-1 indicates the bfd back-end
@@ -57,6 +58,9 @@ struct ppc64_elf_params
/* Whether to use power10 instructions in linkage stubs. */
int power10_stubs;
+ /* Whether R_PPC64_PCREL_OPT should be ignored. */
+ int no_pcrel_opt;
+
/* Whether to canonicalize .opd so that there are no overlapping
.opd entries. */
int non_overlapping_opd;
@@ -77,7 +81,7 @@ bfd_boolean ppc64_elf_edit_opd
(struct bfd_link_info *);
bfd_boolean ppc64_elf_inline_plt
(struct bfd_link_info *);
-asection *ppc64_elf_tls_setup
+bfd_boolean ppc64_elf_tls_setup
(struct bfd_link_info *);
bfd_boolean ppc64_elf_tls_optimize
(struct bfd_link_info *);
diff -rup binutils.orig/gas/config/tc-ppc.c binutils-2.35.1/gas/config/tc-ppc.c
--- binutils.orig/gas/config/tc-ppc.c 2020-10-08 13:50:31.069910539 +0100
+++ binutils-2.35.1/gas/config/tc-ppc.c 2020-10-08 13:51:29.102731857 +0100
@@ -3335,6 +3335,15 @@ md_assemble (char *str)
}
insn = opcode->opcode;
+ if (!target_big_endian
+ && ((insn & ~(1 << 26)) == 46u << 26
+ || (insn & ~(0xc0 << 1)) == (31u << 26 | 533 << 1)))
+ {
+ /* lmw, stmw, lswi, lswx, stswi, stswx */
+ as_bad (_("`%s' invalid when little-endian"), str);
+ ppc_clear_labels ();
+ return;
+ }
str = s;
while (ISSPACE (*str))
diff -rup binutils.orig/gas/testsuite/gas/ppc/476.d binutils-2.35.1/gas/testsuite/gas/ppc/476.d
--- binutils.orig/gas/testsuite/gas/ppc/476.d 2020-10-08 13:50:31.313909788 +0100
+++ binutils-2.35.1/gas/testsuite/gas/ppc/476.d 2020-10-08 13:51:29.102731857 +0100
@@ -7,491 +7,485 @@
Disassembly of section \.text:
0+00 <ppc476>:
- 0: (7c 64 2a 14|14 2a 64 7c) add r3,r4,r5
- 4: (7c 64 2a 15|15 2a 64 7c) add\. r3,r4,r5
- 8: (7c 64 28 14|14 28 64 7c) addc r3,r4,r5
- c: (7c 64 28 15|15 28 64 7c) addc\. r3,r4,r5
- 10: (7c 64 2c 14|14 2c 64 7c) addco r3,r4,r5
- 14: (7c 64 2c 15|15 2c 64 7c) addco\. r3,r4,r5
- 18: (7c 64 29 14|14 29 64 7c) adde r3,r4,r5
- 1c: (7c 64 29 15|15 29 64 7c) adde\. r3,r4,r5
- 20: (7c 64 2d 14|14 2d 64 7c) addeo r3,r4,r5
- 24: (7c 64 2d 15|15 2d 64 7c) addeo\. r3,r4,r5
- 28: (38 64 ff 80|80 ff 64 38) addi r3,r4,-128
- 2c: (30 64 ff 80|80 ff 64 30) addic r3,r4,-128
- 30: (34 64 ff 80|80 ff 64 34) addic\. r3,r4,-128
- 34: (3c 64 ff 80|80 ff 64 3c) addis r3,r4,-128
- 38: (7c 64 01 d4|d4 01 64 7c) addme r3,r4
- 3c: (7c 64 01 d5|d5 01 64 7c) addme\. r3,r4
- 40: (7c 64 05 d4|d4 05 64 7c) addmeo r3,r4
- 44: (7c 64 05 d5|d5 05 64 7c) addmeo\. r3,r4
- 48: (7c 64 2e 14|14 2e 64 7c) addo r3,r4,r5
- 4c: (7c 64 2e 15|15 2e 64 7c) addo\. r3,r4,r5
- 50: (7c 64 01 94|94 01 64 7c) addze r3,r4
- 54: (7c 64 01 95|95 01 64 7c) addze\. r3,r4
- 58: (7c 64 05 94|94 05 64 7c) addzeo r3,r4
- 5c: (7c 64 05 95|95 05 64 7c) addzeo\. r3,r4
- 60: (7c 83 28 38|38 28 83 7c) and r3,r4,r5
- 64: (7c 83 28 39|39 28 83 7c) and\. r3,r4,r5
- 68: (7d cd 78 78|78 78 cd 7d) andc r13,r14,r15
- 6c: (7e 30 90 79|79 90 30 7e) andc\. r16,r17,r18
- 70: (70 83 de ad|ad de 83 70) andi\. r3,r4,57005
- 74: (74 83 de ad|ad de 83 74) andis\. r3,r4,57005
- 78: (48 00 00 02|02 00 00 48) ba 0 <ppc476>
- 7c: (40 01 00 00|00 00 01 40) bdnzf gt,7c <ppc476\+0x7c>
- 80: (40 85 00 02|02 00 85 40) blea cr1,0 <ppc476>
- 84: (4d 80 04 20|20 04 80 4d) bltctr
- 88: (4c 8a 04 20|20 04 8a 4c) bnectr cr2
- 8c: (4c 86 04 20|20 04 86 4c) bnectr cr1
- 90: (4c 86 04 20|20 04 86 4c) bnectr cr1
- 94: (4d 80 04 21|21 04 80 4d) bltctrl
- 98: (4c 8a 04 21|21 04 8a 4c) bnectrl cr2
- 9c: (4c 86 04 21|21 04 86 4c) bnectrl cr1
- a0: (4c 86 04 21|21 04 86 4c) bnectrl cr1
- a4: (40 43 00 01|01 00 43 40) bdzfl so,a4 <ppc476\+0xa4>
- a8: (4d 80 00 20|20 00 80 4d) bltlr
- ac: (4c 8a 00 20|20 00 8a 4c) bnelr cr2
- b0: (4c 86 00 20|20 00 86 4c) bnelr cr1
- b4: (4c 86 00 20|20 00 86 4c) bnelr cr1
- b8: (4d 80 00 21|21 00 80 4d) bltlrl
- bc: (4c 8a 00 21|21 00 8a 4c) bnelrl cr2
- c0: (4c 86 00 21|21 00 86 4c) bnelrl cr1
- c4: (4c 86 00 21|21 00 86 4c) bnelrl cr1
- c8: (48 00 00 00|00 00 00 48) b c8 <ppc476\+0xc8>
- cc: (48 00 00 01|01 00 00 48) bl cc <ppc476\+0xcc>
- d0: (54 83 00 36|36 00 83 54) rlwinm r3,r4,0,0,27
- d4: (7c 03 20 00|00 20 03 7c) cmpw r3,r4
- d8: (7f 83 20 00|00 20 83 7f) cmpw cr7,r3,r4
- dc: (7c 83 2b f8|f8 2b 83 7c) cmpb r3,r4,r5
- e0: (7c 83 2b f8|f8 2b 83 7c) cmpb r3,r4,r5
- e4: (2c 03 ff 59|59 ff 03 2c) cmpwi r3,-167
- e8: (2f 83 ff 59|59 ff 83 2f) cmpwi cr7,r3,-167
- ec: (7c 03 20 40|40 20 03 7c) cmplw r3,r4
- f0: (7f 83 20 40|40 20 83 7f) cmplw cr7,r3,r4
- f4: (28 03 00 a7|a7 00 03 28) cmplwi r3,167
- f8: (2b 83 00 a7|a7 00 83 2b) cmplwi cr7,r3,167
- fc: (7c 03 20 40|40 20 03 7c) cmplw r3,r4
- 100: (28 03 00 a7|a7 00 03 28) cmplwi r3,167
- 104: (7c 03 20 00|00 20 03 7c) cmpw r3,r4
- 108: (2c 03 ff 59|59 ff 03 2c) cmpwi r3,-167
- 10c: (7d 6a 00 34|34 00 6a 7d) cntlzw r10,r11
- 110: (7d 6a 00 35|35 00 6a 7d) cntlzw\. r10,r11
- 114: (4c 85 32 02|02 32 85 4c) crand 4\*cr1\+lt,4\*cr1\+gt,4\*cr1\+eq
- 118: (4c 64 29 02|02 29 64 4c) crandc so,4\*cr1\+lt,4\*cr1\+gt
- 11c: (4c e0 0a 42|42 0a e0 4c) creqv 4\*cr1\+so,lt,gt
- 120: (4c 22 19 c2|c2 19 22 4c) crnand gt,eq,so
- 124: (4c 01 10 42|42 10 01 4c) crnor lt,gt,eq
- 128: (4c a6 3b 82|82 3b a6 4c) cror 4\*cr1\+gt,4\*cr1\+eq,4\*cr1\+so
- 12c: (4c 43 23 42|42 23 43 4c) crorc eq,so,4\*cr1\+lt
- 130: (4c c7 01 82|82 01 c7 4c) crxor 4\*cr1\+eq,4\*cr1\+so,lt
- 134: (7c 09 55 ec|ec 55 09 7c) dcba r9,r10
- 138: (7c 06 38 ac|ac 38 06 7c) dcbf r6,r7
- 13c: (7c 06 38 ac|ac 38 06 7c) dcbf r6,r7
- 140: (7c 06 3b ac|ac 3b 06 7c) dcbi r6,r7
- 144: (7c 85 33 0c|0c 33 85 7c) dcblc 4,r5,r6
- 148: (7c 06 38 6c|6c 38 06 7c) dcbst r6,r7
- 14c: (7c 05 32 2c|2c 32 05 7c) dcbt r5,r6
- 150: (7c 05 32 2c|2c 32 05 7c) dcbt r5,r6
- 154: (7d 05 32 2c|2c 32 05 7d) dcbt 8,r5,r6
- 158: (7c e8 49 4c|4c 49 e8 7c) dcbtls 7,r8,r9
- 15c: (7c 06 39 ec|ec 39 06 7c) dcbtst r6,r7
- 160: (7c 06 39 ec|ec 39 06 7c) dcbtst r6,r7
- 164: (7d 26 39 ec|ec 39 26 7d) dcbtst 9,r6,r7
- 168: (7d 4b 61 0c|0c 61 4b 7d) dcbtstls 10,r11,r12
- 16c: (7c 01 17 ec|ec 17 01 7c) dcbz r1,r2
- 170: (7c 05 37 ec|ec 37 05 7c) dcbz r5,r6
- 174: (7c 00 03 8c|8c 03 00 7c) dccci
- 178: (7c 00 03 8c|8c 03 00 7c) dccci
- 17c: (7c 00 03 8c|8c 03 00 7c) dccci
- 180: (7c 20 03 8c|8c 03 20 7c) dci 1
- 184: (7d 4b 63 d6|d6 63 4b 7d) divw r10,r11,r12
- 188: (7d 6c 6b d7|d7 6b 6c 7d) divw\. r11,r12,r13
- 18c: (7d 4b 67 d6|d6 67 4b 7d) divwo r10,r11,r12
- 190: (7d 6c 6f d7|d7 6f 6c 7d) divwo\. r11,r12,r13
- 194: (7d 4b 63 96|96 63 4b 7d) divwu r10,r11,r12
- 198: (7d 6c 6b 97|97 6b 6c 7d) divwu\. r11,r12,r13
- 19c: (7d 4b 67 96|96 67 4b 7d) divwuo r10,r11,r12
- 1a0: (7d 6c 6f 97|97 6f 6c 7d) divwuo\. r11,r12,r13
- 1a4: (7c 83 28 9c|9c 28 83 7c) dlmzb r3,r4,r5
- 1a8: (7c 83 28 9d|9d 28 83 7c) dlmzb\. r3,r4,r5
- 1ac: (7d 6a 62 38|38 62 6a 7d) eqv r10,r11,r12
- 1b0: (7d 6a 62 39|39 62 6a 7d) eqv\. r10,r11,r12
- 1b4: (54 83 20 26|26 20 83 54) rlwinm r3,r4,4,0,19
- 1b8: (7c 83 07 74|74 07 83 7c) extsb r3,r4
- 1bc: (7c 83 07 75|75 07 83 7c) extsb\. r3,r4
- 1c0: (7c 83 07 34|34 07 83 7c) extsh r3,r4
- 1c4: (7c 83 07 35|35 07 83 7c) extsh\. r3,r4
- 1c8: (fe a0 fa 10|10 fa a0 fe) fabs f21,f31
- 1cc: (fe a0 fa 11|11 fa a0 fe) fabs\. f21,f31
- 1d0: (fd 4b 60 2a|2a 60 4b fd) fadd f10,f11,f12
- 1d4: (fd 4b 60 2b|2b 60 4b fd) fadd\. f10,f11,f12
- 1d8: (ed 4b 60 2a|2a 60 4b ed) fadds f10,f11,f12
- 1dc: (ed 4b 60 2b|2b 60 4b ed) fadds\. f10,f11,f12
- 1e0: (fd 40 5e 9c|9c 5e 40 fd) fcfid f10,f11
- 1e4: (fd 40 5e 9d|9d 5e 40 fd) fcfid\. f10,f11
- 1e8: (fd 8a 58 40|40 58 8a fd) fcmpo cr3,f10,f11
- 1ec: (fd 84 28 00|00 28 84 fd) fcmpu cr3,f4,f5
- 1f0: (fd 4b 60 10|10 60 4b fd) fcpsgn f10,f11,f12
- 1f4: (fd 4b 60 11|11 60 4b fd) fcpsgn\. f10,f11,f12
- 1f8: (fd 40 5e 5c|5c 5e 40 fd) fctid f10,f11
- 1fc: (fd 40 5e 5d|5d 5e 40 fd) fctid\. f10,f11
- 200: (fd 40 5e 5e|5e 5e 40 fd) fctidz f10,f11
- 204: (fd 40 5e 5f|5f 5e 40 fd) fctidz\. f10,f11
- 208: (fd 40 58 1c|1c 58 40 fd) fctiw f10,f11
- 20c: (fd 40 58 1d|1d 58 40 fd) fctiw\. f10,f11
- 210: (fd 40 58 1e|1e 58 40 fd) fctiwz f10,f11
- 214: (fd 40 58 1f|1f 58 40 fd) fctiwz\. f10,f11
- 218: (fd 4b 60 24|24 60 4b fd) fdiv f10,f11,f12
- 21c: (fd 4b 60 25|25 60 4b fd) fdiv\. f10,f11,f12
- 220: (ed 4b 60 24|24 60 4b ed) fdivs f10,f11,f12
- 224: (ed 4b 60 25|25 60 4b ed) fdivs\. f10,f11,f12
- 228: (fd 4b 6b 3a|3a 6b 4b fd) fmadd f10,f11,f12,f13
- 22c: (fd 4b 6b 3b|3b 6b 4b fd) fmadd\. f10,f11,f12,f13
- 230: (ed 4b 6b 3a|3a 6b 4b ed) fmadds f10,f11,f12,f13
- 234: (ed 4b 6b 3b|3b 6b 4b ed) fmadds\. f10,f11,f12,f13
- 238: (fc 60 20 90|90 20 60 fc) fmr f3,f4
- 23c: (fc 60 20 91|91 20 60 fc) fmr\. f3,f4
- 240: (fd 4b 6b 38|38 6b 4b fd) fmsub f10,f11,f12,f13
- 244: (fd 4b 6b 39|39 6b 4b fd) fmsub\. f10,f11,f12,f13
- 248: (ed 4b 6b 38|38 6b 4b ed) fmsubs f10,f11,f12,f13
- 24c: (ed 4b 6b 39|39 6b 4b ed) fmsubs\. f10,f11,f12,f13
- 250: (fd 4b 03 32|32 03 4b fd) fmul f10,f11,f12
- 254: (fd 4b 03 33|33 03 4b fd) fmul\. f10,f11,f12
- 258: (ed 4b 03 32|32 03 4b ed) fmuls f10,f11,f12
- 25c: (ed 4b 03 33|33 03 4b ed) fmuls\. f10,f11,f12
- 260: (fe 80 f1 10|10 f1 80 fe) fnabs f20,f30
- 264: (fe 80 f1 11|11 f1 80 fe) fnabs\. f20,f30
- 268: (fc 60 20 50|50 20 60 fc) fneg f3,f4
- 26c: (fc 60 20 51|51 20 60 fc) fneg\. f3,f4
- 270: (fd 4b 6b 3e|3e 6b 4b fd) fnmadd f10,f11,f12,f13
- 274: (fd 4b 6b 3f|3f 6b 4b fd) fnmadd\. f10,f11,f12,f13
- 278: (ed 4b 6b 3e|3e 6b 4b ed) fnmadds f10,f11,f12,f13
- 27c: (ed 4b 6b 3f|3f 6b 4b ed) fnmadds\. f10,f11,f12,f13
- 280: (fd 4b 6b 3c|3c 6b 4b fd) fnmsub f10,f11,f12,f13
- 284: (fd 4b 6b 3d|3d 6b 4b fd) fnmsub\. f10,f11,f12,f13
- 288: (ed 4b 6b 3c|3c 6b 4b ed) fnmsubs f10,f11,f12,f13
- 28c: (ed 4b 6b 3d|3d 6b 4b ed) fnmsubs\. f10,f11,f12,f13
- 290: (fd c0 78 30|30 78 c0 fd) fre f14,f15
- 294: (fd c0 78 31|31 78 c0 fd) fre\. f14,f15
- 298: (ed c0 78 30|30 78 c0 ed) fres f14,f15
- 29c: (ed c0 78 31|31 78 c0 ed) fres\. f14,f15
- 2a0: (fd 40 5b d0|d0 5b 40 fd) frim f10,f11
- 2a4: (fd 40 5b d1|d1 5b 40 fd) frim\. f10,f11
- 2a8: (fd 40 5b 10|10 5b 40 fd) frin f10,f11
- 2ac: (fd 40 5b 11|11 5b 40 fd) frin\. f10,f11
- 2b0: (fd 40 5b 90|90 5b 40 fd) frip f10,f11
- 2b4: (fd 40 5b 91|91 5b 40 fd) frip\. f10,f11
- 2b8: (fd 40 5b 50|50 5b 40 fd) friz f10,f11
- 2bc: (fd 40 5b 51|51 5b 40 fd) friz\. f10,f11
- 2c0: (fc c0 38 18|18 38 c0 fc) frsp f6,f7
- 2c4: (fd 00 48 19|19 48 00 fd) frsp\. f8,f9
- 2c8: (fd c0 78 34|34 78 c0 fd) frsqrte f14,f15
- 2cc: (fd c0 78 35|35 78 c0 fd) frsqrte\. f14,f15
- 2d0: (ed c0 78 34|34 78 c0 ed) frsqrtes f14,f15
- 2d4: (ed c0 78 35|35 78 c0 ed) frsqrtes\. f14,f15
- 2d8: (fd 4b 6b 2e|2e 6b 4b fd) fsel f10,f11,f12,f13
- 2dc: (fd 4b 6b 2f|2f 6b 4b fd) fsel\. f10,f11,f12,f13
- 2e0: (fd 40 58 2c|2c 58 40 fd) fsqrt f10,f11
- 2e4: (fd 40 58 2d|2d 58 40 fd) fsqrt\. f10,f11
- 2e8: (ed 40 58 2c|2c 58 40 ed) fsqrts f10,f11
- 2ec: (ed 40 58 2d|2d 58 40 ed) fsqrts\. f10,f11
- 2f0: (fd 4b 60 28|28 60 4b fd) fsub f10,f11,f12
- 2f4: (fd 4b 60 29|29 60 4b fd) fsub\. f10,f11,f12
- 2f8: (ed 4b 60 28|28 60 4b ed) fsubs f10,f11,f12
- 2fc: (ed 4b 60 29|29 60 4b ed) fsubs\. f10,f11,f12
- 300: (7c 03 27 ac|ac 27 03 7c) icbi r3,r4
- 304: (7e 11 91 cc|cc 91 11 7e) icblc 16,r17,r18
- 308: (7c a8 48 2c|2c 48 a8 7c) icbt 5,r8,r9
- 30c: (7d ae 7b cc|cc 7b ae 7d) icbtls 13,r14,r15
- 310: (7c 00 07 8c|8c 07 00 7c) iccci
- 314: (7c 00 07 8c|8c 07 00 7c) iccci
- 318: (7c 00 07 8c|8c 07 00 7c) iccci
- 31c: (7c 20 07 8c|8c 07 20 7c) ici 1
- 320: (7c 03 27 cc|cc 27 03 7c) icread r3,r4
- 324: (50 83 65 36|36 65 83 50) rlwimi r3,r4,12,20,27
- 328: (7c 43 27 1e|1e 27 43 7c) isel r2,r3,r4,28
- 32c: (4c 00 01 2c|2c 01 00 4c) isync
- 330: (89 21 00 00|00 00 21 89) lbz r9,0\(r1\)
- 334: (8d 41 00 01|01 00 41 8d) lbzu r10,1\(r1\)
- 338: (7e 95 b0 ee|ee b0 95 7e) lbzux r20,r21,r22
- 33c: (7c 64 28 ae|ae 28 64 7c) lbzx r3,r4,r5
- 340: (ca a1 00 08|08 00 a1 ca) lfd f21,8\(r1\)
- 344: (ce c1 00 10|10 00 c1 ce) lfdu f22,16\(r1\)
- 348: (7e 95 b4 ee|ee b4 95 7e) lfdux f20,r21,r22
- 34c: (7d ae 7c ae|ae 7c ae 7d) lfdx f13,r14,r15
- 350: (7d 43 26 ae|ae 26 43 7d) lfiwax f10,r3,r4
- 354: (c2 61 00 00|00 00 61 c2) lfs f19,0\(r1\)
- 358: (c6 81 00 04|04 00 81 c6) lfsu f20,4\(r1\)
- 35c: (7d 4b 64 6e|6e 64 4b 7d) lfsux f10,r11,r12
- 360: (7d 4b 64 2e|2e 64 4b 7d) lfsx f10,r11,r12
- 364: (a9 e1 00 06|06 00 e1 a9) lha r15,6\(r1\)
- 368: (ae 01 00 08|08 00 01 ae) lhau r16,8\(r1\)
- 36c: (7d 2a 5a ee|ee 5a 2a 7d) lhaux r9,r10,r11
- 370: (7d 2a 5a ae|ae 5a 2a 7d) lhax r9,r10,r11
- 374: (7c 64 2e 2c|2c 2e 64 7c) lhbrx r3,r4,r5
- 378: (a1 a1 00 00|00 00 a1 a1) lhz r13,0\(r1\)
- 37c: (a5 c1 00 02|02 00 c1 a5) lhzu r14,2\(r1\)
- 380: (7e 96 c2 6e|6e c2 96 7e) lhzux r20,r22,r24
- 384: (7e f8 ca 2e|2e ca f8 7e) lhzx r23,r24,r25
- 388: (b8 61 ff f0|f0 ff 61 b8) lmw r3,-16\(r1\)
- 38c: (7c a4 84 aa|aa 84 a4 7c) lswi r5,r4,16
- 390: (7c 64 2c 2a|2a 2c 64 7c) lswx r3,r4,r5
- 394: (7c 64 28 28|28 28 64 7c) lwarx r3,r4,r5
- 398: (7c 64 28 28|28 28 64 7c) lwarx r3,r4,r5
- 39c: (7c 64 28 29|29 28 64 7c) lwarx r3,r4,r5,1
- 3a0: (7c 64 2c 2c|2c 2c 64 7c) lwbrx r3,r4,r5
- 3a4: (80 c7 00 00|00 00 c7 80) lwz r6,0\(r7\)
- 3a8: (84 61 00 10|10 00 61 84) lwzu r3,16\(r1\)
- 3ac: (7c 64 28 6e|6e 28 64 7c) lwzux r3,r4,r5
- 3b0: (7c 64 28 2e|2e 28 64 7c) lwzx r3,r4,r5
- 3b4: (10 64 29 58|58 29 64 10) macchw r3,r4,r5
- 3b8: (10 64 29 59|59 29 64 10) macchw\. r3,r4,r5
- 3bc: (10 64 2d 58|58 2d 64 10) macchwo r3,r4,r5
- 3c0: (10 64 2d 59|59 2d 64 10) macchwo\. r3,r4,r5
- 3c4: (10 64 29 d8|d8 29 64 10) macchws r3,r4,r5
- 3c8: (10 64 29 d9|d9 29 64 10) macchws\. r3,r4,r5
- 3cc: (10 64 2d d8|d8 2d 64 10) macchwso r3,r4,r5
- 3d0: (10 64 2d d9|d9 2d 64 10) macchwso\. r3,r4,r5
- 3d4: (10 64 29 98|98 29 64 10) macchwsu r3,r4,r5
- 3d8: (10 64 29 99|99 29 64 10) macchwsu\. r3,r4,r5
- 3dc: (10 64 2d 98|98 2d 64 10) macchwsuo r3,r4,r5
- 3e0: (10 64 2d 99|99 2d 64 10) macchwsuo\. r3,r4,r5
- 3e4: (10 64 29 18|18 29 64 10) macchwu r3,r4,r5
- 3e8: (10 64 29 19|19 29 64 10) macchwu\. r3,r4,r5
- 3ec: (10 64 2d 18|18 2d 64 10) macchwuo r3,r4,r5
- 3f0: (10 64 2d 19|19 2d 64 10) macchwuo\. r3,r4,r5
- 3f4: (10 64 28 58|58 28 64 10) machhw r3,r4,r5
- 3f8: (10 64 28 59|59 28 64 10) machhw\. r3,r4,r5
- 3fc: (10 64 2c 58|58 2c 64 10) machhwo r3,r4,r5
- 400: (10 64 2c 59|59 2c 64 10) machhwo\. r3,r4,r5
- 404: (10 64 28 d8|d8 28 64 10) machhws r3,r4,r5
- 408: (10 64 28 d9|d9 28 64 10) machhws\. r3,r4,r5
- 40c: (10 64 2c d8|d8 2c 64 10) machhwso r3,r4,r5
- 410: (10 64 2c d9|d9 2c 64 10) machhwso\. r3,r4,r5
- 414: (10 64 28 98|98 28 64 10) machhwsu r3,r4,r5
- 418: (10 64 28 99|99 28 64 10) machhwsu\. r3,r4,r5
- 41c: (10 64 2c 98|98 2c 64 10) machhwsuo r3,r4,r5
- 420: (10 64 2c 99|99 2c 64 10) machhwsuo\. r3,r4,r5
- 424: (10 64 28 18|18 28 64 10) machhwu r3,r4,r5
- 428: (10 64 28 19|19 28 64 10) machhwu\. r3,r4,r5
- 42c: (10 64 2c 18|18 2c 64 10) machhwuo r3,r4,r5
- 430: (10 64 2c 19|19 2c 64 10) machhwuo\. r3,r4,r5
- 434: (10 64 2b 58|58 2b 64 10) maclhw r3,r4,r5
- 438: (10 64 2b 59|59 2b 64 10) maclhw\. r3,r4,r5
- 43c: (10 64 2f 58|58 2f 64 10) maclhwo r3,r4,r5
- 440: (10 64 2f 59|59 2f 64 10) maclhwo\. r3,r4,r5
- 444: (10 64 2b d8|d8 2b 64 10) maclhws r3,r4,r5
- 448: (10 64 2b d9|d9 2b 64 10) maclhws\. r3,r4,r5
- 44c: (10 64 2f d8|d8 2f 64 10) maclhwso r3,r4,r5
- 450: (10 64 2f d9|d9 2f 64 10) maclhwso\. r3,r4,r5
- 454: (10 64 2b 98|98 2b 64 10) maclhwsu r3,r4,r5
- 458: (10 64 2b 99|99 2b 64 10) maclhwsu\. r3,r4,r5
- 45c: (10 64 2f 98|98 2f 64 10) maclhwsuo r3,r4,r5
- 460: (10 64 2f 99|99 2f 64 10) maclhwsuo\. r3,r4,r5
- 464: (10 64 2b 18|18 2b 64 10) maclhwu r3,r4,r5
- 468: (10 64 2b 19|19 2b 64 10) maclhwu\. r3,r4,r5
- 46c: (10 64 2f 18|18 2f 64 10) maclhwuo r3,r4,r5
- 470: (10 64 2f 19|19 2f 64 10) maclhwuo\. r3,r4,r5
- 474: (7c 00 06 ac|ac 06 00 7c) mbar
- 478: (7c 00 06 ac|ac 06 00 7c) mbar
- 47c: (7c 20 06 ac|ac 06 20 7c) mbar 1
- 480: (4c 04 00 00|00 00 04 4c) mcrf cr0,cr1
- 484: (fd 90 00 80|80 00 90 fd) mcrfs cr3,cr4
- 488: (7d 80 04 00|00 04 80 7d) mcrxr cr3
- 48c: (7c 60 00 26|26 00 60 7c) mfcr r3
- 490: (7c 60 00 26|26 00 60 7c) mfcr r3
- 494: (7c aa 3a 86|86 3a aa 7c) mfdcr r5,234
- 498: (7c 64 02 46|46 02 64 7c) mfdcrux r3,r4
- 49c: (7c 85 02 06|06 02 85 7c) mfdcrx r4,r5
- 4a0: (ff c0 04 8e|8e 04 c0 ff) mffs f30
- 4a4: (ff e0 04 8f|8f 04 e0 ff) mffs\. f31
- 4a8: (7e 60 00 a6|a6 00 60 7e) mfmsr r19
- 4ac: (7c 78 00 26|26 00 78 7c) mfocrf r3,128
- 4b0: (7c 60 22 a6|a6 22 60 7c) mfspr r3,128
- 4b4: (7c 6c 42 a6|a6 42 6c 7c) mftb r3
- 4b8: (7c 00 04 ac|ac 04 00 7c) msync
- 4bc: (7c 78 01 20|20 01 78 7c) mtocrf 128,r3
- 4c0: (7c 6f f1 20|20 f1 6f 7c) mtcr r3
- 4c4: (7d 10 6b 86|86 6b 10 7d) mtdcr 432,r8
- 4c8: (7c 83 03 46|46 03 83 7c) mtdcrux r3,r4
- 4cc: (7c e6 03 06|06 03 e6 7c) mtdcrx r6,r7
- 4d0: (fc 60 00 8c|8c 00 60 fc) mtfsb0 3
- 4d4: (fc 60 00 8d|8d 00 60 fc) mtfsb0\. 3
- 4d8: (fc 60 00 4c|4c 00 60 fc) mtfsb1 3
- 4dc: (fc 60 00 4d|4d 00 60 fc) mtfsb1\. 3
- 4e0: (fc 0c 55 8e|8e 55 0c fc) mtfsf 6,f10
- 4e4: (fc 0c 55 8e|8e 55 0c fc) mtfsf 6,f10
- 4e8: (fc 0d 55 8e|8e 55 0d fc) mtfsf 6,f10,0,1
- 4ec: (fe 0c 55 8e|8e 55 0c fe) mtfsf 6,f10,1
- 4f0: (fc 0c 5d 8f|8f 5d 0c fc) mtfsf\. 6,f11
- 4f4: (fc 0c 5d 8f|8f 5d 0c fc) mtfsf\. 6,f11
- 4f8: (fc 0d 5d 8f|8f 5d 0d fc) mtfsf\. 6,f11,0,1
- 4fc: (fe 0c 5d 8f|8f 5d 0c fe) mtfsf\. 6,f11,1
- 500: (ff 00 01 0c|0c 01 00 ff) mtfsfi 6,0
- 504: (ff 00 01 0c|0c 01 00 ff) mtfsfi 6,0
- 508: (ff 00 01 0c|0c 01 00 ff) mtfsfi 6,0
- 50c: (ff 01 01 0c|0c 01 01 ff) mtfsfi 6,0,1
- 510: (ff 00 f1 0d|0d f1 00 ff) mtfsfi\. 6,15
- 514: (ff 00 f1 0d|0d f1 00 ff) mtfsfi\. 6,15
- 518: (ff 00 f1 0d|0d f1 00 ff) mtfsfi\. 6,15
- 51c: (ff 01 f1 0d|0d f1 01 ff) mtfsfi\. 6,15,1
- 520: (7d 40 01 24|24 01 40 7d) mtmsr r10
- 524: (7c 78 01 20|20 01 78 7c) mtocrf 128,r3
- 528: (7c 60 23 a6|a6 23 60 7c) mtspr 128,r3
- 52c: (10 64 29 50|50 29 64 10) mulchw r3,r4,r5
- 530: (10 64 29 51|51 29 64 10) mulchw\. r3,r4,r5
- 534: (10 64 29 10|10 29 64 10) mulchwu r3,r4,r5
- 538: (10 64 29 11|11 29 64 10) mulchwu\. r3,r4,r5
- 53c: (10 64 28 50|50 28 64 10) mulhhw r3,r4,r5
- 540: (10 64 28 51|51 28 64 10) mulhhw\. r3,r4,r5
- 544: (10 64 28 10|10 28 64 10) mulhhwu r3,r4,r5
- 548: (10 64 28 11|11 28 64 10) mulhhwu\. r3,r4,r5
- 54c: (7c 64 28 96|96 28 64 7c) mulhw r3,r4,r5
- 550: (7c 64 28 97|97 28 64 7c) mulhw\. r3,r4,r5
- 554: (7c 64 28 16|16 28 64 7c) mulhwu r3,r4,r5
- 558: (7c 64 28 17|17 28 64 7c) mulhwu\. r3,r4,r5
- 55c: (10 64 2b 50|50 2b 64 10) mullhw r3,r4,r5
- 560: (10 64 2b 51|51 2b 64 10) mullhw\. r3,r4,r5
- 564: (10 64 2b 10|10 2b 64 10) mullhwu r3,r4,r5
- 568: (10 64 2b 11|11 2b 64 10) mullhwu\. r3,r4,r5
- 56c: (1c 64 00 05|05 00 64 1c) mulli r3,r4,5
- 570: (7c 64 29 d6|d6 29 64 7c) mullw r3,r4,r5
- 574: (7c 64 29 d7|d7 29 64 7c) mullw\. r3,r4,r5
- 578: (7c 64 2d d6|d6 2d 64 7c) mullwo r3,r4,r5
- 57c: (7c 64 2d d7|d7 2d 64 7c) mullwo\. r3,r4,r5
- 580: (7f bc f3 b8|b8 f3 bc 7f) nand r28,r29,r30
- 584: (7f bc f3 b9|b9 f3 bc 7f) nand\. r28,r29,r30
- 588: (7c 64 00 d0|d0 00 64 7c) neg r3,r4
- 58c: (7c 64 00 d1|d1 00 64 7c) neg\. r3,r4
- 590: (7e 11 04 d0|d0 04 11 7e) nego r16,r17
- 594: (7e 53 04 d1|d1 04 53 7e) nego\. r18,r19
- 598: (10 64 29 5c|5c 29 64 10) nmacchw r3,r4,r5
- 59c: (10 64 29 5d|5d 29 64 10) nmacchw\. r3,r4,r5
- 5a0: (10 64 2d 5c|5c 2d 64 10) nmacchwo r3,r4,r5
- 5a4: (10 64 2d 5d|5d 2d 64 10) nmacchwo\. r3,r4,r5
- 5a8: (10 64 29 dc|dc 29 64 10) nmacchws r3,r4,r5
- 5ac: (10 64 29 dd|dd 29 64 10) nmacchws\. r3,r4,r5
- 5b0: (10 64 2d dc|dc 2d 64 10) nmacchwso r3,r4,r5
- 5b4: (10 64 2d dd|dd 2d 64 10) nmacchwso\. r3,r4,r5
- 5b8: (10 64 28 5c|5c 28 64 10) nmachhw r3,r4,r5
- 5bc: (10 64 28 5d|5d 28 64 10) nmachhw\. r3,r4,r5
- 5c0: (10 64 2c 5c|5c 2c 64 10) nmachhwo r3,r4,r5
- 5c4: (10 64 2c 5d|5d 2c 64 10) nmachhwo\. r3,r4,r5
- 5c8: (10 64 28 dc|dc 28 64 10) nmachhws r3,r4,r5
- 5cc: (10 64 28 dd|dd 28 64 10) nmachhws\. r3,r4,r5
- 5d0: (10 64 2c dc|dc 2c 64 10) nmachhwso r3,r4,r5
- 5d4: (10 64 2c dd|dd 2c 64 10) nmachhwso\. r3,r4,r5
- 5d8: (10 64 2b 5c|5c 2b 64 10) nmaclhw r3,r4,r5
- 5dc: (10 64 2b 5d|5d 2b 64 10) nmaclhw\. r3,r4,r5
- 5e0: (10 64 2f 5c|5c 2f 64 10) nmaclhwo r3,r4,r5
- 5e4: (10 64 2f 5d|5d 2f 64 10) nmaclhwo\. r3,r4,r5
- 5e8: (10 64 2b dc|dc 2b 64 10) nmaclhws r3,r4,r5
- 5ec: (10 64 2b dd|dd 2b 64 10) nmaclhws\. r3,r4,r5
- 5f0: (10 64 2f dc|dc 2f 64 10) nmaclhwso r3,r4,r5
- 5f4: (10 64 2f dd|dd 2f 64 10) nmaclhwso\. r3,r4,r5
- 5f8: (7e b4 b0 f8|f8 b0 b4 7e) nor r20,r21,r22
- 5fc: (7e b4 b0 f9|f9 b0 b4 7e) nor\. r20,r21,r22
- 600: (7c 40 23 78|78 23 40 7c) or r0,r2,r4
- 604: (7d cc 83 79|79 83 cc 7d) or\. r12,r14,r16
- 608: (7e 0f 8b 38|38 8b 0f 7e) orc r15,r16,r17
- 60c: (7e 72 a3 39|39 a3 72 7e) orc\. r18,r19,r20
- 610: (60 21 00 00|00 00 21 60) ori r1,r1,0
- 614: (64 83 de ad|ad de 83 64) oris r3,r4,57005
- 618: (7c 83 00 f4|f4 00 83 7c) popcntb r3,r4
- 61c: (7c 83 01 34|34 01 83 7c) prtyw r3,r4
- 620: (4c 00 00 66|66 00 00 4c) rfci
- 624: (4c 00 00 64|64 00 00 4c) rfi
- 628: (4c 00 00 4c|4c 00 00 4c) rfmci
- 62c: (50 83 65 36|36 65 83 50) rlwimi r3,r4,12,20,27
- 630: (50 83 65 37|37 65 83 50) rlwimi\. r3,r4,12,20,27
- 634: (54 83 00 36|36 00 83 54) rlwinm r3,r4,0,0,27
- 638: (54 83 d1 be|be d1 83 54) rlwinm r3,r4,26,6,31
- 63c: (54 83 20 26|26 20 83 54) rlwinm r3,r4,4,0,19
- 640: (54 83 00 37|37 00 83 54) rlwinm\. r3,r4,0,0,27
- 644: (5c 83 28 3e|3e 28 83 5c) rotlw r3,r4,r5
- 648: (5c 83 28 3f|3f 28 83 5c) rotlw\. r3,r4,r5
- 64c: (5c 83 28 3e|3e 28 83 5c) rotlw r3,r4,r5
- 650: (5c 83 28 3f|3f 28 83 5c) rotlw\. r3,r4,r5
- 654: (44 00 00 02|02 00 00 44) sc
- 658: (7c 83 28 30|30 28 83 7c) slw r3,r4,r5
- 65c: (7c 83 28 31|31 28 83 7c) slw\. r3,r4,r5
- 660: (7c 83 2e 30|30 2e 83 7c) sraw r3,r4,r5
- 664: (7c 83 2e 31|31 2e 83 7c) sraw\. r3,r4,r5
- 668: (7c 83 86 70|70 86 83 7c) srawi r3,r4,16
- 66c: (7c 83 86 71|71 86 83 7c) srawi\. r3,r4,16
- 670: (7c 83 2c 30|30 2c 83 7c) srw r3,r4,r5
- 674: (7c 83 2c 31|31 2c 83 7c) srw\. r3,r4,r5
- 678: (54 83 d1 be|be d1 83 54) rlwinm r3,r4,26,6,31
- 67c: (99 61 00 02|02 00 61 99) stb r11,2\(r1\)
- 680: (9d 81 00 03|03 00 81 9d) stbu r12,3\(r1\)
- 684: (7d ae 79 ee|ee 79 ae 7d) stbux r13,r14,r15
- 688: (7c 64 29 ae|ae 29 64 7c) stbx r3,r4,r5
- 68c: (db 21 00 20|20 00 21 db) stfd f25,32\(r1\)
- 690: (df 41 00 28|28 00 41 df) stfdu f26,40\(r1\)
- 694: (7c 01 15 ee|ee 15 01 7c) stfdux f0,r1,r2
- 698: (7f be fd ae|ae fd be 7f) stfdx f29,r30,r31
- 69c: (7d 43 27 ae|ae 27 43 7d) stfiwx f10,r3,r4
- 6a0: (d2 e1 00 14|14 00 e1 d2) stfs f23,20\(r1\)
- 6a4: (d7 01 00 18|18 00 01 d7) stfsu f24,24\(r1\)
- 6a8: (7f 5b e5 6e|6e e5 5b 7f) stfsux f26,r27,r28
- 6ac: (7e f8 cd 2e|2e cd f8 7e) stfsx f23,r24,r25
- 6b0: (b2 21 00 0a|0a 00 21 b2) sth r17,10\(r1\)
- 6b4: (7c c7 47 2c|2c 47 c7 7c) sthbrx r6,r7,r8
- 6b8: (b6 41 00 0c|0c 00 41 b6) sthu r18,12\(r1\)
- 6bc: (7e b6 bb 6e|6e bb b6 7e) sthux r21,r22,r23
- 6c0: (7d 8d 73 2e|2e 73 8d 7d) sthx r12,r13,r14
- 6c4: (bc c1 ff f0|f0 ff c1 bc) stmw r6,-16\(r1\)
- 6c8: (7c 64 85 aa|aa 85 64 7c) stswi r3,r4,16
- 6cc: (7c 64 2d 2a|2a 2d 64 7c) stswx r3,r4,r5
- 6d0: (90 c7 ff f0|f0 ff c7 90) stw r6,-16\(r7\)
- 6d4: (7c 64 2d 2c|2c 2d 64 7c) stwbrx r3,r4,r5
- 6d8: (7c 64 29 2d|2d 29 64 7c) stwcx\. r3,r4,r5
- 6dc: (94 61 00 10|10 00 61 94) stwu r3,16\(r1\)
- 6e0: (7c 64 29 6e|6e 29 64 7c) stwux r3,r4,r5
- 6e4: (7c 64 29 2e|2e 29 64 7c) stwx r3,r4,r5
- 6e8: (7c 64 28 50|50 28 64 7c) subf r3,r4,r5
- 6ec: (7c 64 28 51|51 28 64 7c) subf\. r3,r4,r5
- 6f0: (7c 64 28 10|10 28 64 7c) subfc r3,r4,r5
- 6f4: (7c 64 28 11|11 28 64 7c) subfc\. r3,r4,r5
- 6f8: (7c 64 2c 10|10 2c 64 7c) subfco r3,r4,r5
- 6fc: (7c 64 2c 11|11 2c 64 7c) subfco\. r3,r4,r5
- 700: (7c 64 29 10|10 29 64 7c) subfe r3,r4,r5
- 704: (7c 64 29 11|11 29 64 7c) subfe\. r3,r4,r5
- 708: (7c 64 2d 10|10 2d 64 7c) subfeo r3,r4,r5
- 70c: (7c 64 2d 11|11 2d 64 7c) subfeo\. r3,r4,r5
- 710: (20 64 00 05|05 00 64 20) subfic r3,r4,5
- 714: (7c 64 01 d0|d0 01 64 7c) subfme r3,r4
- 718: (7c 64 01 d1|d1 01 64 7c) subfme\. r3,r4
- 71c: (7c 64 05 d0|d0 05 64 7c) subfmeo r3,r4
- 720: (7c 64 05 d1|d1 05 64 7c) subfmeo\. r3,r4
- 724: (7c 64 2c 50|50 2c 64 7c) subfo r3,r4,r5
- 728: (7c 64 2c 51|51 2c 64 7c) subfo\. r3,r4,r5
- 72c: (7c 64 01 90|90 01 64 7c) subfze r3,r4
- 730: (7c 64 01 91|91 01 64 7c) subfze\. r3,r4
- 734: (7c 64 05 90|90 05 64 7c) subfzeo r3,r4
- 738: (7c 64 05 91|91 05 64 7c) subfzeo\. r3,r4
- 73c: (7c 07 46 24|24 46 07 7c) tlbivax r7,r8
- 740: (7c 22 3f 64|64 3f 22 7c) tlbre r1,r2,7
- 744: (7c 0b 67 24|24 67 0b 7c) tlbsx r11,r12
- 748: (7d 8d 77 24|24 77 8d 7d) tlbsx r12,r13,r14
- 74c: (7d 8d 77 25|25 77 8d 7d) tlbsx\. r12,r13,r14
- 750: (7c 00 04 6c|6c 04 00 7c) tlbsync
- 754: (7c 00 07 a4|a4 07 00 7c) tlbwe
- 758: (7c 00 07 a4|a4 07 00 7c) tlbwe
- 75c: (7c 21 0f a4|a4 0f 21 7c) tlbwe r1,r1,1
- 760: (7f e0 00 08|08 00 e0 7f) trap
- 764: (7f e0 00 08|08 00 e0 7f) trap
- 768: (7c 83 20 08|08 20 83 7c) tweq r3,r4
- 76c: (7c a3 20 08|08 20 a3 7c) twlge r3,r4
- 770: (7c 83 20 08|08 20 83 7c) tweq r3,r4
- 774: (0d 03 00 0f|0f 00 03 0d) twgti r3,15
- 778: (0c c3 00 0f|0f 00 c3 0c) twllei r3,15
- 77c: (0d 03 00 0f|0f 00 03 0d) twgti r3,15
- 780: (7c a3 20 08|08 20 a3 7c) twlge r3,r4
- 784: (0c c3 00 0f|0f 00 c3 0c) twllei r3,15
- 788: (7c 60 01 06|06 01 60 7c) wrtee r3
- 78c: (7c 00 81 46|46 81 00 7c) wrteei 1
- 790: (7f dd fa 78|78 fa dd 7f) xor r29,r30,r31
- 794: (7f dd fa 79|79 fa dd 7f) xor\. r29,r30,r31
- 798: (68 83 de ad|ad de 83 68) xori r3,r4,57005
- 79c: (6c 83 de ad|ad de 83 6c) xoris r3,r4,57005
+.*: (7c 64 2a 14|14 2a 64 7c) add r3,r4,r5
+.*: (7c 64 2a 15|15 2a 64 7c) add\. r3,r4,r5
+.*: (7c 64 28 14|14 28 64 7c) addc r3,r4,r5
+.*: (7c 64 28 15|15 28 64 7c) addc\. r3,r4,r5
+.*: (7c 64 2c 14|14 2c 64 7c) addco r3,r4,r5
+.*: (7c 64 2c 15|15 2c 64 7c) addco\. r3,r4,r5
+.*: (7c 64 29 14|14 29 64 7c) adde r3,r4,r5
+.*: (7c 64 29 15|15 29 64 7c) adde\. r3,r4,r5
+.*: (7c 64 2d 14|14 2d 64 7c) addeo r3,r4,r5
+.*: (7c 64 2d 15|15 2d 64 7c) addeo\. r3,r4,r5
+.*: (38 64 ff 80|80 ff 64 38) addi r3,r4,-128
+.*: (30 64 ff 80|80 ff 64 30) addic r3,r4,-128
+.*: (34 64 ff 80|80 ff 64 34) addic\. r3,r4,-128
+.*: (3c 64 ff 80|80 ff 64 3c) addis r3,r4,-128
+.*: (7c 64 01 d4|d4 01 64 7c) addme r3,r4
+.*: (7c 64 01 d5|d5 01 64 7c) addme\. r3,r4
+.*: (7c 64 05 d4|d4 05 64 7c) addmeo r3,r4
+.*: (7c 64 05 d5|d5 05 64 7c) addmeo\. r3,r4
+.*: (7c 64 2e 14|14 2e 64 7c) addo r3,r4,r5
+.*: (7c 64 2e 15|15 2e 64 7c) addo\. r3,r4,r5
+.*: (7c 64 01 94|94 01 64 7c) addze r3,r4
+.*: (7c 64 01 95|95 01 64 7c) addze\. r3,r4
+.*: (7c 64 05 94|94 05 64 7c) addzeo r3,r4
+.*: (7c 64 05 95|95 05 64 7c) addzeo\. r3,r4
+.*: (7c 83 28 38|38 28 83 7c) and r3,r4,r5
+.*: (7c 83 28 39|39 28 83 7c) and\. r3,r4,r5
+.*: (7d cd 78 78|78 78 cd 7d) andc r13,r14,r15
+.*: (7e 30 90 79|79 90 30 7e) andc\. r16,r17,r18
+.*: (70 83 de ad|ad de 83 70) andi\. r3,r4,57005
+.*: (74 83 de ad|ad de 83 74) andis\. r3,r4,57005
+.*: (48 00 00 02|02 00 00 48) ba 0 <ppc476>
+.*: (40 01 00 00|00 00 01 40) bdnzf gt,7c <ppc476\+0x7c>
+.*: (40 85 00 02|02 00 85 40) blea cr1,0 <ppc476>
+.*: (4d 80 04 20|20 04 80 4d) bltctr
+.*: (4c 8a 04 20|20 04 8a 4c) bnectr cr2
+.*: (4c 86 04 20|20 04 86 4c) bnectr cr1
+.*: (4c 86 04 20|20 04 86 4c) bnectr cr1
+.*: (4d 80 04 21|21 04 80 4d) bltctrl
+.*: (4c 8a 04 21|21 04 8a 4c) bnectrl cr2
+.*: (4c 86 04 21|21 04 86 4c) bnectrl cr1
+.*: (4c 86 04 21|21 04 86 4c) bnectrl cr1
+.*: (40 43 00 01|01 00 43 40) bdzfl so,a4 <ppc476\+0xa4>
+.*: (4d 80 00 20|20 00 80 4d) bltlr
+.*: (4c 8a 00 20|20 00 8a 4c) bnelr cr2
+.*: (4c 86 00 20|20 00 86 4c) bnelr cr1
+.*: (4c 86 00 20|20 00 86 4c) bnelr cr1
+.*: (4d 80 00 21|21 00 80 4d) bltlrl
+.*: (4c 8a 00 21|21 00 8a 4c) bnelrl cr2
+.*: (4c 86 00 21|21 00 86 4c) bnelrl cr1
+.*: (4c 86 00 21|21 00 86 4c) bnelrl cr1
+.*: (48 00 00 00|00 00 00 48) b c8 <ppc476\+0xc8>
+.*: (48 00 00 01|01 00 00 48) bl cc <ppc476\+0xcc>
+.*: (54 83 00 36|36 00 83 54) rlwinm r3,r4,0,0,27
+.*: (7c 03 20 00|00 20 03 7c) cmpw r3,r4
+.*: (7f 83 20 00|00 20 83 7f) cmpw cr7,r3,r4
+.*: (7c 83 2b f8|f8 2b 83 7c) cmpb r3,r4,r5
+.*: (7c 83 2b f8|f8 2b 83 7c) cmpb r3,r4,r5
+.*: (2c 03 ff 59|59 ff 03 2c) cmpwi r3,-167
+.*: (2f 83 ff 59|59 ff 83 2f) cmpwi cr7,r3,-167
+.*: (7c 03 20 40|40 20 03 7c) cmplw r3,r4
+.*: (7f 83 20 40|40 20 83 7f) cmplw cr7,r3,r4
+.*: (28 03 00 a7|a7 00 03 28) cmplwi r3,167
+.*: (2b 83 00 a7|a7 00 83 2b) cmplwi cr7,r3,167
+.*: (7c 03 20 40|40 20 03 7c) cmplw r3,r4
+.*: (28 03 00 a7|a7 00 03 28) cmplwi r3,167
+.*: (7c 03 20 00|00 20 03 7c) cmpw r3,r4
+.*: (2c 03 ff 59|59 ff 03 2c) cmpwi r3,-167
+.*: (7d 6a 00 34|34 00 6a 7d) cntlzw r10,r11
+.*: (7d 6a 00 35|35 00 6a 7d) cntlzw\. r10,r11
+.*: (4c 85 32 02|02 32 85 4c) crand 4\*cr1\+lt,4\*cr1\+gt,4\*cr1\+eq
+.*: (4c 64 29 02|02 29 64 4c) crandc so,4\*cr1\+lt,4\*cr1\+gt
+.*: (4c e0 0a 42|42 0a e0 4c) creqv 4\*cr1\+so,lt,gt
+.*: (4c 22 19 c2|c2 19 22 4c) crnand gt,eq,so
+.*: (4c 01 10 42|42 10 01 4c) crnor lt,gt,eq
+.*: (4c a6 3b 82|82 3b a6 4c) cror 4\*cr1\+gt,4\*cr1\+eq,4\*cr1\+so
+.*: (4c 43 23 42|42 23 43 4c) crorc eq,so,4\*cr1\+lt
+.*: (4c c7 01 82|82 01 c7 4c) crxor 4\*cr1\+eq,4\*cr1\+so,lt
+.*: (7c 09 55 ec|ec 55 09 7c) dcba r9,r10
+.*: (7c 06 38 ac|ac 38 06 7c) dcbf r6,r7
+.*: (7c 06 38 ac|ac 38 06 7c) dcbf r6,r7
+.*: (7c 06 3b ac|ac 3b 06 7c) dcbi r6,r7
+.*: (7c 85 33 0c|0c 33 85 7c) dcblc 4,r5,r6
+.*: (7c 06 38 6c|6c 38 06 7c) dcbst r6,r7
+.*: (7c 05 32 2c|2c 32 05 7c) dcbt r5,r6
+.*: (7c 05 32 2c|2c 32 05 7c) dcbt r5,r6
+.*: (7d 05 32 2c|2c 32 05 7d) dcbt 8,r5,r6
+.*: (7c e8 49 4c|4c 49 e8 7c) dcbtls 7,r8,r9
+.*: (7c 06 39 ec|ec 39 06 7c) dcbtst r6,r7
+.*: (7c 06 39 ec|ec 39 06 7c) dcbtst r6,r7
+.*: (7d 26 39 ec|ec 39 26 7d) dcbtst 9,r6,r7
+.*: (7d 4b 61 0c|0c 61 4b 7d) dcbtstls 10,r11,r12
+.*: (7c 01 17 ec|ec 17 01 7c) dcbz r1,r2
+.*: (7c 05 37 ec|ec 37 05 7c) dcbz r5,r6
+.*: (7c 00 03 8c|8c 03 00 7c) dccci
+.*: (7c 00 03 8c|8c 03 00 7c) dccci
+.*: (7c 00 03 8c|8c 03 00 7c) dccci
+.*: (7c 20 03 8c|8c 03 20 7c) dci 1
+.*: (7d 4b 63 d6|d6 63 4b 7d) divw r10,r11,r12
+.*: (7d 6c 6b d7|d7 6b 6c 7d) divw\. r11,r12,r13
+.*: (7d 4b 67 d6|d6 67 4b 7d) divwo r10,r11,r12
+.*: (7d 6c 6f d7|d7 6f 6c 7d) divwo\. r11,r12,r13
+.*: (7d 4b 63 96|96 63 4b 7d) divwu r10,r11,r12
+.*: (7d 6c 6b 97|97 6b 6c 7d) divwu\. r11,r12,r13
+.*: (7d 4b 67 96|96 67 4b 7d) divwuo r10,r11,r12
+.*: (7d 6c 6f 97|97 6f 6c 7d) divwuo\. r11,r12,r13
+.*: (7c 83 28 9c|9c 28 83 7c) dlmzb r3,r4,r5
+.*: (7c 83 28 9d|9d 28 83 7c) dlmzb\. r3,r4,r5
+.*: (7d 6a 62 38|38 62 6a 7d) eqv r10,r11,r12
+.*: (7d 6a 62 39|39 62 6a 7d) eqv\. r10,r11,r12
+.*: (54 83 20 26|26 20 83 54) rlwinm r3,r4,4,0,19
+.*: (7c 83 07 74|74 07 83 7c) extsb r3,r4
+.*: (7c 83 07 75|75 07 83 7c) extsb\. r3,r4
+.*: (7c 83 07 34|34 07 83 7c) extsh r3,r4
+.*: (7c 83 07 35|35 07 83 7c) extsh\. r3,r4
+.*: (fe a0 fa 10|10 fa a0 fe) fabs f21,f31
+.*: (fe a0 fa 11|11 fa a0 fe) fabs\. f21,f31
+.*: (fd 4b 60 2a|2a 60 4b fd) fadd f10,f11,f12
+.*: (fd 4b 60 2b|2b 60 4b fd) fadd\. f10,f11,f12
+.*: (ed 4b 60 2a|2a 60 4b ed) fadds f10,f11,f12
+.*: (ed 4b 60 2b|2b 60 4b ed) fadds\. f10,f11,f12
+.*: (fd 40 5e 9c|9c 5e 40 fd) fcfid f10,f11
+.*: (fd 40 5e 9d|9d 5e 40 fd) fcfid\. f10,f11
+.*: (fd 8a 58 40|40 58 8a fd) fcmpo cr3,f10,f11
+.*: (fd 84 28 00|00 28 84 fd) fcmpu cr3,f4,f5
+.*: (fd 4b 60 10|10 60 4b fd) fcpsgn f10,f11,f12
+.*: (fd 4b 60 11|11 60 4b fd) fcpsgn\. f10,f11,f12
+.*: (fd 40 5e 5c|5c 5e 40 fd) fctid f10,f11
+.*: (fd 40 5e 5d|5d 5e 40 fd) fctid\. f10,f11
+.*: (fd 40 5e 5e|5e 5e 40 fd) fctidz f10,f11
+.*: (fd 40 5e 5f|5f 5e 40 fd) fctidz\. f10,f11
+.*: (fd 40 58 1c|1c 58 40 fd) fctiw f10,f11
+.*: (fd 40 58 1d|1d 58 40 fd) fctiw\. f10,f11
+.*: (fd 40 58 1e|1e 58 40 fd) fctiwz f10,f11
+.*: (fd 40 58 1f|1f 58 40 fd) fctiwz\. f10,f11
+.*: (fd 4b 60 24|24 60 4b fd) fdiv f10,f11,f12
+.*: (fd 4b 60 25|25 60 4b fd) fdiv\. f10,f11,f12
+.*: (ed 4b 60 24|24 60 4b ed) fdivs f10,f11,f12
+.*: (ed 4b 60 25|25 60 4b ed) fdivs\. f10,f11,f12
+.*: (fd 4b 6b 3a|3a 6b 4b fd) fmadd f10,f11,f12,f13
+.*: (fd 4b 6b 3b|3b 6b 4b fd) fmadd\. f10,f11,f12,f13
+.*: (ed 4b 6b 3a|3a 6b 4b ed) fmadds f10,f11,f12,f13
+.*: (ed 4b 6b 3b|3b 6b 4b ed) fmadds\. f10,f11,f12,f13
+.*: (fc 60 20 90|90 20 60 fc) fmr f3,f4
+.*: (fc 60 20 91|91 20 60 fc) fmr\. f3,f4
+.*: (fd 4b 6b 38|38 6b 4b fd) fmsub f10,f11,f12,f13
+.*: (fd 4b 6b 39|39 6b 4b fd) fmsub\. f10,f11,f12,f13
+.*: (ed 4b 6b 38|38 6b 4b ed) fmsubs f10,f11,f12,f13
+.*: (ed 4b 6b 39|39 6b 4b ed) fmsubs\. f10,f11,f12,f13
+.*: (fd 4b 03 32|32 03 4b fd) fmul f10,f11,f12
+.*: (fd 4b 03 33|33 03 4b fd) fmul\. f10,f11,f12
+.*: (ed 4b 03 32|32 03 4b ed) fmuls f10,f11,f12
+.*: (ed 4b 03 33|33 03 4b ed) fmuls\. f10,f11,f12
+.*: (fe 80 f1 10|10 f1 80 fe) fnabs f20,f30
+.*: (fe 80 f1 11|11 f1 80 fe) fnabs\. f20,f30
+.*: (fc 60 20 50|50 20 60 fc) fneg f3,f4
+.*: (fc 60 20 51|51 20 60 fc) fneg\. f3,f4
+.*: (fd 4b 6b 3e|3e 6b 4b fd) fnmadd f10,f11,f12,f13
+.*: (fd 4b 6b 3f|3f 6b 4b fd) fnmadd\. f10,f11,f12,f13
+.*: (ed 4b 6b 3e|3e 6b 4b ed) fnmadds f10,f11,f12,f13
+.*: (ed 4b 6b 3f|3f 6b 4b ed) fnmadds\. f10,f11,f12,f13
+.*: (fd 4b 6b 3c|3c 6b 4b fd) fnmsub f10,f11,f12,f13
+.*: (fd 4b 6b 3d|3d 6b 4b fd) fnmsub\. f10,f11,f12,f13
+.*: (ed 4b 6b 3c|3c 6b 4b ed) fnmsubs f10,f11,f12,f13
+.*: (ed 4b 6b 3d|3d 6b 4b ed) fnmsubs\. f10,f11,f12,f13
+.*: (fd c0 78 30|30 78 c0 fd) fre f14,f15
+.*: (fd c0 78 31|31 78 c0 fd) fre\. f14,f15
+.*: (ed c0 78 30|30 78 c0 ed) fres f14,f15
+.*: (ed c0 78 31|31 78 c0 ed) fres\. f14,f15
+.*: (fd 40 5b d0|d0 5b 40 fd) frim f10,f11
+.*: (fd 40 5b d1|d1 5b 40 fd) frim\. f10,f11
+.*: (fd 40 5b 10|10 5b 40 fd) frin f10,f11
+.*: (fd 40 5b 11|11 5b 40 fd) frin\. f10,f11
+.*: (fd 40 5b 90|90 5b 40 fd) frip f10,f11
+.*: (fd 40 5b 91|91 5b 40 fd) frip\. f10,f11
+.*: (fd 40 5b 50|50 5b 40 fd) friz f10,f11
+.*: (fd 40 5b 51|51 5b 40 fd) friz\. f10,f11
+.*: (fc c0 38 18|18 38 c0 fc) frsp f6,f7
+.*: (fd 00 48 19|19 48 00 fd) frsp\. f8,f9
+.*: (fd c0 78 34|34 78 c0 fd) frsqrte f14,f15
+.*: (fd c0 78 35|35 78 c0 fd) frsqrte\. f14,f15
+.*: (ed c0 78 34|34 78 c0 ed) frsqrtes f14,f15
+.*: (ed c0 78 35|35 78 c0 ed) frsqrtes\. f14,f15
+.*: (fd 4b 6b 2e|2e 6b 4b fd) fsel f10,f11,f12,f13
+.*: (fd 4b 6b 2f|2f 6b 4b fd) fsel\. f10,f11,f12,f13
+.*: (fd 40 58 2c|2c 58 40 fd) fsqrt f10,f11
+.*: (fd 40 58 2d|2d 58 40 fd) fsqrt\. f10,f11
+.*: (ed 40 58 2c|2c 58 40 ed) fsqrts f10,f11
+.*: (ed 40 58 2d|2d 58 40 ed) fsqrts\. f10,f11
+.*: (fd 4b 60 28|28 60 4b fd) fsub f10,f11,f12
+.*: (fd 4b 60 29|29 60 4b fd) fsub\. f10,f11,f12
+.*: (ed 4b 60 28|28 60 4b ed) fsubs f10,f11,f12
+.*: (ed 4b 60 29|29 60 4b ed) fsubs\. f10,f11,f12
+.*: (7c 03 27 ac|ac 27 03 7c) icbi r3,r4
+.*: (7e 11 91 cc|cc 91 11 7e) icblc 16,r17,r18
+.*: (7c a8 48 2c|2c 48 a8 7c) icbt 5,r8,r9
+.*: (7d ae 7b cc|cc 7b ae 7d) icbtls 13,r14,r15
+.*: (7c 00 07 8c|8c 07 00 7c) iccci
+.*: (7c 00 07 8c|8c 07 00 7c) iccci
+.*: (7c 00 07 8c|8c 07 00 7c) iccci
+.*: (7c 20 07 8c|8c 07 20 7c) ici 1
+.*: (7c 03 27 cc|cc 27 03 7c) icread r3,r4
+.*: (50 83 65 36|36 65 83 50) rlwimi r3,r4,12,20,27
+.*: (7c 43 27 1e|1e 27 43 7c) isel r2,r3,r4,28
+.*: (4c 00 01 2c|2c 01 00 4c) isync
+.*: (89 21 00 00|00 00 21 89) lbz r9,0\(r1\)
+.*: (8d 41 00 01|01 00 41 8d) lbzu r10,1\(r1\)
+.*: (7e 95 b0 ee|ee b0 95 7e) lbzux r20,r21,r22
+.*: (7c 64 28 ae|ae 28 64 7c) lbzx r3,r4,r5
+.*: (ca a1 00 08|08 00 a1 ca) lfd f21,8\(r1\)
+.*: (ce c1 00 10|10 00 c1 ce) lfdu f22,16\(r1\)
+.*: (7e 95 b4 ee|ee b4 95 7e) lfdux f20,r21,r22
+.*: (7d ae 7c ae|ae 7c ae 7d) lfdx f13,r14,r15
+.*: (7d 43 26 ae|ae 26 43 7d) lfiwax f10,r3,r4
+.*: (c2 61 00 00|00 00 61 c2) lfs f19,0\(r1\)
+.*: (c6 81 00 04|04 00 81 c6) lfsu f20,4\(r1\)
+.*: (7d 4b 64 6e|6e 64 4b 7d) lfsux f10,r11,r12
+.*: (7d 4b 64 2e|2e 64 4b 7d) lfsx f10,r11,r12
+.*: (a9 e1 00 06|06 00 e1 a9) lha r15,6\(r1\)
+.*: (ae 01 00 08|08 00 01 ae) lhau r16,8\(r1\)
+.*: (7d 2a 5a ee|ee 5a 2a 7d) lhaux r9,r10,r11
+.*: (7d 2a 5a ae|ae 5a 2a 7d) lhax r9,r10,r11
+.*: (7c 64 2e 2c|2c 2e 64 7c) lhbrx r3,r4,r5
+.*: (a1 a1 00 00|00 00 a1 a1) lhz r13,0\(r1\)
+.*: (a5 c1 00 02|02 00 c1 a5) lhzu r14,2\(r1\)
+.*: (7e 96 c2 6e|6e c2 96 7e) lhzux r20,r22,r24
+.*: (7e f8 ca 2e|2e ca f8 7e) lhzx r23,r24,r25
+.*: (7c 64 28 28|28 28 64 7c) lwarx r3,r4,r5
+.*: (7c 64 28 28|28 28 64 7c) lwarx r3,r4,r5
+.*: (7c 64 28 29|29 28 64 7c) lwarx r3,r4,r5,1
+.*: (7c 64 2c 2c|2c 2c 64 7c) lwbrx r3,r4,r5
+.*: (80 c7 00 00|00 00 c7 80) lwz r6,0\(r7\)
+.*: (84 61 00 10|10 00 61 84) lwzu r3,16\(r1\)
+.*: (7c 64 28 6e|6e 28 64 7c) lwzux r3,r4,r5
+.*: (7c 64 28 2e|2e 28 64 7c) lwzx r3,r4,r5
+.*: (10 64 29 58|58 29 64 10) macchw r3,r4,r5
+.*: (10 64 29 59|59 29 64 10) macchw\. r3,r4,r5
+.*: (10 64 2d 58|58 2d 64 10) macchwo r3,r4,r5
+.*: (10 64 2d 59|59 2d 64 10) macchwo\. r3,r4,r5
+.*: (10 64 29 d8|d8 29 64 10) macchws r3,r4,r5
+.*: (10 64 29 d9|d9 29 64 10) macchws\. r3,r4,r5
+.*: (10 64 2d d8|d8 2d 64 10) macchwso r3,r4,r5
+.*: (10 64 2d d9|d9 2d 64 10) macchwso\. r3,r4,r5
+.*: (10 64 29 98|98 29 64 10) macchwsu r3,r4,r5
+.*: (10 64 29 99|99 29 64 10) macchwsu\. r3,r4,r5
+.*: (10 64 2d 98|98 2d 64 10) macchwsuo r3,r4,r5
+.*: (10 64 2d 99|99 2d 64 10) macchwsuo\. r3,r4,r5
+.*: (10 64 29 18|18 29 64 10) macchwu r3,r4,r5
+.*: (10 64 29 19|19 29 64 10) macchwu\. r3,r4,r5
+.*: (10 64 2d 18|18 2d 64 10) macchwuo r3,r4,r5
+.*: (10 64 2d 19|19 2d 64 10) macchwuo\. r3,r4,r5
+.*: (10 64 28 58|58 28 64 10) machhw r3,r4,r5
+.*: (10 64 28 59|59 28 64 10) machhw\. r3,r4,r5
+.*: (10 64 2c 58|58 2c 64 10) machhwo r3,r4,r5
+.*: (10 64 2c 59|59 2c 64 10) machhwo\. r3,r4,r5
+.*: (10 64 28 d8|d8 28 64 10) machhws r3,r4,r5
+.*: (10 64 28 d9|d9 28 64 10) machhws\. r3,r4,r5
+.*: (10 64 2c d8|d8 2c 64 10) machhwso r3,r4,r5
+.*: (10 64 2c d9|d9 2c 64 10) machhwso\. r3,r4,r5
+.*: (10 64 28 98|98 28 64 10) machhwsu r3,r4,r5
+.*: (10 64 28 99|99 28 64 10) machhwsu\. r3,r4,r5
+.*: (10 64 2c 98|98 2c 64 10) machhwsuo r3,r4,r5
+.*: (10 64 2c 99|99 2c 64 10) machhwsuo\. r3,r4,r5
+.*: (10 64 28 18|18 28 64 10) machhwu r3,r4,r5
+.*: (10 64 28 19|19 28 64 10) machhwu\. r3,r4,r5
+.*: (10 64 2c 18|18 2c 64 10) machhwuo r3,r4,r5
+.*: (10 64 2c 19|19 2c 64 10) machhwuo\. r3,r4,r5
+.*: (10 64 2b 58|58 2b 64 10) maclhw r3,r4,r5
+.*: (10 64 2b 59|59 2b 64 10) maclhw\. r3,r4,r5
+.*: (10 64 2f 58|58 2f 64 10) maclhwo r3,r4,r5
+.*: (10 64 2f 59|59 2f 64 10) maclhwo\. r3,r4,r5
+.*: (10 64 2b d8|d8 2b 64 10) maclhws r3,r4,r5
+.*: (10 64 2b d9|d9 2b 64 10) maclhws\. r3,r4,r5
+.*: (10 64 2f d8|d8 2f 64 10) maclhwso r3,r4,r5
+.*: (10 64 2f d9|d9 2f 64 10) maclhwso\. r3,r4,r5
+.*: (10 64 2b 98|98 2b 64 10) maclhwsu r3,r4,r5
+.*: (10 64 2b 99|99 2b 64 10) maclhwsu\. r3,r4,r5
+.*: (10 64 2f 98|98 2f 64 10) maclhwsuo r3,r4,r5
+.*: (10 64 2f 99|99 2f 64 10) maclhwsuo\. r3,r4,r5
+.*: (10 64 2b 18|18 2b 64 10) maclhwu r3,r4,r5
+.*: (10 64 2b 19|19 2b 64 10) maclhwu\. r3,r4,r5
+.*: (10 64 2f 18|18 2f 64 10) maclhwuo r3,r4,r5
+.*: (10 64 2f 19|19 2f 64 10) maclhwuo\. r3,r4,r5
+.*: (7c 00 06 ac|ac 06 00 7c) mbar
+.*: (7c 00 06 ac|ac 06 00 7c) mbar
+.*: (7c 20 06 ac|ac 06 20 7c) mbar 1
+.*: (4c 04 00 00|00 00 04 4c) mcrf cr0,cr1
+.*: (fd 90 00 80|80 00 90 fd) mcrfs cr3,cr4
+.*: (7d 80 04 00|00 04 80 7d) mcrxr cr3
+.*: (7c 60 00 26|26 00 60 7c) mfcr r3
+.*: (7c 60 00 26|26 00 60 7c) mfcr r3
+.*: (7c aa 3a 86|86 3a aa 7c) mfdcr r5,234
+.*: (7c 64 02 46|46 02 64 7c) mfdcrux r3,r4
+.*: (7c 85 02 06|06 02 85 7c) mfdcrx r4,r5
+.*: (ff c0 04 8e|8e 04 c0 ff) mffs f30
+.*: (ff e0 04 8f|8f 04 e0 ff) mffs\. f31
+.*: (7e 60 00 a6|a6 00 60 7e) mfmsr r19
+.*: (7c 78 00 26|26 00 78 7c) mfocrf r3,128
+.*: (7c 60 22 a6|a6 22 60 7c) mfspr r3,128
+.*: (7c 6c 42 a6|a6 42 6c 7c) mftb r3
+.*: (7c 00 04 ac|ac 04 00 7c) msync
+.*: (7c 78 01 20|20 01 78 7c) mtocrf 128,r3
+.*: (7c 6f f1 20|20 f1 6f 7c) mtcr r3
+.*: (7d 10 6b 86|86 6b 10 7d) mtdcr 432,r8
+.*: (7c 83 03 46|46 03 83 7c) mtdcrux r3,r4
+.*: (7c e6 03 06|06 03 e6 7c) mtdcrx r6,r7
+.*: (fc 60 00 8c|8c 00 60 fc) mtfsb0 3
+.*: (fc 60 00 8d|8d 00 60 fc) mtfsb0\. 3
+.*: (fc 60 00 4c|4c 00 60 fc) mtfsb1 3
+.*: (fc 60 00 4d|4d 00 60 fc) mtfsb1\. 3
+.*: (fc 0c 55 8e|8e 55 0c fc) mtfsf 6,f10
+.*: (fc 0c 55 8e|8e 55 0c fc) mtfsf 6,f10
+.*: (fc 0d 55 8e|8e 55 0d fc) mtfsf 6,f10,0,1
+.*: (fe 0c 55 8e|8e 55 0c fe) mtfsf 6,f10,1
+.*: (fc 0c 5d 8f|8f 5d 0c fc) mtfsf\. 6,f11
+.*: (fc 0c 5d 8f|8f 5d 0c fc) mtfsf\. 6,f11
+.*: (fc 0d 5d 8f|8f 5d 0d fc) mtfsf\. 6,f11,0,1
+.*: (fe 0c 5d 8f|8f 5d 0c fe) mtfsf\. 6,f11,1
+.*: (ff 00 01 0c|0c 01 00 ff) mtfsfi 6,0
+.*: (ff 00 01 0c|0c 01 00 ff) mtfsfi 6,0
+.*: (ff 00 01 0c|0c 01 00 ff) mtfsfi 6,0
+.*: (ff 01 01 0c|0c 01 01 ff) mtfsfi 6,0,1
+.*: (ff 00 f1 0d|0d f1 00 ff) mtfsfi\. 6,15
+.*: (ff 00 f1 0d|0d f1 00 ff) mtfsfi\. 6,15
+.*: (ff 00 f1 0d|0d f1 00 ff) mtfsfi\. 6,15
+.*: (ff 01 f1 0d|0d f1 01 ff) mtfsfi\. 6,15,1
+.*: (7d 40 01 24|24 01 40 7d) mtmsr r10
+.*: (7c 78 01 20|20 01 78 7c) mtocrf 128,r3
+.*: (7c 60 23 a6|a6 23 60 7c) mtspr 128,r3
+.*: (10 64 29 50|50 29 64 10) mulchw r3,r4,r5
+.*: (10 64 29 51|51 29 64 10) mulchw\. r3,r4,r5
+.*: (10 64 29 10|10 29 64 10) mulchwu r3,r4,r5
+.*: (10 64 29 11|11 29 64 10) mulchwu\. r3,r4,r5
+.*: (10 64 28 50|50 28 64 10) mulhhw r3,r4,r5
+.*: (10 64 28 51|51 28 64 10) mulhhw\. r3,r4,r5
+.*: (10 64 28 10|10 28 64 10) mulhhwu r3,r4,r5
+.*: (10 64 28 11|11 28 64 10) mulhhwu\. r3,r4,r5
+.*: (7c 64 28 96|96 28 64 7c) mulhw r3,r4,r5
+.*: (7c 64 28 97|97 28 64 7c) mulhw\. r3,r4,r5
+.*: (7c 64 28 16|16 28 64 7c) mulhwu r3,r4,r5
+.*: (7c 64 28 17|17 28 64 7c) mulhwu\. r3,r4,r5
+.*: (10 64 2b 50|50 2b 64 10) mullhw r3,r4,r5
+.*: (10 64 2b 51|51 2b 64 10) mullhw\. r3,r4,r5
+.*: (10 64 2b 10|10 2b 64 10) mullhwu r3,r4,r5
+.*: (10 64 2b 11|11 2b 64 10) mullhwu\. r3,r4,r5
+.*: (1c 64 00 05|05 00 64 1c) mulli r3,r4,5
+.*: (7c 64 29 d6|d6 29 64 7c) mullw r3,r4,r5
+.*: (7c 64 29 d7|d7 29 64 7c) mullw\. r3,r4,r5
+.*: (7c 64 2d d6|d6 2d 64 7c) mullwo r3,r4,r5
+.*: (7c 64 2d d7|d7 2d 64 7c) mullwo\. r3,r4,r5
+.*: (7f bc f3 b8|b8 f3 bc 7f) nand r28,r29,r30
+.*: (7f bc f3 b9|b9 f3 bc 7f) nand\. r28,r29,r30
+.*: (7c 64 00 d0|d0 00 64 7c) neg r3,r4
+.*: (7c 64 00 d1|d1 00 64 7c) neg\. r3,r4
+.*: (7e 11 04 d0|d0 04 11 7e) nego r16,r17
+.*: (7e 53 04 d1|d1 04 53 7e) nego\. r18,r19
+.*: (10 64 29 5c|5c 29 64 10) nmacchw r3,r4,r5
+.*: (10 64 29 5d|5d 29 64 10) nmacchw\. r3,r4,r5
+.*: (10 64 2d 5c|5c 2d 64 10) nmacchwo r3,r4,r5
+.*: (10 64 2d 5d|5d 2d 64 10) nmacchwo\. r3,r4,r5
+.*: (10 64 29 dc|dc 29 64 10) nmacchws r3,r4,r5
+.*: (10 64 29 dd|dd 29 64 10) nmacchws\. r3,r4,r5
+.*: (10 64 2d dc|dc 2d 64 10) nmacchwso r3,r4,r5
+.*: (10 64 2d dd|dd 2d 64 10) nmacchwso\. r3,r4,r5
+.*: (10 64 28 5c|5c 28 64 10) nmachhw r3,r4,r5
+.*: (10 64 28 5d|5d 28 64 10) nmachhw\. r3,r4,r5
+.*: (10 64 2c 5c|5c 2c 64 10) nmachhwo r3,r4,r5
+.*: (10 64 2c 5d|5d 2c 64 10) nmachhwo\. r3,r4,r5
+.*: (10 64 28 dc|dc 28 64 10) nmachhws r3,r4,r5
+.*: (10 64 28 dd|dd 28 64 10) nmachhws\. r3,r4,r5
+.*: (10 64 2c dc|dc 2c 64 10) nmachhwso r3,r4,r5
+.*: (10 64 2c dd|dd 2c 64 10) nmachhwso\. r3,r4,r5
+.*: (10 64 2b 5c|5c 2b 64 10) nmaclhw r3,r4,r5
+.*: (10 64 2b 5d|5d 2b 64 10) nmaclhw\. r3,r4,r5
+.*: (10 64 2f 5c|5c 2f 64 10) nmaclhwo r3,r4,r5
+.*: (10 64 2f 5d|5d 2f 64 10) nmaclhwo\. r3,r4,r5
+.*: (10 64 2b dc|dc 2b 64 10) nmaclhws r3,r4,r5
+.*: (10 64 2b dd|dd 2b 64 10) nmaclhws\. r3,r4,r5
+.*: (10 64 2f dc|dc 2f 64 10) nmaclhwso r3,r4,r5
+.*: (10 64 2f dd|dd 2f 64 10) nmaclhwso\. r3,r4,r5
+.*: (7e b4 b0 f8|f8 b0 b4 7e) nor r20,r21,r22
+.*: (7e b4 b0 f9|f9 b0 b4 7e) nor\. r20,r21,r22
+.*: (7c 40 23 78|78 23 40 7c) or r0,r2,r4
+.*: (7d cc 83 79|79 83 cc 7d) or\. r12,r14,r16
+.*: (7e 0f 8b 38|38 8b 0f 7e) orc r15,r16,r17
+.*: (7e 72 a3 39|39 a3 72 7e) orc\. r18,r19,r20
+.*: (60 21 00 00|00 00 21 60) ori r1,r1,0
+.*: (64 83 de ad|ad de 83 64) oris r3,r4,57005
+.*: (7c 83 00 f4|f4 00 83 7c) popcntb r3,r4
+.*: (7c 83 01 34|34 01 83 7c) prtyw r3,r4
+.*: (4c 00 00 66|66 00 00 4c) rfci
+.*: (4c 00 00 64|64 00 00 4c) rfi
+.*: (4c 00 00 4c|4c 00 00 4c) rfmci
+.*: (50 83 65 36|36 65 83 50) rlwimi r3,r4,12,20,27
+.*: (50 83 65 37|37 65 83 50) rlwimi\. r3,r4,12,20,27
+.*: (54 83 00 36|36 00 83 54) rlwinm r3,r4,0,0,27
+.*: (54 83 d1 be|be d1 83 54) rlwinm r3,r4,26,6,31
+.*: (54 83 20 26|26 20 83 54) rlwinm r3,r4,4,0,19
+.*: (54 83 00 37|37 00 83 54) rlwinm\. r3,r4,0,0,27
+.*: (5c 83 28 3e|3e 28 83 5c) rotlw r3,r4,r5
+.*: (5c 83 28 3f|3f 28 83 5c) rotlw\. r3,r4,r5
+.*: (5c 83 28 3e|3e 28 83 5c) rotlw r3,r4,r5
+.*: (5c 83 28 3f|3f 28 83 5c) rotlw\. r3,r4,r5
+.*: (44 00 00 02|02 00 00 44) sc
+.*: (7c 83 28 30|30 28 83 7c) slw r3,r4,r5
+.*: (7c 83 28 31|31 28 83 7c) slw\. r3,r4,r5
+.*: (7c 83 2e 30|30 2e 83 7c) sraw r3,r4,r5
+.*: (7c 83 2e 31|31 2e 83 7c) sraw\. r3,r4,r5
+.*: (7c 83 86 70|70 86 83 7c) srawi r3,r4,16
+.*: (7c 83 86 71|71 86 83 7c) srawi\. r3,r4,16
+.*: (7c 83 2c 30|30 2c 83 7c) srw r3,r4,r5
+.*: (7c 83 2c 31|31 2c 83 7c) srw\. r3,r4,r5
+.*: (54 83 d1 be|be d1 83 54) rlwinm r3,r4,26,6,31
+.*: (99 61 00 02|02 00 61 99) stb r11,2\(r1\)
+.*: (9d 81 00 03|03 00 81 9d) stbu r12,3\(r1\)
+.*: (7d ae 79 ee|ee 79 ae 7d) stbux r13,r14,r15
+.*: (7c 64 29 ae|ae 29 64 7c) stbx r3,r4,r5
+.*: (db 21 00 20|20 00 21 db) stfd f25,32\(r1\)
+.*: (df 41 00 28|28 00 41 df) stfdu f26,40\(r1\)
+.*: (7c 01 15 ee|ee 15 01 7c) stfdux f0,r1,r2
+.*: (7f be fd ae|ae fd be 7f) stfdx f29,r30,r31
+.*: (7d 43 27 ae|ae 27 43 7d) stfiwx f10,r3,r4
+.*: (d2 e1 00 14|14 00 e1 d2) stfs f23,20\(r1\)
+.*: (d7 01 00 18|18 00 01 d7) stfsu f24,24\(r1\)
+.*: (7f 5b e5 6e|6e e5 5b 7f) stfsux f26,r27,r28
+.*: (7e f8 cd 2e|2e cd f8 7e) stfsx f23,r24,r25
+.*: (b2 21 00 0a|0a 00 21 b2) sth r17,10\(r1\)
+.*: (7c c7 47 2c|2c 47 c7 7c) sthbrx r6,r7,r8
+.*: (b6 41 00 0c|0c 00 41 b6) sthu r18,12\(r1\)
+.*: (7e b6 bb 6e|6e bb b6 7e) sthux r21,r22,r23
+.*: (7d 8d 73 2e|2e 73 8d 7d) sthx r12,r13,r14
+.*: (90 c7 ff f0|f0 ff c7 90) stw r6,-16\(r7\)
+.*: (7c 64 2d 2c|2c 2d 64 7c) stwbrx r3,r4,r5
+.*: (7c 64 29 2d|2d 29 64 7c) stwcx\. r3,r4,r5
+.*: (94 61 00 10|10 00 61 94) stwu r3,16\(r1\)
+.*: (7c 64 29 6e|6e 29 64 7c) stwux r3,r4,r5
+.*: (7c 64 29 2e|2e 29 64 7c) stwx r3,r4,r5
+.*: (7c 64 28 50|50 28 64 7c) subf r3,r4,r5
+.*: (7c 64 28 51|51 28 64 7c) subf\. r3,r4,r5
+.*: (7c 64 28 10|10 28 64 7c) subfc r3,r4,r5
+.*: (7c 64 28 11|11 28 64 7c) subfc\. r3,r4,r5
+.*: (7c 64 2c 10|10 2c 64 7c) subfco r3,r4,r5
+.*: (7c 64 2c 11|11 2c 64 7c) subfco\. r3,r4,r5
+.*: (7c 64 29 10|10 29 64 7c) subfe r3,r4,r5
+.*: (7c 64 29 11|11 29 64 7c) subfe\. r3,r4,r5
+.*: (7c 64 2d 10|10 2d 64 7c) subfeo r3,r4,r5
+.*: (7c 64 2d 11|11 2d 64 7c) subfeo\. r3,r4,r5
+.*: (20 64 00 05|05 00 64 20) subfic r3,r4,5
+.*: (7c 64 01 d0|d0 01 64 7c) subfme r3,r4
+.*: (7c 64 01 d1|d1 01 64 7c) subfme\. r3,r4
+.*: (7c 64 05 d0|d0 05 64 7c) subfmeo r3,r4
+.*: (7c 64 05 d1|d1 05 64 7c) subfmeo\. r3,r4
+.*: (7c 64 2c 50|50 2c 64 7c) subfo r3,r4,r5
+.*: (7c 64 2c 51|51 2c 64 7c) subfo\. r3,r4,r5
+.*: (7c 64 01 90|90 01 64 7c) subfze r3,r4
+.*: (7c 64 01 91|91 01 64 7c) subfze\. r3,r4
+.*: (7c 64 05 90|90 05 64 7c) subfzeo r3,r4
+.*: (7c 64 05 91|91 05 64 7c) subfzeo\. r3,r4
+.*: (7c 07 46 24|24 46 07 7c) tlbivax r7,r8
+.*: (7c 22 3f 64|64 3f 22 7c) tlbre r1,r2,7
+.*: (7c 0b 67 24|24 67 0b 7c) tlbsx r11,r12
+.*: (7d 8d 77 24|24 77 8d 7d) tlbsx r12,r13,r14
+.*: (7d 8d 77 25|25 77 8d 7d) tlbsx\. r12,r13,r14
+.*: (7c 00 04 6c|6c 04 00 7c) tlbsync
+.*: (7c 00 07 a4|a4 07 00 7c) tlbwe
+.*: (7c 00 07 a4|a4 07 00 7c) tlbwe
+.*: (7c 21 0f a4|a4 0f 21 7c) tlbwe r1,r1,1
+.*: (7f e0 00 08|08 00 e0 7f) trap
+.*: (7f e0 00 08|08 00 e0 7f) trap
+.*: (7c 83 20 08|08 20 83 7c) tweq r3,r4
+.*: (7c a3 20 08|08 20 a3 7c) twlge r3,r4
+.*: (7c 83 20 08|08 20 83 7c) tweq r3,r4
+.*: (0d 03 00 0f|0f 00 03 0d) twgti r3,15
+.*: (0c c3 00 0f|0f 00 c3 0c) twllei r3,15
+.*: (0d 03 00 0f|0f 00 03 0d) twgti r3,15
+.*: (7c a3 20 08|08 20 a3 7c) twlge r3,r4
+.*: (0c c3 00 0f|0f 00 c3 0c) twllei r3,15
+.*: (7c 60 01 06|06 01 60 7c) wrtee r3
+.*: (7c 00 81 46|46 81 00 7c) wrteei 1
+.*: (7f dd fa 78|78 fa dd 7f) xor r29,r30,r31
+.*: (7f dd fa 79|79 fa dd 7f) xor\. r29,r30,r31
+.*: (68 83 de ad|ad de 83 68) xori r3,r4,57005
+.*: (6c 83 de ad|ad de 83 6c) xoris r3,r4,57005
diff -rup binutils.orig/gas/testsuite/gas/ppc/476.s binutils-2.35.1/gas/testsuite/gas/ppc/476.s
--- binutils.orig/gas/testsuite/gas/ppc/476.s 2020-10-08 13:50:31.310909797 +0100
+++ binutils-2.35.1/gas/testsuite/gas/ppc/476.s 2020-10-08 13:51:29.102731857 +0100
@@ -226,9 +226,6 @@ ppc476:
lhzu 14,2(1)
lhzux 20,22,24
lhzx 23,24,25
- lmw 3,-16(1)
- lswi 5,4,16
- lswx 3,4,5
lwarx 3,4,5
lwarx 3,4,5,0
lwarx 3,4,5,1
@@ -433,9 +430,6 @@ ppc476:
sthu 18,12(1)
sthux 21,22,23
sthx 12,13,14
- stmw 6,-16(1)
- stswi 3,4,16
- stswx 3,4,5
stw 6,-16(7)
stwbrx 3,4,5
stwcx. 3,4,5
diff -rup binutils.orig/gas/testsuite/gas/ppc/a2.d binutils-2.35.1/gas/testsuite/gas/ppc/a2.d
--- binutils.orig/gas/testsuite/gas/ppc/a2.d 2020-10-08 13:50:31.314909784 +0100
+++ binutils-2.35.1/gas/testsuite/gas/ppc/a2.d 2020-10-08 13:51:29.102731857 +0100
@@ -9,577 +9,569 @@
Disassembly of section \.text:
0+00 <start>:
- 0: (7c 85 32 15|15 32 85 7c) add\. r4,r5,r6
- 4: (7c 85 32 14|14 32 85 7c) add r4,r5,r6
- 8: (7c 85 30 15|15 30 85 7c) addc\. r4,r5,r6
- c: (7c 85 30 14|14 30 85 7c) addc r4,r5,r6
- 10: (7c 85 34 15|15 34 85 7c) addco\. r4,r5,r6
- 14: (7c 85 34 14|14 34 85 7c) addco r4,r5,r6
- 18: (7c 85 31 15|15 31 85 7c) adde\. r4,r5,r6
- 1c: (7c 85 31 14|14 31 85 7c) adde r4,r5,r6
- 20: (7c 85 35 15|15 35 85 7c) addeo\. r4,r5,r6
- 24: (7c 85 35 14|14 35 85 7c) addeo r4,r5,r6
- 28: (38 85 00 0d|0d 00 85 38) addi r4,r5,13
- 2c: (38 85 ff f3|f3 ff 85 38) addi r4,r5,-13
- 30: (34 85 00 0d|0d 00 85 34) addic\. r4,r5,13
- 34: (34 85 ff f3|f3 ff 85 34) addic\. r4,r5,-13
- 38: (30 85 00 0d|0d 00 85 30) addic r4,r5,13
- 3c: (30 85 ff f3|f3 ff 85 30) addic r4,r5,-13
- 40: (3c 85 00 17|17 00 85 3c) addis r4,r5,23
- 44: (3c 85 ff e9|e9 ff 85 3c) addis r4,r5,-23
- 48: (7c 85 01 d5|d5 01 85 7c) addme\. r4,r5
- 4c: (7c 85 01 d4|d4 01 85 7c) addme r4,r5
- 50: (7c 85 05 d5|d5 05 85 7c) addmeo\. r4,r5
- 54: (7c 85 05 d4|d4 05 85 7c) addmeo r4,r5
- 58: (7c 85 36 15|15 36 85 7c) addo\. r4,r5,r6
- 5c: (7c 85 36 14|14 36 85 7c) addo r4,r5,r6
- 60: (7c 85 01 95|95 01 85 7c) addze\. r4,r5
- 64: (7c 85 01 94|94 01 85 7c) addze r4,r5
- 68: (7c 85 05 95|95 05 85 7c) addzeo\. r4,r5
- 6c: (7c 85 05 94|94 05 85 7c) addzeo r4,r5
- 70: (7c a4 30 39|39 30 a4 7c) and\. r4,r5,r6
- 74: (7c a4 30 38|38 30 a4 7c) and r4,r5,r6
- 78: (7c a4 30 79|79 30 a4 7c) andc\. r4,r5,r6
- 7c: (7c a4 30 78|78 30 a4 7c) andc r4,r5,r6
- 80: (70 a4 00 06|06 00 a4 70) andi\. r4,r5,6
- 84: (74 a4 00 06|06 00 a4 74) andis\. r4,r5,6
- 88: (00 00 02 00|00 02 00 00) attn
- 8c: (48 00 00 02|02 00 00 48) ba 0 <start>
- 8c: R_PPC(|64)_ADDR24 label_abs
- 90: (40 8a 00 00|00 00 8a 40) bne cr2,90 <start\+0x90>
- 90: R_PPC(|64)_REL14 foo
- 94: (40 ca 00 00|00 00 ca 40) bne- cr2,94 <start\+0x94>
- 94: R_PPC(|64)_REL14 foo
- 98: (40 ea 00 00|00 00 ea 40) bne\+ cr2,98 <start\+0x98>
- 98: R_PPC(|64)_REL14 foo
- 9c: (40 85 00 02|02 00 85 40) blea cr1,0 <start>
- 9c: R_PPC(|64)_ADDR14 foo_abs
- a0: (40 c5 00 02|02 00 c5 40) blea- cr1,0 <start>
- a0: R_PPC(|64)_ADDR14 foo_abs
- a4: (40 e5 00 02|02 00 e5 40) blea\+ cr1,0 <start>
- a4: R_PPC(|64)_ADDR14 foo_abs
- a8: (4c 86 0c 20|20 0c 86 4c) bcctr 4,4\*cr1\+eq,1
- ac: (4c c6 04 20|20 04 c6 4c) bnectr- cr1
- b0: (4c e6 04 20|20 04 e6 4c) bnectr\+ cr1
- b4: (4c 86 0c 21|21 0c 86 4c) bcctrl 4,4\*cr1\+eq,1
- b8: (4c c6 04 21|21 04 c6 4c) bnectrl- cr1
- bc: (4c e6 04 21|21 04 e6 4c) bnectrl\+ cr1
- c0: (40 8a 00 01|01 00 8a 40) bnel cr2,c0 <start\+0xc0>
- c0: R_PPC(|64)_REL14 foo
- c4: (40 ca 00 01|01 00 ca 40) bnel- cr2,c4 <start\+0xc4>
- c4: R_PPC(|64)_REL14 foo
- c8: (40 ea 00 01|01 00 ea 40) bnel\+ cr2,c8 <start\+0xc8>
- c8: R_PPC(|64)_REL14 foo
- cc: (40 85 00 03|03 00 85 40) blela cr1,0 <start>
- cc: R_PPC(|64)_ADDR14 foo_abs
- d0: (40 c5 00 03|03 00 c5 40) blela- cr1,0 <start>
- d0: R_PPC(|64)_ADDR14 foo_abs
- d4: (40 e5 00 03|03 00 e5 40) blela\+ cr1,0 <start>
- d4: R_PPC(|64)_ADDR14 foo_abs
- d8: (4c 86 08 20|20 08 86 4c) bclr 4,4\*cr1\+eq,1
- dc: (4c c6 00 20|20 00 c6 4c) bnelr- cr1
- e0: (4c e6 00 20|20 00 e6 4c) bnelr\+ cr1
- e4: (4c 86 08 21|21 08 86 4c) bclrl 4,4\*cr1\+eq,1
- e8: (4c c6 00 21|21 00 c6 4c) bnelrl- cr1
- ec: (4c e6 00 21|21 00 e6 4c) bnelrl\+ cr1
- f0: (48 00 00 00|00 00 00 48) b f0 <start\+0xf0>
- f0: R_PPC(|64)_REL24 label
- f4: (48 00 00 03|03 00 00 48) bla 0 <start>
- f4: R_PPC(|64)_ADDR24 label_abs
- f8: (48 00 00 01|01 00 00 48) bl f8 <start\+0xf8>
- f8: R_PPC(|64)_REL24 label
- fc: (7d 6a 61 f8|f8 61 6a 7d) bpermd r10,r11,r12
- 100: (7c a7 40 00|00 40 a7 7c) cmpd cr1,r7,r8
- 104: (7d 6a 63 f8|f8 63 6a 7d) cmpb r10,r11,r12
- 108: (2c aa 00 0d|0d 00 aa 2c) cmpdi cr1,r10,13
- 10c: (2c aa ff f3|f3 ff aa 2c) cmpdi cr1,r10,-13
- 110: (7c a7 40 40|40 40 a7 7c) cmpld cr1,r7,r8
- 114: (28 aa 00 64|64 00 aa 28) cmpldi cr1,r10,100
- 118: (7e b4 00 75|75 00 b4 7e) cntlzd\. r20,r21
- 11c: (7e b4 00 74|74 00 b4 7e) cntlzd r20,r21
- 120: (7e b4 00 35|35 00 b4 7e) cntlzw\. r20,r21
- 124: (7e b4 00 34|34 00 b4 7e) cntlzw r20,r21
- 128: (4c 22 1a 02|02 1a 22 4c) crand gt,eq,so
- 12c: (4c 22 19 02|02 19 22 4c) crandc gt,eq,so
- 130: (4c 22 1a 42|42 1a 22 4c) creqv gt,eq,so
- 134: (4c 22 19 c2|c2 19 22 4c) crnand gt,eq,so
- 138: (4c 22 18 42|42 18 22 4c) crnor gt,eq,so
- 13c: (4c 22 1b 82|82 1b 22 4c) cror gt,eq,so
- 140: (4c 22 1b 42|42 1b 22 4c) crorc gt,eq,so
- 144: (4c 22 19 82|82 19 22 4c) crxor gt,eq,so
- 148: (7c 0a 5d ec|ec 5d 0a 7c) dcba r10,r11
- 14c: (7c 0a 58 ac|ac 58 0a 7c) dcbf r10,r11
- 150: (7c 2a 58 ac|ac 58 2a 7c) dcbfl r10,r11
- 154: (7c 0a 58 fe|fe 58 0a 7c) dcbfep r10,r11
- 158: (7c 0a 5b ac|ac 5b 0a 7c) dcbi r10,r11
- 15c: (7c 0a 5b 0c|0c 5b 0a 7c) dcblc r10,r11
- 160: (7c 2a 5b 0c|0c 5b 2a 7c) dcblc 1,r10,r11
- 164: (7c 0a 58 6c|6c 58 0a 7c) dcbst r10,r11
- 168: (7c 0a 58 7e|7e 58 0a 7c) dcbstep r10,r11
- 16c: (7c 0a 5a 2c|2c 5a 0a 7c) dcbt r10,r11
- 170: (7c 2a 5a 2c|2c 5a 2a 7c) dcbt 1,r10,r11
- 174: (7d 4b 62 7e|7e 62 4b 7d) dcbtep r10,r11,r12
- 178: (7c 0a 59 4c|4c 59 0a 7c) dcbtls r10,r11
- 17c: (7c 2a 59 4c|4c 59 2a 7c) dcbtls 1,r10,r11
- 180: (7c 0a 59 ec|ec 59 0a 7c) dcbtst r10,r11
- 184: (7c 2a 59 ec|ec 59 2a 7c) dcbtst 1,r10,r11
- 188: (7d 4b 61 fe|fe 61 4b 7d) dcbtstep r10,r11,r12
- 18c: (7c 0a 59 0c|0c 59 0a 7c) dcbtstls r10,r11
- 190: (7c 2a 59 0c|0c 59 2a 7c) dcbtstls 1,r10,r11
- 194: (7c 0a 5f ec|ec 5f 0a 7c) dcbz r10,r11
- 198: (7c 0a 5f fe|fe 5f 0a 7c) dcbzep r10,r11
- 19c: (7c 00 03 8c|8c 03 00 7c) dccci
- 1a0: (7c 00 03 8c|8c 03 00 7c) dccci
- 1a4: (7c 00 03 8c|8c 03 00 7c) dccci
- 1a8: (7d 40 03 8c|8c 03 40 7d) dci 10
- 1ac: (7e 95 b3 d3|d3 b3 95 7e) divd\. r20,r21,r22
- 1b0: (7e 95 b3 d2|d2 b3 95 7e) divd r20,r21,r22
- 1b4: (7e 95 b7 d3|d3 b7 95 7e) divdo\. r20,r21,r22
- 1b8: (7e 95 b7 d2|d2 b7 95 7e) divdo r20,r21,r22
- 1bc: (7e 95 b3 93|93 b3 95 7e) divdu\. r20,r21,r22
- 1c0: (7e 95 b3 92|92 b3 95 7e) divdu r20,r21,r22
- 1c4: (7e 95 b7 93|93 b7 95 7e) divduo\. r20,r21,r22
- 1c8: (7e 95 b7 92|92 b7 95 7e) divduo r20,r21,r22
- 1cc: (7e 95 b3 d7|d7 b3 95 7e) divw\. r20,r21,r22
- 1d0: (7e 95 b3 d6|d6 b3 95 7e) divw r20,r21,r22
- 1d4: (7e 95 b7 d7|d7 b7 95 7e) divwo\. r20,r21,r22
- 1d8: (7e 95 b7 d6|d6 b7 95 7e) divwo r20,r21,r22
- 1dc: (7e 95 b3 97|97 b3 95 7e) divwu\. r20,r21,r22
- 1e0: (7e 95 b3 96|96 b3 95 7e) divwu r20,r21,r22
- 1e4: (7e 95 b7 97|97 b7 95 7e) divwuo\. r20,r21,r22
- 1e8: (7e 95 b7 96|96 b7 95 7e) divwuo r20,r21,r22
- 1ec: (7e b4 b2 39|39 b2 b4 7e) eqv\. r20,r21,r22
- 1f0: (7e b4 b2 38|38 b2 b4 7e) eqv r20,r21,r22
- 1f4: (7c 0a 58 66|66 58 0a 7c) eratilx 0,r10,r11
- 1f8: (7c 2a 58 66|66 58 2a 7c) eratilx 1,r10,r11
- 1fc: (7c ea 58 66|66 58 ea 7c) eratilx 7,r10,r11
- 200: (7d 4b 66 66|66 66 4b 7d) erativax r10,r11,r12
- 204: (7d 4b 01 66|66 01 4b 7d) eratre r10,r11,0
- 208: (7d 4b 19 66|66 19 4b 7d) eratre r10,r11,3
- 20c: (7d 4b 61 27|27 61 4b 7d) eratsx\. r10,r11,r12
- 210: (7d 4b 61 26|26 61 4b 7d) eratsx r10,r11,r12
- 214: (7d 4b 01 a6|a6 01 4b 7d) eratwe r10,r11,0
- 218: (7d 4b 19 a6|a6 19 4b 7d) eratwe r10,r11,3
- 21c: (7d 6a 07 75|75 07 6a 7d) extsb\. r10,r11
- 220: (7d 6a 07 74|74 07 6a 7d) extsb r10,r11
- 224: (7d 6a 07 35|35 07 6a 7d) extsh\. r10,r11
- 228: (7d 6a 07 34|34 07 6a 7d) extsh r10,r11
- 22c: (7d 6a 07 b5|b5 07 6a 7d) extsw\. r10,r11
- 230: (7d 6a 07 b4|b4 07 6a 7d) extsw r10,r11
- 234: (fe 80 aa 11|11 aa 80 fe) fabs\. f20,f21
- 238: (fe 80 aa 10|10 aa 80 fe) fabs f20,f21
- 23c: (fe 95 b0 2b|2b b0 95 fe) fadd\. f20,f21,f22
- 240: (fe 95 b0 2a|2a b0 95 fe) fadd f20,f21,f22
- 244: (ee 95 b0 2b|2b b0 95 ee) fadds\. f20,f21,f22
- 248: (ee 95 b0 2a|2a b0 95 ee) fadds f20,f21,f22
- 24c: (fe 80 ae 9d|9d ae 80 fe) fcfid\. f20,f21
- 250: (fe 80 ae 9c|9c ae 80 fe) fcfid f20,f21
- 254: (fc 14 a8 40|40 a8 14 fc) fcmpo cr0,f20,f21
- 258: (fc 94 a8 40|40 a8 94 fc) fcmpo cr1,f20,f21
- 25c: (fc 14 a8 00|00 a8 14 fc) fcmpu cr0,f20,f21
- 260: (fc 94 a8 00|00 a8 94 fc) fcmpu cr1,f20,f21
- 264: (fe 95 b0 11|11 b0 95 fe) fcpsgn\. f20,f21,f22
- 268: (fe 95 b0 10|10 b0 95 fe) fcpsgn f20,f21,f22
- 26c: (fe 80 ae 5d|5d ae 80 fe) fctid\. f20,f21
- 270: (fe 80 ae 5c|5c ae 80 fe) fctid f20,f21
- 274: (fe 80 ae 5f|5f ae 80 fe) fctidz\. f20,f21
- 278: (fe 80 ae 5e|5e ae 80 fe) fctidz f20,f21
- 27c: (fe 80 a8 1d|1d a8 80 fe) fctiw\. f20,f21
- 280: (fe 80 a8 1c|1c a8 80 fe) fctiw f20,f21
- 284: (fe 80 a8 1f|1f a8 80 fe) fctiwz\. f20,f21
- 288: (fe 80 a8 1e|1e a8 80 fe) fctiwz f20,f21
- 28c: (fe 95 b0 25|25 b0 95 fe) fdiv\. f20,f21,f22
- 290: (fe 95 b0 24|24 b0 95 fe) fdiv f20,f21,f22
- 294: (ee 95 b0 25|25 b0 95 ee) fdivs\. f20,f21,f22
- 298: (ee 95 b0 24|24 b0 95 ee) fdivs f20,f21,f22
- 29c: (fe 95 bd bb|bb bd 95 fe) fmadd\. f20,f21,f22,f23
- 2a0: (fe 95 bd ba|ba bd 95 fe) fmadd f20,f21,f22,f23
- 2a4: (ee 95 bd bb|bb bd 95 ee) fmadds\. f20,f21,f22,f23
- 2a8: (ee 95 bd ba|ba bd 95 ee) fmadds f20,f21,f22,f23
- 2ac: (fe 80 a8 91|91 a8 80 fe) fmr\. f20,f21
- 2b0: (fe 80 a8 90|90 a8 80 fe) fmr f20,f21
- 2b4: (fe 95 bd b9|b9 bd 95 fe) fmsub\. f20,f21,f22,f23
- 2b8: (fe 95 bd b8|b8 bd 95 fe) fmsub f20,f21,f22,f23
- 2bc: (ee 95 bd b9|b9 bd 95 ee) fmsubs\. f20,f21,f22,f23
- 2c0: (ee 95 bd b8|b8 bd 95 ee) fmsubs f20,f21,f22,f23
- 2c4: (fe 95 05 b3|b3 05 95 fe) fmul\. f20,f21,f22
- 2c8: (fe 95 05 b2|b2 05 95 fe) fmul f20,f21,f22
- 2cc: (ee 95 05 b3|b3 05 95 ee) fmuls\. f20,f21,f22
- 2d0: (ee 95 05 b2|b2 05 95 ee) fmuls f20,f21,f22
- 2d4: (fe 80 a9 11|11 a9 80 fe) fnabs\. f20,f21
- 2d8: (fe 80 a9 10|10 a9 80 fe) fnabs f20,f21
- 2dc: (fe 80 a8 51|51 a8 80 fe) fneg\. f20,f21
- 2e0: (fe 80 a8 50|50 a8 80 fe) fneg f20,f21
- 2e4: (fe 95 bd bf|bf bd 95 fe) fnmadd\. f20,f21,f22,f23
- 2e8: (fe 95 bd be|be bd 95 fe) fnmadd f20,f21,f22,f23
- 2ec: (ee 95 bd bf|bf bd 95 ee) fnmadds\. f20,f21,f22,f23
- 2f0: (ee 95 bd be|be bd 95 ee) fnmadds f20,f21,f22,f23
- 2f4: (fe 95 bd bd|bd bd 95 fe) fnmsub\. f20,f21,f22,f23
- 2f8: (fe 95 bd bc|bc bd 95 fe) fnmsub f20,f21,f22,f23
- 2fc: (ee 95 bd bd|bd bd 95 ee) fnmsubs\. f20,f21,f22,f23
- 300: (ee 95 bd bc|bc bd 95 ee) fnmsubs f20,f21,f22,f23
- 304: (fe 80 a8 31|31 a8 80 fe) fre\. f20,f21
- 308: (fe 80 a8 30|30 a8 80 fe) fre f20,f21
- 30c: (fe 80 a8 31|31 a8 80 fe) fre\. f20,f21
- 310: (fe 80 a8 30|30 a8 80 fe) fre f20,f21
- 314: (fe 81 a8 31|31 a8 81 fe) fre\. f20,f21,1
- 318: (fe 81 a8 30|30 a8 81 fe) fre f20,f21,1
- 31c: (ee 80 a8 31|31 a8 80 ee) fres\. f20,f21
- 320: (ee 80 a8 30|30 a8 80 ee) fres f20,f21
- 324: (ee 80 a8 31|31 a8 80 ee) fres\. f20,f21
- 328: (ee 80 a8 30|30 a8 80 ee) fres f20,f21
- 32c: (ee 81 a8 31|31 a8 81 ee) fres\. f20,f21,1
- 330: (ee 81 a8 30|30 a8 81 ee) fres f20,f21,1
- 334: (fe 80 ab d1|d1 ab 80 fe) frim\. f20,f21
- 338: (fe 80 ab d0|d0 ab 80 fe) frim f20,f21
- 33c: (fe 80 ab 11|11 ab 80 fe) frin\. f20,f21
- 340: (fe 80 ab 10|10 ab 80 fe) frin f20,f21
- 344: (fe 80 ab 91|91 ab 80 fe) frip\. f20,f21
- 348: (fe 80 ab 90|90 ab 80 fe) frip f20,f21
- 34c: (fe 80 ab 51|51 ab 80 fe) friz\. f20,f21
- 350: (fe 80 ab 50|50 ab 80 fe) friz f20,f21
- 354: (fe 80 a8 19|19 a8 80 fe) frsp\. f20,f21
- 358: (fe 80 a8 18|18 a8 80 fe) frsp f20,f21
- 35c: (fe 80 a8 35|35 a8 80 fe) frsqrte\. f20,f21
- 360: (fe 80 a8 34|34 a8 80 fe) frsqrte f20,f21
- 364: (fe 80 a8 35|35 a8 80 fe) frsqrte\. f20,f21
- 368: (fe 80 a8 34|34 a8 80 fe) frsqrte f20,f21
- 36c: (fe 81 a8 35|35 a8 81 fe) frsqrte\. f20,f21,1
- 370: (fe 81 a8 34|34 a8 81 fe) frsqrte f20,f21,1
- 374: (ee 80 a8 34|34 a8 80 ee) frsqrtes f20,f21
- 378: (ee 80 a8 35|35 a8 80 ee) frsqrtes\. f20,f21
- 37c: (ee 80 a8 34|34 a8 80 ee) frsqrtes f20,f21
- 380: (ee 80 a8 35|35 a8 80 ee) frsqrtes\. f20,f21
- 384: (ee 81 a8 34|34 a8 81 ee) frsqrtes f20,f21,1
- 388: (ee 81 a8 35|35 a8 81 ee) frsqrtes\. f20,f21,1
- 38c: (fe 95 bd af|af bd 95 fe) fsel\. f20,f21,f22,f23
- 390: (fe 95 bd ae|ae bd 95 fe) fsel f20,f21,f22,f23
- 394: (fe 80 a8 2d|2d a8 80 fe) fsqrt\. f20,f21
- 398: (fe 80 a8 2c|2c a8 80 fe) fsqrt f20,f21
- 39c: (ee 80 a8 2d|2d a8 80 ee) fsqrts\. f20,f21
- 3a0: (ee 80 a8 2c|2c a8 80 ee) fsqrts f20,f21
- 3a4: (fe 95 b0 29|29 b0 95 fe) fsub\. f20,f21,f22
- 3a8: (fe 95 b0 28|28 b0 95 fe) fsub f20,f21,f22
- 3ac: (ee 95 b0 29|29 b0 95 ee) fsubs\. f20,f21,f22
- 3b0: (ee 95 b0 28|28 b0 95 ee) fsubs f20,f21,f22
- 3b4: (7c 0a 5f ac|ac 5f 0a 7c) icbi r10,r11
- 3b8: (7c 0a 5f be|be 5f 0a 7c) icbiep r10,r11
- 3bc: (7c 0a 58 2c|2c 58 0a 7c) icbt r10,r11
- 3c0: (7c ea 58 2c|2c 58 ea 7c) icbt 7,r10,r11
- 3c4: (7c 0a 5b cc|cc 5b 0a 7c) icbtls r10,r11
- 3c8: (7c ea 5b cc|cc 5b ea 7c) icbtls 7,r10,r11
- 3cc: (7c 00 07 8c|8c 07 00 7c) iccci
- 3d0: (7c 00 07 8c|8c 07 00 7c) iccci
- 3d4: (7c 00 07 8c|8c 07 00 7c) iccci
- 3d8: (7d 40 07 8c|8c 07 40 7d) ici 10
- 3dc: (7d 4b 63 2d|2d 63 4b 7d) icswx\. r10,r11,r12
- 3e0: (7d 4b 63 2c|2c 63 4b 7d) icswx r10,r11,r12
- 3e4: (7d 4b 65 de|de 65 4b 7d) isel r10,r11,r12,23
- 3e8: (4c 00 01 2c|2c 01 00 4c) isync
- 3ec: (7d 4b 60 be|be 60 4b 7d) lbepx r10,r11,r12
- 3f0: (89 4b ff ef|ef ff 4b 89) lbz r10,-17\(r11\)
- 3f4: (89 4b 00 11|11 00 4b 89) lbz r10,17\(r11\)
- 3f8: (8d 4b ff ff|ff ff 4b 8d) lbzu r10,-1\(r11\)
- 3fc: (8d 4b 00 01|01 00 4b 8d) lbzu r10,1\(r11\)
- 400: (7d 4b 68 ee|ee 68 4b 7d) lbzux r10,r11,r13
- 404: (7d 4b 68 ae|ae 68 4b 7d) lbzx r10,r11,r13
- 408: (e9 4b ff f8|f8 ff 4b e9) ld r10,-8\(r11\)
- 40c: (e9 4b 00 08|08 00 4b e9) ld r10,8\(r11\)
- 410: (7d 4b 60 a8|a8 60 4b 7d) ldarx r10,r11,r12
- 414: (7d 4b 60 a9|a9 60 4b 7d) ldarx r10,r11,r12,1
- 418: (7d 4b 64 28|28 64 4b 7d) ldbrx r10,r11,r12
- 41c: (7d 4b 60 3a|3a 60 4b 7d) ldepx r10,r11,r12
- 420: (e9 4b ff f9|f9 ff 4b e9) ldu r10,-8\(r11\)
- 424: (e9 4b 00 09|09 00 4b e9) ldu r10,8\(r11\)
- 428: (7d 4b 60 6a|6a 60 4b 7d) ldux r10,r11,r12
- 42c: (7d 4b 60 2a|2a 60 4b 7d) ldx r10,r11,r12
- 430: (ca 8a ff f8|f8 ff 8a ca) lfd f20,-8\(r10\)
- 434: (ca 8a 00 08|08 00 8a ca) lfd f20,8\(r10\)
- 438: (7e 8a 5c be|be 5c 8a 7e) lfdepx f20,r10,r11
- 43c: (ce 8a ff f8|f8 ff 8a ce) lfdu f20,-8\(r10\)
- 440: (ce 8a 00 08|08 00 8a ce) lfdu f20,8\(r10\)
- 444: (7e 8a 5c ee|ee 5c 8a 7e) lfdux f20,r10,r11
- 448: (7e 8a 5c ae|ae 5c 8a 7e) lfdx f20,r10,r11
- 44c: (7e 8a 5e ae|ae 5e 8a 7e) lfiwax f20,r10,r11
- 450: (7e 8a 5e ee|ee 5e 8a 7e) lfiwzx f20,r10,r11
- 454: (c2 8a ff fc|fc ff 8a c2) lfs f20,-4\(r10\)
- 458: (c2 8a 00 04|04 00 8a c2) lfs f20,4\(r10\)
- 45c: (c6 8a ff fc|fc ff 8a c6) lfsu f20,-4\(r10\)
- 460: (c6 8a 00 04|04 00 8a c6) lfsu f20,4\(r10\)
- 464: (7e 8a 5c 6e|6e 5c 8a 7e) lfsux f20,r10,r11
- 468: (7e 8a 5c 2e|2e 5c 8a 7e) lfsx f20,r10,r11
- 46c: (a9 4b 00 02|02 00 4b a9) lha r10,2\(r11\)
- 470: (ad 4b ff fe|fe ff 4b ad) lhau r10,-2\(r11\)
- 474: (7d 4b 62 ee|ee 62 4b 7d) lhaux r10,r11,r12
- 478: (7d 4b 62 ae|ae 62 4b 7d) lhax r10,r11,r12
- 47c: (7d 4b 66 2c|2c 66 4b 7d) lhbrx r10,r11,r12
- 480: (7d 4b 62 3e|3e 62 4b 7d) lhepx r10,r11,r12
- 484: (a1 4b ff fe|fe ff 4b a1) lhz r10,-2\(r11\)
- 488: (a1 4b 00 02|02 00 4b a1) lhz r10,2\(r11\)
- 48c: (a5 4b ff fe|fe ff 4b a5) lhzu r10,-2\(r11\)
- 490: (a5 4b 00 02|02 00 4b a5) lhzu r10,2\(r11\)
- 494: (7d 4b 62 6e|6e 62 4b 7d) lhzux r10,r11,r12
- 498: (7d 4b 62 2e|2e 62 4b 7d) lhzx r10,r11,r12
- 49c: (ba 8a 00 10|10 00 8a ba) lmw r20,16\(r10\)
- 4a0: (7d 4b 0c aa|aa 0c 4b 7d) lswi r10,r11,1
- 4a4: (7d 8b 04 aa|aa 04 8b 7d) lswi r12,r11,32
- 4a8: (7d 4b 64 2a|2a 64 4b 7d) lswx r10,r11,r12
- 4ac: (e9 4b ff fe|fe ff 4b e9) lwa r10,-4\(r11\)
- 4b0: (e9 4b 00 06|06 00 4b e9) lwa r10,4\(r11\)
- 4b4: (7d 4b 60 28|28 60 4b 7d) lwarx r10,r11,r12
- 4b8: (7d 4b 60 29|29 60 4b 7d) lwarx r10,r11,r12,1
- 4bc: (7d 4b 62 ea|ea 62 4b 7d) lwaux r10,r11,r12
- 4c0: (7d 4b 62 aa|aa 62 4b 7d) lwax r10,r11,r12
- 4c4: (7d 4b 64 2c|2c 64 4b 7d) lwbrx r10,r11,r12
- 4c8: (7d 4b 60 3e|3e 60 4b 7d) lwepx r10,r11,r12
- 4cc: (81 4b ff fc|fc ff 4b 81) lwz r10,-4\(r11\)
- 4d0: (81 4b 00 04|04 00 4b 81) lwz r10,4\(r11\)
- 4d4: (85 4b ff fc|fc ff 4b 85) lwzu r10,-4\(r11\)
- 4d8: (85 4b 00 04|04 00 4b 85) lwzu r10,4\(r11\)
- 4dc: (7d 4b 60 6e|6e 60 4b 7d) lwzux r10,r11,r12
- 4e0: (7d 4b 60 2e|2e 60 4b 7d) lwzx r10,r11,r12
- 4e4: (7c 00 06 ac|ac 06 00 7c) mbar
- 4e8: (7c 00 06 ac|ac 06 00 7c) mbar
- 4ec: (7c 00 06 ac|ac 06 00 7c) mbar
- 4f0: (7c 20 06 ac|ac 06 20 7c) mbar 1
- 4f4: (4c 04 00 00|00 00 04 4c) mcrf cr0,cr1
- 4f8: (fd 90 00 80|80 00 90 fd) mcrfs cr3,cr4
- 4fc: (7c 00 04 00|00 04 00 7c) mcrxr cr0
- 500: (7d 80 04 00|00 04 80 7d) mcrxr cr3
- 504: (7c 60 00 26|26 00 60 7c) mfcr r3
- 508: (7c 70 20 26|26 20 70 7c) mfocrf r3,2
- 50c: (7c 70 10 26|26 10 70 7c) mfocrf r3,1
- 510: (7c 78 00 26|26 00 78 7c) mfocrf r3,128
- 514: (7d 4a 3a 87|87 3a 4a 7d) mfdcr\. r10,234
- 518: (7d 4a 3a 86|86 3a 4a 7d) mfdcr r10,234
- 51c: (7d 4b 02 07|07 02 4b 7d) mfdcrx\. r10,r11
- 520: (7d 4b 02 06|06 02 4b 7d) mfdcrx r10,r11
- 524: (fe 80 04 8f|8f 04 80 fe) mffs\. f20
- 528: (fe 80 04 8e|8e 04 80 fe) mffs f20
- 52c: (7d 40 00 a6|a6 00 40 7d) mfmsr r10
- 530: (7c 70 10 26|26 10 70 7c) mfocrf r3,1
- 534: (7c 78 00 26|26 00 78 7c) mfocrf r3,128
- 538: (7d 4a 3a a6|a6 3a 4a 7d) mfspr r10,234
- 53c: (7d 4c 42 a6|a6 42 4c 7d) mftb r10
- 540: (7d 4d 42 a6|a6 42 4d 7d) mftbu r10
- 544: (7c 00 51 dc|dc 51 00 7c) msgclr r10
- 548: (7c 00 51 9c|9c 51 00 7c) msgsnd r10
- 54c: (7c 60 01 20|20 01 60 7c) mtcrf 0,r3
- 550: (7c 70 11 20|20 11 70 7c) mtocrf 1,r3
- 554: (7c 78 01 20|20 01 78 7c) mtocrf 128,r3
- 558: (7c 6f f1 20|20 f1 6f 7c) mtcr r3
- 55c: (7d 4a 3b 87|87 3b 4a 7d) mtdcr\. 234,r10
- 560: (7d 4a 3b 86|86 3b 4a 7d) mtdcr 234,r10
- 564: (7d 6a 03 07|07 03 6a 7d) mtdcrx\. r10,r11
- 568: (7d 6a 03 06|06 03 6a 7d) mtdcrx r10,r11
- 56c: (fc 60 00 8d|8d 00 60 fc) mtfsb0\. 3
- 570: (fc 60 00 8c|8c 00 60 fc) mtfsb0 3
- 574: (fc 60 00 4d|4d 00 60 fc) mtfsb1\. 3
- 578: (fc 60 00 4c|4c 00 60 fc) mtfsb1 3
- 57c: (fc 0c a5 8f|8f a5 0c fc) mtfsf\. 6,f20
- 580: (fc 0c a5 8e|8e a5 0c fc) mtfsf 6,f20
- 584: (fc 0c a5 8f|8f a5 0c fc) mtfsf\. 6,f20
- 588: (fc 0c a5 8e|8e a5 0c fc) mtfsf 6,f20
- 58c: (fe 0d a5 8f|8f a5 0d fe) mtfsf\. 6,f20,1,1
- 590: (fe 0d a5 8e|8e a5 0d fe) mtfsf 6,f20,1,1
- 594: (ff 00 01 0d|0d 01 00 ff) mtfsfi\. 6,0
- 598: (ff 00 01 0c|0c 01 00 ff) mtfsfi 6,0
- 59c: (ff 00 d1 0d|0d d1 00 ff) mtfsfi\. 6,13
- 5a0: (ff 00 d1 0c|0c d1 00 ff) mtfsfi 6,13
- 5a4: (ff 01 d1 0d|0d d1 01 ff) mtfsfi\. 6,13,1
- 5a8: (ff 01 d1 0c|0c d1 01 ff) mtfsfi 6,13,1
- 5ac: (7d 40 01 24|24 01 40 7d) mtmsr r10
- 5b0: (7d 40 01 24|24 01 40 7d) mtmsr r10
- 5b4: (7d 41 01 24|24 01 41 7d) mtmsr r10,1
- 5b8: (7c 70 11 20|20 11 70 7c) mtocrf 1,r3
- 5bc: (7c 78 01 20|20 01 78 7c) mtocrf 128,r3
- 5c0: (7d 4a 3b a6|a6 3b 4a 7d) mtspr 234,r10
- 5c4: (7e 95 b0 93|93 b0 95 7e) mulhd\. r20,r21,r22
- 5c8: (7e 95 b0 92|92 b0 95 7e) mulhd r20,r21,r22
- 5cc: (7e 95 b0 13|13 b0 95 7e) mulhdu\. r20,r21,r22
- 5d0: (7e 95 b0 12|12 b0 95 7e) mulhdu r20,r21,r22
- 5d4: (7e 95 b0 97|97 b0 95 7e) mulhw\. r20,r21,r22
- 5d8: (7e 95 b0 96|96 b0 95 7e) mulhw r20,r21,r22
- 5dc: (7e 95 b0 17|17 b0 95 7e) mulhwu\. r20,r21,r22
- 5e0: (7e 95 b0 16|16 b0 95 7e) mulhwu r20,r21,r22
- 5e4: (7e 95 b1 d3|d3 b1 95 7e) mulld\. r20,r21,r22
- 5e8: (7e 95 b1 d2|d2 b1 95 7e) mulld r20,r21,r22
- 5ec: (7e 95 b5 d3|d3 b5 95 7e) mulldo\. r20,r21,r22
- 5f0: (7e 95 b5 d2|d2 b5 95 7e) mulldo r20,r21,r22
- 5f4: (1e 95 00 64|64 00 95 1e) mulli r20,r21,100
- 5f8: (1e 95 ff 9c|9c ff 95 1e) mulli r20,r21,-100
- 5fc: (7e 95 b1 d7|d7 b1 95 7e) mullw\. r20,r21,r22
- 600: (7e 95 b1 d6|d6 b1 95 7e) mullw r20,r21,r22
- 604: (7e 95 b5 d7|d7 b5 95 7e) mullwo\. r20,r21,r22
- 608: (7e 95 b5 d6|d6 b5 95 7e) mullwo r20,r21,r22
- 60c: (7e b4 b3 b9|b9 b3 b4 7e) nand\. r20,r21,r22
- 610: (7e b4 b3 b8|b8 b3 b4 7e) nand r20,r21,r22
- 614: (7e 95 00 d1|d1 00 95 7e) neg\. r20,r21
- 618: (7e 95 00 d0|d0 00 95 7e) neg r20,r21
- 61c: (7e 95 04 d1|d1 04 95 7e) nego\. r20,r21
- 620: (7e 95 04 d0|d0 04 95 7e) nego r20,r21
- 624: (7e b4 b0 f9|f9 b0 b4 7e) nor\. r20,r21,r22
- 628: (7e b4 b0 f8|f8 b0 b4 7e) nor r20,r21,r22
- 62c: (7e b4 b3 79|79 b3 b4 7e) or\. r20,r21,r22
- 630: (7e b4 b3 78|78 b3 b4 7e) or r20,r21,r22
- 634: (7e b4 b3 39|39 b3 b4 7e) orc\. r20,r21,r22
- 638: (7e b4 b3 38|38 b3 b4 7e) orc r20,r21,r22
- 63c: (62 b4 10 00|00 10 b4 62) ori r20,r21,4096
- 640: (66 b4 10 00|00 10 b4 66) oris r20,r21,4096
- 644: (7d 6a 00 f4|f4 00 6a 7d) popcntb r10,r11
- 648: (7d 6a 03 f4|f4 03 6a 7d) popcntd r10,r11
- 64c: (7d 6a 02 f4|f4 02 6a 7d) popcntw r10,r11
- 650: (7d 6a 01 74|74 01 6a 7d) prtyd r10,r11
- 654: (7d 6a 01 34|34 01 6a 7d) prtyw r10,r11
- 658: (4c 00 00 66|66 00 00 4c) rfci
- 65c: (4c 00 00 cc|cc 00 00 4c) rfgi
- 660: (4c 00 00 64|64 00 00 4c) rfi
- 664: (4c 00 00 4c|4c 00 00 4c) rfmci
- 668: (79 6a 67 f1|f1 67 6a 79) rldcl\. r10,r11,r12,63
- 66c: (79 6a 67 f0|f0 67 6a 79) rldcl r10,r11,r12,63
- 670: (79 6a 67 f3|f3 67 6a 79) rldcr\. r10,r11,r12,63
- 674: (79 6a 67 f2|f2 67 6a 79) rldcr r10,r11,r12,63
- 678: (79 6a bf e9|e9 bf 6a 79) rldic\. r10,r11,23,63
- 67c: (79 6a bf e8|e8 bf 6a 79) rldic r10,r11,23,63
- 680: (79 6a bf e1|e1 bf 6a 79) rldicl\. r10,r11,23,63
- 684: (79 6a bf e0|e0 bf 6a 79) rldicl r10,r11,23,63
- 688: (79 6a bf e5|e5 bf 6a 79) rldicr\. r10,r11,23,63
- 68c: (79 6a bf e4|e4 bf 6a 79) rldicr r10,r11,23,63
- 690: (79 6a bf ed|ed bf 6a 79) rldimi\. r10,r11,23,63
- 694: (79 6a bf ec|ec bf 6a 79) rldimi r10,r11,23,63
- 698: (51 6a b8 3f|3f b8 6a 51) rlwimi\. r10,r11,23,0,31
- 69c: (51 6a b8 3e|3e b8 6a 51) rlwimi r10,r11,23,0,31
- 6a0: (55 6a b8 3f|3f b8 6a 55) rotlwi\. r10,r11,23
- 6a4: (55 6a b8 3e|3e b8 6a 55) rotlwi r10,r11,23
- 6a8: (5d 6a b8 3f|3f b8 6a 5d) rotlw\. r10,r11,r23
- 6ac: (5d 6a b8 3e|3e b8 6a 5d) rotlw r10,r11,r23
- 6b0: (44 00 00 02|02 00 00 44) sc
- 6b4: (44 00 0c 82|82 0c 00 44) sc 100
- 6b8: (7d 6a 60 37|37 60 6a 7d) sld\. r10,r11,r12
- 6bc: (7d 6a 60 36|36 60 6a 7d) sld r10,r11,r12
- 6c0: (7d 6a 60 31|31 60 6a 7d) slw\. r10,r11,r12
- 6c4: (7d 6a 60 30|30 60 6a 7d) slw r10,r11,r12
- 6c8: (7d 6a 66 35|35 66 6a 7d) srad\. r10,r11,r12
- 6cc: (7d 6a 66 34|34 66 6a 7d) srad r10,r11,r12
- 6d0: (7d 6a fe 77|77 fe 6a 7d) sradi\. r10,r11,63
- 6d4: (7d 6a fe 76|76 fe 6a 7d) sradi r10,r11,63
- 6d8: (7d 6a 66 31|31 66 6a 7d) sraw\. r10,r11,r12
- 6dc: (7d 6a 66 30|30 66 6a 7d) sraw r10,r11,r12
- 6e0: (7d 6a fe 71|71 fe 6a 7d) srawi\. r10,r11,31
- 6e4: (7d 6a fe 70|70 fe 6a 7d) srawi r10,r11,31
- 6e8: (7d 6a 64 37|37 64 6a 7d) srd\. r10,r11,r12
- 6ec: (7d 6a 64 36|36 64 6a 7d) srd r10,r11,r12
- 6f0: (7d 6a 64 31|31 64 6a 7d) srw\. r10,r11,r12
- 6f4: (7d 6a 64 30|30 64 6a 7d) srw r10,r11,r12
- 6f8: (99 4b ff ff|ff ff 4b 99) stb r10,-1\(r11\)
- 6fc: (99 4b 00 01|01 00 4b 99) stb r10,1\(r11\)
- 700: (7d 4b 61 be|be 61 4b 7d) stbepx r10,r11,r12
- 704: (9d 4b ff ff|ff ff 4b 9d) stbu r10,-1\(r11\)
- 708: (9d 4b 00 01|01 00 4b 9d) stbu r10,1\(r11\)
- 70c: (7d 4b 61 ee|ee 61 4b 7d) stbux r10,r11,r12
- 710: (7d 4b 61 ae|ae 61 4b 7d) stbx r10,r11,r12
- 714: (f9 4b ff f8|f8 ff 4b f9) std r10,-8\(r11\)
- 718: (f9 4b 00 08|08 00 4b f9) std r10,8\(r11\)
- 71c: (7d 4b 65 28|28 65 4b 7d) stdbrx r10,r11,r12
- 720: (7d 4b 61 ad|ad 61 4b 7d) stdcx\. r10,r11,r12
- 724: (7d 4b 61 3a|3a 61 4b 7d) stdepx r10,r11,r12
- 728: (f9 4b ff f9|f9 ff 4b f9) stdu r10,-8\(r11\)
- 72c: (f9 4b 00 09|09 00 4b f9) stdu r10,8\(r11\)
- 730: (7d 4b 61 6a|6a 61 4b 7d) stdux r10,r11,r12
- 734: (7d 4b 61 2a|2a 61 4b 7d) stdx r10,r11,r12
- 738: (da 8a ff f8|f8 ff 8a da) stfd f20,-8\(r10\)
- 73c: (da 8a 00 08|08 00 8a da) stfd f20,8\(r10\)
- 740: (7e 8a 5d be|be 5d 8a 7e) stfdepx f20,r10,r11
- 744: (de 8a ff f8|f8 ff 8a de) stfdu f20,-8\(r10\)
- 748: (de 8a 00 08|08 00 8a de) stfdu f20,8\(r10\)
- 74c: (7e 8a 5d ee|ee 5d 8a 7e) stfdux f20,r10,r11
- 750: (7e 8a 5d ae|ae 5d 8a 7e) stfdx f20,r10,r11
- 754: (7e 8a 5f ae|ae 5f 8a 7e) stfiwx f20,r10,r11
- 758: (d2 8a ff fc|fc ff 8a d2) stfs f20,-4\(r10\)
- 75c: (d2 8a 00 04|04 00 8a d2) stfs f20,4\(r10\)
- 760: (d6 8a ff fc|fc ff 8a d6) stfsu f20,-4\(r10\)
- 764: (d6 8a 00 04|04 00 8a d6) stfsu f20,4\(r10\)
- 768: (7e 8a 5d 6e|6e 5d 8a 7e) stfsux f20,r10,r11
- 76c: (7e 8a 5d 2e|2e 5d 8a 7e) stfsx f20,r10,r11
- 770: (b1 4b ff fe|fe ff 4b b1) sth r10,-2\(r11\)
- 774: (b1 4b 00 02|02 00 4b b1) sth r10,2\(r11\)
- 778: (b1 4b ff fc|fc ff 4b b1) sth r10,-4\(r11\)
- 77c: (b1 4b 00 04|04 00 4b b1) sth r10,4\(r11\)
- 780: (7d 4b 67 2c|2c 67 4b 7d) sthbrx r10,r11,r12
- 784: (7d 4b 63 3e|3e 63 4b 7d) sthepx r10,r11,r12
- 788: (b5 4b ff fe|fe ff 4b b5) sthu r10,-2\(r11\)
- 78c: (b5 4b 00 02|02 00 4b b5) sthu r10,2\(r11\)
- 790: (7d 4b 63 6e|6e 63 4b 7d) sthux r10,r11,r12
- 794: (7d 4b 63 2e|2e 63 4b 7d) sthx r10,r11,r12
- 798: (be 8a 00 10|10 00 8a be) stmw r20,16\(r10\)
- 79c: (7d 4b 0d aa|aa 0d 4b 7d) stswi r10,r11,1
- 7a0: (7d 4b 05 aa|aa 05 4b 7d) stswi r10,r11,32
- 7a4: (7d 4b 65 2a|2a 65 4b 7d) stswx r10,r11,r12
- 7a8: (7d 4b 65 2c|2c 65 4b 7d) stwbrx r10,r11,r12
- 7ac: (7d 4b 61 2d|2d 61 4b 7d) stwcx\. r10,r11,r12
- 7b0: (7d 4b 61 3e|3e 61 4b 7d) stwepx r10,r11,r12
- 7b4: (95 4b ff fc|fc ff 4b 95) stwu r10,-4\(r11\)
- 7b8: (95 4b 00 04|04 00 4b 95) stwu r10,4\(r11\)
- 7bc: (7d 4b 61 6e|6e 61 4b 7d) stwux r10,r11,r12
- 7c0: (7d 4b 61 2e|2e 61 4b 7d) stwx r10,r11,r12
- 7c4: (7e 95 b0 51|51 b0 95 7e) subf\. r20,r21,r22
- 7c8: (7e 95 b0 50|50 b0 95 7e) subf r20,r21,r22
- 7cc: (7e 95 b0 11|11 b0 95 7e) subfc\. r20,r21,r22
- 7d0: (7e 95 b0 10|10 b0 95 7e) subfc r20,r21,r22
- 7d4: (7e 95 b4 11|11 b4 95 7e) subfco\. r20,r21,r22
- 7d8: (7e 95 b4 10|10 b4 95 7e) subfco r20,r21,r22
- 7dc: (7e 95 b1 11|11 b1 95 7e) subfe\. r20,r21,r22
- 7e0: (7e 95 b1 10|10 b1 95 7e) subfe r20,r21,r22
- 7e4: (7e 95 b5 11|11 b5 95 7e) subfeo\. r20,r21,r22
- 7e8: (7e 95 b5 10|10 b5 95 7e) subfeo r20,r21,r22
- 7ec: (22 95 00 64|64 00 95 22) subfic r20,r21,100
- 7f0: (22 95 ff 9c|9c ff 95 22) subfic r20,r21,-100
- 7f4: (7e 95 01 d1|d1 01 95 7e) subfme\. r20,r21
- 7f8: (7e 95 01 d0|d0 01 95 7e) subfme r20,r21
- 7fc: (7e 95 05 d1|d1 05 95 7e) subfmeo\. r20,r21
- 800: (7e 95 05 d0|d0 05 95 7e) subfmeo r20,r21
- 804: (7e 95 b4 51|51 b4 95 7e) subfo\. r20,r21,r22
- 808: (7e 95 b4 50|50 b4 95 7e) subfo r20,r21,r22
- 80c: (7e 95 01 91|91 01 95 7e) subfze\. r20,r21
- 810: (7e 95 01 90|90 01 95 7e) subfze r20,r21
- 814: (7e 95 05 91|91 05 95 7e) subfzeo\. r20,r21
- 818: (7e 95 05 90|90 05 95 7e) subfzeo r20,r21
- 81c: (7c 00 04 ac|ac 04 00 7c) hwsync
- 820: (7c 00 04 ac|ac 04 00 7c) hwsync
- 824: (7c 00 04 ac|ac 04 00 7c) hwsync
- 828: (7c 20 04 ac|ac 04 20 7c) lwsync
- 82c: (7c aa 58 88|88 58 aa 7c) tdlge r10,r11
- 830: (08 aa 00 64|64 00 aa 08) tdlgei r10,100
- 834: (08 aa ff 9c|9c ff aa 08) tdlgei r10,-100
- 838: (7c 6a 58 24|24 58 6a 7c) tlbilxva r10,r11
- 83c: (7c 0a 5e 24|24 5e 0a 7c) tlbivax r10,r11
- 840: (7c 00 07 64|64 07 00 7c) tlbre
- 844: (7d 4b 3f 64|64 3f 4b 7d) tlbre r10,r11,7
- 848: (7c 0a 5e a5|a5 5e 0a 7c) tlbsrx\. r10,r11
- 84c: (7d 4b 67 25|25 67 4b 7d) tlbsx\. r10,r11,r12
- 850: (7d 4b 67 24|24 67 4b 7d) tlbsx r10,r11,r12
- 854: (7c 00 04 6c|6c 04 00 7c) tlbsync
- 858: (7c 00 07 a4|a4 07 00 7c) tlbwe
- 85c: (7d 4b 3f a4|a4 3f 4b 7d) tlbwe r10,r11,7
- 860: (7c aa 58 08|08 58 aa 7c) twlge r10,r11
- 864: (0c aa 00 64|64 00 aa 0c) twlgei r10,100
- 868: (0c aa ff 9c|9c ff aa 0c) twlgei r10,-100
- 86c: (7c 00 00 7c|7c 00 00 7c) wait
- 870: (7c 00 00 7c|7c 00 00 7c) wait
- 874: (7c 20 00 7c|7c 00 20 7c) waitrsv
- 878: (7c 40 00 7c|7c 00 40 7c) waitimpl
- 87c: (7c 40 00 7c|7c 00 40 7c) waitimpl
- 880: (7c 20 00 7c|7c 00 20 7c) waitrsv
- 884: (7c 00 01 6c|6c 01 00 7c) wchkall
- 888: (7c 00 01 6c|6c 01 00 7c) wchkall
- 88c: (7d 80 01 6c|6c 01 80 7d) wchkall cr3
- 890: (7c 2a 5f 4c|4c 5f 2a 7c) wclr 1,r10,r11
- 894: (7c 20 07 4c|4c 07 20 7c) wclrall 1
- 898: (7c 4a 5f 4c|4c 5f 4a 7c) wclrone r10,r11
- 89c: (7d 40 01 06|06 01 40 7d) wrtee r10
- 8a0: (7c 00 81 46|46 81 00 7c) wrteei 1
- 8a4: (7d 6a 62 79|79 62 6a 7d) xor\. r10,r11,r12
- 8a8: (7d 6a 62 78|78 62 6a 7d) xor r10,r11,r12
- 8ac: (69 6a 10 00|00 10 6a 69) xori r10,r11,4096
- 8b0: (6d 6a 10 00|00 10 6a 6d) xoris r10,r11,4096
+.*: (7c 85 32 15|15 32 85 7c) add\. r4,r5,r6
+.*: (7c 85 32 14|14 32 85 7c) add r4,r5,r6
+.*: (7c 85 30 15|15 30 85 7c) addc\. r4,r5,r6
+.*: (7c 85 30 14|14 30 85 7c) addc r4,r5,r6
+.*: (7c 85 34 15|15 34 85 7c) addco\. r4,r5,r6
+.*: (7c 85 34 14|14 34 85 7c) addco r4,r5,r6
+.*: (7c 85 31 15|15 31 85 7c) adde\. r4,r5,r6
+.*: (7c 85 31 14|14 31 85 7c) adde r4,r5,r6
+.*: (7c 85 35 15|15 35 85 7c) addeo\. r4,r5,r6
+.*: (7c 85 35 14|14 35 85 7c) addeo r4,r5,r6
+.*: (38 85 00 0d|0d 00 85 38) addi r4,r5,13
+.*: (38 85 ff f3|f3 ff 85 38) addi r4,r5,-13
+.*: (34 85 00 0d|0d 00 85 34) addic\. r4,r5,13
+.*: (34 85 ff f3|f3 ff 85 34) addic\. r4,r5,-13
+.*: (30 85 00 0d|0d 00 85 30) addic r4,r5,13
+.*: (30 85 ff f3|f3 ff 85 30) addic r4,r5,-13
+.*: (3c 85 00 17|17 00 85 3c) addis r4,r5,23
+.*: (3c 85 ff e9|e9 ff 85 3c) addis r4,r5,-23
+.*: (7c 85 01 d5|d5 01 85 7c) addme\. r4,r5
+.*: (7c 85 01 d4|d4 01 85 7c) addme r4,r5
+.*: (7c 85 05 d5|d5 05 85 7c) addmeo\. r4,r5
+.*: (7c 85 05 d4|d4 05 85 7c) addmeo r4,r5
+.*: (7c 85 36 15|15 36 85 7c) addo\. r4,r5,r6
+.*: (7c 85 36 14|14 36 85 7c) addo r4,r5,r6
+.*: (7c 85 01 95|95 01 85 7c) addze\. r4,r5
+.*: (7c 85 01 94|94 01 85 7c) addze r4,r5
+.*: (7c 85 05 95|95 05 85 7c) addzeo\. r4,r5
+.*: (7c 85 05 94|94 05 85 7c) addzeo r4,r5
+.*: (7c a4 30 39|39 30 a4 7c) and\. r4,r5,r6
+.*: (7c a4 30 38|38 30 a4 7c) and r4,r5,r6
+.*: (7c a4 30 79|79 30 a4 7c) andc\. r4,r5,r6
+.*: (7c a4 30 78|78 30 a4 7c) andc r4,r5,r6
+.*: (70 a4 00 06|06 00 a4 70) andi\. r4,r5,6
+.*: (74 a4 00 06|06 00 a4 74) andis\. r4,r5,6
+.*: (00 00 02 00|00 02 00 00) attn
+.*: (48 00 00 02|02 00 00 48) ba 0 <start>
+.*: R_PPC(|64)_ADDR24 label_abs
+.*: (40 8a 00 00|00 00 8a 40) bne cr2,90 <start\+0x90>
+.*: R_PPC(|64)_REL14 foo
+.*: (40 ca 00 00|00 00 ca 40) bne- cr2,94 <start\+0x94>
+.*: R_PPC(|64)_REL14 foo
+.*: (40 ea 00 00|00 00 ea 40) bne\+ cr2,98 <start\+0x98>
+.*: R_PPC(|64)_REL14 foo
+.*: (40 85 00 02|02 00 85 40) blea cr1,0 <start>
+.*: R_PPC(|64)_ADDR14 foo_abs
+.*: (40 c5 00 02|02 00 c5 40) blea- cr1,0 <start>
+.*: R_PPC(|64)_ADDR14 foo_abs
+.*: (40 e5 00 02|02 00 e5 40) blea\+ cr1,0 <start>
+.*: R_PPC(|64)_ADDR14 foo_abs
+.*: (4c 86 0c 20|20 0c 86 4c) bcctr 4,4\*cr1\+eq,1
+.*: (4c c6 04 20|20 04 c6 4c) bnectr- cr1
+.*: (4c e6 04 20|20 04 e6 4c) bnectr\+ cr1
+.*: (4c 86 0c 21|21 0c 86 4c) bcctrl 4,4\*cr1\+eq,1
+.*: (4c c6 04 21|21 04 c6 4c) bnectrl- cr1
+.*: (4c e6 04 21|21 04 e6 4c) bnectrl\+ cr1
+.*: (40 8a 00 01|01 00 8a 40) bnel cr2,c0 <start\+0xc0>
+.*: R_PPC(|64)_REL14 foo
+.*: (40 ca 00 01|01 00 ca 40) bnel- cr2,c4 <start\+0xc4>
+.*: R_PPC(|64)_REL14 foo
+.*: (40 ea 00 01|01 00 ea 40) bnel\+ cr2,c8 <start\+0xc8>
+.*: R_PPC(|64)_REL14 foo
+.*: (40 85 00 03|03 00 85 40) blela cr1,0 <start>
+.*: R_PPC(|64)_ADDR14 foo_abs
+.*: (40 c5 00 03|03 00 c5 40) blela- cr1,0 <start>
+.*: R_PPC(|64)_ADDR14 foo_abs
+.*: (40 e5 00 03|03 00 e5 40) blela\+ cr1,0 <start>
+.*: R_PPC(|64)_ADDR14 foo_abs
+.*: (4c 86 08 20|20 08 86 4c) bclr 4,4\*cr1\+eq,1
+.*: (4c c6 00 20|20 00 c6 4c) bnelr- cr1
+.*: (4c e6 00 20|20 00 e6 4c) bnelr\+ cr1
+.*: (4c 86 08 21|21 08 86 4c) bclrl 4,4\*cr1\+eq,1
+.*: (4c c6 00 21|21 00 c6 4c) bnelrl- cr1
+.*: (4c e6 00 21|21 00 e6 4c) bnelrl\+ cr1
+.*: (48 00 00 00|00 00 00 48) b f0 <start\+0xf0>
+.*: R_PPC(|64)_REL24 label
+.*: (48 00 00 03|03 00 00 48) bla 0 <start>
+.*: R_PPC(|64)_ADDR24 label_abs
+.*: (48 00 00 01|01 00 00 48) bl f8 <start\+0xf8>
+.*: R_PPC(|64)_REL24 label
+.*: (7d 6a 61 f8|f8 61 6a 7d) bpermd r10,r11,r12
+.*: (7c a7 40 00|00 40 a7 7c) cmpd cr1,r7,r8
+.*: (7d 6a 63 f8|f8 63 6a 7d) cmpb r10,r11,r12
+.*: (2c aa 00 0d|0d 00 aa 2c) cmpdi cr1,r10,13
+.*: (2c aa ff f3|f3 ff aa 2c) cmpdi cr1,r10,-13
+.*: (7c a7 40 40|40 40 a7 7c) cmpld cr1,r7,r8
+.*: (28 aa 00 64|64 00 aa 28) cmpldi cr1,r10,100
+.*: (7e b4 00 75|75 00 b4 7e) cntlzd\. r20,r21
+.*: (7e b4 00 74|74 00 b4 7e) cntlzd r20,r21
+.*: (7e b4 00 35|35 00 b4 7e) cntlzw\. r20,r21
+.*: (7e b4 00 34|34 00 b4 7e) cntlzw r20,r21
+.*: (4c 22 1a 02|02 1a 22 4c) crand gt,eq,so
+.*: (4c 22 19 02|02 19 22 4c) crandc gt,eq,so
+.*: (4c 22 1a 42|42 1a 22 4c) creqv gt,eq,so
+.*: (4c 22 19 c2|c2 19 22 4c) crnand gt,eq,so
+.*: (4c 22 18 42|42 18 22 4c) crnor gt,eq,so
+.*: (4c 22 1b 82|82 1b 22 4c) cror gt,eq,so
+.*: (4c 22 1b 42|42 1b 22 4c) crorc gt,eq,so
+.*: (4c 22 19 82|82 19 22 4c) crxor gt,eq,so
+.*: (7c 0a 5d ec|ec 5d 0a 7c) dcba r10,r11
+.*: (7c 0a 58 ac|ac 58 0a 7c) dcbf r10,r11
+.*: (7c 2a 58 ac|ac 58 2a 7c) dcbfl r10,r11
+.*: (7c 0a 58 fe|fe 58 0a 7c) dcbfep r10,r11
+.*: (7c 0a 5b ac|ac 5b 0a 7c) dcbi r10,r11
+.*: (7c 0a 5b 0c|0c 5b 0a 7c) dcblc r10,r11
+.*: (7c 2a 5b 0c|0c 5b 2a 7c) dcblc 1,r10,r11
+.*: (7c 0a 58 6c|6c 58 0a 7c) dcbst r10,r11
+.*: (7c 0a 58 7e|7e 58 0a 7c) dcbstep r10,r11
+.*: (7c 0a 5a 2c|2c 5a 0a 7c) dcbt r10,r11
+.*: (7c 2a 5a 2c|2c 5a 2a 7c) dcbt 1,r10,r11
+.*: (7d 4b 62 7e|7e 62 4b 7d) dcbtep r10,r11,r12
+.*: (7c 0a 59 4c|4c 59 0a 7c) dcbtls r10,r11
+.*: (7c 2a 59 4c|4c 59 2a 7c) dcbtls 1,r10,r11
+.*: (7c 0a 59 ec|ec 59 0a 7c) dcbtst r10,r11
+.*: (7c 2a 59 ec|ec 59 2a 7c) dcbtst 1,r10,r11
+.*: (7d 4b 61 fe|fe 61 4b 7d) dcbtstep r10,r11,r12
+.*: (7c 0a 59 0c|0c 59 0a 7c) dcbtstls r10,r11
+.*: (7c 2a 59 0c|0c 59 2a 7c) dcbtstls 1,r10,r11
+.*: (7c 0a 5f ec|ec 5f 0a 7c) dcbz r10,r11
+.*: (7c 0a 5f fe|fe 5f 0a 7c) dcbzep r10,r11
+.*: (7c 00 03 8c|8c 03 00 7c) dccci
+.*: (7c 00 03 8c|8c 03 00 7c) dccci
+.*: (7c 00 03 8c|8c 03 00 7c) dccci
+.*: (7d 40 03 8c|8c 03 40 7d) dci 10
+.*: (7e 95 b3 d3|d3 b3 95 7e) divd\. r20,r21,r22
+.*: (7e 95 b3 d2|d2 b3 95 7e) divd r20,r21,r22
+.*: (7e 95 b7 d3|d3 b7 95 7e) divdo\. r20,r21,r22
+.*: (7e 95 b7 d2|d2 b7 95 7e) divdo r20,r21,r22
+.*: (7e 95 b3 93|93 b3 95 7e) divdu\. r20,r21,r22
+.*: (7e 95 b3 92|92 b3 95 7e) divdu r20,r21,r22
+.*: (7e 95 b7 93|93 b7 95 7e) divduo\. r20,r21,r22
+.*: (7e 95 b7 92|92 b7 95 7e) divduo r20,r21,r22
+.*: (7e 95 b3 d7|d7 b3 95 7e) divw\. r20,r21,r22
+.*: (7e 95 b3 d6|d6 b3 95 7e) divw r20,r21,r22
+.*: (7e 95 b7 d7|d7 b7 95 7e) divwo\. r20,r21,r22
+.*: (7e 95 b7 d6|d6 b7 95 7e) divwo r20,r21,r22
+.*: (7e 95 b3 97|97 b3 95 7e) divwu\. r20,r21,r22
+.*: (7e 95 b3 96|96 b3 95 7e) divwu r20,r21,r22
+.*: (7e 95 b7 97|97 b7 95 7e) divwuo\. r20,r21,r22
+.*: (7e 95 b7 96|96 b7 95 7e) divwuo r20,r21,r22
+.*: (7e b4 b2 39|39 b2 b4 7e) eqv\. r20,r21,r22
+.*: (7e b4 b2 38|38 b2 b4 7e) eqv r20,r21,r22
+.*: (7c 0a 58 66|66 58 0a 7c) eratilx 0,r10,r11
+.*: (7c 2a 58 66|66 58 2a 7c) eratilx 1,r10,r11
+.*: (7c ea 58 66|66 58 ea 7c) eratilx 7,r10,r11
+.*: (7d 4b 66 66|66 66 4b 7d) erativax r10,r11,r12
+.*: (7d 4b 01 66|66 01 4b 7d) eratre r10,r11,0
+.*: (7d 4b 19 66|66 19 4b 7d) eratre r10,r11,3
+.*: (7d 4b 61 27|27 61 4b 7d) eratsx\. r10,r11,r12
+.*: (7d 4b 61 26|26 61 4b 7d) eratsx r10,r11,r12
+.*: (7d 4b 01 a6|a6 01 4b 7d) eratwe r10,r11,0
+.*: (7d 4b 19 a6|a6 19 4b 7d) eratwe r10,r11,3
+.*: (7d 6a 07 75|75 07 6a 7d) extsb\. r10,r11
+.*: (7d 6a 07 74|74 07 6a 7d) extsb r10,r11
+.*: (7d 6a 07 35|35 07 6a 7d) extsh\. r10,r11
+.*: (7d 6a 07 34|34 07 6a 7d) extsh r10,r11
+.*: (7d 6a 07 b5|b5 07 6a 7d) extsw\. r10,r11
+.*: (7d 6a 07 b4|b4 07 6a 7d) extsw r10,r11
+.*: (fe 80 aa 11|11 aa 80 fe) fabs\. f20,f21
+.*: (fe 80 aa 10|10 aa 80 fe) fabs f20,f21
+.*: (fe 95 b0 2b|2b b0 95 fe) fadd\. f20,f21,f22
+.*: (fe 95 b0 2a|2a b0 95 fe) fadd f20,f21,f22
+.*: (ee 95 b0 2b|2b b0 95 ee) fadds\. f20,f21,f22
+.*: (ee 95 b0 2a|2a b0 95 ee) fadds f20,f21,f22
+.*: (fe 80 ae 9d|9d ae 80 fe) fcfid\. f20,f21
+.*: (fe 80 ae 9c|9c ae 80 fe) fcfid f20,f21
+.*: (fc 14 a8 40|40 a8 14 fc) fcmpo cr0,f20,f21
+.*: (fc 94 a8 40|40 a8 94 fc) fcmpo cr1,f20,f21
+.*: (fc 14 a8 00|00 a8 14 fc) fcmpu cr0,f20,f21
+.*: (fc 94 a8 00|00 a8 94 fc) fcmpu cr1,f20,f21
+.*: (fe 95 b0 11|11 b0 95 fe) fcpsgn\. f20,f21,f22
+.*: (fe 95 b0 10|10 b0 95 fe) fcpsgn f20,f21,f22
+.*: (fe 80 ae 5d|5d ae 80 fe) fctid\. f20,f21
+.*: (fe 80 ae 5c|5c ae 80 fe) fctid f20,f21
+.*: (fe 80 ae 5f|5f ae 80 fe) fctidz\. f20,f21
+.*: (fe 80 ae 5e|5e ae 80 fe) fctidz f20,f21
+.*: (fe 80 a8 1d|1d a8 80 fe) fctiw\. f20,f21
+.*: (fe 80 a8 1c|1c a8 80 fe) fctiw f20,f21
+.*: (fe 80 a8 1f|1f a8 80 fe) fctiwz\. f20,f21
+.*: (fe 80 a8 1e|1e a8 80 fe) fctiwz f20,f21
+.*: (fe 95 b0 25|25 b0 95 fe) fdiv\. f20,f21,f22
+.*: (fe 95 b0 24|24 b0 95 fe) fdiv f20,f21,f22
+.*: (ee 95 b0 25|25 b0 95 ee) fdivs\. f20,f21,f22
+.*: (ee 95 b0 24|24 b0 95 ee) fdivs f20,f21,f22
+.*: (fe 95 bd bb|bb bd 95 fe) fmadd\. f20,f21,f22,f23
+.*: (fe 95 bd ba|ba bd 95 fe) fmadd f20,f21,f22,f23
+.*: (ee 95 bd bb|bb bd 95 ee) fmadds\. f20,f21,f22,f23
+.*: (ee 95 bd ba|ba bd 95 ee) fmadds f20,f21,f22,f23
+.*: (fe 80 a8 91|91 a8 80 fe) fmr\. f20,f21
+.*: (fe 80 a8 90|90 a8 80 fe) fmr f20,f21
+.*: (fe 95 bd b9|b9 bd 95 fe) fmsub\. f20,f21,f22,f23
+.*: (fe 95 bd b8|b8 bd 95 fe) fmsub f20,f21,f22,f23
+.*: (ee 95 bd b9|b9 bd 95 ee) fmsubs\. f20,f21,f22,f23
+.*: (ee 95 bd b8|b8 bd 95 ee) fmsubs f20,f21,f22,f23
+.*: (fe 95 05 b3|b3 05 95 fe) fmul\. f20,f21,f22
+.*: (fe 95 05 b2|b2 05 95 fe) fmul f20,f21,f22
+.*: (ee 95 05 b3|b3 05 95 ee) fmuls\. f20,f21,f22
+.*: (ee 95 05 b2|b2 05 95 ee) fmuls f20,f21,f22
+.*: (fe 80 a9 11|11 a9 80 fe) fnabs\. f20,f21
+.*: (fe 80 a9 10|10 a9 80 fe) fnabs f20,f21
+.*: (fe 80 a8 51|51 a8 80 fe) fneg\. f20,f21
+.*: (fe 80 a8 50|50 a8 80 fe) fneg f20,f21
+.*: (fe 95 bd bf|bf bd 95 fe) fnmadd\. f20,f21,f22,f23
+.*: (fe 95 bd be|be bd 95 fe) fnmadd f20,f21,f22,f23
+.*: (ee 95 bd bf|bf bd 95 ee) fnmadds\. f20,f21,f22,f23
+.*: (ee 95 bd be|be bd 95 ee) fnmadds f20,f21,f22,f23
+.*: (fe 95 bd bd|bd bd 95 fe) fnmsub\. f20,f21,f22,f23
+.*: (fe 95 bd bc|bc bd 95 fe) fnmsub f20,f21,f22,f23
+.*: (ee 95 bd bd|bd bd 95 ee) fnmsubs\. f20,f21,f22,f23
+.*: (ee 95 bd bc|bc bd 95 ee) fnmsubs f20,f21,f22,f23
+.*: (fe 80 a8 31|31 a8 80 fe) fre\. f20,f21
+.*: (fe 80 a8 30|30 a8 80 fe) fre f20,f21
+.*: (fe 80 a8 31|31 a8 80 fe) fre\. f20,f21
+.*: (fe 80 a8 30|30 a8 80 fe) fre f20,f21
+.*: (fe 81 a8 31|31 a8 81 fe) fre\. f20,f21,1
+.*: (fe 81 a8 30|30 a8 81 fe) fre f20,f21,1
+.*: (ee 80 a8 31|31 a8 80 ee) fres\. f20,f21
+.*: (ee 80 a8 30|30 a8 80 ee) fres f20,f21
+.*: (ee 80 a8 31|31 a8 80 ee) fres\. f20,f21
+.*: (ee 80 a8 30|30 a8 80 ee) fres f20,f21
+.*: (ee 81 a8 31|31 a8 81 ee) fres\. f20,f21,1
+.*: (ee 81 a8 30|30 a8 81 ee) fres f20,f21,1
+.*: (fe 80 ab d1|d1 ab 80 fe) frim\. f20,f21
+.*: (fe 80 ab d0|d0 ab 80 fe) frim f20,f21
+.*: (fe 80 ab 11|11 ab 80 fe) frin\. f20,f21
+.*: (fe 80 ab 10|10 ab 80 fe) frin f20,f21
+.*: (fe 80 ab 91|91 ab 80 fe) frip\. f20,f21
+.*: (fe 80 ab 90|90 ab 80 fe) frip f20,f21
+.*: (fe 80 ab 51|51 ab 80 fe) friz\. f20,f21
+.*: (fe 80 ab 50|50 ab 80 fe) friz f20,f21
+.*: (fe 80 a8 19|19 a8 80 fe) frsp\. f20,f21
+.*: (fe 80 a8 18|18 a8 80 fe) frsp f20,f21
+.*: (fe 80 a8 35|35 a8 80 fe) frsqrte\. f20,f21
+.*: (fe 80 a8 34|34 a8 80 fe) frsqrte f20,f21
+.*: (fe 80 a8 35|35 a8 80 fe) frsqrte\. f20,f21
+.*: (fe 80 a8 34|34 a8 80 fe) frsqrte f20,f21
+.*: (fe 81 a8 35|35 a8 81 fe) frsqrte\. f20,f21,1
+.*: (fe 81 a8 34|34 a8 81 fe) frsqrte f20,f21,1
+.*: (ee 80 a8 34|34 a8 80 ee) frsqrtes f20,f21
+.*: (ee 80 a8 35|35 a8 80 ee) frsqrtes\. f20,f21
+.*: (ee 80 a8 34|34 a8 80 ee) frsqrtes f20,f21
+.*: (ee 80 a8 35|35 a8 80 ee) frsqrtes\. f20,f21
+.*: (ee 81 a8 34|34 a8 81 ee) frsqrtes f20,f21,1
+.*: (ee 81 a8 35|35 a8 81 ee) frsqrtes\. f20,f21,1
+.*: (fe 95 bd af|af bd 95 fe) fsel\. f20,f21,f22,f23
+.*: (fe 95 bd ae|ae bd 95 fe) fsel f20,f21,f22,f23
+.*: (fe 80 a8 2d|2d a8 80 fe) fsqrt\. f20,f21
+.*: (fe 80 a8 2c|2c a8 80 fe) fsqrt f20,f21
+.*: (ee 80 a8 2d|2d a8 80 ee) fsqrts\. f20,f21
+.*: (ee 80 a8 2c|2c a8 80 ee) fsqrts f20,f21
+.*: (fe 95 b0 29|29 b0 95 fe) fsub\. f20,f21,f22
+.*: (fe 95 b0 28|28 b0 95 fe) fsub f20,f21,f22
+.*: (ee 95 b0 29|29 b0 95 ee) fsubs\. f20,f21,f22
+.*: (ee 95 b0 28|28 b0 95 ee) fsubs f20,f21,f22
+.*: (7c 0a 5f ac|ac 5f 0a 7c) icbi r10,r11
+.*: (7c 0a 5f be|be 5f 0a 7c) icbiep r10,r11
+.*: (7c 0a 58 2c|2c 58 0a 7c) icbt r10,r11
+.*: (7c ea 58 2c|2c 58 ea 7c) icbt 7,r10,r11
+.*: (7c 0a 5b cc|cc 5b 0a 7c) icbtls r10,r11
+.*: (7c ea 5b cc|cc 5b ea 7c) icbtls 7,r10,r11
+.*: (7c 00 07 8c|8c 07 00 7c) iccci
+.*: (7c 00 07 8c|8c 07 00 7c) iccci
+.*: (7c 00 07 8c|8c 07 00 7c) iccci
+.*: (7d 40 07 8c|8c 07 40 7d) ici 10
+.*: (7d 4b 63 2d|2d 63 4b 7d) icswx\. r10,r11,r12
+.*: (7d 4b 63 2c|2c 63 4b 7d) icswx r10,r11,r12
+.*: (7d 4b 65 de|de 65 4b 7d) isel r10,r11,r12,23
+.*: (4c 00 01 2c|2c 01 00 4c) isync
+.*: (7d 4b 60 be|be 60 4b 7d) lbepx r10,r11,r12
+.*: (89 4b ff ef|ef ff 4b 89) lbz r10,-17\(r11\)
+.*: (89 4b 00 11|11 00 4b 89) lbz r10,17\(r11\)
+.*: (8d 4b ff ff|ff ff 4b 8d) lbzu r10,-1\(r11\)
+.*: (8d 4b 00 01|01 00 4b 8d) lbzu r10,1\(r11\)
+.*: (7d 4b 68 ee|ee 68 4b 7d) lbzux r10,r11,r13
+.*: (7d 4b 68 ae|ae 68 4b 7d) lbzx r10,r11,r13
+.*: (e9 4b ff f8|f8 ff 4b e9) ld r10,-8\(r11\)
+.*: (e9 4b 00 08|08 00 4b e9) ld r10,8\(r11\)
+.*: (7d 4b 60 a8|a8 60 4b 7d) ldarx r10,r11,r12
+.*: (7d 4b 60 a9|a9 60 4b 7d) ldarx r10,r11,r12,1
+.*: (7d 4b 64 28|28 64 4b 7d) ldbrx r10,r11,r12
+.*: (7d 4b 60 3a|3a 60 4b 7d) ldepx r10,r11,r12
+.*: (e9 4b ff f9|f9 ff 4b e9) ldu r10,-8\(r11\)
+.*: (e9 4b 00 09|09 00 4b e9) ldu r10,8\(r11\)
+.*: (7d 4b 60 6a|6a 60 4b 7d) ldux r10,r11,r12
+.*: (7d 4b 60 2a|2a 60 4b 7d) ldx r10,r11,r12
+.*: (ca 8a ff f8|f8 ff 8a ca) lfd f20,-8\(r10\)
+.*: (ca 8a 00 08|08 00 8a ca) lfd f20,8\(r10\)
+.*: (7e 8a 5c be|be 5c 8a 7e) lfdepx f20,r10,r11
+.*: (ce 8a ff f8|f8 ff 8a ce) lfdu f20,-8\(r10\)
+.*: (ce 8a 00 08|08 00 8a ce) lfdu f20,8\(r10\)
+.*: (7e 8a 5c ee|ee 5c 8a 7e) lfdux f20,r10,r11
+.*: (7e 8a 5c ae|ae 5c 8a 7e) lfdx f20,r10,r11
+.*: (7e 8a 5e ae|ae 5e 8a 7e) lfiwax f20,r10,r11
+.*: (7e 8a 5e ee|ee 5e 8a 7e) lfiwzx f20,r10,r11
+.*: (c2 8a ff fc|fc ff 8a c2) lfs f20,-4\(r10\)
+.*: (c2 8a 00 04|04 00 8a c2) lfs f20,4\(r10\)
+.*: (c6 8a ff fc|fc ff 8a c6) lfsu f20,-4\(r10\)
+.*: (c6 8a 00 04|04 00 8a c6) lfsu f20,4\(r10\)
+.*: (7e 8a 5c 6e|6e 5c 8a 7e) lfsux f20,r10,r11
+.*: (7e 8a 5c 2e|2e 5c 8a 7e) lfsx f20,r10,r11
+.*: (a9 4b 00 02|02 00 4b a9) lha r10,2\(r11\)
+.*: (ad 4b ff fe|fe ff 4b ad) lhau r10,-2\(r11\)
+.*: (7d 4b 62 ee|ee 62 4b 7d) lhaux r10,r11,r12
+.*: (7d 4b 62 ae|ae 62 4b 7d) lhax r10,r11,r12
+.*: (7d 4b 66 2c|2c 66 4b 7d) lhbrx r10,r11,r12
+.*: (7d 4b 62 3e|3e 62 4b 7d) lhepx r10,r11,r12
+.*: (a1 4b ff fe|fe ff 4b a1) lhz r10,-2\(r11\)
+.*: (a1 4b 00 02|02 00 4b a1) lhz r10,2\(r11\)
+.*: (a5 4b ff fe|fe ff 4b a5) lhzu r10,-2\(r11\)
+.*: (a5 4b 00 02|02 00 4b a5) lhzu r10,2\(r11\)
+.*: (7d 4b 62 6e|6e 62 4b 7d) lhzux r10,r11,r12
+.*: (7d 4b 62 2e|2e 62 4b 7d) lhzx r10,r11,r12
+.*: (e9 4b ff fe|fe ff 4b e9) lwa r10,-4\(r11\)
+.*: (e9 4b 00 06|06 00 4b e9) lwa r10,4\(r11\)
+.*: (7d 4b 60 28|28 60 4b 7d) lwarx r10,r11,r12
+.*: (7d 4b 60 29|29 60 4b 7d) lwarx r10,r11,r12,1
+.*: (7d 4b 62 ea|ea 62 4b 7d) lwaux r10,r11,r12
+.*: (7d 4b 62 aa|aa 62 4b 7d) lwax r10,r11,r12
+.*: (7d 4b 64 2c|2c 64 4b 7d) lwbrx r10,r11,r12
+.*: (7d 4b 60 3e|3e 60 4b 7d) lwepx r10,r11,r12
+.*: (81 4b ff fc|fc ff 4b 81) lwz r10,-4\(r11\)
+.*: (81 4b 00 04|04 00 4b 81) lwz r10,4\(r11\)
+.*: (85 4b ff fc|fc ff 4b 85) lwzu r10,-4\(r11\)
+.*: (85 4b 00 04|04 00 4b 85) lwzu r10,4\(r11\)
+.*: (7d 4b 60 6e|6e 60 4b 7d) lwzux r10,r11,r12
+.*: (7d 4b 60 2e|2e 60 4b 7d) lwzx r10,r11,r12
+.*: (7c 00 06 ac|ac 06 00 7c) mbar
+.*: (7c 00 06 ac|ac 06 00 7c) mbar
+.*: (7c 00 06 ac|ac 06 00 7c) mbar
+.*: (7c 20 06 ac|ac 06 20 7c) mbar 1
+.*: (4c 04 00 00|00 00 04 4c) mcrf cr0,cr1
+.*: (fd 90 00 80|80 00 90 fd) mcrfs cr3,cr4
+.*: (7c 00 04 00|00 04 00 7c) mcrxr cr0
+.*: (7d 80 04 00|00 04 80 7d) mcrxr cr3
+.*: (7c 60 00 26|26 00 60 7c) mfcr r3
+.*: (7c 70 20 26|26 20 70 7c) mfocrf r3,2
+.*: (7c 70 10 26|26 10 70 7c) mfocrf r3,1
+.*: (7c 78 00 26|26 00 78 7c) mfocrf r3,128
+.*: (7d 4a 3a 87|87 3a 4a 7d) mfdcr\. r10,234
+.*: (7d 4a 3a 86|86 3a 4a 7d) mfdcr r10,234
+.*: (7d 4b 02 07|07 02 4b 7d) mfdcrx\. r10,r11
+.*: (7d 4b 02 06|06 02 4b 7d) mfdcrx r10,r11
+.*: (fe 80 04 8f|8f 04 80 fe) mffs\. f20
+.*: (fe 80 04 8e|8e 04 80 fe) mffs f20
+.*: (7d 40 00 a6|a6 00 40 7d) mfmsr r10
+.*: (7c 70 10 26|26 10 70 7c) mfocrf r3,1
+.*: (7c 78 00 26|26 00 78 7c) mfocrf r3,128
+.*: (7d 4a 3a a6|a6 3a 4a 7d) mfspr r10,234
+.*: (7d 4c 42 a6|a6 42 4c 7d) mftb r10
+.*: (7d 4d 42 a6|a6 42 4d 7d) mftbu r10
+.*: (7c 00 51 dc|dc 51 00 7c) msgclr r10
+.*: (7c 00 51 9c|9c 51 00 7c) msgsnd r10
+.*: (7c 60 01 20|20 01 60 7c) mtcrf 0,r3
+.*: (7c 70 11 20|20 11 70 7c) mtocrf 1,r3
+.*: (7c 78 01 20|20 01 78 7c) mtocrf 128,r3
+.*: (7c 6f f1 20|20 f1 6f 7c) mtcr r3
+.*: (7d 4a 3b 87|87 3b 4a 7d) mtdcr\. 234,r10
+.*: (7d 4a 3b 86|86 3b 4a 7d) mtdcr 234,r10
+.*: (7d 6a 03 07|07 03 6a 7d) mtdcrx\. r10,r11
+.*: (7d 6a 03 06|06 03 6a 7d) mtdcrx r10,r11
+.*: (fc 60 00 8d|8d 00 60 fc) mtfsb0\. 3
+.*: (fc 60 00 8c|8c 00 60 fc) mtfsb0 3
+.*: (fc 60 00 4d|4d 00 60 fc) mtfsb1\. 3
+.*: (fc 60 00 4c|4c 00 60 fc) mtfsb1 3
+.*: (fc 0c a5 8f|8f a5 0c fc) mtfsf\. 6,f20
+.*: (fc 0c a5 8e|8e a5 0c fc) mtfsf 6,f20
+.*: (fc 0c a5 8f|8f a5 0c fc) mtfsf\. 6,f20
+.*: (fc 0c a5 8e|8e a5 0c fc) mtfsf 6,f20
+.*: (fe 0d a5 8f|8f a5 0d fe) mtfsf\. 6,f20,1,1
+.*: (fe 0d a5 8e|8e a5 0d fe) mtfsf 6,f20,1,1
+.*: (ff 00 01 0d|0d 01 00 ff) mtfsfi\. 6,0
+.*: (ff 00 01 0c|0c 01 00 ff) mtfsfi 6,0
+.*: (ff 00 d1 0d|0d d1 00 ff) mtfsfi\. 6,13
+.*: (ff 00 d1 0c|0c d1 00 ff) mtfsfi 6,13
+.*: (ff 01 d1 0d|0d d1 01 ff) mtfsfi\. 6,13,1
+.*: (ff 01 d1 0c|0c d1 01 ff) mtfsfi 6,13,1
+.*: (7d 40 01 24|24 01 40 7d) mtmsr r10
+.*: (7d 40 01 24|24 01 40 7d) mtmsr r10
+.*: (7d 41 01 24|24 01 41 7d) mtmsr r10,1
+.*: (7c 70 11 20|20 11 70 7c) mtocrf 1,r3
+.*: (7c 78 01 20|20 01 78 7c) mtocrf 128,r3
+.*: (7d 4a 3b a6|a6 3b 4a 7d) mtspr 234,r10
+.*: (7e 95 b0 93|93 b0 95 7e) mulhd\. r20,r21,r22
+.*: (7e 95 b0 92|92 b0 95 7e) mulhd r20,r21,r22
+.*: (7e 95 b0 13|13 b0 95 7e) mulhdu\. r20,r21,r22
+.*: (7e 95 b0 12|12 b0 95 7e) mulhdu r20,r21,r22
+.*: (7e 95 b0 97|97 b0 95 7e) mulhw\. r20,r21,r22
+.*: (7e 95 b0 96|96 b0 95 7e) mulhw r20,r21,r22
+.*: (7e 95 b0 17|17 b0 95 7e) mulhwu\. r20,r21,r22
+.*: (7e 95 b0 16|16 b0 95 7e) mulhwu r20,r21,r22
+.*: (7e 95 b1 d3|d3 b1 95 7e) mulld\. r20,r21,r22
+.*: (7e 95 b1 d2|d2 b1 95 7e) mulld r20,r21,r22
+.*: (7e 95 b5 d3|d3 b5 95 7e) mulldo\. r20,r21,r22
+.*: (7e 95 b5 d2|d2 b5 95 7e) mulldo r20,r21,r22
+.*: (1e 95 00 64|64 00 95 1e) mulli r20,r21,100
+.*: (1e 95 ff 9c|9c ff 95 1e) mulli r20,r21,-100
+.*: (7e 95 b1 d7|d7 b1 95 7e) mullw\. r20,r21,r22
+.*: (7e 95 b1 d6|d6 b1 95 7e) mullw r20,r21,r22
+.*: (7e 95 b5 d7|d7 b5 95 7e) mullwo\. r20,r21,r22
+.*: (7e 95 b5 d6|d6 b5 95 7e) mullwo r20,r21,r22
+.*: (7e b4 b3 b9|b9 b3 b4 7e) nand\. r20,r21,r22
+.*: (7e b4 b3 b8|b8 b3 b4 7e) nand r20,r21,r22
+.*: (7e 95 00 d1|d1 00 95 7e) neg\. r20,r21
+.*: (7e 95 00 d0|d0 00 95 7e) neg r20,r21
+.*: (7e 95 04 d1|d1 04 95 7e) nego\. r20,r21
+.*: (7e 95 04 d0|d0 04 95 7e) nego r20,r21
+.*: (7e b4 b0 f9|f9 b0 b4 7e) nor\. r20,r21,r22
+.*: (7e b4 b0 f8|f8 b0 b4 7e) nor r20,r21,r22
+.*: (7e b4 b3 79|79 b3 b4 7e) or\. r20,r21,r22
+.*: (7e b4 b3 78|78 b3 b4 7e) or r20,r21,r22
+.*: (7e b4 b3 39|39 b3 b4 7e) orc\. r20,r21,r22
+.*: (7e b4 b3 38|38 b3 b4 7e) orc r20,r21,r22
+.*: (62 b4 10 00|00 10 b4 62) ori r20,r21,4096
+.*: (66 b4 10 00|00 10 b4 66) oris r20,r21,4096
+.*: (7d 6a 00 f4|f4 00 6a 7d) popcntb r10,r11
+.*: (7d 6a 03 f4|f4 03 6a 7d) popcntd r10,r11
+.*: (7d 6a 02 f4|f4 02 6a 7d) popcntw r10,r11
+.*: (7d 6a 01 74|74 01 6a 7d) prtyd r10,r11
+.*: (7d 6a 01 34|34 01 6a 7d) prtyw r10,r11
+.*: (4c 00 00 66|66 00 00 4c) rfci
+.*: (4c 00 00 cc|cc 00 00 4c) rfgi
+.*: (4c 00 00 64|64 00 00 4c) rfi
+.*: (4c 00 00 4c|4c 00 00 4c) rfmci
+.*: (79 6a 67 f1|f1 67 6a 79) rldcl\. r10,r11,r12,63
+.*: (79 6a 67 f0|f0 67 6a 79) rldcl r10,r11,r12,63
+.*: (79 6a 67 f3|f3 67 6a 79) rldcr\. r10,r11,r12,63
+.*: (79 6a 67 f2|f2 67 6a 79) rldcr r10,r11,r12,63
+.*: (79 6a bf e9|e9 bf 6a 79) rldic\. r10,r11,23,63
+.*: (79 6a bf e8|e8 bf 6a 79) rldic r10,r11,23,63
+.*: (79 6a bf e1|e1 bf 6a 79) rldicl\. r10,r11,23,63
+.*: (79 6a bf e0|e0 bf 6a 79) rldicl r10,r11,23,63
+.*: (79 6a bf e5|e5 bf 6a 79) rldicr\. r10,r11,23,63
+.*: (79 6a bf e4|e4 bf 6a 79) rldicr r10,r11,23,63
+.*: (79 6a bf ed|ed bf 6a 79) rldimi\. r10,r11,23,63
+.*: (79 6a bf ec|ec bf 6a 79) rldimi r10,r11,23,63
+.*: (51 6a b8 3f|3f b8 6a 51) rlwimi\. r10,r11,23,0,31
+.*: (51 6a b8 3e|3e b8 6a 51) rlwimi r10,r11,23,0,31
+.*: (55 6a b8 3f|3f b8 6a 55) rotlwi\. r10,r11,23
+.*: (55 6a b8 3e|3e b8 6a 55) rotlwi r10,r11,23
+.*: (5d 6a b8 3f|3f b8 6a 5d) rotlw\. r10,r11,r23
+.*: (5d 6a b8 3e|3e b8 6a 5d) rotlw r10,r11,r23
+.*: (44 00 00 02|02 00 00 44) sc
+.*: (44 00 0c 82|82 0c 00 44) sc 100
+.*: (7d 6a 60 37|37 60 6a 7d) sld\. r10,r11,r12
+.*: (7d 6a 60 36|36 60 6a 7d) sld r10,r11,r12
+.*: (7d 6a 60 31|31 60 6a 7d) slw\. r10,r11,r12
+.*: (7d 6a 60 30|30 60 6a 7d) slw r10,r11,r12
+.*: (7d 6a 66 35|35 66 6a 7d) srad\. r10,r11,r12
+.*: (7d 6a 66 34|34 66 6a 7d) srad r10,r11,r12
+.*: (7d 6a fe 77|77 fe 6a 7d) sradi\. r10,r11,63
+.*: (7d 6a fe 76|76 fe 6a 7d) sradi r10,r11,63
+.*: (7d 6a 66 31|31 66 6a 7d) sraw\. r10,r11,r12
+.*: (7d 6a 66 30|30 66 6a 7d) sraw r10,r11,r12
+.*: (7d 6a fe 71|71 fe 6a 7d) srawi\. r10,r11,31
+.*: (7d 6a fe 70|70 fe 6a 7d) srawi r10,r11,31
+.*: (7d 6a 64 37|37 64 6a 7d) srd\. r10,r11,r12
+.*: (7d 6a 64 36|36 64 6a 7d) srd r10,r11,r12
+.*: (7d 6a 64 31|31 64 6a 7d) srw\. r10,r11,r12
+.*: (7d 6a 64 30|30 64 6a 7d) srw r10,r11,r12
+.*: (99 4b ff ff|ff ff 4b 99) stb r10,-1\(r11\)
+.*: (99 4b 00 01|01 00 4b 99) stb r10,1\(r11\)
+.*: (7d 4b 61 be|be 61 4b 7d) stbepx r10,r11,r12
+.*: (9d 4b ff ff|ff ff 4b 9d) stbu r10,-1\(r11\)
+.*: (9d 4b 00 01|01 00 4b 9d) stbu r10,1\(r11\)
+.*: (7d 4b 61 ee|ee 61 4b 7d) stbux r10,r11,r12
+.*: (7d 4b 61 ae|ae 61 4b 7d) stbx r10,r11,r12
+.*: (f9 4b ff f8|f8 ff 4b f9) std r10,-8\(r11\)
+.*: (f9 4b 00 08|08 00 4b f9) std r10,8\(r11\)
+.*: (7d 4b 65 28|28 65 4b 7d) stdbrx r10,r11,r12
+.*: (7d 4b 61 ad|ad 61 4b 7d) stdcx\. r10,r11,r12
+.*: (7d 4b 61 3a|3a 61 4b 7d) stdepx r10,r11,r12
+.*: (f9 4b ff f9|f9 ff 4b f9) stdu r10,-8\(r11\)
+.*: (f9 4b 00 09|09 00 4b f9) stdu r10,8\(r11\)
+.*: (7d 4b 61 6a|6a 61 4b 7d) stdux r10,r11,r12
+.*: (7d 4b 61 2a|2a 61 4b 7d) stdx r10,r11,r12
+.*: (da 8a ff f8|f8 ff 8a da) stfd f20,-8\(r10\)
+.*: (da 8a 00 08|08 00 8a da) stfd f20,8\(r10\)
+.*: (7e 8a 5d be|be 5d 8a 7e) stfdepx f20,r10,r11
+.*: (de 8a ff f8|f8 ff 8a de) stfdu f20,-8\(r10\)
+.*: (de 8a 00 08|08 00 8a de) stfdu f20,8\(r10\)
+.*: (7e 8a 5d ee|ee 5d 8a 7e) stfdux f20,r10,r11
+.*: (7e 8a 5d ae|ae 5d 8a 7e) stfdx f20,r10,r11
+.*: (7e 8a 5f ae|ae 5f 8a 7e) stfiwx f20,r10,r11
+.*: (d2 8a ff fc|fc ff 8a d2) stfs f20,-4\(r10\)
+.*: (d2 8a 00 04|04 00 8a d2) stfs f20,4\(r10\)
+.*: (d6 8a ff fc|fc ff 8a d6) stfsu f20,-4\(r10\)
+.*: (d6 8a 00 04|04 00 8a d6) stfsu f20,4\(r10\)
+.*: (7e 8a 5d 6e|6e 5d 8a 7e) stfsux f20,r10,r11
+.*: (7e 8a 5d 2e|2e 5d 8a 7e) stfsx f20,r10,r11
+.*: (b1 4b ff fe|fe ff 4b b1) sth r10,-2\(r11\)
+.*: (b1 4b 00 02|02 00 4b b1) sth r10,2\(r11\)
+.*: (b1 4b ff fc|fc ff 4b b1) sth r10,-4\(r11\)
+.*: (b1 4b 00 04|04 00 4b b1) sth r10,4\(r11\)
+.*: (7d 4b 67 2c|2c 67 4b 7d) sthbrx r10,r11,r12
+.*: (7d 4b 63 3e|3e 63 4b 7d) sthepx r10,r11,r12
+.*: (b5 4b ff fe|fe ff 4b b5) sthu r10,-2\(r11\)
+.*: (b5 4b 00 02|02 00 4b b5) sthu r10,2\(r11\)
+.*: (7d 4b 63 6e|6e 63 4b 7d) sthux r10,r11,r12
+.*: (7d 4b 63 2e|2e 63 4b 7d) sthx r10,r11,r12
+.*: (7d 4b 65 2c|2c 65 4b 7d) stwbrx r10,r11,r12
+.*: (7d 4b 61 2d|2d 61 4b 7d) stwcx\. r10,r11,r12
+.*: (7d 4b 61 3e|3e 61 4b 7d) stwepx r10,r11,r12
+.*: (95 4b ff fc|fc ff 4b 95) stwu r10,-4\(r11\)
+.*: (95 4b 00 04|04 00 4b 95) stwu r10,4\(r11\)
+.*: (7d 4b 61 6e|6e 61 4b 7d) stwux r10,r11,r12
+.*: (7d 4b 61 2e|2e 61 4b 7d) stwx r10,r11,r12
+.*: (7e 95 b0 51|51 b0 95 7e) subf\. r20,r21,r22
+.*: (7e 95 b0 50|50 b0 95 7e) subf r20,r21,r22
+.*: (7e 95 b0 11|11 b0 95 7e) subfc\. r20,r21,r22
+.*: (7e 95 b0 10|10 b0 95 7e) subfc r20,r21,r22
+.*: (7e 95 b4 11|11 b4 95 7e) subfco\. r20,r21,r22
+.*: (7e 95 b4 10|10 b4 95 7e) subfco r20,r21,r22
+.*: (7e 95 b1 11|11 b1 95 7e) subfe\. r20,r21,r22
+.*: (7e 95 b1 10|10 b1 95 7e) subfe r20,r21,r22
+.*: (7e 95 b5 11|11 b5 95 7e) subfeo\. r20,r21,r22
+.*: (7e 95 b5 10|10 b5 95 7e) subfeo r20,r21,r22
+.*: (22 95 00 64|64 00 95 22) subfic r20,r21,100
+.*: (22 95 ff 9c|9c ff 95 22) subfic r20,r21,-100
+.*: (7e 95 01 d1|d1 01 95 7e) subfme\. r20,r21
+.*: (7e 95 01 d0|d0 01 95 7e) subfme r20,r21
+.*: (7e 95 05 d1|d1 05 95 7e) subfmeo\. r20,r21
+.*: (7e 95 05 d0|d0 05 95 7e) subfmeo r20,r21
+.*: (7e 95 b4 51|51 b4 95 7e) subfo\. r20,r21,r22
+.*: (7e 95 b4 50|50 b4 95 7e) subfo r20,r21,r22
+.*: (7e 95 01 91|91 01 95 7e) subfze\. r20,r21
+.*: (7e 95 01 90|90 01 95 7e) subfze r20,r21
+.*: (7e 95 05 91|91 05 95 7e) subfzeo\. r20,r21
+.*: (7e 95 05 90|90 05 95 7e) subfzeo r20,r21
+.*: (7c 00 04 ac|ac 04 00 7c) hwsync
+.*: (7c 00 04 ac|ac 04 00 7c) hwsync
+.*: (7c 00 04 ac|ac 04 00 7c) hwsync
+.*: (7c 20 04 ac|ac 04 20 7c) lwsync
+.*: (7c aa 58 88|88 58 aa 7c) tdlge r10,r11
+.*: (08 aa 00 64|64 00 aa 08) tdlgei r10,100
+.*: (08 aa ff 9c|9c ff aa 08) tdlgei r10,-100
+.*: (7c 6a 58 24|24 58 6a 7c) tlbilxva r10,r11
+.*: (7c 0a 5e 24|24 5e 0a 7c) tlbivax r10,r11
+.*: (7c 00 07 64|64 07 00 7c) tlbre
+.*: (7d 4b 3f 64|64 3f 4b 7d) tlbre r10,r11,7
+.*: (7c 0a 5e a5|a5 5e 0a 7c) tlbsrx\. r10,r11
+.*: (7d 4b 67 25|25 67 4b 7d) tlbsx\. r10,r11,r12
+.*: (7d 4b 67 24|24 67 4b 7d) tlbsx r10,r11,r12
+.*: (7c 00 04 6c|6c 04 00 7c) tlbsync
+.*: (7c 00 07 a4|a4 07 00 7c) tlbwe
+.*: (7d 4b 3f a4|a4 3f 4b 7d) tlbwe r10,r11,7
+.*: (7c aa 58 08|08 58 aa 7c) twlge r10,r11
+.*: (0c aa 00 64|64 00 aa 0c) twlgei r10,100
+.*: (0c aa ff 9c|9c ff aa 0c) twlgei r10,-100
+.*: (7c 00 00 7c|7c 00 00 7c) wait
+.*: (7c 00 00 7c|7c 00 00 7c) wait
+.*: (7c 20 00 7c|7c 00 20 7c) waitrsv
+.*: (7c 40 00 7c|7c 00 40 7c) waitimpl
+.*: (7c 40 00 7c|7c 00 40 7c) waitimpl
+.*: (7c 20 00 7c|7c 00 20 7c) waitrsv
+.*: (7c 00 01 6c|6c 01 00 7c) wchkall
+.*: (7c 00 01 6c|6c 01 00 7c) wchkall
+.*: (7d 80 01 6c|6c 01 80 7d) wchkall cr3
+.*: (7c 2a 5f 4c|4c 5f 2a 7c) wclr 1,r10,r11
+.*: (7c 20 07 4c|4c 07 20 7c) wclrall 1
+.*: (7c 4a 5f 4c|4c 5f 4a 7c) wclrone r10,r11
+.*: (7d 40 01 06|06 01 40 7d) wrtee r10
+.*: (7c 00 81 46|46 81 00 7c) wrteei 1
+.*: (7d 6a 62 79|79 62 6a 7d) xor\. r10,r11,r12
+.*: (7d 6a 62 78|78 62 6a 7d) xor r10,r11,r12
+.*: (69 6a 10 00|00 10 6a 69) xori r10,r11,4096
+.*: (6d 6a 10 00|00 10 6a 6d) xoris r10,r11,4096
#pass
diff -rup binutils.orig/gas/testsuite/gas/ppc/a2.s binutils-2.35.1/gas/testsuite/gas/ppc/a2.s
--- binutils.orig/gas/testsuite/gas/ppc/a2.s 2020-10-08 13:50:31.311909794 +0100
+++ binutils-2.35.1/gas/testsuite/gas/ppc/a2.s 2020-10-08 13:51:29.102731857 +0100
@@ -295,10 +295,6 @@ start:
lhzu 10,2(11)
lhzux 10,11,12
lhzx 10,11,12
- lmw 20,16(10)
- lswi 10,11,1
- lswi 12,11,32
- lswx 10,11,12
lwa 10,-4(11)
lwa 10,4(11)
lwarx 10,11,12,0
@@ -486,10 +482,6 @@ start:
sthu 10,2(11)
sthux 10,11,12
sthx 10,11,12
- stmw 20,16(10)
- stswi 10,11,1
- stswi 10,11,32
- stswx 10,11,12
stwbrx 10,11,12
stwcx. 10,11,12
stwepx 10,11,12
diff -rup binutils.orig/gas/testsuite/gas/ppc/int128.d binutils-2.35.1/gas/testsuite/gas/ppc/int128.d
--- binutils.orig/gas/testsuite/gas/ppc/int128.d 2020-10-08 13:50:31.313909788 +0100
+++ binutils-2.35.1/gas/testsuite/gas/ppc/int128.d 2020-10-08 13:50:58.204826992 +0100
@@ -20,7 +20,7 @@ Disassembly of section \.text:
.*: (13 9d f7 0b|0b f7 9d 13) vmodsq v28,v29,v30
.*: (13 e0 0e 0b|0b 0e e0 13) vmoduq v31,v0,v1
.*: (10 5b 1e 02|02 1e 5b 10) vextsd2q v2,v3
-.*: (10 04 29 01|01 29 04 10) vcmpuq v4,v5
+.*: (10 04 29 01|01 29 04 10) vcmpuq cr0,v4,v5
.*: (10 86 39 41|41 39 86 10) vcmpsq cr1,v6,v7
.*: (11 09 51 c7|c7 51 09 11) vcmpequq v8,v9,v10
.*: (11 6c 6d c7|c7 6d 6c 11) vcmpequq. v11,v12,v13
diff -rup binutils.orig/gas/testsuite/gas/ppc/int128.s binutils-2.35.1/gas/testsuite/gas/ppc/int128.s
--- binutils.orig/gas/testsuite/gas/ppc/int128.s 2020-10-08 13:50:31.313909788 +0100
+++ binutils-2.35.1/gas/testsuite/gas/ppc/int128.s 2020-10-08 13:50:58.204826992 +0100
@@ -12,7 +12,7 @@ _start:
vmodsq 28,29,30
vmoduq 31,0,1
vextsd2q 2,3
- vcmpuq 4,5
+ vcmpuq 0,4,5
vcmpsq 1,6,7
vcmpequq 8,9,10
vcmpequq. 11,12,13
diff -rup binutils.orig/gas/testsuite/gas/ppc/power8.d binutils-2.35.1/gas/testsuite/gas/ppc/power8.d
--- binutils.orig/gas/testsuite/gas/ppc/power8.d 2020-10-08 13:50:31.311909794 +0100
+++ binutils-2.35.1/gas/testsuite/gas/ppc/power8.d 2020-10-08 13:56:18.490840878 +0100
@@ -7,151 +7,151 @@
Disassembly of section \.text:
0+00 <power8>:
- 0: (7c 05 07 1d|1d 07 05 7c) tabort\. r5
- 4: (7c e8 86 1d|1d 86 e8 7c) tabortwc\. 7,r8,r16
- 8: (7e 8b 56 5d|5d 56 8b 7e) tabortdc\. 20,r11,r10
- c: (7e 2a 9e 9d|9d 9e 2a 7e) tabortwci\. 17,r10,-13
- 10: (7f a3 de dd|dd de a3 7f) tabortdci\. 29,r3,-5
- 14: (7c 00 05 1d|1d 05 00 7c) tbegin\.
- 18: (7f 80 05 9c|9c 05 80 7f) tcheck cr7
- 1c: (7c 00 05 5d|5d 05 00 7c) tend\.
- 20: (7c 00 05 5d|5d 05 00 7c) tend\.
- 24: (7e 00 05 5d|5d 05 00 7e) tendall\.
- 28: (7e 00 05 5d|5d 05 00 7e) tendall\.
- 2c: (7c 18 07 5d|5d 07 18 7c) treclaim\. r24
- 30: (7c 00 07 dd|dd 07 00 7c) trechkpt\.
- 34: (7c 00 05 dd|dd 05 00 7c) tsuspend\.
- 38: (7c 00 05 dd|dd 05 00 7c) tsuspend\.
- 3c: (7c 20 05 dd|dd 05 20 7c) tresume\.
- 40: (7c 20 05 dd|dd 05 20 7c) tresume\.
- 44: (60 42 00 00|00 00 42 60) ori r2,r2,0
- 48: (60 00 00 00|00 00 00 60) nop
- 4c: (60 42 00 00|00 00 42 60) ori r2,r2,0
- 50: (4c 00 01 24|24 01 00 4c) rfebb 0
- 54: (4c 00 09 24|24 09 00 4c) rfebb
- 58: (4c 00 09 24|24 09 00 4c) rfebb
- 5c: (4d d5 04 60|60 04 d5 4d) bgttar- cr5
- 60: (4c c7 04 61|61 04 c7 4c) bnstarl- cr1
- 64: (4d ec 04 60|60 04 ec 4d) blttar\+ cr3
- 68: (4c e2 04 61|61 04 e2 4c) bnetarl\+
- 6c: (4c 88 0c 60|60 0c 88 4c) bctar 4,4\*cr2\+lt,1
- 70: (4c 87 14 61|61 14 87 4c) bctarl 4,4\*cr1\+so,2
- 74: (7c 00 00 3c|3c 00 00 7c) waitasec
- 78: (7c 00 41 1c|1c 41 00 7c) msgsndp r8
- 7c: (7c 20 01 26|26 01 20 7c) mtsle 1
- 80: (7c 00 d9 5c|5c d9 00 7c) msgclrp r27
- 84: (7d 4a 61 6d|6d 61 4a 7d) stqcx\. r10,r10,r12
- 88: (7f 80 39 6d|6d 39 80 7f) stqcx\. r28,0,r7
- 8c: (7f 13 5a 28|28 5a 13 7f) lqarx r24,r19,r11
- 90: (7e c0 5a 28|28 5a c0 7e) lqarx r22,0,r11
- 94: (7e 80 32 5c|5c 32 80 7e) mfbhrbe r20,6
- 98: (7f b1 83 29|29 83 b1 7f) pbt\. r29,r17,r16
- 9c: (7d c0 3b 29|29 3b c0 7d) pbt\. r14,0,r7
- a0: (7c 00 03 5c|5c 03 00 7c) clrbhrb
- a4: (11 6a 05 ed|ed 05 6a 11) vpermxor v11,v10,v0,v23
- a8: (13 02 39 3c|3c 39 02 13) vaddeuqm v24,v2,v7,v4
- ac: (11 4a 40 bd|bd 40 4a 11) vaddecuq v10,v10,v8,v2
- b0: (10 af 44 fe|fe 44 af 10) vsubeuqm v5,v15,v8,v19
- b4: (11 9f 87 7f|7f 87 9f 11) vsubecuq v12,v31,v16,v29
- b8: (12 9d 68 88|88 68 9d 12) vmulouw v20,v29,v13
- bc: (13 a0 d0 89|89 d0 a0 13) vmuluwm v29,v0,v26
- c0: (11 15 e0 c0|c0 e0 15 11) vaddudm v8,v21,v28
- c4: (10 3a 08 c2|c2 08 3a 10) vmaxud v1,v26,v1
- c8: (12 83 08 c4|c4 08 83 12) vrld v20,v3,v1
- cc: (10 93 58 c7|c7 58 93 10) vcmpequd v4,v19,v11
- d0: (12 ee f1 00|00 f1 ee 12) vadduqm v23,v14,v30
- d4: (11 08 69 40|40 69 08 11) vaddcuq v8,v8,v13
- d8: (13 9b 21 88|88 21 9b 13) vmulosw v28,v27,v4
- dc: (10 64 21 c2|c2 21 64 10) vmaxsd v3,v4,v4
- e0: (10 13 aa 88|88 aa 13 10) vmuleuw v0,v19,v21
- e4: (13 14 9a c2|c2 9a 14 13) vminud v24,v20,v19
- e8: (10 1c 7a c7|c7 7a 1c 10) vcmpgtud v0,v28,v15
- ec: (12 a0 13 88|88 13 a0 12) vmulesw v21,v0,v2
- f0: (11 3a 4b c2|c2 4b 3a 11) vminsd v9,v26,v9
- f4: (13 3d 5b c4|c4 5b 3d 13) vsrad v25,v29,v11
- f8: (11 7c 5b c7|c7 5b 7c 11) vcmpgtsd v11,v28,v11
- fc: (10 a8 d6 01|01 d6 a8 10) bcdadd\. v5,v8,v26,1
- 100: (10 83 64 08|08 64 83 10) vpmsumb v4,v3,v12
- 104: (13 5f ae 41|41 ae 5f 13) bcdsub\. v26,v31,v21,1
- 108: (10 b1 84 48|48 84 b1 10) vpmsumh v5,v17,v16
- 10c: (12 f1 a4 4e|4e a4 f1 12) vpkudum v23,v17,v20
- 110: (13 15 ec 88|88 ec 15 13) vpmsumw v24,v21,v29
- 114: (11 36 6c c8|c8 6c 36 11) vpmsumd v9,v22,v13
- 118: (12 53 94 ce|ce 94 53 12) vpkudus v18,v19,v18
- 11c: (13 d0 b5 00|00 b5 d0 13) vsubuqm v30,v16,v22
- 120: (11 cb 3d 08|08 3d cb 11) vcipher v14,v11,v7
- 124: (11 42 b5 09|09 b5 42 11) vcipherlast v10,v2,v22
- 128: (12 e0 6d 0c|0c 6d e0 12) vgbbd v23,v13
- 12c: (12 19 85 40|40 85 19 12) vsubcuq v16,v25,v16
- 130: (13 e1 2d 44|44 2d e1 13) vorc v31,v1,v5
- 134: (10 91 fd 48|48 fd 91 10) vncipher v4,v17,v31
- 138: (13 02 dd 49|49 dd 02 13) vncipherlast v24,v2,v27
- 13c: (12 f5 bd 4c|4c bd f5 12) vbpermq v23,v21,v23
- 140: (13 72 4d 4e|4e 4d 72 13) vpksdus v27,v18,v9
- 144: (13 7d dd 84|84 dd 7d 13) vnand v27,v29,v27
- 148: (12 73 c5 c4|c4 c5 73 12) vsld v19,v19,v24
- 14c: (10 ad 05 c8|c8 05 ad 10) vsbox v5,v13
- 150: (13 23 3d ce|ce 3d 23 13) vpksdss v25,v3,v7
- 154: (13 88 04 c7|c7 04 88 13) vcmpequd\. v28,v8,v0
- 158: (13 40 d6 4e|4e d6 40 13) vupkhsw v26,v26
- 15c: (10 a7 36 82|82 36 a7 10) vshasigmaw v5,v7,0,6
- 160: (13 95 76 84|84 76 95 13) veqv v28,v21,v14
- 164: (10 28 9e 8c|8c 9e 28 10) vmrgow v1,v8,v19
- 168: (10 0a 56 c2|c2 56 0a 10) vshasigmad v0,v10,0,10
- 16c: (10 bb 76 c4|c4 76 bb 10) vsrd v5,v27,v14
- 170: (11 60 6e ce|ce 6e 60 11) vupklsw v11,v13
- 174: (11 c0 87 02|02 87 c0 11) vclzb v14,v16
- 178: (12 80 df 03|03 df 80 12) vpopcntb v20,v27
- 17c: (13 80 5f 42|42 5f 80 13) vclzh v28,v11
- 180: (13 00 4f 43|43 4f 00 13) vpopcnth v24,v9
- 184: (13 60 ff 82|82 ff 60 13) vclzw v27,v31
- 188: (12 20 9f 83|83 9f 20 12) vpopcntw v17,v19
- 18c: (11 80 ef c2|c2 ef 80 11) vclzd v12,v29
- 190: (12 e0 b7 c3|c3 b7 e0 12) vpopcntd v23,v22
- 194: (13 14 ee c7|c7 ee 14 13) vcmpgtud\. v24,v20,v29
- 198: (11 26 df c7|c7 df 26 11) vcmpgtsd\. v9,v6,v27
- 19c: (7f ce d0 19|19 d0 ce 7f) lxsiwzx vs62,r14,r26
- 1a0: (7d 00 c8 19|19 c8 00 7d) lxsiwzx vs40,0,r25
- 1a4: (7f 20 d0 98|98 d0 20 7f) lxsiwax vs25,0,r26
- 1a8: (7c 60 18 98|98 18 60 7c) lxsiwax vs3,0,r3
- 1ac: (7f cc 00 67|67 00 cc 7f) mfvsrd r12,vs62
- 1b0: (7d 94 00 e6|e6 00 94 7d) mffprwz r20,f12
- 1b4: (7d c9 71 18|18 71 c9 7d) stxsiwx vs14,r9,r14
- 1b8: (7e a0 41 18|18 41 a0 7e) stxsiwx vs21,0,r8
- 1bc: (7e 0b 01 67|67 01 0b 7e) mtvsrd vs48,r11
- 1c0: (7f f7 01 a7|a7 01 f7 7f) mtvrwa v31,r23
- 1c4: (7e 1a 01 e6|e6 01 1a 7e) mtfprwz f16,r26
- 1c8: (7d b3 6c 18|18 6c b3 7d) lxsspx vs13,r19,r13
- 1cc: (7e 40 6c 18|18 6c 40 7e) lxsspx vs18,0,r13
- 1d0: (7d 62 25 19|19 25 62 7d) stxsspx vs43,r2,r4
- 1d4: (7e e0 5d 19|19 5d e0 7e) stxsspx vs55,0,r11
- 1d8: (f2 d0 c8 05|05 c8 d0 f2) xsaddsp vs54,vs48,vs25
- 1dc: (f1 d2 08 0c|0c 08 d2 f1) xsmaddasp vs14,vs50,vs1
- 1e0: (f3 56 50 42|42 50 56 f3) xssubsp vs26,vs22,vs42
- 1e4: (f3 75 a0 4e|4e a0 75 f3) xsmaddmsp vs27,vs53,vs52
- 1e8: (f1 00 d8 2a|2a d8 00 f1) xsrsqrtesp vs8,vs59
- 1ec: (f1 80 48 2e|2e 48 80 f1) xssqrtsp vs12,vs41
- 1f0: (f3 2b 00 83|83 00 2b f3) xsmulsp vs57,vs11,vs32
- 1f4: (f0 d4 d0 89|89 d0 d4 f0) xsmsubasp vs38,vs20,vs26
- 1f8: (f3 53 30 c0|c0 30 53 f3) xsdivsp vs26,vs19,vs6
- 1fc: (f0 65 b8 cf|cf b8 65 f0) xsmsubmsp vs35,vs37,vs55
- 200: (f3 60 40 69|69 40 60 f3) xsresp vs59,vs8
- 204: (f1 81 0c 0f|0f 0c 81 f1) xsnmaddasp vs44,vs33,vs33
- 208: (f2 3e f4 4c|4c f4 3e f2) xsnmaddmsp vs17,vs62,vs30
- 20c: (f2 d4 fc 8d|8d fc d4 f2) xsnmsubasp vs54,vs52,vs31
- 210: (f0 a5 d4 cb|cb d4 a5 f0) xsnmsubmsp vs37,vs5,vs58
- 214: (f3 d6 65 56|56 65 d6 f3) xxlorc vs30,vs54,vs44
- 218: (f2 2e ed 91|91 ed 2e f2) xxlnand vs49,vs14,vs29
- 21c: (f3 d6 f5 d1|d1 f5 d6 f3) xxleqv vs62,vs22,vs30
- 220: (f3 80 b4 2f|2f b4 80 f3) xscvdpspn vs60,vs54
- 224: (f2 c0 6c 66|66 6c c0 f2) xsrsp vs22,vs45
- 228: (f3 40 dc a2|a2 dc 40 f3) xscvuxdsp vs26,vs59
- 22c: (f0 c0 8c e3|e3 8c c0 f0) xscvsxdsp vs38,vs49
- 230: (f3 60 d5 2d|2d d5 60 f3) xscvspdpn vs59,vs26
- 234: (ff 0e 16 8c|8c 16 0e ff) fmrgow f24,f14,f2
- 238: (fe c7 2f 8c|8c 2f c7 fe) fmrgew f22,f7,f5
- 23c: (7c 00 71 9c|9c 71 00 7c) msgsnd r14
- 240: (7c 00 b9 dc|dc b9 00 7c) msgclr r23
+.*: (7c 05 07 1d|1d 07 05 7c) tabort\. r5
+.*: (7c e8 86 1d|1d 86 e8 7c) tabortwc\. 7,r8,r16
+.*: (7e 8b 56 5d|5d 56 8b 7e) tabortdc\. 20,r11,r10
+.*: (7e 2a 9e 9d|9d 9e 2a 7e) tabortwci\. 17,r10,-13
+.*: (7f a3 de dd|dd de a3 7f) tabortdci\. 29,r3,-5
+.*: (7c 00 05 1d|1d 05 00 7c) tbegin\.
+.*: (7f 80 05 9c|9c 05 80 7f) tcheck cr7
+.*: (7c 00 05 5d|5d 05 00 7c) tend\.
+.*: (7c 00 05 5d|5d 05 00 7c) tend\.
+.*: (7e 00 05 5d|5d 05 00 7e) tendall\.
+.*: (7e 00 05 5d|5d 05 00 7e) tendall\.
+.*: (7c 18 07 5d|5d 07 18 7c) treclaim\. r24
+.*: (7c 00 07 dd|dd 07 00 7c) trechkpt\.
+.*: (7c 00 05 dd|dd 05 00 7c) tsuspend\.
+.*: (7c 00 05 dd|dd 05 00 7c) tsuspend\.
+.*: (7c 20 05 dd|dd 05 20 7c) tresume\.
+.*: (7c 20 05 dd|dd 05 20 7c) tresume\.
+.*: (60 42 00 00|00 00 42 60) ori r2,r2,0
+.*: (60 00 00 00|00 00 00 60) nop
+.*: (60 42 00 00|00 00 42 60) ori r2,r2,0
+.*: (4c 00 01 24|24 01 00 4c) rfebb 0
+.*: (4c 00 09 24|24 09 00 4c) rfebb
+.*: (4c 00 09 24|24 09 00 4c) rfebb
+.*: (4d d5 04 60|60 04 d5 4d) bgttar- cr5
+.*: (4c c7 04 61|61 04 c7 4c) bnstarl- cr1
+.*: (4d ec 04 60|60 04 ec 4d) blttar\+ cr3
+.*: (4c e2 04 61|61 04 e2 4c) bnetarl\+
+.*: (4c 88 0c 60|60 0c 88 4c) bctar 4,4\*cr2\+lt,1
+.*: (4c 87 14 61|61 14 87 4c) bctarl 4,4\*cr1\+so,2
+.*: (7c 00 00 3c|3c 00 00 7c) waitasec
+.*: (7c 00 41 1c|1c 41 00 7c) msgsndp r8
+.*: (7c 20 01 26|26 01 20 7c) mtsle 1
+.*: (7c 00 d9 5c|5c d9 00 7c) msgclrp r27
+.*: (7d 4a 61 6d|6d 61 4a 7d) stqcx\. r10,r10,r12
+.*: (7f 80 39 6d|6d 39 80 7f) stqcx\. r28,0,r7
+.*: (7f 13 5a 28|28 5a 13 7f) lqarx r24,r19,r11
+.*: (7e c0 5a 28|28 5a c0 7e) lqarx r22,0,r11
+.*: (7e 80 32 5c|5c 32 80 7e) mfbhrbe r20,6
+.*: (7f b1 83 29|29 83 b1 7f) pbt\. r29,r17,r16
+.*: (7d c0 3b 29|29 3b c0 7d) pbt\. r14,0,r7
+.*: (7c 00 03 5c|5c 03 00 7c) clrbhrb
+.*: (11 6a 05 ed|ed 05 6a 11) vpermxor v11,v10,v0,v23
+.*: (13 02 39 3c|3c 39 02 13) vaddeuqm v24,v2,v7,v4
+.*: (11 4a 40 bd|bd 40 4a 11) vaddecuq v10,v10,v8,v2
+.*: (10 af 44 fe|fe 44 af 10) vsubeuqm v5,v15,v8,v19
+.*: (11 9f 87 7f|7f 87 9f 11) vsubecuq v12,v31,v16,v29
+.*: (12 9d 68 88|88 68 9d 12) vmulouw v20,v29,v13
+.*: (13 a0 d0 89|89 d0 a0 13) vmuluwm v29,v0,v26
+.*: (11 15 e0 c0|c0 e0 15 11) vaddudm v8,v21,v28
+.*: (10 3a 08 c2|c2 08 3a 10) vmaxud v1,v26,v1
+.*: (12 83 08 c4|c4 08 83 12) vrld v20,v3,v1
+.*: (10 93 58 c7|c7 58 93 10) vcmpequd v4,v19,v11
+.*: (12 ee f1 00|00 f1 ee 12) vadduqm v23,v14,v30
+.*: (11 08 69 40|40 69 08 11) vaddcuq v8,v8,v13
+.*: (13 9b 21 88|88 21 9b 13) vmulosw v28,v27,v4
+.*: (10 64 21 c2|c2 21 64 10) vmaxsd v3,v4,v4
+.*: (10 13 aa 88|88 aa 13 10) vmuleuw v0,v19,v21
+.*: (13 14 9a c2|c2 9a 14 13) vminud v24,v20,v19
+.*: (10 1c 7a c7|c7 7a 1c 10) vcmpgtud v0,v28,v15
+.*: (12 a0 13 88|88 13 a0 12) vmulesw v21,v0,v2
+.*: (11 3a 4b c2|c2 4b 3a 11) vminsd v9,v26,v9
+.*: (13 3d 5b c4|c4 5b 3d 13) vsrad v25,v29,v11
+.*: (11 7c 5b c7|c7 5b 7c 11) vcmpgtsd v11,v28,v11
+.*: (10 a8 d6 01|01 d6 a8 10) bcdadd\. v5,v8,v26,1
+.*: (10 83 64 08|08 64 83 10) vpmsumb v4,v3,v12
+.*: (13 5f ae 41|41 ae 5f 13) bcdsub\. v26,v31,v21,1
+.*: (10 b1 84 48|48 84 b1 10) vpmsumh v5,v17,v16
+.*: (12 f1 a4 4e|4e a4 f1 12) vpkudum v23,v17,v20
+.*: (13 15 ec 88|88 ec 15 13) vpmsumw v24,v21,v29
+.*: (11 36 6c c8|c8 6c 36 11) vpmsumd v9,v22,v13
+.*: (12 53 94 ce|ce 94 53 12) vpkudus v18,v19,v18
+.*: (13 d0 b5 00|00 b5 d0 13) vsubuqm v30,v16,v22
+.*: (11 cb 3d 08|08 3d cb 11) vcipher v14,v11,v7
+.*: (11 42 b5 09|09 b5 42 11) vcipherlast v10,v2,v22
+.*: (12 e0 6d 0c|0c 6d e0 12) vgbbd v23,v13
+.*: (12 19 85 40|40 85 19 12) vsubcuq v16,v25,v16
+.*: (13 e1 2d 44|44 2d e1 13) vorc v31,v1,v5
+.*: (10 91 fd 48|48 fd 91 10) vncipher v4,v17,v31
+.*: (13 02 dd 49|49 dd 02 13) vncipherlast v24,v2,v27
+.*: (12 f5 bd 4c|4c bd f5 12) vbpermq v23,v21,v23
+.*: (13 72 4d 4e|4e 4d 72 13) vpksdus v27,v18,v9
+.*: (13 7d dd 84|84 dd 7d 13) vnand v27,v29,v27
+.*: (12 73 c5 c4|c4 c5 73 12) vsld v19,v19,v24
+.*: (10 ad 05 c8|c8 05 ad 10) vsbox v5,v13
+.*: (13 23 3d ce|ce 3d 23 13) vpksdss v25,v3,v7
+.*: (13 88 04 c7|c7 04 88 13) vcmpequd\. v28,v8,v0
+.*: (13 40 d6 4e|4e d6 40 13) vupkhsw v26,v26
+.*: (10 a7 36 82|82 36 a7 10) vshasigmaw v5,v7,0,6
+.*: (13 95 76 84|84 76 95 13) veqv v28,v21,v14
+.*: (10 28 9e 8c|8c 9e 28 10) vmrgow v1,v8,v19
+.*: (10 0a 56 c2|c2 56 0a 10) vshasigmad v0,v10,0,10
+.*: (10 bb 76 c4|c4 76 bb 10) vsrd v5,v27,v14
+.*: (11 60 6e ce|ce 6e 60 11) vupklsw v11,v13
+.*: (11 c0 87 02|02 87 c0 11) vclzb v14,v16
+.*: (12 80 df 03|03 df 80 12) vpopcntb v20,v27
+.*: (13 80 5f 42|42 5f 80 13) vclzh v28,v11
+.*: (13 00 4f 43|43 4f 00 13) vpopcnth v24,v9
+.*: (13 60 ff 82|82 ff 60 13) vclzw v27,v31
+.*: (12 20 9f 83|83 9f 20 12) vpopcntw v17,v19
+.*: (11 80 ef c2|c2 ef 80 11) vclzd v12,v29
+.*: (12 e0 b7 c3|c3 b7 e0 12) vpopcntd v23,v22
+.*: (13 14 ee c7|c7 ee 14 13) vcmpgtud\. v24,v20,v29
+.*: (11 26 df c7|c7 df 26 11) vcmpgtsd\. v9,v6,v27
+.*: (7f ce d0 19|19 d0 ce 7f) lxsiwzx vs62,r14,r26
+.*: (7d 00 c8 19|19 c8 00 7d) lxsiwzx vs40,0,r25
+.*: (7f 20 d0 98|98 d0 20 7f) lxsiwax vs25,0,r26
+.*: (7c 60 18 98|98 18 60 7c) lxsiwax vs3,0,r3
+.*: (7f cc 00 67|67 00 cc 7f) (mfvrd r12,v30|mfvsrd r12,vs62)
+.*: (7d 94 00 e6|e6 00 94 7d) (mffprwz r20,f12|mfvsrwz r20,vs12)
+.*: (7d c9 71 18|18 71 c9 7d) stxsiwx vs14,r9,r14
+.*: (7e a0 41 18|18 41 a0 7e) stxsiwx vs21,0,r8
+.*: (7e 0b 01 67|67 01 0b 7e) (mtvrd v16,r11|mtvsrd vs48,r11)
+.*: (7f f7 01 a7|a7 01 f7 7f) (mtvrwa v31,r23|mtvsrwa vs63,r23)
+.*: (7e 1a 01 e6|e6 01 1a 7e) (mtfprwz f16,r26|mtvsrwz vs16,r26)
+.*: (7d b3 6c 18|18 6c b3 7d) lxsspx vs13,r19,r13
+.*: (7e 40 6c 18|18 6c 40 7e) lxsspx vs18,0,r13
+.*: (7d 62 25 19|19 25 62 7d) stxsspx vs43,r2,r4
+.*: (7e e0 5d 19|19 5d e0 7e) stxsspx vs55,0,r11
+.*: (f2 d0 c8 05|05 c8 d0 f2) xsaddsp vs54,vs48,vs25
+.*: (f1 d2 08 0c|0c 08 d2 f1) xsmaddasp vs14,vs50,vs1
+.*: (f3 56 50 42|42 50 56 f3) xssubsp vs26,vs22,vs42
+.*: (f3 75 a0 4e|4e a0 75 f3) xsmaddmsp vs27,vs53,vs52
+.*: (f1 00 d8 2a|2a d8 00 f1) xsrsqrtesp vs8,vs59
+.*: (f1 80 48 2e|2e 48 80 f1) xssqrtsp vs12,vs41
+.*: (f3 2b 00 83|83 00 2b f3) xsmulsp vs57,vs11,vs32
+.*: (f0 d4 d0 89|89 d0 d4 f0) xsmsubasp vs38,vs20,vs26
+.*: (f3 53 30 c0|c0 30 53 f3) xsdivsp vs26,vs19,vs6
+.*: (f0 65 b8 cf|cf b8 65 f0) xsmsubmsp vs35,vs37,vs55
+.*: (f3 60 40 69|69 40 60 f3) xsresp vs59,vs8
+.*: (f1 81 0c 0f|0f 0c 81 f1) xsnmaddasp vs44,vs33,vs33
+.*: (f2 3e f4 4c|4c f4 3e f2) xsnmaddmsp vs17,vs62,vs30
+.*: (f2 d4 fc 8d|8d fc d4 f2) xsnmsubasp vs54,vs52,vs31
+.*: (f0 a5 d4 cb|cb d4 a5 f0) xsnmsubmsp vs37,vs5,vs58
+.*: (f3 d6 65 56|56 65 d6 f3) xxlorc vs30,vs54,vs44
+.*: (f2 2e ed 91|91 ed 2e f2) xxlnand vs49,vs14,vs29
+.*: (f3 d6 f5 d1|d1 f5 d6 f3) xxleqv vs62,vs22,vs30
+.*: (f3 80 b4 2f|2f b4 80 f3) xscvdpspn vs60,vs54
+.*: (f2 c0 6c 66|66 6c c0 f2) xsrsp vs22,vs45
+.*: (f3 40 dc a2|a2 dc 40 f3) xscvuxdsp vs26,vs59
+.*: (f0 c0 8c e3|e3 8c c0 f0) xscvsxdsp vs38,vs49
+.*: (f3 60 d5 2d|2d d5 60 f3) xscvspdpn vs59,vs26
+.*: (ff 0e 16 8c|8c 16 0e ff) fmrgow f24,f14,f2
+.*: (fe c7 2f 8c|8c 2f c7 fe) fmrgew f22,f7,f5
+.*: (7c 00 71 9c|9c 71 00 7c) msgsnd r14
+.*: (7c 00 b9 dc|dc b9 00 7c) msgclr r23
.*: (7d 00 2e 99|99 2e 00 7d) lxvd2x vs40,0,r5
.*: (7d 00 2e 99|99 2e 00 7d) lxvd2x vs40,0,r5
.*: (7d 54 36 98|98 36 54 7d) lxvd2x vs10,r20,r6
@@ -310,4 +310,6 @@ Disassembly of section \.text:
.*: (4d 89 04 61|61 04 89 4d) bgttarl cr2
.*: (4d 89 04 61|61 04 89 4d) bgttarl cr2
.*: (4d 89 1c 61|61 1c 89 4d) bctarl 12,4\*cr2\+gt,3
+.*: (7f 5a d3 78|78 d3 5a 7f) miso
+.*: (7f 5a d3 78|78 d3 5a 7f) miso
#pass
diff -rup binutils.orig/gas/testsuite/gas/ppc/power8.s binutils-2.35.1/gas/testsuite/gas/ppc/power8.s
--- binutils.orig/gas/testsuite/gas/ppc/power8.s 2020-10-08 13:50:31.310909797 +0100
+++ binutils-2.35.1/gas/testsuite/gas/ppc/power8.s 2020-10-08 13:56:18.491840875 +0100
@@ -302,3 +302,5 @@ power8:
bctarl 0b01100,4*cr2+gt
bctarl 0b01100,4*cr2+gt,0
bctarl 0b01100,4*cr2+gt,3
+ or 26,26,26
+ miso
diff -rup binutils.orig/gas/testsuite/gas/ppc/power9.d binutils-2.35.1/gas/testsuite/gas/ppc/power9.d
--- binutils.orig/gas/testsuite/gas/ppc/power9.d 2020-10-08 13:50:31.312909791 +0100
+++ binutils-2.35.1/gas/testsuite/gas/ppc/power9.d 2020-10-08 13:56:18.491840875 +0100
@@ -399,4 +399,8 @@ Disassembly of section \.text:
.*: (7c 20 20 ac|ac 20 20 7c) dcbfl 0,r4
.*: (7c 60 28 ac|ac 28 60 7c) dcbflp 0,r5
.*: (7c 60 28 ac|ac 28 60 7c) dcbflp 0,r5
+.*: (63 ff 00 00|00 00 ff 63) exser
+.*: (63 ff 00 00|00 00 ff 63) exser
+.*: (7c 00 18 9c|9c 18 00 7c) msgsndu r3
+.*: (7c 00 d8 dc|dc d8 00 7c) msgclru r27
#pass
diff -rup binutils.orig/gas/testsuite/gas/ppc/power9.s binutils-2.35.1/gas/testsuite/gas/ppc/power9.s
--- binutils.orig/gas/testsuite/gas/ppc/power9.s 2020-10-08 13:50:31.314909784 +0100
+++ binutils-2.35.1/gas/testsuite/gas/ppc/power9.s 2020-10-08 13:56:18.492840872 +0100
@@ -390,3 +390,7 @@ power9:
dcbf 0,4,1
dcbflp 0,5
dcbf 0,5,3
+ ori 31,31,0
+ exser
+ msgsndu 3
+ msgclru 27
diff -rup binutils.orig/gas/testsuite/gas/ppc/ppc.exp binutils-2.35.1/gas/testsuite/gas/ppc/ppc.exp
--- binutils.orig/gas/testsuite/gas/ppc/ppc.exp 2020-10-08 13:50:31.314909784 +0100
+++ binutils-2.35.1/gas/testsuite/gas/ppc/ppc.exp 2020-10-08 13:51:29.102731857 +0100
@@ -76,6 +76,8 @@ if { [istarget powerpc64*-*-*] || [istar
run_dump_test "common"
run_dump_test "476"
run_dump_test "a2"
+run_dump_test "be"
+run_dump_test "le_error"
run_dump_test "pr21303"
run_dump_test "vle"
run_dump_test "vle-reloc"
diff -rup binutils.orig/gas/testsuite/gas/ppc/vsx2.d binutils-2.35.1/gas/testsuite/gas/ppc/vsx2.d
--- binutils.orig/gas/testsuite/gas/ppc/vsx2.d 2020-10-08 13:50:31.312909791 +0100
+++ binutils-2.35.1/gas/testsuite/gas/ppc/vsx2.d 2020-10-08 13:56:07.796873810 +0100
@@ -7,59 +7,59 @@
Disassembly of section \.text:
0+00 <vsx2>:
- 0: (7f ce d0 19|19 d0 ce 7f) lxsiwzx vs62,r14,r26
- 4: (7d 00 c8 19|19 c8 00 7d) lxsiwzx vs40,0,r25
- 8: (7f 20 d0 98|98 d0 20 7f) lxsiwax vs25,0,r26
- c: (7c 60 18 98|98 18 60 7c) lxsiwax vs3,0,r3
- 10: (7f cc 00 66|66 00 cc 7f) mfvsrd r12,vs30
- 14: (7f cc 00 66|66 00 cc 7f) mfvsrd r12,vs30
- 18: (7f cc 00 67|67 00 cc 7f) mfvsrd r12,vs62
- 1c: (7f cc 00 67|67 00 cc 7f) mfvsrd r12,vs62
- 20: (7d 94 00 e6|e6 00 94 7d) mffprwz r20,f12
- 24: (7d 94 00 e6|e6 00 94 7d) mffprwz r20,f12
- 28: (7d 95 00 e7|e7 00 95 7d) mfvrwz r21,v12
- 2c: (7d 95 00 e7|e7 00 95 7d) mfvrwz r21,v12
- 30: (7d c9 71 18|18 71 c9 7d) stxsiwx vs14,r9,r14
- 34: (7e a0 41 18|18 41 a0 7e) stxsiwx vs21,0,r8
- 38: (7d 7c 01 66|66 01 7c 7d) mtvsrd vs11,r28
- 3c: (7d 7c 01 66|66 01 7c 7d) mtvsrd vs11,r28
- 40: (7d 7d 01 67|67 01 7d 7d) mtvsrd vs43,r29
- 44: (7d 7d 01 67|67 01 7d 7d) mtvsrd vs43,r29
- 48: (7f 16 01 a6|a6 01 16 7f) mtfprwa f24,r22
- 4c: (7f 16 01 a6|a6 01 16 7f) mtfprwa f24,r22
- 50: (7f 37 01 a7|a7 01 37 7f) mtvrwa v25,r23
- 54: (7f 37 01 a7|a7 01 37 7f) mtvrwa v25,r23
- 58: (7f 5b 01 e6|e6 01 5b 7f) mtfprwz f26,r27
- 5c: (7f 5b 01 e6|e6 01 5b 7f) mtfprwz f26,r27
- 60: (7f 7c 01 e7|e7 01 7c 7f) mtvrwz v27,r28
- 64: (7f 7c 01 e7|e7 01 7c 7f) mtvrwz v27,r28
- 68: (7d b3 6c 18|18 6c b3 7d) lxsspx vs13,r19,r13
- 6c: (7e 40 6c 18|18 6c 40 7e) lxsspx vs18,0,r13
- 70: (7d 62 25 19|19 25 62 7d) stxsspx vs43,r2,r4
- 74: (7e e0 5d 19|19 5d e0 7e) stxsspx vs55,0,r11
- 78: (f2 d0 c8 05|05 c8 d0 f2) xsaddsp vs54,vs48,vs25
- 7c: (f1 d2 08 0c|0c 08 d2 f1) xsmaddasp vs14,vs50,vs1
- 80: (f3 56 50 42|42 50 56 f3) xssubsp vs26,vs22,vs42
- 84: (f3 75 a0 4e|4e a0 75 f3) xsmaddmsp vs27,vs53,vs52
- 88: (f1 00 d8 2a|2a d8 00 f1) xsrsqrtesp vs8,vs59
- 8c: (f1 80 48 2e|2e 48 80 f1) xssqrtsp vs12,vs41
- 90: (f3 2b 00 83|83 00 2b f3) xsmulsp vs57,vs11,vs32
- 94: (f0 d4 d0 89|89 d0 d4 f0) xsmsubasp vs38,vs20,vs26
- 98: (f3 53 30 c0|c0 30 53 f3) xsdivsp vs26,vs19,vs6
- 9c: (f0 65 b8 cf|cf b8 65 f0) xsmsubmsp vs35,vs37,vs55
- a0: (f3 60 40 69|69 40 60 f3) xsresp vs59,vs8
- a4: (f1 81 0c 0f|0f 0c 81 f1) xsnmaddasp vs44,vs33,vs33
- a8: (f2 3e f4 4c|4c f4 3e f2) xsnmaddmsp vs17,vs62,vs30
- ac: (f2 d4 fc 8d|8d fc d4 f2) xsnmsubasp vs54,vs52,vs31
- b0: (f0 a5 d4 cb|cb d4 a5 f0) xsnmsubmsp vs37,vs5,vs58
- b4: (f3 d6 65 56|56 65 d6 f3) xxlorc vs30,vs54,vs44
- b8: (f2 2e ed 91|91 ed 2e f2) xxlnand vs49,vs14,vs29
- bc: (f3 d6 f5 d1|d1 f5 d6 f3) xxleqv vs62,vs22,vs30
- c0: (f3 80 b4 2f|2f b4 80 f3) xscvdpspn vs60,vs54
- c4: (f2 c0 6c 66|66 6c c0 f2) xsrsp vs22,vs45
- c8: (f3 40 dc a2|a2 dc 40 f3) xscvuxdsp vs26,vs59
- cc: (f0 c0 8c e3|e3 8c c0 f0) xscvsxdsp vs38,vs49
- d0: (f3 60 d5 2d|2d d5 60 f3) xscvspdpn vs59,vs26
- d4: (ff 0e 16 8c|8c 16 0e ff) fmrgow f24,f14,f2
- d8: (fe c7 2f 8c|8c 2f c7 fe) fmrgew f22,f7,f5
+.*: (7f ce d0 19|19 d0 ce 7f) lxsiwzx vs62,r14,r26
+.*: (7d 00 c8 19|19 c8 00 7d) lxsiwzx vs40,0,r25
+.*: (7f 20 d0 98|98 d0 20 7f) lxsiwax vs25,0,r26
+.*: (7c 60 18 98|98 18 60 7c) lxsiwax vs3,0,r3
+.*: (7f cc 00 66|66 00 cc 7f) (mffprd r12,f30|mfvsrd r12,vs30)
+.*: (7f cc 00 66|66 00 cc 7f) (mffprd r12,f30|mfvsrd r12,vs30)
+.*: (7f cc 00 67|67 00 cc 7f) (mfvrd r12,v30|mfvsrd r12,vs62)
+.*: (7f cc 00 67|67 00 cc 7f) (mfvrd r12,v30|mfvsrd r12,vs62)
+.*: (7d 94 00 e6|e6 00 94 7d) (mffprwz r20,f12|mfvsrwz r20,vs12)
+.*: (7d 94 00 e6|e6 00 94 7d) (mffprwz r20,f12|mfvsrwz r20,vs12)
+.*: (7d 95 00 e7|e7 00 95 7d) (mfvrwz r21,v12|mfvsrwz r21,vs44)
+.*: (7d 95 00 e7|e7 00 95 7d) (mfvrwz r21,v12|mfvsrwz r21,vs44)
+.*: (7d c9 71 18|18 71 c9 7d) stxsiwx vs14,r9,r14
+.*: (7e a0 41 18|18 41 a0 7e) stxsiwx vs21,0,r8
+.*: (7d 7c 01 66|66 01 7c 7d) (mtfprd f11,r28|mtvsrd vs11,r28)
+.*: (7d 7c 01 66|66 01 7c 7d) (mtfprd f11,r28|mtvsrd vs11,r28)
+.*: (7d 7d 01 67|67 01 7d 7d) (mtvrd v11,r29|mtvsrd vs43,r29)
+.*: (7d 7d 01 67|67 01 7d 7d) (mtvrd v11,r29|mtvsrd vs43,r29)
+.*: (7f 16 01 a6|a6 01 16 7f) (mtfprwa f24,r22|mtvsrwa vs24,r22)
+.*: (7f 16 01 a6|a6 01 16 7f) (mtfprwa f24,r22|mtvsrwa vs24,r22)
+.*: (7f 37 01 a7|a7 01 37 7f) (mtvrwa v25,r23|mtvsrwa vs57,r23)
+.*: (7f 37 01 a7|a7 01 37 7f) (mtvrwa v25,r23|mtvsrwa vs57,r23)
+.*: (7f 5b 01 e6|e6 01 5b 7f) (mtfprwz f26,r27|mtvsrwz vs26,r27)
+.*: (7f 5b 01 e6|e6 01 5b 7f) (mtfprwz f26,r27|mtvsrwz vs26,r27)
+.*: (7f 7c 01 e7|e7 01 7c 7f) (mtvrwz v27,r28|mtvsrwz vs59,r28)
+.*: (7f 7c 01 e7|e7 01 7c 7f) (mtvrwz v27,r28|mtvsrwz vs59,r28)
+.*: (7d b3 6c 18|18 6c b3 7d) lxsspx vs13,r19,r13
+.*: (7e 40 6c 18|18 6c 40 7e) lxsspx vs18,0,r13
+.*: (7d 62 25 19|19 25 62 7d) stxsspx vs43,r2,r4
+.*: (7e e0 5d 19|19 5d e0 7e) stxsspx vs55,0,r11
+.*: (f2 d0 c8 05|05 c8 d0 f2) xsaddsp vs54,vs48,vs25
+.*: (f1 d2 08 0c|0c 08 d2 f1) xsmaddasp vs14,vs50,vs1
+.*: (f3 56 50 42|42 50 56 f3) xssubsp vs26,vs22,vs42
+.*: (f3 75 a0 4e|4e a0 75 f3) xsmaddmsp vs27,vs53,vs52
+.*: (f1 00 d8 2a|2a d8 00 f1) xsrsqrtesp vs8,vs59
+.*: (f1 80 48 2e|2e 48 80 f1) xssqrtsp vs12,vs41
+.*: (f3 2b 00 83|83 00 2b f3) xsmulsp vs57,vs11,vs32
+.*: (f0 d4 d0 89|89 d0 d4 f0) xsmsubasp vs38,vs20,vs26
+.*: (f3 53 30 c0|c0 30 53 f3) xsdivsp vs26,vs19,vs6
+.*: (f0 65 b8 cf|cf b8 65 f0) xsmsubmsp vs35,vs37,vs55
+.*: (f3 60 40 69|69 40 60 f3) xsresp vs59,vs8
+.*: (f1 81 0c 0f|0f 0c 81 f1) xsnmaddasp vs44,vs33,vs33
+.*: (f2 3e f4 4c|4c f4 3e f2) xsnmaddmsp vs17,vs62,vs30
+.*: (f2 d4 fc 8d|8d fc d4 f2) xsnmsubasp vs54,vs52,vs31
+.*: (f0 a5 d4 cb|cb d4 a5 f0) xsnmsubmsp vs37,vs5,vs58
+.*: (f3 d6 65 56|56 65 d6 f3) xxlorc vs30,vs54,vs44
+.*: (f2 2e ed 91|91 ed 2e f2) xxlnand vs49,vs14,vs29
+.*: (f3 d6 f5 d1|d1 f5 d6 f3) xxleqv vs62,vs22,vs30
+.*: (f3 80 b4 2f|2f b4 80 f3) xscvdpspn vs60,vs54
+.*: (f2 c0 6c 66|66 6c c0 f2) xsrsp vs22,vs45
+.*: (f3 40 dc a2|a2 dc 40 f3) xscvuxdsp vs26,vs59
+.*: (f0 c0 8c e3|e3 8c c0 f0) xscvsxdsp vs38,vs49
+.*: (f3 60 d5 2d|2d d5 60 f3) xscvspdpn vs59,vs26
+.*: (ff 0e 16 8c|8c 16 0e ff) fmrgow f24,f14,f2
+.*: (fe c7 2f 8c|8c 2f c7 fe) fmrgew f22,f7,f5
#pass
diff -rup binutils.orig/gas/testsuite/gas/ppc/xvtlsbb.d binutils-2.35.1/gas/testsuite/gas/ppc/xvtlsbb.d
--- binutils.orig/gas/testsuite/gas/ppc/xvtlsbb.d 2020-10-08 13:50:31.314909784 +0100
+++ binutils-2.35.1/gas/testsuite/gas/ppc/xvtlsbb.d 2020-10-08 13:50:58.204826992 +0100
@@ -7,7 +7,7 @@
Disassembly of section \.text:
0+0 <_start>:
-.*: (f0 02 ff 6e|6e ff 02 f0) xvtlsbb vs63
+.*: (f0 02 ff 6e|6e ff 02 f0) xvtlsbb cr0,vs63
.*: (f0 82 07 6c|6c 07 82 f0) xvtlsbb cr1,vs0
.*: (f1 02 f7 6e|6e f7 02 f1) xvtlsbb cr2,vs62
.*: (f1 82 0f 6c|6c 0f 82 f1) xvtlsbb cr3,vs1
diff -rup binutils.orig/gold/options.cc binutils-2.35.1/gold/options.cc
--- binutils.orig/gold/options.cc 2020-10-08 13:50:31.446909378 +0100
+++ binutils-2.35.1/gold/options.cc 2020-10-08 13:54:38.747147982 +0100
@@ -465,6 +465,14 @@ General_options::parse_plugin_opt(const
}
void
+General_options::parse_no_power10_stubs(const char*, const char*,
+ Command_line*)
+{
+ this->set_power10_stubs("no");
+ this->set_user_set_power10_stubs();
+}
+
+void
General_options::parse_R(const char* option, const char* arg,
Command_line* cmdline)
{
@@ -1183,6 +1191,27 @@ General_options::finalize()
this->set_start_stop_visibility_enum(elfcpp::STV_PROTECTED);
}
+ // Parse the --power10-stubs argument.
+ if (!this->user_set_power10_stubs())
+ {
+ // --power10-stubs without an arg is equivalent to --power10-stubs=yes
+ // but not specifying --power10-stubs at all should be equivalent to
+ // --power10-stubs=auto. This doesn't fit into the notion of
+ // "default_value", used both as a static initializer and to provide
+ // a missing optional arg. Fix it here.
+ this->set_power10_stubs("auto");
+ this->set_power10_stubs_enum(POWER10_STUBS_AUTO);
+ }
+ else
+ {
+ if (strcmp(this->power10_stubs(), "auto") == 0)
+ this->set_power10_stubs_enum(POWER10_STUBS_AUTO);
+ else if (strcmp(this->power10_stubs(), "no") == 0)
+ this->set_power10_stubs_enum(POWER10_STUBS_NO);
+ else if (strcmp(this->power10_stubs(), "yes") == 0)
+ this->set_power10_stubs_enum(POWER10_STUBS_YES);
+ }
+
// -M is equivalent to "-Map -".
if (this->print_map() && !this->user_set_Map())
{
diff -rup binutils.orig/gold/options.h binutils-2.35.1/gold/options.h
--- binutils.orig/gold/options.h 2020-10-08 13:50:31.447909375 +0100
+++ binutils-2.35.1/gold/options.h 2020-10-08 13:54:38.748147979 +0100
@@ -481,9 +481,9 @@ struct Struct_special : public Struct_va
// After helparg__ should come an initializer list, like
// {"foo", "bar", "baz"}
#define DEFINE_enum(varname__, dashes__, shortname__, default_value__, \
- helpstring__, helparg__, ...) \
+ helpstring__, helparg__, optional_arg__, ...) \
DEFINE_var(varname__, dashes__, shortname__, default_value__, \
- default_value__, helpstring__, helparg__, false, \
+ default_value__, helpstring__, helparg__, optional_arg__, \
const char*, const char*, parse_choices_##varname__, false) \
private: \
static void parse_choices_##varname__(const char* option_name, \
@@ -703,7 +703,7 @@ class General_options
N_("Use DT_NEEDED for all shared libraries"));
DEFINE_enum(assert, options::ONE_DASH, '\0', NULL,
- N_("Ignored"), N_("[ignored]"),
+ N_("Ignored"), N_("[ignored]"), false,
{"definitions", "nodefinitions", "nosymbolic", "pure-text"});
// b
@@ -761,7 +761,7 @@ class General_options
DEFINE_enum(compress_debug_sections, options::TWO_DASHES, '\0', "none",
N_("Compress .debug_* sections in the output file"),
- ("[none,zlib,zlib-gnu,zlib-gabi]"),
+ ("[none,zlib,zlib-gnu,zlib-gabi]"), false,
{"none", "zlib", "zlib-gnu", "zlib-gabi"});
DEFINE_bool(copy_dt_needed_entries, options::TWO_DASHES, '\0', false,
@@ -934,7 +934,7 @@ class General_options
N_("FRACTION"));
DEFINE_enum(hash_style, options::TWO_DASHES, '\0', DEFAULT_HASH_STYLE,
- N_("Dynamic hash style"), N_("[sysv,gnu,both]"),
+ N_("Dynamic hash style"), N_("[sysv,gnu,both]"), false,
{"sysv", "gnu", "both"});
// i
@@ -946,7 +946,7 @@ class General_options
N_("Identical Code Folding. "
"\'--icf=safe\' Folds ctors, dtors and functions whose"
" pointers are definitely not taken"),
- ("[none,all,safe]"),
+ ("[none,all,safe]"), false,
{"none", "all", "safe"});
DEFINE_uint(icf_iterations, options::TWO_DASHES , '\0', 0,
@@ -1086,7 +1086,7 @@ class General_options
DEFINE_enum(orphan_handling, options::TWO_DASHES, '\0', "place",
N_("Orphan section handling"), N_("[place,discard,warn,error]"),
- {"place", "discard", "warn", "error"});
+ false, {"place", "discard", "warn", "error"});
// p
@@ -1141,6 +1141,12 @@ class General_options
N_("Use posix_fallocate to reserve space in the output file"),
N_("Use fallocate or ftruncate to reserve space"));
+ DEFINE_enum(power10_stubs, options::TWO_DASHES, '\0', "yes",
+ N_("(PowerPC64 only) stubs use power10 insns"),
+ N_("[=auto,no,yes]"), true, {"auto", "no", "yes"});
+ DEFINE_special(no_power10_stubs, options::TWO_DASHES, '\0',
+ N_("(PowerPC64 only) stubs do not use power10 insns"), NULL);
+
DEFINE_bool(preread_archive_symbols, options::TWO_DASHES, '\0', false,
N_("Preread archive symbols when multi-threaded"), NULL);
@@ -1236,7 +1242,7 @@ class General_options
DEFINE_enum(sort_section, options::TWO_DASHES, '\0', "none",
N_("Sort sections by name. \'--no-text-reorder\'"
" will override \'--sort-section=name\' for .text"),
- N_("[none,name]"),
+ N_("[none,name]"), false,
{"none", "name"});
DEFINE_uint(spare_dynamic_tags, options::TWO_DASHES, '\0', 5,
@@ -1287,7 +1293,7 @@ class General_options
NULL);
DEFINE_enum(target2, options::TWO_DASHES, '\0', NULL,
N_("(ARM only) Set R_ARM_TARGET2 relocation type"),
- N_("[rel, abs, got-rel"),
+ N_("[rel, abs, got-rel"), false,
{"rel", "abs", "got-rel"});
DEFINE_bool(text_reorder, options::TWO_DASHES, '\0', true,
@@ -1344,7 +1350,7 @@ class General_options
DEFINE_enum(unresolved_symbols, options::TWO_DASHES, '\0', NULL,
N_("How to handle unresolved symbols"),
("ignore-all,report-all,ignore-in-object-files,"
- "ignore-in-shared-libs"),
+ "ignore-in-shared-libs"), false,
{"ignore-all", "report-all", "ignore-in-object-files",
"ignore-in-shared-libs"});
@@ -1507,7 +1513,7 @@ class General_options
DEFINE_enum(start_stop_visibility, options::DASH_Z, '\0', "protected",
N_("ELF symbol visibility for synthesized "
"__start_* and __stop_* symbols"),
- ("[default,internal,hidden,protected]"),
+ ("[default,internal,hidden,protected]"), false,
{"default", "internal", "hidden", "protected"});
DEFINE_bool(text, options::DASH_Z, '\0', false,
N_("Do not permit relocations in read-only segments"),
@@ -1763,6 +1769,20 @@ class General_options
start_stop_visibility_enum() const
{ return this->start_stop_visibility_enum_; }
+ enum Power10_stubs
+ {
+ // Use Power10 insns on @notoc calls/branches, non-Power10 elsewhere.
+ POWER10_STUBS_AUTO,
+ // Don't use Power10 insns
+ POWER10_STUBS_NO,
+ // Always use Power10 insns
+ POWER10_STUBS_YES
+ };
+
+ Power10_stubs
+ power10_stubs_enum() const
+ { return this->power10_stubs_enum_; }
+
private:
// Don't copy this structure.
General_options(const General_options&);
@@ -1826,6 +1846,10 @@ class General_options
set_start_stop_visibility_enum(elfcpp::STV value)
{ this->start_stop_visibility_enum_ = value; }
+ void
+ set_power10_stubs_enum(Power10_stubs value)
+ { this->power10_stubs_enum_ = value; }
+
// These are called by finalize() to set up the search-path correctly.
void
add_to_library_path_with_sysroot(const std::string& arg)
@@ -1895,6 +1919,8 @@ class General_options
Orphan_handling orphan_handling_enum_;
// Symbol visibility for __start_* / __stop_* magic symbols.
elfcpp::STV start_stop_visibility_enum_;
+ // Power10 stubs option
+ Power10_stubs power10_stubs_enum_;
};
// The position-dependent options. We use this to store the state of
diff -rup binutils.orig/gold/powerpc.cc binutils-2.35.1/gold/powerpc.cc
--- binutils.orig/gold/powerpc.cc 2020-10-08 13:50:31.445909381 +0100
+++ binutils-2.35.1/gold/powerpc.cc 2020-10-08 13:55:52.171921920 +0100
@@ -647,7 +647,7 @@ class Target_powerpc : public Sized_targ
glink_(NULL), rela_dyn_(NULL), copy_relocs_(),
tlsld_got_offset_(-1U),
stub_tables_(), branch_lookup_table_(), branch_info_(), tocsave_loc_(),
- power10_stubs_(false), plt_thread_safe_(false), plt_localentry0_(false),
+ power10_relocs_(false), plt_thread_safe_(false), plt_localentry0_(false),
plt_localentry0_init_(false), has_localentry0_(false),
has_tls_get_addr_opt_(false),
tprel_opt_(parameters->options().tls_optimize()),
@@ -1079,14 +1079,25 @@ class Target_powerpc : public Sized_targ
sym->set_dynsym_index(-1U);
}
+ void
+ set_power10_relocs()
+ {
+ this->power10_relocs_ = true;
+ }
+
bool
power10_stubs() const
- { return this->power10_stubs_; }
+ {
+ return (this->power10_relocs_
+ && (parameters->options().power10_stubs_enum()
+ != General_options::POWER10_STUBS_NO));
+ }
- void
- set_power10_stubs()
+ bool
+ power10_stubs_auto() const
{
- this->power10_stubs_ = true;
+ return (parameters->options().power10_stubs_enum()
+ == General_options::POWER10_STUBS_AUTO);
}
bool
@@ -1097,6 +1108,10 @@ class Target_powerpc : public Sized_targ
plt_localentry0() const
{ return this->plt_localentry0_; }
+ bool
+ has_localentry0() const
+ { return this->has_localentry0_; }
+
void
set_has_localentry0()
{
@@ -1696,7 +1711,7 @@ class Target_powerpc : public Sized_targ
Branches branch_info_;
Tocsave_loc tocsave_loc_;
- bool power10_stubs_;
+ bool power10_relocs_;
bool plt_thread_safe_;
bool plt_localentry0_;
bool plt_localentry0_init_;
@@ -4181,6 +4196,7 @@ static const uint32_t cmpwi_11_0 = 0x2c0
static const uint32_t cror_15_15_15 = 0x4def7b82;
static const uint32_t cror_31_31_31 = 0x4ffffb82;
static const uint32_t ld_0_1 = 0xe8010000;
+static const uint32_t ld_0_11 = 0xe80b0000;
static const uint32_t ld_0_12 = 0xe80c0000;
static const uint32_t ld_2_1 = 0xe8410000;
static const uint32_t ld_2_2 = 0xe8420000;
@@ -4563,9 +4579,9 @@ static const unsigned char glink_eh_fram
0, 0, 0, 0, // Replaced with offset to .glink.
0, 0, 0, 0, // Replaced with size of .glink.
0, // Augmentation size.
- elfcpp::DW_CFA_advance_loc + 1,
+ elfcpp::DW_CFA_advance_loc + 2,
elfcpp::DW_CFA_register, 65, 12,
- elfcpp::DW_CFA_advance_loc + 5,
+ elfcpp::DW_CFA_advance_loc + 4,
elfcpp::DW_CFA_restore_extended, 65
};
@@ -4575,9 +4591,20 @@ static const unsigned char glink_eh_fram
0, 0, 0, 0, // Replaced with offset to .glink.
0, 0, 0, 0, // Replaced with size of .glink.
0, // Augmentation size.
- elfcpp::DW_CFA_advance_loc + 1,
+ elfcpp::DW_CFA_advance_loc + 2,
elfcpp::DW_CFA_register, 65, 0,
- elfcpp::DW_CFA_advance_loc + 7,
+ elfcpp::DW_CFA_advance_loc + 2,
+ elfcpp::DW_CFA_restore_extended, 65
+};
+
+static const unsigned char glink_eh_frame_fde_64v2_localentry0[] =
+{
+ 0, 0, 0, 0, // Replaced with offset to .glink.
+ 0, 0, 0, 0, // Replaced with size of .glink.
+ 0, // Augmentation size.
+ elfcpp::DW_CFA_advance_loc + 3,
+ elfcpp::DW_CFA_register, 65, 0,
+ elfcpp::DW_CFA_advance_loc + 2,
elfcpp::DW_CFA_restore_extended, 65
};
@@ -4631,26 +4658,32 @@ class Stub_table : public Output_relaxed
struct Plt_stub_ent
{
Plt_stub_ent(unsigned int off, unsigned int indx)
- : off_(off), indx_(indx), iter_(0), notoc_(0), r2save_(0), localentry0_(0)
+ : off_(off), indx_(indx), iter_(0), notoc_(0), toc_(0),
+ r2save_(0), localentry0_(0), tocoff_(0)
{ }
unsigned int off_;
- unsigned int indx_ : 28;
+ unsigned int indx_;
unsigned int iter_ : 1;
unsigned int notoc_ : 1;
+ unsigned int toc_ : 1;
unsigned int r2save_ : 1;
unsigned int localentry0_ : 1;
+ unsigned int tocoff_ : 8;
};
struct Branch_stub_ent
{
Branch_stub_ent(unsigned int off, bool notoc, bool save_res)
- : off_(off), iter_(false), notoc_(notoc), save_res_(save_res)
+ : off_(off), iter_(0), notoc_(notoc), toc_(0), save_res_(save_res),
+ tocoff_(0)
{ }
unsigned int off_;
- bool iter_;
- bool notoc_;
- bool save_res_;
+ unsigned int iter_ : 1;
+ unsigned int notoc_ : 1;
+ unsigned int toc_ : 1;
+ unsigned int save_res_ : 1;
+ unsigned int tocoff_ : 8;
};
typedef typename elfcpp::Elf_types<size>::Elf_Addr Address;
static const Address invalid_address = static_cast<Address>(0) - 1;
@@ -4898,7 +4931,7 @@ class Stub_table : public Output_relaxed
// Size of a given plt call stub.
unsigned int
- plt_call_size(typename Plt_stub_entries::const_iterator p) const;
+ plt_call_size(typename Plt_stub_entries::iterator p) const;
unsigned int
plt_call_align(unsigned int bytes) const
@@ -4909,16 +4942,14 @@ class Stub_table : public Output_relaxed
// Return long branch stub size.
unsigned int
- branch_stub_size(typename Branch_stub_entries::const_iterator p,
+ branch_stub_size(typename Branch_stub_entries::iterator p,
bool* need_lt);
- bool
- build_tls_opt_head(unsigned char** pp,
- typename Plt_stub_entries::const_iterator cs);
+ void
+ build_tls_opt_head(unsigned char** pp, bool save_lr);
- bool
- build_tls_opt_tail(unsigned char* p,
- typename Plt_stub_entries::const_iterator cs);
+ void
+ build_tls_opt_tail(unsigned char* p);
void
plt_error(const Plt_stub_key& p);
@@ -5083,15 +5114,22 @@ Stub_table<size, big_endian>::add_plt_ca
if (r_type == elfcpp::R_PPC64_REL24_NOTOC)
{
if (!p.second && !p.first->second.notoc_
- && !this->targ_->power10_stubs())
+ && (!this->targ_->power10_stubs()
+ || this->targ_->power10_stubs_auto()))
this->need_resize_ = true;
p.first->second.notoc_ = 1;
}
- else if (!tocsave && !p.first->second.localentry0_)
+ else
{
- if (!p.second && !p.first->second.r2save_)
+ if (!p.second && !p.first->second.toc_)
this->need_resize_ = true;
- p.first->second.r2save_ = 1;
+ p.first->second.toc_ = 1;
+ if (!tocsave && !p.first->second.localentry0_)
+ {
+ if (!p.second && !p.first->second.r2save_)
+ this->need_resize_ = true;
+ p.first->second.r2save_ = 1;
+ }
}
}
if (p.second || (this->resizing_ && !p.first->second.iter_))
@@ -5134,15 +5172,22 @@ Stub_table<size, big_endian>::add_plt_ca
if (r_type == elfcpp::R_PPC64_REL24_NOTOC)
{
if (!p.second && !p.first->second.notoc_
- && !this->targ_->power10_stubs())
+ && (!this->targ_->power10_stubs()
+ || this->targ_->power10_stubs_auto()))
this->need_resize_ = true;
p.first->second.notoc_ = 1;
}
- else if (!tocsave && !p.first->second.localentry0_)
+ else
{
- if (!p.second && !p.first->second.r2save_)
+ if (!p.second && !p.first->second.toc_)
this->need_resize_ = true;
- p.first->second.r2save_ = 1;
+ p.first->second.toc_ = 1;
+ if (!tocsave && !p.first->second.localentry0_)
+ {
+ if (!p.second && !p.first->second.r2save_)
+ this->need_resize_ = true;
+ p.first->second.r2save_ = 1;
+ }
}
}
if (p.second || (this->resizing_ && !p.first->second.iter_))
@@ -5231,11 +5276,18 @@ Stub_table<size, big_endian>::add_long_b
Branch_stub_ent ent(this->branch_size_, notoc, save_res);
std::pair<typename Branch_stub_entries::iterator, bool> p
= this->long_branch_stubs_.insert(std::make_pair(key, ent));
- if (notoc && !p.first->second.notoc_)
+ if (notoc)
{
- this->need_resize_ = true;
+ if (!p.second && !p.first->second.notoc_)
+ this->need_resize_ = true;
p.first->second.notoc_ = true;
}
+ else
+ {
+ if (!p.second && !p.first->second.toc_)
+ this->need_resize_ = true;
+ p.first->second.toc_ = true;
+ }
gold_assert(save_res == p.first->second.save_res_);
if (p.second || (this->resizing_ && !p.first->second.iter_))
{
@@ -5330,7 +5382,7 @@ Stub_table<size, big_endian>::add_eh_fra
if (!this->targ_->has_glink())
return;
- typedef typename Plt_stub_entries::const_iterator plt_iter;
+ typedef typename Plt_stub_entries::iterator plt_iter;
std::vector<plt_iter> calls;
if (!this->plt_call_stubs_.empty())
for (plt_iter cs = this->plt_call_stubs_.begin();
@@ -5491,7 +5543,8 @@ class Output_data_glink : public Output_
{
if (size == 64)
return (8
- + (this->targ_->abiversion() < 2 ? 11 * 4 : 14 * 4));
+ + (this->targ_->abiversion() < 2 ? 11 * 4
+ : this->targ_->has_localentry0() ? 14 * 4 : 13 * 4));
return 16 * 4;
}
@@ -5534,6 +5587,12 @@ Output_data_glink<size, big_endian>::add
sizeof (Eh_cie<64>::eh_frame_cie),
glink_eh_frame_fde_64v1,
sizeof (glink_eh_frame_fde_64v1));
+ else if (this->targ_->has_localentry0())
+ layout->add_eh_frame_for_plt(this,
+ Eh_cie<64>::eh_frame_cie,
+ sizeof (Eh_cie<64>::eh_frame_cie),
+ glink_eh_frame_fde_64v2_localentry0,
+ sizeof (glink_eh_frame_fde_64v2));
else
layout->add_eh_frame_for_plt(this,
Eh_cie<64>::eh_frame_cie,
@@ -5632,7 +5691,7 @@ Stub_table<size, big_endian>::define_stu
// output .symtab ordering depends on the order in which symbols
// are added to the linker symtab. We want reproducible output
// so must sort the call stub symbols.
- typedef typename Plt_stub_entries::const_iterator plt_iter;
+ typedef typename Plt_stub_entries::iterator plt_iter;
std::vector<plt_iter> sorted;
sorted.resize(this->plt_call_stubs_.size());
@@ -5676,7 +5735,7 @@ Stub_table<size, big_endian>::define_stu
}
}
- typedef typename Branch_stub_entries::const_iterator branch_iter;
+ typedef typename Branch_stub_entries::iterator branch_iter;
for (branch_iter bs = this->long_branch_stubs_.begin();
bs != this->long_branch_stubs_.end();
++bs)
@@ -5698,88 +5757,72 @@ Stub_table<size, big_endian>::define_stu
// Emit the start of a __tls_get_addr_opt plt call stub.
template<int size, bool big_endian>
-bool
-Stub_table<size, big_endian>::build_tls_opt_head(
- unsigned char** pp,
- typename Plt_stub_entries::const_iterator cs)
+void
+Stub_table<size, big_endian>::build_tls_opt_head(unsigned char** pp,
+ bool save_lr)
{
- if (this->targ_->is_tls_get_addr_opt(cs->first.sym_))
+ unsigned char* p = *pp;
+ if (size == 64)
{
- unsigned char* p = *pp;
- if (size == 64)
- {
- write_insn<big_endian>(p, ld_11_3 + 0);
- p += 4;
- write_insn<big_endian>(p, ld_12_3 + 8);
- p += 4;
- write_insn<big_endian>(p, mr_0_3);
- p += 4;
- write_insn<big_endian>(p, cmpdi_11_0);
- p += 4;
- write_insn<big_endian>(p, add_3_12_13);
- p += 4;
- write_insn<big_endian>(p, beqlr);
- p += 4;
- write_insn<big_endian>(p, mr_3_0);
- p += 4;
- if (cs->second.r2save_ && !cs->second.localentry0_)
- {
- write_insn<big_endian>(p, mflr_11);
- p += 4;
- write_insn<big_endian>(p, (std_11_1 + this->targ_->stk_linker()));
- p += 4;
- }
- }
- else
+ write_insn<big_endian>(p, ld_11_3 + 0);
+ p += 4;
+ write_insn<big_endian>(p, ld_12_3 + 8);
+ p += 4;
+ write_insn<big_endian>(p, mr_0_3);
+ p += 4;
+ write_insn<big_endian>(p, cmpdi_11_0);
+ p += 4;
+ write_insn<big_endian>(p, add_3_12_13);
+ p += 4;
+ write_insn<big_endian>(p, beqlr);
+ p += 4;
+ write_insn<big_endian>(p, mr_3_0);
+ p += 4;
+ if (save_lr)
{
- write_insn<big_endian>(p, lwz_11_3 + 0);
- p += 4;
- write_insn<big_endian>(p, lwz_12_3 + 4);
+ write_insn<big_endian>(p, mflr_11);
p += 4;
- write_insn<big_endian>(p, mr_0_3);
- p += 4;
- write_insn<big_endian>(p, cmpwi_11_0);
- p += 4;
- write_insn<big_endian>(p, add_3_12_2);
- p += 4;
- write_insn<big_endian>(p, beqlr);
- p += 4;
- write_insn<big_endian>(p, mr_3_0);
- p += 4;
- write_insn<big_endian>(p, nop);
+ write_insn<big_endian>(p, (std_11_1 + this->targ_->stk_linker()));
p += 4;
}
- *pp = p;
- return true;
}
- return false;
-}
-
-// Emit the tail of a __tls_get_addr_opt plt call stub.
-
-template<int size, bool big_endian>
-bool
-Stub_table<size, big_endian>::build_tls_opt_tail(
- unsigned char* p,
- typename Plt_stub_entries::const_iterator cs)
-{
- if (size == 64
- && cs->second.r2save_
- && !cs->second.localentry0_
- && this->targ_->is_tls_get_addr_opt(cs->first.sym_))
+ else
{
- write_insn<big_endian>(p, bctrl);
+ write_insn<big_endian>(p, lwz_11_3 + 0);
p += 4;
- write_insn<big_endian>(p, ld_2_1 + this->targ_->stk_toc());
+ write_insn<big_endian>(p, lwz_12_3 + 4);
p += 4;
- write_insn<big_endian>(p, ld_11_1 + this->targ_->stk_linker());
+ write_insn<big_endian>(p, mr_0_3);
p += 4;
- write_insn<big_endian>(p, mtlr_11);
+ write_insn<big_endian>(p, cmpwi_11_0);
+ p += 4;
+ write_insn<big_endian>(p, add_3_12_2);
+ p += 4;
+ write_insn<big_endian>(p, beqlr);
+ p += 4;
+ write_insn<big_endian>(p, mr_3_0);
+ p += 4;
+ write_insn<big_endian>(p, nop);
p += 4;
- write_insn<big_endian>(p, blr);
- return true;
}
- return false;
+ *pp = p;
+}
+
+// Emit the tail of a __tls_get_addr_opt plt call stub.
+
+template<int size, bool big_endian>
+void
+Stub_table<size, big_endian>::build_tls_opt_tail(unsigned char* p)
+{
+ write_insn<big_endian>(p, bctrl);
+ p += 4;
+ write_insn<big_endian>(p, ld_2_1 + this->targ_->stk_toc());
+ p += 4;
+ write_insn<big_endian>(p, ld_11_1 + this->targ_->stk_linker());
+ p += 4;
+ write_insn<big_endian>(p, mtlr_11);
+ p += 4;
+ write_insn<big_endian>(p, blr);
}
// Emit pc-relative plt call stub code.
@@ -5949,7 +5992,7 @@ build_notoc_offset(unsigned char* p, uin
template<int size, bool big_endian>
unsigned int
Stub_table<size, big_endian>::plt_call_size(
- typename Plt_stub_entries::const_iterator p) const
+ typename Plt_stub_entries::iterator p) const
{
if (size == 32)
{
@@ -5961,77 +6004,122 @@ Stub_table<size, big_endian>::plt_call_s
const Output_data_plt_powerpc<size, big_endian>* plt;
uint64_t plt_addr = this->plt_off(p, &plt);
plt_addr += plt->address();
- unsigned int bytes = 0;
- const Symbol* gsym = p->first.sym_;
- if (this->targ_->is_tls_get_addr_opt(gsym))
+ if (this->targ_->power10_stubs()
+ && this->targ_->power10_stubs_auto())
{
- if (p->second.r2save_ && !p->second.localentry0_)
- bytes = 13 * 4;
- else
- bytes = 7 * 4;
+ unsigned int bytes = 0;
+ if (p->second.notoc_)
+ {
+ if (this->targ_->is_tls_get_addr_opt(p->first.sym_))
+ bytes = 7 * 4;
+ uint64_t from = this->stub_address() + p->second.off_ + bytes;
+ uint64_t odd = from & 4;
+ uint64_t off = plt_addr - from;
+ if (off - odd + (1ULL << 33) < 1ULL << 34)
+ bytes += odd + 4 * 4;
+ else if (off - (8 - odd) + (0x20002ULL << 32) < 0x40004ULL << 32)
+ bytes += 7 * 4;
+ else
+ bytes += 8 * 4;
+ bytes = this->plt_call_align(bytes);
+ }
+ unsigned int tail = 0;
+ if (p->second.toc_)
+ {
+ p->second.tocoff_ = bytes;
+ if (this->targ_->is_tls_get_addr_opt(p->first.sym_))
+ {
+ bytes += 7 * 4;
+ if (p->second.r2save_ && !p->second.localentry0_)
+ {
+ bytes += 2 * 4;
+ tail = 4 * 4;
+ }
+ }
+ if (p->second.r2save_)
+ bytes += 4;
+ uint64_t got_addr
+ = this->targ_->got_section()->output_section()->address();
+ const Powerpc_relobj<size, big_endian>* ppcobj = static_cast
+ <const Powerpc_relobj<size, big_endian>*>(p->first.object_);
+ got_addr += ppcobj->toc_base_offset();
+ uint64_t off = plt_addr - got_addr;
+ bytes += 3 * 4 + 4 * (ha(off) != 0);
+ }
+ return bytes + tail;
}
-
- if (p->second.r2save_)
- bytes += 4;
-
- if (this->targ_->power10_stubs())
+ else
{
- uint64_t from = this->stub_address() + p->second.off_ + bytes;
- if (bytes > 8 * 4)
- from -= 4 * 4;
- uint64_t odd = from & 4;
- uint64_t off = plt_addr - from;
- if (off - odd + (1ULL << 33) < 1ULL << 34)
- bytes += odd + 4 * 4;
- else if (off - (8 - odd) + (0x20002ULL << 32) < 0x40004ULL << 32)
- bytes += 7 * 4;
- else
- bytes += 8 * 4;
- return bytes;
- }
+ unsigned int bytes = 0;
+ unsigned int tail = 0;
+ if (this->targ_->is_tls_get_addr_opt(p->first.sym_))
+ {
+ bytes = 7 * 4;
+ if (p->second.r2save_ && !p->second.localentry0_)
+ {
+ bytes = 9 * 4;
+ tail = 4 * 4;
+ }
+ }
- if (p->second.notoc_)
- {
- uint64_t from = this->stub_address() + p->second.off_ + bytes + 2 * 4;
- if (bytes > 32)
- from -= 4 * 4;
- uint64_t off = plt_addr - from;
- if (off + 0x8000 < 0x10000)
- bytes += 7 * 4;
- else if (off + 0x80008000ULL < 0x100000000ULL)
- bytes += 8 * 4;
- else
+ if (p->second.r2save_)
+ bytes += 4;
+
+ if (this->targ_->power10_stubs())
{
- bytes += 8 * 4;
- if (off + 0x800000000000ULL >= 0x1000000000000ULL
- && ((off >> 32) & 0xffff) != 0)
- bytes += 4;
- if (((off >> 32) & 0xffffffffULL) != 0)
- bytes += 4;
- if (hi(off) != 0)
- bytes += 4;
- if (l(off) != 0)
- bytes += 4;
+ uint64_t from = this->stub_address() + p->second.off_ + bytes;
+ uint64_t odd = from & 4;
+ uint64_t off = plt_addr - from;
+ if (off - odd + (1ULL << 33) < 1ULL << 34)
+ bytes += odd + 4 * 4;
+ else if (off - (8 - odd) + (0x20002ULL << 32) < 0x40004ULL << 32)
+ bytes += 7 * 4;
+ else
+ bytes += 8 * 4;
+ return bytes + tail;
}
- return bytes;
- }
- uint64_t got_addr = this->targ_->got_section()->output_section()->address();
- const Powerpc_relobj<size, big_endian>* ppcobj = static_cast
- <const Powerpc_relobj<size, big_endian>*>(p->first.object_);
- got_addr += ppcobj->toc_base_offset();
- uint64_t off = plt_addr - got_addr;
- bytes += 3 * 4 + 4 * (ha(off) != 0);
- if (this->targ_->abiversion() < 2)
- {
- bool static_chain = parameters->options().plt_static_chain();
- bool thread_safe = this->targ_->plt_thread_safe();
- bytes += (4
- + 4 * static_chain
- + 8 * thread_safe
- + 4 * (ha(off + 8 + 8 * static_chain) != ha(off)));
+ if (p->second.notoc_)
+ {
+ uint64_t from = this->stub_address() + p->second.off_ + bytes + 2 * 4;
+ uint64_t off = plt_addr - from;
+ if (off + 0x8000 < 0x10000)
+ bytes += 7 * 4;
+ else if (off + 0x80008000ULL < 0x100000000ULL)
+ bytes += 8 * 4;
+ else
+ {
+ bytes += 8 * 4;
+ if (off + 0x800000000000ULL >= 0x1000000000000ULL
+ && ((off >> 32) & 0xffff) != 0)
+ bytes += 4;
+ if (((off >> 32) & 0xffffffffULL) != 0)
+ bytes += 4;
+ if (hi(off) != 0)
+ bytes += 4;
+ if (l(off) != 0)
+ bytes += 4;
+ }
+ return bytes + tail;
+ }
+
+ uint64_t got_addr = this->targ_->got_section()->output_section()->address();
+ const Powerpc_relobj<size, big_endian>* ppcobj = static_cast
+ <const Powerpc_relobj<size, big_endian>*>(p->first.object_);
+ got_addr += ppcobj->toc_base_offset();
+ uint64_t off = plt_addr - got_addr;
+ bytes += 3 * 4 + 4 * (ha(off) != 0);
+ if (this->targ_->abiversion() < 2)
+ {
+ bool static_chain = parameters->options().plt_static_chain();
+ bool thread_safe = this->targ_->plt_thread_safe();
+ bytes += (4
+ + 4 * static_chain
+ + 8 * thread_safe
+ + 4 * (ha(off + 8 + 8 * static_chain) != ha(off)));
+ }
+ return bytes + tail;
}
- return bytes;
}
// Return long branch stub size.
@@ -6039,7 +6127,7 @@ Stub_table<size, big_endian>::plt_call_s
template<int size, bool big_endian>
unsigned int
Stub_table<size, big_endian>::branch_stub_size(
- typename Branch_stub_entries::const_iterator p,
+ typename Branch_stub_entries::iterator p,
bool* need_lt)
{
Address loc = this->stub_address() + this->last_plt_size_ + p->second.off_;
@@ -6053,46 +6141,56 @@ Stub_table<size, big_endian>::branch_stu
}
uint64_t off = p->first.dest_ - loc;
+ unsigned int bytes = 0;
if (p->second.notoc_)
{
if (this->targ_->power10_stubs())
{
Address odd = loc & 4;
if (off + (1 << 25) < 2 << 25)
- return odd + 12;
- if (off - odd + (1ULL << 33) < 1ULL << 34)
- return odd + 16;
- if (off - (8 - odd) + (0x20002ULL << 32) < 0x40004ULL << 32)
- return 28;
- return 32;
- }
- off -= 8;
- if (off + 0x8000 < 0x10000)
- return 24;
- if (off + 0x80008000ULL < 0x100000000ULL)
- {
- if (off + 24 + (1 << 25) < 2 << 25)
- return 28;
- return 32;
- }
- unsigned int bytes = 32;
- if (off + 0x800000000000ULL >= 0x1000000000000ULL
- && ((off >> 32) & 0xffff) != 0)
- bytes += 4;
- if (((off >> 32) & 0xffffffffULL) != 0)
- bytes += 4;
- if (hi(off) != 0)
- bytes += 4;
- if (l(off) != 0)
- bytes += 4;
- return bytes;
+ bytes = odd + 12;
+ else if (off - odd + (1ULL << 33) < 1ULL << 34)
+ bytes = odd + 16;
+ else if (off - (8 - odd) + (0x20002ULL << 32) < 0x40004ULL << 32)
+ bytes = 28;
+ else
+ bytes = 32;
+ if (!(p->second.toc_ && this->targ_->power10_stubs_auto()))
+ return bytes;
+ p->second.tocoff_ = bytes;
+ }
+ else
+ {
+ off -= 8;
+ if (off + 0x8000 < 0x10000)
+ return 24;
+ if (off + 0x80008000ULL < 0x100000000ULL)
+ {
+ if (off + 24 + (1 << 25) < 2 << 25)
+ return 28;
+ return 32;
+ }
+
+ bytes = 32;
+ if (off + 0x800000000000ULL >= 0x1000000000000ULL
+ && ((off >> 32) & 0xffff) != 0)
+ bytes += 4;
+ if (((off >> 32) & 0xffffffffULL) != 0)
+ bytes += 4;
+ if (hi(off) != 0)
+ bytes += 4;
+ if (l(off) != 0)
+ bytes += 4;
+ return bytes;
+ }
}
if (off + (1 << 25) < 2 << 25)
- return 4;
- if (!this->targ_->power10_stubs())
+ return bytes + 4;
+ if (!this->targ_->power10_stubs()
+ || (p->second.toc_ && this->targ_->power10_stubs_auto()))
*need_lt = true;
- return 16;
+ return bytes + 16;
}
template<int size, bool big_endian>
@@ -6128,6 +6226,10 @@ Stub_table<size, big_endian>::do_write(O
if (size == 64
&& this->targ_->power10_stubs())
{
+ const Output_data_got_powerpc<size, big_endian>* got
+ = this->targ_->got_section();
+ Address got_os_addr = got->output_section()->address();
+
if (!this->plt_call_stubs_.empty())
{
// Write out plt call stubs.
@@ -6137,22 +6239,94 @@ Stub_table<size, big_endian>::do_write(O
++cs)
{
p = oview + cs->second.off_;
- this->build_tls_opt_head(&p, cs);
- if (cs->second.r2save_)
- {
- write_insn<big_endian>(p, std_2_1 + this->targ_->stk_toc());
- p += 4;
- }
const Output_data_plt_powerpc<size, big_endian>* plt;
Address pltoff = this->plt_off(cs, &plt);
Address plt_addr = pltoff + plt->address();
- Address from = this->stub_address() + (p - oview);
- Address delta = plt_addr - from;
- p = build_power10_offset<big_endian>(p, delta, from & 4, true);
- write_insn<big_endian>(p, mtctr_12);
- p += 4;
- if (!this->build_tls_opt_tail(p, cs))
- write_insn<big_endian>(p, bctr);
+ if (this->targ_->power10_stubs_auto())
+ {
+ if (cs->second.notoc_)
+ {
+ if (this->targ_->is_tls_get_addr_opt(cs->first.sym_))
+ this->build_tls_opt_head(&p, false);
+ Address from = this->stub_address() + (p - oview);
+ Address delta = plt_addr - from;
+ p = build_power10_offset<big_endian>(p, delta, from & 4,
+ true);
+ write_insn<big_endian>(p, mtctr_12);
+ p += 4;
+ write_insn<big_endian>(p, bctr);
+ p += 4;
+ p = oview + this->plt_call_align(p - oview);
+ }
+ if (cs->second.toc_)
+ {
+ if (this->targ_->is_tls_get_addr_opt(cs->first.sym_))
+ {
+ bool save_lr
+ = cs->second.r2save_ && !cs->second.localentry0_;
+ this->build_tls_opt_head(&p, save_lr);
+ }
+ const Powerpc_relobj<size, big_endian>* ppcobj
+ = static_cast<const Powerpc_relobj<size, big_endian>*>(
+ cs->first.object_);
+ Address got_addr = got_os_addr + ppcobj->toc_base_offset();
+ Address off = plt_addr - got_addr;
+
+ if (off + 0x80008000 > 0xffffffff || (off & 7) != 0)
+ this->plt_error(cs->first);
+
+ if (cs->second.r2save_)
+ {
+ write_insn<big_endian>(p, std_2_1 + this->targ_->stk_toc());
+ p += 4;
+ }
+ if (ha(off) != 0)
+ {
+ write_insn<big_endian>(p, addis_12_2 + ha(off));
+ p += 4;
+ write_insn<big_endian>(p, ld_12_12 + l(off));
+ p += 4;
+ }
+ else
+ {
+ write_insn<big_endian>(p, ld_12_2 + l(off));
+ p += 4;
+ }
+ write_insn<big_endian>(p, mtctr_12);
+ p += 4;
+ if (cs->second.r2save_
+ && !cs->second.localentry0_
+ && this->targ_->is_tls_get_addr_opt(cs->first.sym_))
+ this->build_tls_opt_tail(p);
+ else
+ write_insn<big_endian>(p, bctr);
+ }
+ }
+ else
+ {
+ if (this->targ_->is_tls_get_addr_opt(cs->first.sym_))
+ {
+ bool save_lr
+ = cs->second.r2save_ && !cs->second.localentry0_;
+ this->build_tls_opt_head(&p, save_lr);
+ }
+ if (cs->second.r2save_)
+ {
+ write_insn<big_endian>(p, std_2_1 + this->targ_->stk_toc());
+ p += 4;
+ }
+ Address from = this->stub_address() + (p - oview);
+ Address delta = plt_addr - from;
+ p = build_power10_offset<big_endian>(p, delta, from & 4, true);
+ write_insn<big_endian>(p, mtctr_12);
+ p += 4;
+ if (cs->second.r2save_
+ && !cs->second.localentry0_
+ && this->targ_->is_tls_get_addr_opt(cs->first.sym_))
+ this->build_tls_opt_tail(p);
+ else
+ write_insn<big_endian>(p, bctr);
+ }
}
}
@@ -6168,19 +6342,76 @@ Stub_table<size, big_endian>::do_write(O
p = oview + off;
Address loc = this->stub_address() + off;
Address delta = bs->first.dest_ - loc;
- if (bs->second.notoc_ || delta + (1 << 25) >= 2 << 25)
+ if (this->targ_->power10_stubs_auto())
{
- unsigned char* startp = p;
- p = build_power10_offset<big_endian>(p, delta, loc & 4, false);
- delta -= p - startp;
+ if (bs->second.notoc_)
+ {
+ unsigned char* startp = p;
+ p = build_power10_offset<big_endian>(p, delta,
+ loc & 4, false);
+ delta -= p - startp;
+ startp = p;
+ if (delta + (1 << 25) < 2 << 25)
+ write_insn<big_endian>(p, b | (delta & 0x3fffffc));
+ else
+ {
+ write_insn<big_endian>(p, mtctr_12);
+ p += 4;
+ write_insn<big_endian>(p, bctr);
+ }
+ p += 4;
+ delta -= p - startp;
+ }
+ if (bs->second.toc_)
+ {
+ if (delta + (1 << 25) >= 2 << 25)
+ {
+ Address brlt_addr
+ = this->targ_->find_branch_lookup_table(bs->first.dest_);
+ gold_assert(brlt_addr != invalid_address);
+ brlt_addr += this->targ_->brlt_section()->address();
+ Address got_addr = got_os_addr + bs->first.toc_base_off_;
+ Address brltoff = brlt_addr - got_addr;
+ if (ha(brltoff) == 0)
+ {
+ write_insn<big_endian>(p, ld_12_2 + l(brltoff));
+ p += 4;
+ }
+ else
+ {
+ write_insn<big_endian>(p, addis_12_2 + ha(brltoff));
+ p += 4;
+ write_insn<big_endian>(p, ld_12_12 + l(brltoff));
+ p += 4;
+ }
+ }
+ if (delta + (1 << 25) < 2 << 25)
+ write_insn<big_endian>(p, b | (delta & 0x3fffffc));
+ else
+ {
+ write_insn<big_endian>(p, mtctr_12);
+ p += 4;
+ write_insn<big_endian>(p, bctr);
+ }
+ }
}
- if (delta + (1 << 25) < 2 << 25)
- write_insn<big_endian>(p, b | (delta & 0x3fffffc));
else
{
- write_insn<big_endian>(p, mtctr_12);
- p += 4;
- write_insn<big_endian>(p, bctr);
+ if (bs->second.notoc_ || delta + (1 << 25) >= 2 << 25)
+ {
+ unsigned char* startp = p;
+ p = build_power10_offset<big_endian>(p, delta,
+ loc & 4, false);
+ delta -= p - startp;
+ }
+ if (delta + (1 << 25) < 2 << 25)
+ write_insn<big_endian>(p, b | (delta & 0x3fffffc));
+ else
+ {
+ write_insn<big_endian>(p, mtctr_12);
+ p += 4;
+ write_insn<big_endian>(p, bctr);
+ }
}
}
}
@@ -6204,7 +6435,11 @@ Stub_table<size, big_endian>::do_write(O
Address plt_addr = pltoff + plt->address();
p = oview + cs->second.off_;
- this->build_tls_opt_head(&p, cs);
+ if (this->targ_->is_tls_get_addr_opt(cs->first.sym_))
+ {
+ bool save_lr = cs->second.r2save_ && !cs->second.localentry0_;
+ this->build_tls_opt_head(&p, save_lr);
+ }
if (cs->second.r2save_)
{
write_insn<big_endian>(p, std_2_1 + this->targ_->stk_toc());
@@ -6241,7 +6476,11 @@ Stub_table<size, big_endian>::do_write(O
}
write_insn<big_endian>(p, mtctr_12);
p += 4;
- if (!this->build_tls_opt_tail(p, cs))
+ if (cs->second.r2save_
+ && !cs->second.localentry0_
+ && this->targ_->is_tls_get_addr_opt(cs->first.sym_))
+ this->build_tls_opt_tail(p);
+ else
write_insn<big_endian>(p, bctr);
}
}
@@ -6292,8 +6531,12 @@ Stub_table<size, big_endian>::do_write(O
}
p = oview + cs->second.off_;
- if (this->build_tls_opt_head(&p, cs))
- use_fake_dep = thread_safe;
+ if (this->targ_->is_tls_get_addr_opt(cs->first.sym_))
+ {
+ bool save_lr = cs->second.r2save_ && !cs->second.localentry0_;
+ this->build_tls_opt_head(&p, save_lr);
+ use_fake_dep = thread_safe;
+ }
if (cs->second.r2save_)
{
write_insn<big_endian>(p, std_2_1 + this->targ_->stk_toc());
@@ -6355,8 +6598,10 @@ Stub_table<size, big_endian>::do_write(O
write_insn<big_endian>(p, ld_2_2 + l(off + 8));
p += 4;
}
- if (this->build_tls_opt_tail(p, cs))
- ;
+ if (cs->second.r2save_
+ && !cs->second.localentry0_
+ && this->targ_->is_tls_get_addr_opt(cs->first.sym_))
+ this->build_tls_opt_tail(p);
else if (thread_safe && !use_fake_dep)
{
write_insn<big_endian>(p, cmpldi_2_0);
@@ -6437,7 +6682,8 @@ Stub_table<size, big_endian>::do_write(O
plt_addr += plt->address();
p = oview + cs->second.off_;
- this->build_tls_opt_head(&p, cs);
+ if (this->targ_->is_tls_get_addr_opt(cs->first.sym_))
+ this->build_tls_opt_head(&p, false);
if (parameters->options().output_is_position_independent())
{
Address got_addr;
@@ -6577,15 +6823,25 @@ Output_data_glink<size, big_endian>::do_
}
else
{
+ if (this->targ_->has_localentry0())
+ {
+ write_insn<big_endian>(p, std_2_1 + 24), p += 4;
+ }
write_insn<big_endian>(p, mflr_0), p += 4;
write_insn<big_endian>(p, bcl_20_31), p += 4;
write_insn<big_endian>(p, mflr_11), p += 4;
- write_insn<big_endian>(p, std_2_1 + 24), p += 4;
- write_insn<big_endian>(p, ld_2_11 + l(-16)), p += 4;
write_insn<big_endian>(p, mtlr_0), p += 4;
+ if (this->targ_->has_localentry0())
+ {
+ write_insn<big_endian>(p, ld_0_11 + l(-20)), p += 4;
+ }
+ else
+ {
+ write_insn<big_endian>(p, ld_0_11 + l(-16)), p += 4;
+ }
write_insn<big_endian>(p, sub_12_12_11), p += 4;
- write_insn<big_endian>(p, add_11_2_11), p += 4;
- write_insn<big_endian>(p, addi_0_12 + l(-48)), p += 4;
+ write_insn<big_endian>(p, add_11_0_11), p += 4;
+ write_insn<big_endian>(p, addi_0_12 + l(-44)), p += 4;
write_insn<big_endian>(p, ld_12_11 + 0), p += 4;
write_insn<big_endian>(p, srdi_0_0_2), p += 4;
write_insn<big_endian>(p, mtctr_12), p += 4;
@@ -8230,7 +8486,7 @@ Target_powerpc<size, big_endian>::Scan::
case elfcpp::R_PPC64_GOT_TLSLD_PCREL34:
case elfcpp::R_PPC64_GOT_DTPREL_PCREL34:
case elfcpp::R_PPC64_GOT_TPREL_PCREL34:
- target->set_power10_stubs();
+ target->set_power10_relocs();
break;
default:
break;
@@ -9027,7 +9283,7 @@ Target_powerpc<size, big_endian>::Scan::
case elfcpp::R_PPC64_GOT_TLSLD_PCREL34:
case elfcpp::R_PPC64_GOT_DTPREL_PCREL34:
case elfcpp::R_PPC64_GOT_TPREL_PCREL34:
- target->set_power10_stubs();
+ target->set_power10_relocs();
break;
default:
break;
@@ -9369,6 +9625,13 @@ Target_powerpc<size, big_endian>::scan_r
needs_special_offset_handling,
local_symbol_count,
plocal_symbols);
+
+ if (this->plt_localentry0_ && this->power10_relocs_)
+ {
+ gold_warning(_("--plt-localentry is incompatible with "
+ "power10 pc-relative code"));
+ this->plt_localentry0_ = false;
+ }
}
// Functor class for processing the global symbol table.
@@ -10176,18 +10439,28 @@ Target_powerpc<size, big_endian>::Reloca
elfcpp::Shdr<size, big_endian> shdr(relinfo->reloc_shdr);
size_t reloc_count = shdr.get_sh_size() / reloc_size;
if (size == 64
+ && r_type != elfcpp::R_PPC64_REL24_NOTOC)
+ value += ent->tocoff_;
+ if (size == 64
&& ent->r2save_
- && r_type == elfcpp::R_PPC64_REL24_NOTOC)
- value += 4;
- else if (size == 64
- && ent->r2save_
- && relnum < reloc_count - 1)
+ && !(gsym != NULL
+ && target->is_tls_get_addr_opt(gsym)))
{
- Reltype next_rela(preloc + reloc_size);
- if (elfcpp::elf_r_type<size>(next_rela.get_r_info())
- == elfcpp::R_PPC64_TOCSAVE
- && next_rela.get_r_offset() == rela.get_r_offset() + 4)
- value += 4;
+ if (r_type == elfcpp::R_PPC64_REL24_NOTOC)
+ {
+ if (!(target->power10_stubs()
+ && target->power10_stubs_auto()))
+ value += 4;
+ }
+ else if (relnum < reloc_count - 1)
+ {
+ Reltype next_rela(preloc + reloc_size);
+ if (elfcpp::elf_r_type<size>(next_rela.get_r_info())
+ == elfcpp::R_PPC64_TOCSAVE
+ && (next_rela.get_r_offset()
+ == rela.get_r_offset() + 4))
+ value += 4;
+ }
}
localentry0 = ent->localentry0_;
has_stub_value = true;
@@ -10795,8 +11068,14 @@ Target_powerpc<size, big_endian>::Reloca
value = (value - target->savres_section()->address()
+ stub_table->branch_size());
else
- value = (stub_table->stub_address() + stub_table->plt_size()
- + ent->off_);
+ {
+ value = (stub_table->stub_address()
+ + stub_table->plt_size()
+ + ent->off_);
+ if (size == 64
+ && r_type != elfcpp::R_PPC64_REL24_NOTOC)
+ value += ent->tocoff_;
+ }
has_stub_value = true;
}
}
diff -rup binutils.orig/ld/emultempl/ppc64elf.em binutils-2.35.1/ld/emultempl/ppc64elf.em
--- binutils.orig/ld/emultempl/ppc64elf.em 2020-10-08 13:50:30.728911588 +0100
+++ binutils-2.35.1/ld/emultempl/ppc64elf.em 2020-10-08 13:55:41.516954722 +0100
@@ -32,13 +32,15 @@ fragment <<EOF
static asection *ppc_add_stub_section (const char *, asection *);
static void ppc_layout_sections_again (void);
+static void ppc_edit (void);
static struct ppc64_elf_params params = { NULL,
&ppc_add_stub_section,
&ppc_layout_sections_again,
+ &ppc_edit,
1, -1, -1, 0,
${DEFAULT_PLT_STATIC_CHAIN-0}, -1, 5,
- -1, -1, 0, -1, -1, 0};
+ -1, -1, 0, 0, -1, -1, 0};
/* Fake input file for stubs. */
static lang_input_statement_type *stub_file;
@@ -294,7 +296,19 @@ ppc_before_allocation (void)
einfo (_("%X%P: inline PLT: %E\n"));
}
- if (ppc64_elf_tls_setup (&link_info)
+ if (!ppc64_elf_tls_setup (&link_info))
+ einfo (_("%X%P: TLS problem %E\n"));
+ }
+
+ gld${EMULATION_NAME}_before_allocation ();
+}
+
+static void
+ppc_edit (void)
+{
+ if (stub_file != NULL)
+ {
+ if (elf_hash_table (&link_info)->tls_sec != NULL
&& !no_tls_opt)
{
/* Size the sections. This is premature, but we want to know the
@@ -323,8 +337,6 @@ ppc_before_allocation (void)
sort_toc_sections (&toc_os->children, NULL, NULL);
}
}
-
- gld${EMULATION_NAME}_before_allocation ();
}
struct hook_stub_info
@@ -686,6 +698,7 @@ enum ppc64_opt
OPTION_NO_PLT_LOCALENTRY,
OPTION_POWER10_STUBS,
OPTION_NO_POWER10_STUBS,
+ OPTION_NO_PCREL_OPT,
OPTION_STUBSYMS,
OPTION_NO_STUBSYMS,
OPTION_SAVRES,
@@ -717,6 +730,7 @@ PARSE_AND_LIST_LONGOPTS=${PARSE_AND_LIST
{ "plt-localentry", optional_argument, NULL, OPTION_PLT_LOCALENTRY },
{ "no-plt-localentry", no_argument, NULL, OPTION_NO_PLT_LOCALENTRY },
{ "power10-stubs", optional_argument, NULL, OPTION_POWER10_STUBS },
+ { "no-pcrel-optimize", no_argument, NULL, OPTION_NO_PCREL_OPT },
{ "no-power10-stubs", no_argument, NULL, OPTION_NO_POWER10_STUBS },
{ "emit-stub-syms", no_argument, NULL, OPTION_STUBSYMS },
{ "no-emit-stub-syms", no_argument, NULL, OPTION_NO_STUBSYMS },
@@ -776,6 +790,9 @@ PARSE_AND_LIST_OPTIONS=${PARSE_AND_LIST_
--power10-stubs [=auto] Use Power10 PLT call stubs (default auto)\n"
));
fprintf (file, _("\
+ --no-pcrel-optimize Don'\''t perform R_PPC64_PCREL_OPT optimization\n"
+ ));
+ fprintf (file, _("\
--no-power10-stubs Don'\''t use Power10 PLT call stubs\n"
));
fprintf (file, _("\
@@ -909,6 +926,10 @@ PARSE_AND_LIST_ARGS_CASES=${PARSE_AND_LI
params.power10_stubs = 0;
break;
+ case OPTION_NO_PCREL_OPT:
+ params.no_pcrel_opt = 1;
+ break;
+
case OPTION_STUBSYMS:
params.emit_stub_syms = 1;
break;
@@ -985,6 +1006,7 @@ PARSE_AND_LIST_ARGS_CASES=${PARSE_AND_LI
params.no_multi_toc = 1;
no_toc_sort = 1;
params.plt_static_chain = 1;
+ params.no_pcrel_opt = 1;
return FALSE;
'
diff -rup binutils.orig/ld/testsuite/ld-powerpc/elfv2so.d binutils-2.35.1/ld/testsuite/ld-powerpc/elfv2so.d
--- binutils.orig/ld/testsuite/ld-powerpc/elfv2so.d 2020-10-08 13:50:30.844911231 +0100
+++ binutils-2.35.1/ld/testsuite/ld-powerpc/elfv2so.d 2020-10-08 13:51:12.622782597 +0100
@@ -74,12 +74,11 @@ Disassembly of section \.text:
.*: (7c 08 02 a6|a6 02 08 7c) mflr r0
.*: (42 9f 00 05|05 00 9f 42) bcl .*
.*: (7d 68 02 a6|a6 02 68 7d) mflr r11
-.*: (18 00 41 f8|f8 41 00 18) std r2,24\(r1\)
-.*: (e8 4b ff f0|f0 ff 4b e8) ld r2,-16\(r11\)
.*: (7c 08 03 a6|a6 03 08 7c) mtlr r0
+.*: (e8 0b ff f0|f0 ff 0b e8) ld r0,-16\(r11\)
.*: (7d 8b 60 50|50 60 8b 7d) subf r12,r11,r12
-.*: (7d 62 5a 14|14 5a 62 7d) add r11,r2,r11
-.*: (38 0c ff d0|d0 ff 0c 38) addi r0,r12,-48
+.*: (7d 60 5a 14|14 5a 60 7d) add r11,r0,r11
+.*: (38 0c ff d4|d4 ff 0c 38) addi r0,r12,-44
.*: (e9 8b 00 00|00 00 8b e9) ld r12,0\(r11\)
.*: (78 00 f0 82|82 f0 00 78) rldicl r0,r0,62,2
.*: (7d 89 03 a6|a6 03 89 7d) mtctr r12
@@ -87,16 +86,16 @@ Disassembly of section \.text:
.*: (4e 80 04 20|20 04 80 4e) bctr
.* <f5@plt>:
-.*: (4b ff ff c8|c8 ff ff 4b) b .* <__glink_PLTresolve>
+.*: (4b ff ff cc|cc ff ff 4b) b .* <__glink_PLTresolve>
.* <f3@plt>:
-.*: (4b ff ff c4|c4 ff ff 4b) b .* <__glink_PLTresolve>
+.*: (4b ff ff c8|c8 ff ff 4b) b .* <__glink_PLTresolve>
.* <f2@plt>:
-.*: (4b ff ff c0|c0 ff ff 4b) b .* <__glink_PLTresolve>
+.*: (4b ff ff c4|c4 ff ff 4b) b .* <__glink_PLTresolve>
.* <f4@plt>:
-.*: (4b ff ff bc|bc ff ff 4b) b .* <__glink_PLTresolve>
+.*: (4b ff ff c0|c0 ff ff 4b) b .* <__glink_PLTresolve>
.* <f1@plt>:
-.*: (4b ff ff b8|b8 ff ff 4b) b .* <__glink_PLTresolve>
+.*: (4b ff ff bc|bc ff ff 4b) b .* <__glink_PLTresolve>
diff -rup binutils.orig/ld/testsuite/ld-powerpc/notoc2.d binutils-2.35.1/ld/testsuite/ld-powerpc/notoc2.d
--- binutils.orig/ld/testsuite/ld-powerpc/notoc2.d 2020-10-08 13:50:30.846911225 +0100
+++ binutils-2.35.1/ld/testsuite/ld-powerpc/notoc2.d 2020-10-08 13:51:12.622782597 +0100
@@ -22,8 +22,8 @@ Disassembly of section \.text:
.*: (39 80 ff ff|ff ff 80 39)
.*: (06 10 00 00|00 00 10 06) pla r12,0
.*: (39 80 00 00|00 00 80 39)
-.*: (06 10 00 00|00 00 10 06) pla r3,92
-.*: (38 60 00 5c|5c 00 60 38)
+.*: (06 10 00 00|00 00 10 06) pla r3,88
+.*: (38 60 00 58|58 00 60 38)
.*: (4b ff ff 99|99 ff ff 4b) bl .* <.*\.plt_call\.puts>
.*: (60 00 00 00|00 00 00 60) nop
#pass
diff -rup binutils.orig/ld/testsuite/ld-powerpc/tlsdesc.wf binutils-2.35.1/ld/testsuite/ld-powerpc/tlsdesc.wf
--- binutils.orig/ld/testsuite/ld-powerpc/tlsdesc.wf 2020-10-08 13:50:30.848911219 +0100
+++ binutils-2.35.1/ld/testsuite/ld-powerpc/tlsdesc.wf 2020-10-08 13:51:12.622782597 +0100
@@ -38,9 +38,9 @@ Contents of the \.eh_frame section:
DW_CFA_nop
0+4c 0+14 0+50 FDE cie=0+ pc=0+2f8\.\.0+32c
- DW_CFA_advance_loc: 4 to 0+2fc
+ DW_CFA_advance_loc: 8 to 0+300
DW_CFA_register: r65 in r12
- DW_CFA_advance_loc: 20 to 0+310
+ DW_CFA_advance_loc: 16 to 0+310
DW_CFA_restore_extended: r65
0+64 0+10 0+68 FDE cie=0+ pc=0+2e0\.\.0+2ec
diff -rup binutils.orig/ld/testsuite/ld-powerpc/tlsdesc2.d binutils-2.35.1/ld/testsuite/ld-powerpc/tlsdesc2.d
--- binutils.orig/ld/testsuite/ld-powerpc/tlsdesc2.d 2020-10-08 13:50:30.846911225 +0100
+++ binutils-2.35.1/ld/testsuite/ld-powerpc/tlsdesc2.d 2020-10-08 13:51:12.622782597 +0100
@@ -53,12 +53,11 @@ Disassembly of section \.text:
.*: (7c 08 02 a6|a6 02 08 7c) mflr r0
.*: (42 9f 00 05|05 00 9f 42) bcl .*
.*: (7d 68 02 a6|a6 02 68 7d) mflr r11
-.*: (f8 41 00 18|18 00 41 f8) std r2,24\(r1\)
-.*: (e8 4b ff f0|f0 ff 4b e8) ld r2,-16\(r11\)
.*: (7c 08 03 a6|a6 03 08 7c) mtlr r0
+.*: (e8 0b ff f0|f0 ff 0b e8) ld r0,-16\(r11\)
.*: (7d 8b 60 50|50 60 8b 7d) subf r12,r11,r12
-.*: (7d 62 5a 14|14 5a 62 7d) add r11,r2,r11
-.*: (38 0c ff d0|d0 ff 0c 38) addi r0,r12,-48
+.*: (7d 60 5a 14|14 5a 60 7d) add r11,r0,r11
+.*: (38 0c ff d4|d4 ff 0c 38) addi r0,r12,-44
.*: (e9 8b 00 00|00 00 8b e9) ld r12,0\(r11\)
.*: (78 00 f0 82|82 f0 00 78) rldicl r0,r0,62,2
.*: (7d 89 03 a6|a6 03 89 7d) mtctr r12
@@ -66,4 +65,4 @@ Disassembly of section \.text:
.*: (4e 80 04 20|20 04 80 4e) bctr
.* <__tls_get_addr_opt@plt>:
-.*: (4b ff ff c8|c8 ff ff 4b) b .* <__glink_PLTresolve>
+.*: (4b ff ff cc|cc ff ff 4b) b .* <__glink_PLTresolve>
diff -rup binutils.orig/ld/testsuite/ld-powerpc/tlsdesc2.wf binutils-2.35.1/ld/testsuite/ld-powerpc/tlsdesc2.wf
--- binutils.orig/ld/testsuite/ld-powerpc/tlsdesc2.wf 2020-10-08 13:50:30.850911213 +0100
+++ binutils-2.35.1/ld/testsuite/ld-powerpc/tlsdesc2.wf 2020-10-08 13:51:12.622782597 +0100
@@ -37,10 +37,10 @@ Contents of the \.eh_frame section:
DW_CFA_nop
DW_CFA_nop
-0+4c 0+14 0+50 FDE cie=0+ pc=0+318\.\.0+354
- DW_CFA_advance_loc: 4 to 0+31c
+0+4c 0+14 0+50 FDE cie=0+ pc=0+318\.\.0+350
+ DW_CFA_advance_loc: 8 to 0+320
DW_CFA_register: r65 in r0
- DW_CFA_advance_loc: 28 to 0+338
+ DW_CFA_advance_loc: 8 to 0+328
DW_CFA_restore_extended: r65
0+64 0+10 0+68 FDE cie=0+ pc=0+300\.\.0+30c
diff -rup binutils.orig/ld/testsuite/ld-powerpc/tlsopt5.d binutils-2.35.1/ld/testsuite/ld-powerpc/tlsopt5.d
--- binutils.orig/ld/testsuite/ld-powerpc/tlsopt5.d 2020-10-08 13:50:30.843911234 +0100
+++ binutils-2.35.1/ld/testsuite/ld-powerpc/tlsopt5.d 2020-10-08 13:51:12.623782594 +0100
@@ -49,12 +49,11 @@ Disassembly of section \.text:
.*: (a6 02 08 7c|7c 08 02 a6) mflr r0
.*: (05 00 9f 42|42 9f 00 05) bcl .*
.*: (a6 02 68 7d|7d 68 02 a6) mflr r11
-.*: (18 00 41 f8|f8 41 00 18) std r2,24\(r1\)
-.*: (f0 ff 4b e8|e8 4b ff f0) ld r2,-16\(r11\)
.*: (a6 03 08 7c|7c 08 03 a6) mtlr r0
+.*: (f0 ff 0b e8|e8 0b ff f0) ld r0,-16\(r11\)
.*: (50 60 8b 7d|7d 8b 60 50) subf r12,r11,r12
-.*: (14 5a 62 7d|7d 62 5a 14) add r11,r2,r11
-.*: (d0 ff 0c 38|38 0c ff d0) addi r0,r12,-48
+.*: (14 5a 60 7d|7d 60 5a 14) add r11,r0,r11
+.*: (d4 ff 0c 38|38 0c ff d4) addi r0,r12,-44
.*: (00 00 8b e9|e9 8b 00 00) ld r12,0\(r11\)
.*: (82 f0 00 78|78 00 f0 82) rldicl r0,r0,62,2
.*: (a6 03 89 7d|7d 89 03 a6) mtctr r12
@@ -62,7 +61,7 @@ Disassembly of section \.text:
.*: (20 04 80 4e|4e 80 04 20) bctr
.* <__tls_get_addr_opt@plt>:
-.* (c8 ff ff 4b|4b ff ff c8) b .*
+.* (cc ff ff 4b|4b ff ff cc) b .*
.* <aaaaa@plt>:
-.*: (c4 ff ff 4b|4b ff ff c4) b .*
+.*: (c8 ff ff 4b|4b ff ff c8) b .*
diff -rup binutils.orig/ld/testsuite/ld-powerpc/tlsopt5.wf binutils-2.35.1/ld/testsuite/ld-powerpc/tlsopt5.wf
--- binutils.orig/ld/testsuite/ld-powerpc/tlsopt5.wf 2020-10-08 13:50:30.844911231 +0100
+++ binutils-2.35.1/ld/testsuite/ld-powerpc/tlsopt5.wf 2020-10-08 13:51:12.623782594 +0100
@@ -16,9 +16,9 @@ Contents of the \.eh_frame section:
DW_CFA_restore_extended: r65
0+2c 0+14 0+30 FDE cie=0+ pc=.*
- DW_CFA_advance_loc: 4 to .*
+ DW_CFA_advance_loc: 8 to .*
DW_CFA_register: r65 in r0
- DW_CFA_advance_loc: 28 to .*
+ DW_CFA_advance_loc: 8 to .*
DW_CFA_restore_extended: r65
0+44 0+10 0+48 FDE cie=0+ pc=.*
diff -rup binutils.orig/ld/testsuite/ld-powerpc/tlsopt6.d binutils-2.35.1/ld/testsuite/ld-powerpc/tlsopt6.d
--- binutils.orig/ld/testsuite/ld-powerpc/tlsopt6.d 2020-10-08 13:50:30.848911219 +0100
+++ binutils-2.35.1/ld/testsuite/ld-powerpc/tlsopt6.d 2020-10-08 13:51:12.623782594 +0100
@@ -67,12 +67,11 @@ Disassembly of section \.text:
.*: (a6 02 08 7c|7c 08 02 a6) mflr r0
.*: (05 00 9f 42|42 9f 00 05) bcl .*
.*: (a6 02 68 7d|7d 68 02 a6) mflr r11
-.*: (18 00 41 f8|f8 41 00 18) std r2,24\(r1\)
-.*: (f0 ff 4b e8|e8 4b ff f0) ld r2,-16\(r11\)
.*: (a6 03 08 7c|7c 08 03 a6) mtlr r0
+.*: (f0 ff 0b e8|e8 0b ff f0) ld r0,-16\(r11\)
.*: (50 60 8b 7d|7d 8b 60 50) subf r12,r11,r12
-.*: (14 5a 62 7d|7d 62 5a 14) add r11,r2,r11
-.*: (d0 ff 0c 38|38 0c ff d0) addi r0,r12,-48
+.*: (14 5a 60 7d|7d 60 5a 14) add r11,r0,r11
+.*: (d4 ff 0c 38|38 0c ff d4) addi r0,r12,-44
.*: (00 00 8b e9|e9 8b 00 00) ld r12,0\(r11\)
.*: (82 f0 00 78|78 00 f0 82) rldicl r0,r0,62,2
.*: (a6 03 89 7d|7d 89 03 a6) mtctr r12
@@ -80,7 +79,7 @@ Disassembly of section \.text:
.*: (20 04 80 4e|4e 80 04 20) bctr
.* <__tls_get_addr_opt@plt>:
-.* (c8 ff ff 4b|4b ff ff c8) b .*
+.* (cc ff ff 4b|4b ff ff cc) b .*
.* <aaaaa@plt>:
-.*: (c4 ff ff 4b|4b ff ff c4) b .*
+.*: (c8 ff ff 4b|4b ff ff c8) b .*
diff -rup binutils.orig/ld/testsuite/ld-powerpc/tlsopt6.wf binutils-2.35.1/ld/testsuite/ld-powerpc/tlsopt6.wf
--- binutils.orig/ld/testsuite/ld-powerpc/tlsopt6.wf 2020-10-08 13:50:30.845911228 +0100
+++ binutils-2.35.1/ld/testsuite/ld-powerpc/tlsopt6.wf 2020-10-08 13:51:12.623782594 +0100
@@ -38,9 +38,9 @@ Contents of the \.eh_frame section:
DW_CFA_nop
0+4c 0+14 0+50 FDE cie=0+ pc=.*
- DW_CFA_advance_loc: 4 to .*
+ DW_CFA_advance_loc: 8 to .*
DW_CFA_register: r65 in r0
- DW_CFA_advance_loc: 28 to .*
+ DW_CFA_advance_loc: 8 to .*
DW_CFA_restore_extended: r65
0+64 0+10 0+68 FDE cie=0+ pc=.*
diff -rup binutils.orig/opcodes/ppc-opc.c binutils-2.35.1/opcodes/ppc-opc.c
--- binutils.orig/opcodes/ppc-opc.c 2020-10-08 13:50:31.025910674 +0100
+++ binutils-2.35.1/opcodes/ppc-opc.c 2020-10-08 13:56:36.923784122 +0100
@@ -4441,7 +4441,7 @@ const struct powerpc_opcode powerpc_opco
{"nmachhws", XO (4, 110,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
{"nmachhws.", XO (4, 110,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
{"vadduqm", VX (4, 256), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
-{"vcmpuq", VX (4, 257), VXBF_MASK, POWER10, 0, {OBF, VA, VB}},
+{"vcmpuq", VX (4, 257), VXBF_MASK, POWER10, 0, {BF, VA, VB}},
{"vmaxsb", VX (4, 258), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
{"vslb", VX (4, 260), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
{"vslq", VX (4, 261), VX_MASK, POWER10, 0, {VD, VA, VB}},
@@ -4459,7 +4459,7 @@ const struct powerpc_opcode powerpc_opco
{"macchwu", XO (4, 140,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
{"macchwu.", XO (4, 140,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
{"vaddcuq", VX (4, 320), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
-{"vcmpsq", VX (4, 321), VXBF_MASK, POWER10, 0, {OBF, VA, VB}},
+{"vcmpsq", VX (4, 321), VXBF_MASK, POWER10, 0, {BF, VA, VB}},
{"vmaxsh", VX (4, 322), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
{"vslh", VX (4, 324), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
{"vrlqnm", VX (4, 325), VX_MASK, POWER10, 0, {VD, VA, VB}},
@@ -6114,6 +6114,7 @@ const struct powerpc_opcode powerpc_opco
{"rlnm.", M(23,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
{"nop", OP(24), 0xffffffff, PPCCOM, PPCVLE, {0}},
+{"exser", 0x63ff0000, 0xffffffff, POWER9, PPCVLE, {0}},
{"ori", OP(24), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
{"oril", OP(24), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
@@ -6236,7 +6237,7 @@ const struct powerpc_opcode powerpc_opco
{"ldx", X(31,21), X_MASK, PPC64, 0, {RT, RA0, RB}},
-{"icbt", X(31,22), X_MASK, BOOKE|PPCE300|PPCA2|PPC476, 0, {CT, RA0, RB}},
+{"icbt", X(31,22), X_MASK, POWER5|BOOKE|PPCE300, 0, {CT, RA0, RB}},
{"lwzx", X(31,23), X_MASK, PPCCOM, 0, {RT, RA0, RB}},
{"lx", X(31,23), X_MASK, PWRCOM, 0, {RT, RA, RB}},
@@ -6302,9 +6303,9 @@ const struct powerpc_opcode powerpc_opco
{"subf.", XO(31,40,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
{"sub.", XO(31,40,0,1), XO_MASK, PPC, 0, {RT, RB, RA}},
-{"mfvsrd", X(31,51), XX1RB_MASK, PPCVSX2, 0, {RA, XS6}},
{"mffprd", X(31,51), XX1RB_MASK|1, PPCVSX2, 0, {RA, FRS}},
{"mfvrd", X(31,51)|1, XX1RB_MASK|1, PPCVSX2, 0, {RA, VS}},
+{"mfvsrd", X(31,51), XX1RB_MASK, PPCVSX2, 0, {RA, XS6}},
{"eratilx", X(31,51), X_MASK, PPCA2, 0, {ERAT_T, RA, RB}},
{"lbarx", X(31,52), XEH_MASK, POWER8|E6500, 0, {RT, RA0, RB, EH}},
@@ -6354,6 +6355,7 @@ const struct powerpc_opcode powerpc_opco
{"mulhw", XO(31,75,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
{"mulhw.", XO(31,75,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
+{"msgsndu", XRTRA(31,78,0,0), XRTRA_MASK, POWER9, 0, {RB}},
{"dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440|PPC476|TITAN, 0, {RA, RS, RB}},
{"dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440|PPC476|TITAN, 0, {RA, RS, RB}},
@@ -6387,6 +6389,7 @@ const struct powerpc_opcode powerpc_opco
{"lxvrdx", X(31,109), XX1_MASK, POWER10, 0, {XT6, RA0, RB}},
+{"msgclru", XRTRA(31,110,0,0), XRTRA_MASK, POWER9, 0, {RB}},
{"mvidsplt", X(31,110), X_MASK, E6500, 0, {VD, RA, RB}},
{"mtsrdin", X(31,114), XRA_MASK, PPC64, 0, {RS, RB}},
@@ -6489,9 +6492,9 @@ const struct powerpc_opcode powerpc_opco
{"mtmsrd", X(31,178), XRLARB_MASK, PPC64, 0, {RS, A_L}},
-{"mtvsrd", X(31,179), XX1RB_MASK, PPCVSX2, 0, {XT6, RA}},
{"mtfprd", X(31,179), XX1RB_MASK|1, PPCVSX2, 0, {FRT, RA}},
{"mtvrd", X(31,179)|1, XX1RB_MASK|1, PPCVSX2, 0, {VD, RA}},
+{"mtvsrd", X(31,179), XX1RB_MASK, PPCVSX2, 0, {XT6, RA}},
{"eratre", X(31,179), X_MASK, PPCA2, 0, {RT, RA, WS}},
{"stdux", X(31,181), X_MASK, PPC64, 0, {RS, RAS, RB}},
@@ -6738,11 +6741,13 @@ const struct powerpc_opcode powerpc_opco
{"mfmq", XSPR(31,339, 0), XSPR_MASK, M601, 0, {RT}},
{"mfxer", XSPR(31,339, 1), XSPR_MASK, COM, 0, {RT}},
+{"mfudscr", XSPR(31,339, 3), XSPR_MASK, POWER9, 0, {RS}},
{"mfrtcu", XSPR(31,339, 4), XSPR_MASK, COM, TITAN, {RT}},
{"mfrtcl", XSPR(31,339, 5), XSPR_MASK, COM, TITAN, {RT}},
{"mfdec", XSPR(31,339, 6), XSPR_MASK, MFDEC1, 0, {RT}},
{"mflr", XSPR(31,339, 8), XSPR_MASK, COM, 0, {RT}},
{"mfctr", XSPR(31,339, 9), XSPR_MASK, COM, 0, {RT}},
+{"mfuamr", XSPR(31,339, 13), XSPR_MASK, POWER9, 0, {RS}},
{"mfdscr", XSPR(31,339, 17), XSPR_MASK, POWER6, 0, {RT}},
{"mftid", XSPR(31,339, 17), XSPR_MASK, POWER, 0, {RT}},
{"mfdsisr", XSPR(31,339, 18), XSPR_MASK, COM, TITAN, {RT}},
@@ -6753,9 +6758,12 @@ const struct powerpc_opcode powerpc_opco
{"mfsrr0", XSPR(31,339, 26), XSPR_MASK, COM, 0, {RT}},
{"mfsrr1", XSPR(31,339, 27), XSPR_MASK, COM, 0, {RT}},
{"mfcfar", XSPR(31,339, 28), XSPR_MASK, POWER6, 0, {RT}},
+{"mfamr", XSPR(31,339, 29), XSPR_MASK, POWER7, 0, {RS}},
+{"mfpidr", XSPR(31,339, 48), XSPR_MASK, POWER10, 0, {RS}},
{"mfpid", XSPR(31,339, 48), XSPR_MASK, BOOKE, 0, {RT}},
{"mfcsrr0", XSPR(31,339, 58), XSPR_MASK, BOOKE, 0, {RT}},
{"mfcsrr1", XSPR(31,339, 59), XSPR_MASK, BOOKE, 0, {RT}},
+{"mfiamr", XSPR(31,339, 61), XSPR_MASK, POWER10, 0, {RS}},
{"mfdear", XSPR(31,339, 61), XSPR_MASK, BOOKE, 0, {RT}},
{"mfesr", XSPR(31,339, 62), XSPR_MASK, BOOKE, 0, {RT}},
{"mfivpr", XSPR(31,339, 63), XSPR_MASK, BOOKE, 0, {RT}},
@@ -6769,16 +6777,28 @@ const struct powerpc_opcode powerpc_opco
{"mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, 0, {RT}},
{"mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, 0, {RT}},
{"mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, 0, {RT}},
+{"mffscr", XSPR(31,339,153), XSPR_MASK, POWER10, 0, {RS}},
{"mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, 0, {RT}},
{"mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, 0, {RT}},
{"mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, 0, {RT}},
{"mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, 0, {RT}},
+{"mfuamor", XSPR(31,339,157), XSPR_MASK, POWER7, 0, {RS}},
{"mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, 0, {RT}},
{"mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, 0, {RT}},
+{"mfpspb", XSPR(31,339,159), XSPR_MASK, POWER10, 0, {RS}},
{"mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, 0, {RT}},
+{"mfdpdes", XSPR(31,339,176), XSPR_MASK, POWER10, 0, {RS}},
+{"mfdawr0", XSPR(31,339,180), XSPR_MASK, POWER10, 0, {RS}},
+{"mfdawr1", XSPR(31,339,181), XSPR_MASK, POWER10, 0, {RS}},
+{"mfrpr", XSPR(31,339,186), XSPR_MASK, POWER10, 0, {RS}},
+{"mfciabr", XSPR(31,339,187), XSPR_MASK, POWER10, 0, {RS}},
+{"mfdawrx0", XSPR(31,339,188), XSPR_MASK, POWER10, 0, {RS}},
+{"mfdawrx1", XSPR(31,339,189), XSPR_MASK, POWER10, 0, {RS}},
+{"mfhfscr", XSPR(31,339,190), XSPR_MASK, POWER10, 0, {RS}},
{"mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, 0, {RT}},
{"mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE, 0, {RT}},
{"mfsprg", XSPR(31,339,256), XSPRG_MASK, PPC, 0, {RT, SPRG}},
+{"mfusprg3", XSPR(31,339,259), XSPR_MASK, POWER10, 0, {RT}},
{"mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405|BOOKE, 0, {RT}},
{"mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405|BOOKE, 0, {RT}},
{"mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405|BOOKE, 0, {RT}},
@@ -6794,20 +6814,37 @@ const struct powerpc_opcode powerpc_opco
{"mfear", XSPR(31,339,282), XSPR_MASK, PPC, TITAN, {RT}},
{"mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE, 0, {RT}},
{"mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, 0, {RT}},
+{"mfhsprg0", XSPR(31,339,304), XSPR_MASK, POWER10, 0, {RS}},
{"mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE, 0, {RT}},
+{"mfhsprg1", XSPR(31,339,305), XSPR_MASK, POWER10, 0, {RS}},
+{"mfhdisr", XSPR(31,339,306), XSPR_MASK, POWER10, 0, {RS}},
+{"mfhdar", XSPR(31,339,307), XSPR_MASK, POWER10, 0, {RS}},
+{"mfspurr", XSPR(31,339,308), XSPR_MASK, POWER10, 0, {RS}},
{"mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE, 0, {RT}},
+{"mfpurr", XSPR(31,339,309), XSPR_MASK, POWER10, 0, {RS}},
{"mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE, 0, {RT}},
+{"mfhdec", XSPR(31,339,310), XSPR_MASK, POWER10, 0, {RS}},
{"mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE, 0, {RT}},
{"mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE, 0, {RT}},
+{"mfhrmor", XSPR(31,339,313), XSPR_MASK, POWER10, 0, {RS}},
{"mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE, 0, {RT}},
+{"mfhsrr0", XSPR(31,339,314), XSPR_MASK, POWER10, 0, {RS}},
{"mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE, 0, {RT}},
+{"mfhsrr1", XSPR(31,339,315), XSPR_MASK, POWER10, 0, {RS}},
{"mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE, 0, {RT}},
{"mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE, 0, {RT}},
{"mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE, 0, {RT}},
+{"mflpcr", XSPR(31,339,318), XSPR_MASK, POWER10, 0, {RS}},
{"mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE, 0, {RT}},
+{"mflpidr", XSPR(31,339,319), XSPR_MASK, POWER10, 0, {RS}},
{"mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE, 0, {RT}},
+{"mfhmer", XSPR(31,339,336), XSPR_MASK, POWER7, 0, {RS}},
{"mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE, 0, {RT}},
+{"mfhmeer", XSPR(31,339,337), XSPR_MASK, POWER7, 0, {RS}},
+{"mfpcr", XSPR(31,339,338), XSPR_MASK, POWER10, 0, {RS}},
+{"mfheir", XSPR(31,339,339), XSPR_MASK, POWER10, 0, {RS}},
{"mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE, 0, {RT}},
+{"mfamor", XSPR(31,339,349), XSPR_MASK, POWER7, 0, {RS}},
{"mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE, 0, {RT}},
{"mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE, 0, {RT}},
{"mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE, 0, {RT}},
@@ -6824,6 +6861,14 @@ const struct powerpc_opcode powerpc_opco
{"mfivor13", XSPR(31,339,413), XSPR_MASK, BOOKE, 0, {RT}},
{"mfivor14", XSPR(31,339,414), XSPR_MASK, BOOKE, 0, {RT}},
{"mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE, 0, {RT}},
+{"mftir", XSPR(31,339,446), XSPR_MASK, POWER10, 0, {RS}},
+{"mfptcr", XSPR(31,339,464), XSPR_MASK, POWER10, 0, {RS}},
+{"mfuspgr0", XSPR(31,339,496), XSPR_MASK, POWER10, 0, {RS}},
+{"mfuspgr1", XSPR(31,339,497), XSPR_MASK, POWER10, 0, {RS}},
+{"mfurmor", XSPR(31,339,505), XSPR_MASK, POWER10, 0, {RS}},
+{"mfusrr0", XSPR(31,339,506), XSPR_MASK, POWER10, 0, {RS}},
+{"mfusrr1", XSPR(31,339,507), XSPR_MASK, POWER10, 0, {RS}},
+{"mfsmfctrl", XSPR(31,339,511), XSPR_MASK, POWER10, 0, {RS}},
{"mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, 0, {RT}},
{"mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, 0, {RT}},
{"mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, 0, {RT}},
@@ -6848,18 +6893,36 @@ const struct powerpc_opcode powerpc_opco
{"mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, 0, {RT}},
{"mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, 0, {RT}},
{"mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, 0, {RT}},
+{"mfusier2", XSPR(31,339,736), XSPR_MASK, POWER10, 0, {RT}},
+{"mfsier2", XSPR(31,339,736), XSPR_MASK, POWER10, 0, {RT}},
+{"mfusier3", XSPR(31,339,737), XSPR_MASK, POWER10, 0, {RT}},
+{"mfsier3", XSPR(31,339,737), XSPR_MASK, POWER10, 0, {RT}},
+{"mfummcr3", XSPR(31,339,738), XSPR_MASK, POWER10, 0, {RT}},
+{"mfmmcr3", XSPR(31,339,738), XSPR_MASK, POWER10, 0, {RT}},
+{"mfusier", XSPR(31,339,768), XSPR_MASK, POWER10, 0, {RT}},
+{"mfsier", XSPR(31,339,768), XSPR_MASK, POWER10, 0, {RT}},
+{"mfummcra", XSPR(31,339,770), XSPR_MASK, POWER9, 0, {RS}},
+{"mfmmcra", XSPR(31,339,770), XSPR_MASK, POWER7, 0, {RS}},
{"mfupmc1", XSPR(31,339,771), XSPR_MASK, POWER9, 0, {RT}},
-{"mfpmc1", XSPR(31,339,771), XSPR_MASK, POWER9, 0, {RT}},
+{"mfpmc1", XSPR(31,339,771), XSPR_MASK, POWER7, 0, {RT}},
{"mfupmc2", XSPR(31,339,772), XSPR_MASK, POWER9, 0, {RT}},
-{"mfpmc2", XSPR(31,339,772), XSPR_MASK, POWER9, 0, {RT}},
+{"mfpmc2", XSPR(31,339,772), XSPR_MASK, POWER7, 0, {RT}},
{"mfupmc3", XSPR(31,339,773), XSPR_MASK, POWER9, 0, {RT}},
-{"mfpmc3", XSPR(31,339,773), XSPR_MASK, POWER9, 0, {RT}},
+{"mfpmc3", XSPR(31,339,773), XSPR_MASK, POWER7, 0, {RT}},
{"mfupmc4", XSPR(31,339,774), XSPR_MASK, POWER9, 0, {RT}},
-{"mfpmc4", XSPR(31,339,774), XSPR_MASK, POWER9, 0, {RT}},
+{"mfpmc4", XSPR(31,339,774), XSPR_MASK, POWER7, 0, {RT}},
{"mfupmc5", XSPR(31,339,775), XSPR_MASK, POWER9, 0, {RT}},
-{"mfpmc5", XSPR(31,339,775), XSPR_MASK, POWER9, 0, {RT}},
+{"mfpmc5", XSPR(31,339,775), XSPR_MASK, POWER7, 0, {RT}},
{"mfupmc6", XSPR(31,339,776), XSPR_MASK, POWER9, 0, {RT}},
-{"mfpmc6", XSPR(31,339,776), XSPR_MASK, POWER9, 0, {RT}},
+{"mfpmc6", XSPR(31,339,776), XSPR_MASK, POWER7, 0, {RT}},
+{"mfummcr0", XSPR(31,339,779), XSPR_MASK, POWER9, 0, {RS}},
+{"mfmmcr0", XSPR(31,339,779), XSPR_MASK, POWER7, 0, {RS}},
+{"mfusiar", XSPR(31,339,780), XSPR_MASK, POWER9, 0, {RS}},
+{"mfsiar", XSPR(31,339,780), XSPR_MASK, POWER9, 0, {RS}},
+{"mfusdar", XSPR(31,339,781), XSPR_MASK, POWER9, 0, {RS}},
+{"mfsdar", XSPR(31,339,781), XSPR_MASK, POWER9, 0, {RS}},
+{"mfummcr1", XSPR(31,339,782), XSPR_MASK, POWER9, 0, {RS}},
+{"mfmmcr1", XSPR(31,339,782), XSPR_MASK, POWER7, 0, {RS}},
{"mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, 0, {RT}},
{"mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, 0, {RT}},
{"mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, 0, {RT}},
@@ -6873,12 +6936,25 @@ const struct powerpc_opcode powerpc_opco
{"mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, 0, {RT}},
{"mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, 0, {RT}},
{"mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, 0, {RT}},
+{"mfbescrs", XSPR(31,339,800), XSPR_MASK, POWER9, 0, {RS}},
+{"mfbescrsu", XSPR(31,339,801), XSPR_MASK, POWER9, 0, {RS}},
+{"mfbescrr", XSPR(31,339,802), XSPR_MASK, POWER9, 0, {RS}},
+{"mfbescrru", XSPR(31,339,803), XSPR_MASK, POWER9, 0, {RS}},
+{"mfebbhr", XSPR(31,339,804), XSPR_MASK, POWER9, 0, {RS}},
+{"mfebbrr", XSPR(31,339,805), XSPR_MASK, POWER9, 0, {RS}},
+{"mfbescr", XSPR(31,339,806), XSPR_MASK, POWER9, 0, {RS}},
+{"mftar", XSPR(31,339,815), XSPR_MASK, POWER9, 0, {RS}},
+{"mfasdr", XSPR(31,339,816), XSPR_MASK, POWER10, 0, {RS}},
{"mfmi_dbcam", XSPR(31,339,816), XSPR_MASK, PPC860, 0, {RT}},
{"mfmi_dbram0", XSPR(31,339,817), XSPR_MASK, PPC860, 0, {RT}},
{"mfmi_dbram1", XSPR(31,339,818), XSPR_MASK, PPC860, 0, {RT}},
+{"mfpsscr", XSPR(31,339,823), XSPR_MASK, POWER10, 0, {RS}},
{"mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, 0, {RT}},
{"mfmd_dbram0", XSPR(31,339,825), XSPR_MASK, PPC860, 0, {RT}},
{"mfmd_dbram1", XSPR(31,339,826), XSPR_MASK, PPC860, 0, {RT}},
+{"mfic", XSPR(31,339,848), XSPR_MASK, POWER8, 0, {RS}},
+{"mfvtb", XSPR(31,339,849), XSPR_MASK, POWER8, 0, {RS}},
+{"mfhpsscr", XSPR(31,339,855), XSPR_MASK, POWER10, 0, {RS}},
{"mfivndx", XSPR(31,339,880), XSPR_MASK, TITAN, 0, {RT}},
{"mfdvndx", XSPR(31,339,881), XSPR_MASK, TITAN, 0, {RT}},
{"mfivlim", XSPR(31,339,882), XSPR_MASK, TITAN, 0, {RT}},
@@ -7051,14 +7127,15 @@ const struct powerpc_opcode powerpc_opco
{"sthux", X(31,439), X_MASK, COM, 0, {RS, RAS, RB}},
-{"mdors", 0x7f9ce378, 0xffffffff, E500MC, 0, {0}},
-
-{"miso", 0x7f5ad378, 0xffffffff, E6500, 0, {0}},
-
-/* The "yield", "mdoio" and "mdoom" instructions are extended mnemonics for
- "or rX,rX,rX", with rX being r27, r29 and r30 respectively. */
+/* or 26,26,26 */
+{"miso", 0x7f5ad378, 0xffffffff, POWER8|E6500, 0, {0}},
+/* or 27,27,27 */
{"yield", 0x7f7bdb78, 0xffffffff, POWER7, 0, {0}},
+/* or 28,28,28 */
+{"mdors", 0x7f9ce378, 0xffffffff, E500MC, 0, {0}},
+/* or 29,29,29 */
{"mdoio", 0x7fbdeb78, 0xffffffff, POWER7, 0, {0}},
+/* or 30,30,30 */
{"mdoom", 0x7fdef378, 0xffffffff, POWER7, 0, {0}},
{"mr", XRC(31,444,0), X_MASK, COM, 0, {RA, RSB}},
{"or", XRC(31,444,0), X_MASK, COM, 0, {RA, RS, RB}},
@@ -7124,8 +7201,10 @@ const struct powerpc_opcode powerpc_opco
{"mtmq", XSPR(31,467, 0), XSPR_MASK, M601, 0, {RS}},
{"mtxer", XSPR(31,467, 1), XSPR_MASK, COM, 0, {RS}},
+{"mtudscr", XSPR(31,467, 3), XSPR_MASK, POWER9, 0, {RS}},
{"mtlr", XSPR(31,467, 8), XSPR_MASK, COM, 0, {RS}},
{"mtctr", XSPR(31,467, 9), XSPR_MASK, COM, 0, {RS}},
+{"mtuamr", XSPR(31,467, 13), XSPR_MASK, POWER9, 0, {RS}},
{"mtdscr", XSPR(31,467, 17), XSPR_MASK, POWER6, 0, {RS}},
{"mttid", XSPR(31,467, 17), XSPR_MASK, POWER, 0, {RS}},
{"mtdsisr", XSPR(31,467, 18), XSPR_MASK, COM, TITAN, {RS}},
@@ -7138,13 +7217,20 @@ const struct powerpc_opcode powerpc_opco
{"mtsrr0", XSPR(31,467, 26), XSPR_MASK, COM, 0, {RS}},
{"mtsrr1", XSPR(31,467, 27), XSPR_MASK, COM, 0, {RS}},
{"mtcfar", XSPR(31,467, 28), XSPR_MASK, POWER6, 0, {RS}},
+{"mtamr", XSPR(31,467, 29), XSPR_MASK, POWER7, 0, {RS}},
+{"mtpidr", XSPR(31,467, 48), XSPR_MASK, POWER10, 0, {RS}},
{"mtpid", XSPR(31,467, 48), XSPR_MASK, BOOKE, 0, {RS}},
{"mtdecar", XSPR(31,467, 54), XSPR_MASK, BOOKE, 0, {RS}},
{"mtcsrr0", XSPR(31,467, 58), XSPR_MASK, BOOKE, 0, {RS}},
{"mtcsrr1", XSPR(31,467, 59), XSPR_MASK, BOOKE, 0, {RS}},
+{"mtiamr", XSPR(31,467, 61), XSPR_MASK, POWER10, 0, {RS}},
{"mtdear", XSPR(31,467, 61), XSPR_MASK, BOOKE, 0, {RS}},
{"mtesr", XSPR(31,467, 62), XSPR_MASK, BOOKE, 0, {RS}},
{"mtivpr", XSPR(31,467, 63), XSPR_MASK, BOOKE, 0, {RS}},
+{"mttfhar", XSPR(31,467,128), XSPR_MASK, POWER9, 0, {RS}},
+{"mttfiar", XSPR(31,467,129), XSPR_MASK, POWER9, 0, {RS}},
+{"mttexasr", XSPR(31,467,130), XSPR_MASK, POWER9, 0, {RS}},
+{"mttexasru", XSPR(31,467,131), XSPR_MASK, POWER9, 0, {RS}},
{"mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, 0, {RS}},
{"mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, 0, {RS}},
{"mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, 0, {RS}},
@@ -7155,13 +7241,24 @@ const struct powerpc_opcode powerpc_opco
{"mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, 0, {RS}},
{"mtctrl", XSPR(31,467,152), XSPR_MASK, POWER4, 0, {RS}},
{"mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, 0, {RS}},
+{"mtfscr", XSPR(31,467,153), XSPR_MASK, POWER10, 0, {RS}},
{"mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, 0, {RS}},
{"mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, 0, {RS}},
{"mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, 0, {RS}},
{"mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, 0, {RS}},
+{"mtuamor", XSPR(31,467,157), XSPR_MASK, POWER7, 0, {RS}},
{"mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, 0, {RS}},
{"mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, 0, {RS}},
+{"mtpspb", XSPR(31,467,159), XSPR_MASK, POWER10, 0, {RS}},
{"mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, 0, {RS}},
+{"mtdpdes", XSPR(31,467,176), XSPR_MASK, POWER10, 0, {RS}},
+{"mtdawr0", XSPR(31,467,180), XSPR_MASK, POWER10, 0, {RS}},
+{"mtdawr1", XSPR(31,467,181), XSPR_MASK, POWER10, 0, {RS}},
+{"mtrpr", XSPR(31,467,186), XSPR_MASK, POWER10, 0, {RS}},
+{"mtciabr", XSPR(31,467,187), XSPR_MASK, POWER10, 0, {RS}},
+{"mtdawrx0", XSPR(31,467,188), XSPR_MASK, POWER10, 0, {RS}},
+{"mtdawrx1", XSPR(31,467,189), XSPR_MASK, POWER10, 0, {RS}},
+{"mthfscr", XSPR(31,467,190), XSPR_MASK, POWER10, 0, {RS}},
{"mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, 0, {RS}},
{"mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE, 0, {RS}},
{"mtsprg", XSPR(31,467,256), XSPRG_MASK, PPC, 0, {SPRG, RS}},
@@ -7177,20 +7274,38 @@ const struct powerpc_opcode powerpc_opco
{"mtear", XSPR(31,467,282), XSPR_MASK, PPC, TITAN, {RS}},
{"mttbl", XSPR(31,467,284), XSPR_MASK, PPC, 0, {RS}},
{"mttbu", XSPR(31,467,285), XSPR_MASK, PPC, 0, {RS}},
+{"mttbu40", XSPR(31,467,286), XSPR_MASK, POWER10, 0, {RS}},
+{"mthsprg0", XSPR(31,467,304), XSPR_MASK, POWER10, 0, {RS}},
{"mtdbsr", XSPR(31,467,304), XSPR_MASK, BOOKE, 0, {RS}},
+{"mthsprg1", XSPR(31,467,305), XSPR_MASK, POWER10, 0, {RS}},
+{"mthdisr", XSPR(31,467,306), XSPR_MASK, POWER10, 0, {RS}},
+{"mthdar", XSPR(31,467,307), XSPR_MASK, POWER10, 0, {RS}},
+{"mtspurr", XSPR(31,467,308), XSPR_MASK, POWER10, 0, {RS}},
{"mtdbcr0", XSPR(31,467,308), XSPR_MASK, BOOKE, 0, {RS}},
+{"mtpurr", XSPR(31,467,309), XSPR_MASK, POWER10, 0, {RS}},
{"mtdbcr1", XSPR(31,467,309), XSPR_MASK, BOOKE, 0, {RS}},
+{"mthdec", XSPR(31,467,310), XSPR_MASK, POWER10, 0, {RS}},
{"mtdbcr2", XSPR(31,467,310), XSPR_MASK, BOOKE, 0, {RS}},
{"mtiac1", XSPR(31,467,312), XSPR_MASK, BOOKE, 0, {RS}},
+{"mthrmor", XSPR(31,467,313), XSPR_MASK, POWER10, 0, {RS}},
{"mtiac2", XSPR(31,467,313), XSPR_MASK, BOOKE, 0, {RS}},
+{"mthsrr0", XSPR(31,467,314), XSPR_MASK, POWER10, 0, {RS}},
{"mtiac3", XSPR(31,467,314), XSPR_MASK, BOOKE, 0, {RS}},
+{"mthsrr1", XSPR(31,467,315), XSPR_MASK, POWER10, 0, {RS}},
{"mtiac4", XSPR(31,467,315), XSPR_MASK, BOOKE, 0, {RS}},
{"mtdac1", XSPR(31,467,316), XSPR_MASK, BOOKE, 0, {RS}},
{"mtdac2", XSPR(31,467,317), XSPR_MASK, BOOKE, 0, {RS}},
+{"mtlpcr", XSPR(31,467,318), XSPR_MASK, POWER10, 0, {RS}},
{"mtdvc1", XSPR(31,467,318), XSPR_MASK, BOOKE, 0, {RS}},
+{"mtlpidr", XSPR(31,467,319), XSPR_MASK, POWER10, 0, {RS}},
{"mtdvc2", XSPR(31,467,319), XSPR_MASK, BOOKE, 0, {RS}},
+{"mthmer", XSPR(31,467,336), XSPR_MASK, POWER7, 0, {RS}},
{"mttsr", XSPR(31,467,336), XSPR_MASK, BOOKE, 0, {RS}},
+{"mthmeer", XSPR(31,467,337), XSPR_MASK, POWER7, 0, {RS}},
+{"mtpcr", XSPR(31,467,338), XSPR_MASK, POWER10, 0, {RS}},
+{"mtheir", XSPR(31,467,339), XSPR_MASK, POWER10, 0, {RS}},
{"mttcr", XSPR(31,467,340), XSPR_MASK, BOOKE, 0, {RS}},
+{"mtamor", XSPR(31,467,349), XSPR_MASK, POWER7, 0, {RS}},
{"mtivor0", XSPR(31,467,400), XSPR_MASK, BOOKE, 0, {RS}},
{"mtivor1", XSPR(31,467,401), XSPR_MASK, BOOKE, 0, {RS}},
{"mtivor2", XSPR(31,467,402), XSPR_MASK, BOOKE, 0, {RS}},
@@ -7207,6 +7322,13 @@ const struct powerpc_opcode powerpc_opco
{"mtivor13", XSPR(31,467,413), XSPR_MASK, BOOKE, 0, {RS}},
{"mtivor14", XSPR(31,467,414), XSPR_MASK, BOOKE, 0, {RS}},
{"mtivor15", XSPR(31,467,415), XSPR_MASK, BOOKE, 0, {RS}},
+{"mtptcr", XSPR(31,467,464), XSPR_MASK, POWER10, 0, {RS}},
+{"mtuspgr0", XSPR(31,467,496), XSPR_MASK, POWER10, 0, {RS}},
+{"mtuspgr1", XSPR(31,467,497), XSPR_MASK, POWER10, 0, {RS}},
+{"mturmor", XSPR(31,467,505), XSPR_MASK, POWER10, 0, {RS}},
+{"mtusrr0", XSPR(31,467,506), XSPR_MASK, POWER10, 0, {RS}},
+{"mtusrr1", XSPR(31,467,507), XSPR_MASK, POWER10, 0, {RS}},
+{"mtsmfctrl", XSPR(31,467,511), XSPR_MASK, POWER10, 0, {RS}},
{"mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, 0, {RS}},
{"mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, 0, {RS}},
{"mtbbtar", XSPR(31,467,514), XSPR_MASK, PPCBRLK, 0, {RS}},
@@ -7221,12 +7343,44 @@ const struct powerpc_opcode powerpc_opco
{"mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, 0, {RS}},
{"mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, 0, {RS}},
{"mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, 0, {RS}},
+{"mtsier2", XSPR(31,467,752), XSPR_MASK, POWER10, 0, {RS}},
+{"mtsier3", XSPR(31,467,753), XSPR_MASK, POWER10, 0, {RS}},
+{"mtmmcr3", XSPR(31,467,754), XSPR_MASK, POWER10, 0, {RS}},
+{"mtummcr2", XSPR(31,467,769), XSPR_MASK, POWER9, 0, {RS}},
+{"mtmmcr2", XSPR(31,467,769), XSPR_MASK, POWER9, 0, {RS}},
+{"mtummcra", XSPR(31,467,770), XSPR_MASK, POWER9, 0, {RS}},
{"mtupmc1", XSPR(31,467,771), XSPR_MASK, POWER9, 0, {RS}},
{"mtupmc2", XSPR(31,467,772), XSPR_MASK, POWER9, 0, {RS}},
{"mtupmc3", XSPR(31,467,773), XSPR_MASK, POWER9, 0, {RS}},
{"mtupmc4", XSPR(31,467,774), XSPR_MASK, POWER9, 0, {RS}},
{"mtupmc5", XSPR(31,467,775), XSPR_MASK, POWER9, 0, {RS}},
{"mtupmc6", XSPR(31,467,776), XSPR_MASK, POWER9, 0, {RS}},
+{"mtummcr0", XSPR(31,467,779), XSPR_MASK, POWER9, 0, {RS}},
+{"mtsier", XSPR(31,467,784), XSPR_MASK, POWER10, 0, {RS}},
+{"mtmmcra", XSPR(31,467,786), XSPR_MASK, POWER7, 0, {RS}},
+{"mtpmc1", XSPR(31,467,787), XSPR_MASK, POWER7, 0, {RS}},
+{"mtpmc2", XSPR(31,467,788), XSPR_MASK, POWER7, 0, {RS}},
+{"mtpmc3", XSPR(31,467,789), XSPR_MASK, POWER7, 0, {RS}},
+{"mtpmc4", XSPR(31,467,790), XSPR_MASK, POWER7, 0, {RS}},
+{"mtpmc5", XSPR(31,467,791), XSPR_MASK, POWER7, 0, {RS}},
+{"mtpmc6", XSPR(31,467,792), XSPR_MASK, POWER7, 0, {RS}},
+{"mtmmcr0", XSPR(31,467,795), XSPR_MASK, POWER7, 0, {RS}},
+{"mtsiar", XSPR(31,467,796), XSPR_MASK, POWER10, 0, {RS}},
+{"mtsdar", XSPR(31,467,797), XSPR_MASK, POWER10, 0, {RS}},
+{"mtmmcr1", XSPR(31,467,798), XSPR_MASK, POWER7, 0, {RS}},
+{"mtbescrs", XSPR(31,467,800), XSPR_MASK, POWER9, 0, {RS}},
+{"mtbescrsu", XSPR(31,467,801), XSPR_MASK, POWER9, 0, {RS}},
+{"mtbescrr", XSPR(31,467,802), XSPR_MASK, POWER9, 0, {RS}},
+{"mtbescrru", XSPR(31,467,803), XSPR_MASK, POWER9, 0, {RS}},
+{"mtebbhr", XSPR(31,467,804), XSPR_MASK, POWER9, 0, {RS}},
+{"mtebbrr", XSPR(31,467,805), XSPR_MASK, POWER9, 0, {RS}},
+{"mtbescr", XSPR(31,467,806), XSPR_MASK, POWER9, 0, {RS}},
+{"mttar", XSPR(31,467,815), XSPR_MASK, POWER9, 0, {RS}},
+{"mtasdr", XSPR(31,467,816), XSPR_MASK, POWER10, 0, {RS}},
+{"mtpsscr", XSPR(31,467,823), XSPR_MASK, POWER10, 0, {RS}},
+{"mtic", XSPR(31,467,848), XSPR_MASK, POWER8, 0, {RS}},
+{"mtvtb", XSPR(31,467,849), XSPR_MASK, POWER8, 0, {RS}},
+{"mthpsscr", XSPR(31,467,855), XSPR_MASK, POWER10, 0, {RS}},
{"mtivndx", XSPR(31,467,880), XSPR_MASK, TITAN, 0, {RS}},
{"mtdvndx", XSPR(31,467,881), XSPR_MASK, TITAN, 0, {RS}},
{"mtivlim", XSPR(31,467,882), XSPR_MASK, TITAN, 0, {RS}},
@@ -8301,7 +8455,7 @@ const struct powerpc_opcode powerpc_opco
{"xxgenpcvdm", X(60,949), XX1_MASK, POWER10, PPCVLE, {XT6, VB, UIMM}},
{"xvxexpdp", XX2VA(60,475,0),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
{"xvxsigdp", XX2VA(60,475,1),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
-{"xvtlsbb", XX2VA(60,475,2),XX2BF_MASK, POWER10, PPCVLE, {OBF, XB6}},
+{"xvtlsbb", XX2VA(60,475,2),XX2BF_MASK, POWER10, PPCVLE, {BF, XB6}},
{"xxbrh", XX2VA(60,475,7),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
{"xvxexpsp", XX2VA(60,475,8),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
{"xvxsigsp", XX2VA(60,475,9),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
--- /dev/null 2020-10-08 09:15:33.282859415 +0100
+++ binutils-2.35.1/gas/testsuite/gas/ppc/be.d 2020-10-08 13:51:29.102731857 +0100
@@ -0,0 +1,17 @@
+#objdump: -d -Mcom
+#as: -mcom -be
+#name: BE only instructions
+
+.*
+
+Disassembly of section \.text:
+
+0+00 <start>:
+.*: ba 8a 00 10 lmw r20,16\(r10\)
+.*: 7d 4b 0c aa lswi r10,r11,1
+.*: 7d 8b 04 aa lswi r12,r11,32
+.*: 7d 4b 64 2a lswx r10,r11,r12
+.*: be 8a 00 10 stmw r20,16\(r10\)
+.*: 7d 4b 0d aa stswi r10,r11,1
+.*: 7d 4b 05 aa stswi r10,r11,32
+.*: 7d 4b 65 2a stswx r10,r11,r12
--- /dev/null 2020-10-08 09:15:33.282859415 +0100
+++ binutils-2.35.1/gas/testsuite/gas/ppc/be.s 2020-10-08 13:51:29.102731857 +0100
@@ -0,0 +1,10 @@
+ .text
+start:
+ lmw 20,16(10)
+ lswi 10,11,1
+ lswi 12,11,32
+ lswx 10,11,12
+ stmw 20,16(10)
+ stswi 10,11,1
+ stswi 10,11,32
+ stswx 10,11,12
--- /dev/null 2020-10-08 09:15:33.282859415 +0100
+++ binutils-2.35.1/gas/testsuite/gas/ppc/le_error.d 2020-10-08 13:51:29.102731857 +0100
@@ -0,0 +1,3 @@
+#as: -mcom -le
+#source: be.s
+#error_output: le_error.l
--- /dev/null 2020-10-08 09:15:33.282859415 +0100
+++ binutils-2.35.1/gas/testsuite/gas/ppc/le_error.l 2020-10-08 13:51:29.102731857 +0100
@@ -0,0 +1,9 @@
+.*Assembler messages:
+.*invalid when little-endian
+.*invalid when little-endian
+.*invalid when little-endian
+.*invalid when little-endian
+.*invalid when little-endian
+.*invalid when little-endian
+.*invalid when little-endian
+.*invalid when little-endian